Semiconductor package

Abstract

A semiconductor package is disclosed. The semiconductor package includes a lower redistribution substrate, an upper redistribution substrate, and a semiconductor chip between the lower redistribution substrate and the upper redistribution substrate. The lower redistribution substrate includes a lower dielectric structure, a lower redistribution pattern surrounded by the lower dielectric structure, and a lower shielding structure surrounded by the lower dielectric structure and surrounding the lower redistribution pattern. The upper redistribution substrate includes an upper dielectric structure, an upper redistribution pattern surrounded by the upper dielectric structure, and an upper shielding structure surrounded by the upper dielectric structure and surrounding the upper redistribution pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package. Background Art

[0002] Semiconductor packages are provided to implement integrated circuit chips to meet the use requirements of electronic products. Generally, semiconductor packages are configured so that the semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0003] The disclosed subject matter generally relates to semiconductor packages having improved electrical characteristics and increased reliability.

[0004] In one aspect, a semiconductor package includes: a lower redistribution substrate; an upper redistribution substrate; and a semiconductor chip, the semiconductor chip being located between the lower redistribution substrate and the upper redistribution substrate. The lower redistribution substrate may include: a lower dielectric structure; a lower redistribution pattern, the lower redistribution pattern being surrounded by the lower dielectric structure; and a lower shielding structure, the lower shielding structure being surrounded by the lower dielectric structure and surrounding the lower redistribution pattern. The upper redistribution substrate may include: an upper dielectric structure; an upper redistribution pattern, the upper redistribution pattern being surrounded by the upper dielectric structure; and an upper shielding structure, the upper shielding structure being surrounded by the upper dielectric structure and surrounding the upper redistribution pattern.

[0005] In one aspect, a semiconductor package includes: a lower redistribution substrate; and a semiconductor chip mounted on the lower redistribution substrate. The lower redistribution substrate may include: a lower dielectric structure; a first lower redistribution pattern, the first lower redistribution pattern being surrounded by the lower dielectric structure; a second lower redistribution pattern, the second lower redistribution pattern being located on the first lower redistribution pattern; and a lower shielding structure, the lower shielding structure being surrounded by the lower dielectric structure and surrounding the first lower redistribution pattern and the second lower redistribution pattern. The lower shielding structure may include a first lower shielding pattern and a second lower shielding pattern located on the first lower shielding pattern. The first lower shielding pattern may be located at the same level as that of the first lower redistribution pattern. The second lower shielding pattern may be located at the same level as that of the second lower redistribution pattern.

[0006] In one aspect, a semiconductor package includes: a lower redistribution substrate; a first semiconductor chip mounted on the lower redistribution substrate; a connecting dielectric layer surrounding the first semiconductor chip; a connecting conductive structure located in the connecting dielectric layer; an upper redistribution substrate located on the connecting dielectric layer; and a second semiconductor chip mounted on the upper redistribution substrate. The lower redistribution substrate may include: a lower dielectric structure; a lower redistribution pattern surrounded by the lower dielectric structure; and a lower shielding structure surrounded by the lower dielectric structure and surrounding the lower redistribution pattern. The length of the lower shielding structure may be greater than the length of the first semiconductor chip.

[0007] In one aspect, a method for manufacturing a semiconductor package includes: forming a semiconductor chip; forming a connection dielectric layer surrounding the semiconductor chip; forming a lower redistribution substrate on the semiconductor chip and the connection dielectric layer; and forming an upper redistribution substrate on the connection dielectric layer. The step of forming the lower redistribution substrate may include: forming a first lower dielectric layer on the semiconductor chip and the connection dielectric layer; forming a plurality of openings in the first lower dielectric layer; forming a conductive layer on the first lower dielectric layer; and patterning the conductive layer to form a lower redistribution pattern and a lower shielding pattern. The lower shielding pattern may surround the lower redistribution pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments.

[0009] Figure 1B The diagram shows Figure 1A An enlarged view of section E1.

[0010] Figure 1C The diagram shows Figure 1A A plan view of a planar structure at a level L1.

[0011] Figure 1D The diagram shows Figure 1A A plan view of a planar structure at a level L2.

[0012] Figure 1E A perspective view showing an upper shielding structure is illustrated.

[0013] Figure 1F The diagram shows Figure 1A An enlarged view of section E2.

[0014] Figure 1GA perspective view showing a lower shielding structure is illustrated.

[0015] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E Illustrated are cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments.

[0016] Figure 3 Illustrated is a perspective view partially showing an upper shielding structure in a semiconductor package according to some embodiments.

[0017] Figure 4 An enlarged cross-sectional view showing a semiconductor package according to some embodiments is illustrated.

[0018] Figure 5A An enlarged cross-sectional view showing a semiconductor package according to some embodiments is illustrated.

[0019] Figure 5B The diagram shows Figure 5A A plan view of the planar structure at a level L3.

[0020] Figure 6 A top view illustrating a planar structure of an upper shielding structure in a semiconductor package according to some embodiments is illustrated.

[0021] Figure 7 Illustrated is a plan view showing a plan structure of an upper shield structure in a semiconductor package according to some embodiments.

[0022] Figure 8 Illustrated is a plan view showing a plan structure of an upper shield structure in a semiconductor package according to some embodiments.

[0023] Fig.9A Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments.

[0024] Fig. 9B The diagram shows Fig.9A A plan view of the planar structure at level L4.

[0025] Fig.10 Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments.

[0026] Fig.11 Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments.

[0027] Fig.12 Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments.

[0028] Fig.13 Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0029] Hereinafter, a semiconductor package and a method for manufacturing the same according to some embodiments will be described in detail with reference to the accompanying drawings.

[0030] Figure 1A Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments. Figure 1B The diagram shows Figure 1A A plan view of a planar structure at level L1 of . Figure 1C The diagram shows Figure 1A A plan view of the planar structure at level L2 of . Figure 1D A perspective view showing an upper shielding structure is illustrated. Figure 1E A perspective view showing a lower shielding structure is illustrated. Figure 1F The diagram shows Figure 1A An enlarged view of section E1. Figure 1G The diagram shows Figure 1A An enlarged view of section E2.

[0031] refer to Figure 1A The semiconductor package includes a lower redistribution substrate 10, an upper redistribution substrate 20, a first semiconductor chip 30, a second semiconductor chip 40, a connecting dielectric layer 50, a connecting conductive structure 55, a first molding layer 60, a second molding layer 70, a first bump 81 and a second bump 82.

[0032] The lower redistribution substrate 10 includes a lower dielectric structure 11 , a first lower redistribution pattern 12 a , a second lower redistribution pattern 12 b , a third lower redistribution pattern 12 c , a bump connection pattern 13 , and a lower shielding structure 14 .

[0033] The lower dielectric structure 11 includes a first lower dielectric layer 11a, a second lower dielectric layer 11b located on the first lower dielectric layer 11a, a third lower dielectric layer 11c located on the second lower dielectric layer 11b, and a fourth lower dielectric layer 11d located on the third lower dielectric layer 11c. The first lower dielectric layer 11a, the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d may each have a plate shape extending along a plane extending in the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may intersect with each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other.

[0034] The first lower dielectric layer 11a, the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d may be sequentially stacked along a third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0035] The first lower dielectric layer 11a may include a dielectric material. For example, the first lower dielectric layer 11a may include a photoimageable dielectric (PID) or an ajinomoto buildup film (ABF). The photoimageable dielectric may include, for example, at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer.

[0036] The second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d may include a dielectric material. For example, the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d may include a photoimageable dielectric.

[0037] The first lower redistribution pattern 12a, the second lower redistribution pattern 12b, and the third lower redistribution pattern 12c may be surrounded by the first lower dielectric layer 11a, the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d of the lower dielectric structure 11. The first lower redistribution pattern 12a, the second lower redistribution pattern 12b, and the third lower redistribution pattern 12c may be disposed in the first lower dielectric layer 11a, the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d of the lower dielectric structure 11.

[0038] The second lower redistribution pattern 12b may be disposed on the first lower redistribution pattern 12a. The third lower redistribution pattern 12c may be disposed on the second lower redistribution pattern 12b. The second lower redistribution pattern 12b may be located at a level higher than that of the first lower redistribution pattern 12a. The third lower redistribution pattern 12c may be located at a level higher than that of the second lower redistribution pattern 12b.

[0039] The first lower redistribution pattern 12a, the second lower redistribution pattern 12b, and the third lower redistribution pattern 12c may include a conductive material. For example, the first lower redistribution pattern 12a, the second lower redistribution pattern 12b, and the third lower redistribution pattern 12c may include copper.

[0040] The bump connection pattern 13 may be connected to the first lower redistribution pattern 12a. The bump connection pattern 13 may be exposed outward from the lower dielectric structure 11. The bump connection pattern 13 may include a conductive material. For example, the bump connection pattern 13 may include copper.

[0041] The lower shield structure 14 may surround the first lower redistribution pattern 12a, the second lower redistribution pattern 12b, and the third lower redistribution pattern 12c. The lower shield structure 14 may be surrounded by the first lower dielectric layer 11a, the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d of the lower dielectric structure 11. The lower shield structure 14 may be disposed in the first lower dielectric layer 11a, the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d of the lower dielectric structure 11.

[0042] The lower shield structure 14 may be disposed on an outer region of the lower redistribution substrate 10. The first lower redistribution pattern 12a, the second lower redistribution pattern 12b, and the third lower redistribution pattern 12c and the bump connection pattern 13 may be disposed on an inner region of the lower redistribution substrate 10. The inner region of the lower redistribution substrate 10 may be closer to the center of the lower redistribution substrate 10 than the outer region of the lower redistribution substrate 10. The outer region of the lower redistribution substrate 10 may surround the inner region of the lower redistribution substrate 10.

[0043] The lower shield structure 14 includes a first lower shield pattern 14a, a second lower shield pattern 14b located on the first lower shield pattern 14a, and a third lower shield pattern 14c located on the second lower shield pattern 14b. The second lower shield pattern 14b may be located at a level higher than that of the first lower shield pattern 14a. The third lower shield pattern 14c may be located at a level higher than that of the second lower shield pattern 14b. The first lower shield pattern 14a may be located at the same level as that of the first lower redistribution pattern 12a. The second lower shield pattern 14b may be located at the same level as that of the second lower redistribution pattern 12b. The third lower shield pattern 14c may be located at the same level as that of the third lower redistribution pattern 12c.

[0044] The first lower shield pattern 14a, the second lower shield pattern 14b, and the third lower shield pattern 14c may include the same material as the first lower redistribution pattern 12a, the second lower redistribution pattern 12b, and the third lower redistribution pattern 12c. For example, the first lower shield pattern 14a, the second lower shield pattern 14b, and the third lower shield pattern 14c may include copper.

[0045] The first bumps 81 may be connected to the bump connection patterns 13. The semiconductor package may be electrically connected to an external device through the first bumps 81. The first bumps 81 may include a conductive material.

[0046] The first semiconductor chip 30 may be disposed on the lower redistribution substrate 10. The first semiconductor chip 30 may include at least one selected from a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the first semiconductor chip 30 may be a logic chip including a logic semiconductor device, a memory chip including a memory semiconductor device, an image sensor chip including an image sensor device, or a modem chip.

[0047] The first semiconductor chip 30 includes a first pad 31. The first pad 31 may contact the third lower redistribution pattern 12c. The first pad 31 may include a conductive material. For example, the first pad 31 may include copper.

[0048] The first semiconductor chip 30 may be mounted on the lower redistribution substrate 10. The first semiconductor chip 30 may be electrically connected to the lower redistribution substrate 10. The bottom surface of the first semiconductor chip 30 may be in contact with the top surface of the lower redistribution substrate 10. In some embodiments, a bump may be provided between the first semiconductor chip 30 and the lower redistribution substrate 10, and the first semiconductor chip 30 and the lower redistribution substrate 10 may be electrically connected through the bump.

[0049] The connection dielectric layer 50 may be disposed on the lower redistribution substrate 10. The bottom surface of the connection dielectric layer 50 may be in contact with the top surface of the lower redistribution substrate 10. The connection dielectric layer 50 may surround the first semiconductor chip 30. The connection dielectric layer 50 may include a polymer material. For example, the connection dielectric layer 50 may include at least one selected from phenolic resin, epoxy resin, and polyimide. In some embodiments, the connection dielectric layer 50 may be a multilayer including a plurality of dielectric layers.

[0050] The connection dielectric layer 50 may be provided with a connection conductive structure 55. The connection dielectric layer 50 may surround each connection conductive structure 55. The connection conductive structure 55 includes connection conductive patterns 56 overlapping each other along the third direction D3. The connection conductive structure 55 may contact the third lower redistribution pattern 12c. The connection conductive pattern 56 may include a conductive material. For example, the connection conductive pattern 56 may include copper.

[0051] The distance between the lower shield structure 14 and the first semiconductor chip 30 may be greater than the distance between the connecting conductive structure 55 and the first semiconductor chip 30. For example, the distance between the lower shield structure 14 and the first semiconductor chip 30 in the first direction D1 may be greater than the distance between the connecting conductive structure 55 and the first semiconductor chip 30 in the first direction D1. The distance between the lower shield structure 14 and the first semiconductor chip 30 may be greater than the distance between the lower redistribution patterns 12a, 12b, and 12c and the first semiconductor chip 30. For example, the distance between the lower shield structure 14 and the first semiconductor chip 30 in the first direction D1 may be greater than the distance between the lower redistribution patterns 12a, 12b, and 12c and the first semiconductor chip 30 in the first direction D1. The distance between the outer sidewall of the lower dielectric structure 11 and the lower shield structure 14 may be less than the distance between the outer sidewall of the lower dielectric structure 11 and the lower redistribution patterns 12a, 12b, and 12c. For example, a distance between the outer sidewall of the lower dielectric structure 11 and the lower shield structure 14 in the first direction D1 may be smaller than a distance between the outer sidewall of the lower dielectric structure 11 and the lower redistribution patterns 12a, 12b, and 12c in the first direction D1.

[0052] The first mold layer 60 may be disposed between the first semiconductor chip 30 and the connection dielectric layer 50. The first mold layer 60 may cover the sidewalls and the top surface of the first semiconductor chip 30. The first mold layer 60 may include a polymer material. For example, the first mold layer 60 may include epoxy resin.

[0053] The upper redistribution substrate 20 may be disposed on the first mold layer 60 and the connection dielectric layer 50. The upper redistribution substrate 20 includes an upper dielectric structure 21, a first upper redistribution pattern 22a, a second upper redistribution pattern 22b, and an upper shielding structure 24.

[0054] The upper dielectric structure 21 includes a first upper dielectric layer 21a, a second upper dielectric layer 21b on the first upper dielectric layer 21a, and a third upper dielectric layer 21c on the second upper dielectric layer 21b. The first upper dielectric layer 21a, the second upper dielectric layer 21b, and the third upper dielectric layer 21c may be sequentially stacked along the third direction D3.

[0055] The first upper dielectric layer 21a and the second upper dielectric layer 21b may include a dielectric material. For example, the first upper dielectric layer 21a and the second upper dielectric layer 21b may include a photoimageable dielectric. The third upper dielectric layer 21c may include a dielectric material. For example, the third upper dielectric layer 21c may include a photoimageable dielectric (PID) or an Ajinomoto deposited film (ABF).

[0056] The first upper redistribution pattern 22a and the second upper redistribution pattern 22b may be surrounded by the first upper dielectric layer 21a, the second upper dielectric layer 21b, and the third upper dielectric layer 21c of the upper dielectric structure 21. The first upper redistribution pattern 22a and the second upper redistribution pattern 22b may be disposed in the first upper dielectric layer 21a, the second upper dielectric layer 21b, and the third upper dielectric layer 21c of the upper dielectric structure 21.

[0057] The second upper redistribution pattern 22b may be disposed on the first upper redistribution pattern 22a. The second upper redistribution pattern 22b may be located at a higher level than the first upper redistribution pattern 22a. The first upper redistribution pattern 22a and the second upper redistribution pattern 22b may include a conductive material. For example, the first upper redistribution pattern 22a and the second upper redistribution pattern 22b may include copper.

[0058] The upper shield structure 24 may surround the first upper redistribution pattern 22a and the second upper redistribution pattern 22b. The upper shield structure 24 may be surrounded by the first upper dielectric layer 21a, the second upper dielectric layer 21b, and the third upper dielectric layer 21c of the upper dielectric structure 21. The upper shield structure 24 may be disposed in the first upper dielectric layer 21a, the second upper dielectric layer 21b, and the third upper dielectric layer 21c of the upper dielectric structure 21.

[0059] The upper shield structure 24 may be disposed on an outer region of the upper redistribution substrate 20. The first upper redistribution pattern 22a and the second upper redistribution pattern 22b may be disposed on an inner region of the upper redistribution substrate 20. The outer region of the upper redistribution substrate 20 may surround the inner region of the upper redistribution substrate 20.

[0060] The upper shield structure 24 includes a first upper shield pattern 24a and a second upper shield pattern 24b located on the first upper shield pattern 24a. The second upper shield pattern 24b may be located at a level higher than that of the first upper shield pattern 24a. The first upper shield pattern 24a may be located at the same level as that of the first upper redistribution pattern 22a. The second upper shield pattern 24b may be located at the same level as that of the second upper redistribution pattern 22b.

[0061] The first and second upper shield patterns 24a and 24b may include the same material as the first and second upper redistribution patterns 22a and 22b. For example, the first and second upper shield patterns 24a and 24b may include copper.

[0062] The first and second upper shield patterns 24 a and 24 b of the upper shield structure 24 may overlap the first, second, and third lower shield patterns 14 a, 14 b, and 14 c of the lower shield structure 14 in the third direction D3 .

[0063] The distance between the upper shield structure 24 and the first semiconductor chip 30 may be greater than the distance between the connecting conductive structure 55 and the first semiconductor chip 30. For example, the distance between the upper shield structure 24 and the first semiconductor chip 30 in the first direction D1 may be greater than the distance between the connecting conductive structure 55 and the first semiconductor chip 30 in the first direction D1. The distance between the upper shield structure 24 and the first semiconductor chip 30 may be greater than the distance between the upper redistribution patterns 22a and 22b and the first semiconductor chip 30. For example, the distance between the upper shield structure 24 and the first semiconductor chip 30 in the first direction D1 may be greater than the distance between the upper redistribution patterns 22a and 22b and the first semiconductor chip 30 in the first direction D1. The distance between the outer sidewall of the upper dielectric structure 21 and the upper shield structure 24 may be less than the distance between the outer sidewall of the upper dielectric structure 21 and the upper redistribution patterns 22a and 22b. For example, a distance between the outer sidewall of the upper dielectric structure 21 and the upper shielding structure 24 in the first direction D1 may be smaller than a distance between the outer sidewall of the upper dielectric structure 21 and the upper redistribution patterns 22 a and 22 b in the first direction D1 .

[0064] The second semiconductor chip 40 may be mounted on the upper redistribution substrate 20. The second semiconductor chip 40 may be electrically connected to the upper redistribution substrate 20. The second semiconductor chip 40 may include at least one selected from a semiconductor substrate, a dielectric substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate. In some embodiments, the second semiconductor chip 40 may be a logic chip including a logic semiconductor device, a memory chip including a memory semiconductor device, an image sensor chip including an image sensor device, or a modem chip.

[0065] The second semiconductor chip 40 includes a second pad 41. The second pad 41 may include a conductive material. For example, the second pad 41 may include copper.

[0066] The second bumps 82 may be disposed between the second semiconductor chip 40 and the upper redistribution substrate 20. The second bumps 82 may contact the second upper redistribution pattern 22b and the second pads 41. The second semiconductor chip 40 may be electrically connected to the upper redistribution substrate 20 through the second bumps 82. The second bumps 82 may include a conductive material.

[0067] The second mold layer 70 may be provided to surround the second semiconductor chip 40. The second mold layer 70 may cover the sidewalls and the top surface of the second semiconductor chip 40. The second mold layer 70 may cover the top surface of the upper redistribution substrate 20. The second mold layer 70 may include a polymer material. For example, the second mold layer 70 may include epoxy resin.

[0068] refer to Figure 1B , Figure 1C , Figure 1D and Figure 1E , the second upper shielding pattern 24b includes a shielding passage portion V1 and a shielding base portion B1. The shielding base portion B1 of the second upper shielding pattern 24b may be disposed on the shielding passage portion V1 of the second upper shielding pattern 24b. Although described separately for convenience, the shielding passage portion V1 and the shielding base portion B1 of the second upper shielding pattern 24b may be connected into an integrated structure without a boundary therebetween.

[0069] The shielding passage portion V1 of the second upper shield pattern 24b includes a first portion VP11 extending in the first direction D1 and a second portion VP12 extending in the second direction D2. The first portion VP11 of the shielding passage portion V1 included in the second upper shield pattern 24b may have a line shape whose length in the first direction D1 is greater than the length in the second direction D2. The first portion VP11 of the shielding passage portion V1 included in the second upper shield pattern 24b may have a length in the first direction D1 greater than the length of the first semiconductor chip 30 in the first direction D1. The second portion VP12 of the shielding passage portion V1 included in the second upper shield pattern 24b may have a line shape whose length in the second direction D2 is greater than the length in the first direction D1. The second portion VP12 of the shielding passage portion V1 included in the second upper shield pattern 24b may have a length in the second direction D2 greater than the length of the first semiconductor chip 30 in the second direction D2.

[0070] The first portions VP11 of the shielding via portion V1 included in the second upper shield pattern 24b may be spaced apart from each other in the second direction D2. The second portions VP12 of the shielding via portion V1 included in the second upper shield pattern 24b may be spaced apart from each other in the first direction D1. The first portion VP11 of the shielding via portion V1 included in the second upper shield pattern 24b may be connected to two second portions VP12 of the shielding via portion V1 included in the second upper shield pattern 24b.

[0071] The shielding base portion B1 of the second upper shielding pattern 24b includes a first portion BP11 extending in the first direction D1 and a second portion BP12 extending in the second direction D2. The first portion BP11 of the shielding base portion B1 included in the second upper shielding pattern 24b may have a line shape whose length in the first direction D1 is greater than the length in the second direction D2. The first portion BP11 of the shielding base portion B1 included in the second upper shielding pattern 24b may have a length in the first direction D1 greater than the length of the first semiconductor chip 30 in the first direction D1. The second portion BP12 of the shielding base portion B1 included in the second upper shielding pattern 24b may have a line shape whose length in the second direction D2 is greater than the length in the first direction D1. The second portion BP12 of the shielding base portion B1 included in the second upper shielding pattern 24b may have a length in the second direction D2 greater than the length of the first semiconductor chip 30 in the second direction D2.

[0072] The first portions BP11 of the shielding base portion B1 included in the second upper shield pattern 24b may be spaced apart from each other in the second direction D2. The second portions BP12 of the shielding base portion B1 included in the second upper shield pattern 24b may be spaced apart from each other in the first direction D1. The first portion BP11 of the shielding base portion B1 included in the second upper shield pattern 24b may be connected to the second portion BP12 of the shielding base portion B1 included in the second upper shield pattern 24b.

[0073] Each second upper redistribution pattern 22b includes a redistribution path portion RV1 and a redistribution base portion RB1. The redistribution base portion RB1 of the second upper redistribution pattern 22b may be disposed on the redistribution path portion RV1 of the second upper redistribution pattern 22b. The width of the redistribution path portion RV1 of the second upper redistribution pattern 22b may be smaller than the width of the redistribution base portion RB1 of the second upper redistribution pattern 22b. For example, when Figure 1B When viewed in the vertical cross-section shown, the width of the redistribution via portion RV1 included in the second upper redistribution pattern 22 b in the first direction D1 may be smaller than the width of the redistribution base portion RB1 included in the second upper redistribution pattern 22 b in the first direction D1.

[0074] The width of the redistribution via portion RV1 included in the second upper redistribution pattern 22b may decrease as the horizontal height decreases. The width of the redistribution via portion RV1 included in the second upper redistribution pattern 22b may decrease as the distance from the lower redistribution substrate 10 decreases.

[0075] The redistribution via portion RV1 of the second upper redistribution pattern 22b may be located at the same level as the shielding via portion V1 of the second upper shield pattern 24b. The bottom surface of the redistribution via portion RV1 of the second upper redistribution pattern 22b may be lower than the bottom surface of the shielding via portion V1 of the second upper shield pattern 24b. The bottom surface of the redistribution via portion RV1 included in the second upper redistribution pattern 22b may be coplanar with the bottom surface of the shielding via portion V1 included in the second upper shield pattern 24b.

[0076] The redistribution base bottom RB1 of the second upper redistribution pattern 22b may be located at the same level as the shielding base bottom B1 of the second upper shielding pattern 24b. The top surface of the redistribution base bottom RB1 of the second upper redistribution pattern 22b may be at the same level as the top surface of the shielding base bottom B1 of the second upper shielding pattern 24b. The top surface of the redistribution base bottom RB1 included in the second upper redistribution pattern 22b may be coplanar with the top surface of the shielding base bottom B1 included in the second upper shielding pattern 24b.

[0077] The length of the redistribution via portion RV1 included in each second upper redistribution pattern 22b in the third direction D3 may be the same as the length of the shielding via portion V1 included in the second upper shielding pattern 24b in the third direction D3. The length of the redistribution base portion RB1 included in the second upper redistribution pattern 22b in the third direction D3 may be the same as the length of the shielding base portion B1 included in the second upper shielding pattern 24b in the third direction D3. The length of the second upper redistribution pattern 22b in the third direction D3 may be the same as the length of the second upper shielding pattern 24b in the third direction D3.

[0078] When in Figure 1C When viewed in the plane shown, the redistribution base bottom RB1 of the second upper redistribution pattern 22b may have a circular or bar shape, and the shielding base bottom B1 of the second upper shielding pattern 24b may have a quadrilateral ring shape. The shielding base bottom B1 of the second upper shielding pattern 24b may surround the redistribution base bottom RB1 of the second upper redistribution pattern 22b. The redistribution base bottom RB1 of the second upper redistribution pattern 22b may be disposed between the first portions BP11 of the shielding base bottom B1 included in the second upper shielding pattern 24b. The redistribution base bottom RB1 of the second upper redistribution pattern 22b may be disposed between the second portions BP12 of the shielding base bottom B1 included in the second upper shielding pattern 24b.

[0079] When in Figure 1DWhen viewed in the plane shown, the redistribution passage portion RV1 of the second upper redistribution pattern 22b may have a circular shape, and the shielding passage portion V1 of the second upper shielding pattern 24b may have a quadrilateral ring shape. The shielding passage portion V1 of the second upper shielding pattern 24b may surround the redistribution passage portion RV1 of the second upper redistribution pattern 22b. The redistribution passage portion RV1 of the second upper redistribution pattern 22b may be disposed between the first portions VP11 of the shielding passage portion V1 included in the second upper shielding pattern 24b. The redistribution passage portion RV1 of the second upper redistribution pattern 22b may be disposed between the second portions VP12 of the shielding passage portion V1 included in the second upper shielding pattern 24b.

[0080] refer to Figures 1B to 1E , the width of the shielding passage portion V1 of the second upper shield pattern 24b may be less than the width of the shielding base portion B1 of the second upper shield pattern 24b. For example, the width of each second portion VP12 of the shielding passage portion V1 included in the second upper shield pattern 24b in the first direction D1 may be less than the width of each second portion BP12 of the shielding base portion B1 included in the second upper shield pattern 24b in the first direction D1. The width of the shielding passage portion V1 of the second upper shield pattern 24b may decrease as the horizontal height decreases. The width of the shielding passage portion V1 included in the second upper shield pattern 24b may decrease as the distance from the lower redistribution substrate 10 decreases. For example, the width of each shielding passage portion RV1 included in the second upper shield pattern 24b in the first direction D1 may decrease as the distance from the lower redistribution substrate 10 decreases.

[0081] Each shield via portion RV1 included in the second upper shield pattern 24b may have a width in the first direction D1 in the range of, for example, about 10 μm to about 50 μm. Each second portion BP12 of the shield base portion B1 included in the second upper shield pattern 24b may have a width in the first direction D1 in the range of, for example, about 20 μm to about 100 μm.

[0082] The first upper shield pattern 24a includes a shielding via portion V2 and a shielding base portion B2. The shielding base portion B2 of the first upper shield pattern 24a may be disposed on the shielding via portion V2 of the first upper shield pattern 24a.

[0083] Similar to the shielding via portion V1 of the second upper shield pattern 24b, the shielding via portion V2 of the first upper shield pattern 24a may have a quadrangular ring shape. The shielding via portion V2 of the first upper shield pattern 24a may include a first portion extending in the first direction D1 and a second portion VP22 extending in the second direction D2.

[0084] Similar to the shielding base portion B1 of the second upper shielding pattern 24b, the shielding base portion B2 of the first upper shielding pattern 24a may have a quadrangular ring shape. The shielding base portion B2 of the first upper shielding pattern 24a may include a first portion extending in the first direction D1 and a second portion BP22 extending in the second direction D2.

[0085] The width of the shielding via portion V2 of the first upper shield pattern 24a may be smaller than the width of the shielding base portion B2 of the first upper shield pattern 24a. The width of the shielding via portion V2 included in the first upper shield pattern 24a may decrease as the level decreases.

[0086] The shielding via portion V2 of the first upper shield pattern 24a may overlap the shielding via portion V1 of the second upper shield pattern 24b in the third direction D3. The second portion VP22 of the shielding via portion V2 included in the first upper shield pattern 24a may overlap the second portion VP12 of the shielding via portion V1 included in the second upper shield pattern 24b in the third direction D3.

[0087] Each of the first upper redistribution patterns 22a may include a redistribution passage portion RV2 and a redistribution base portion RB2. The redistribution base portion RB2 of the first upper redistribution pattern 22a may be disposed on the redistribution passage portion RV2 of the first upper redistribution pattern 22a. The width of the redistribution passage portion RV2 of the first upper redistribution pattern 22a may be smaller than the width of the redistribution base portion RB2 of the first upper redistribution pattern 22a. The width of the redistribution passage portion RV2 included in the first upper redistribution pattern 22a may decrease as the horizontal height decreases.

[0088] The redistribution via portion RV2 of the first upper redistribution pattern 22a may be located at the same level as the shielding via portion V2 of the first upper shield pattern 24a. The redistribution base bottom RB2 of the first upper redistribution pattern 22a may be located at the same level as the shielding base bottom B2 of the first upper shield pattern 24a.

[0089] The shielding base portion B2 of the first upper shield pattern 24a may surround the redistribution base portion RB2 of the first upper redistribution pattern 22a. The shielding via portion V2 of the first upper shield pattern 24a may surround the redistribution via portion RV2 of the first upper redistribution pattern 22a.

[0090] The first upper dielectric layer 21a and the second upper dielectric layer 21b each include an inner portion IN surrounded by an upper shielding structure 24 and an outer portion OU surrounding the upper shielding structure 24. The upper shielding structure 24 can separate the inner portion IN and the outer portion OU of each of the first upper dielectric layer 21a and the second upper dielectric layer 21b from each other. The inner portion IN and the outer portion OU of the first upper dielectric layer 21a can be spaced apart from each other via the shielding path portion V2 of the first upper shielding pattern 24a. The inner portion IN and the outer portion OU of the second upper dielectric layer 21b can be spaced apart from each other via the shielding base portion B2 of the first upper shielding pattern 24a and the shielding path portion V1 of the second upper shielding pattern 24b.

[0091] The upper shield structure 24 may have a quadrilateral ring shape. The upper shield structure 24 may include a first portion extending in the first direction D1 and a second portion extending in the second direction D2. The first portion of the upper shield structure 24 may include a first portion of the shielding path portion V2 and a first portion of the shielding base portion B2 included in the first upper shield pattern 24a, and may also include a first portion VP11 of the shielding path portion V1 and a first portion BP11 of the shielding base portion B1 included in the second upper shield pattern 24b. The second portion of the upper shield structure 24 may include a second portion VP22 of the shielding path portion V2 and a second portion BP22 of the shielding base portion B2 included in the first upper shield pattern 24a, and may also include a second portion VP12 of the shielding path portion V1 and a second portion BP12 of the shielding base portion B1 included in the second upper shield pattern 24b.

[0092] The first portion included in the upper shield structure 24 may have a length in the first direction D1 greater than the length of the first semiconductor chip 30 in the first direction D1. The second portion included in the upper shield structure 24 may have a length in the second direction D2 greater than the length of the first semiconductor chip 30 in the second direction D2.

[0093] The first upper redistribution pattern 22a and the second upper redistribution pattern 22b may be disposed between first portions of the upper shield structures 24. The first upper redistribution pattern 22a and the second upper redistribution pattern 22b may be disposed between second portions of the upper shield structures 24.

[0094] refer to Figure 1F and Figure 1G , each of the first lower shield patterns 14a includes a shielding via portion V3 and a shielding base portion B3. The shielding via portion V3 of the first lower shield pattern 14a may be disposed on the shielding base portion B3 of the first lower shield pattern 14a.

[0095] Similar to the shielding via portion V1 of the second upper shield pattern 24b, the shielding via portion V3 of the first lower shield pattern 14a may have a quadrilateral ring shape. The shielding via portion V3 of the first lower shield pattern 14a may include a first portion extending in the first direction D1 and a second portion VP32 extending in the second direction D2.

[0096] Similar to the shielding base portion B1 of the second upper shielding pattern 24b, the shielding base portion B3 of the first lower shielding pattern 14a may have a quadrangular ring shape. The shielding base portion B3 of the first lower shielding pattern 14a may include a first portion extending in the first direction D1 and a second portion BP32 extending in the second direction D2.

[0097] The width of the shielding via portion V3 of the first lower shield pattern 14a may be smaller than the width of the shielding base portion B3 of the first lower shield pattern 14a. The width of the shielding via portion V3 included in the first lower shield pattern 14a may decrease as the level increases. The width of the shielding via portion V3 included in the first lower shield pattern 14a may decrease as the distance from the upper redistribution substrate 20 decreases.

[0098] Each of the first lower redistribution patterns 12a includes a redistribution passage portion RV3 and a redistribution base portion RB3. The redistribution passage portion RV3 of the first lower redistribution pattern 12a may be disposed on the redistribution base portion RB3 of the first lower redistribution pattern 12a. The width of the redistribution passage portion RV3 of the first lower redistribution pattern 12a may be smaller than the width of the redistribution base portion RB3 of the first lower redistribution pattern 12a. The width of the redistribution passage portion RV3 included in the first lower redistribution pattern 12a may decrease as the horizontal height increases.

[0099] The redistribution via portion RV3 of each first lower redistribution pattern 12a may be located at the same level as the shielding via portion V3 of the first lower shield pattern 14a. The redistribution base bottom RB3 of each first lower redistribution pattern 12a may be located at the same level as the shielding base bottom B3 of the first lower shield pattern 14a.

[0100] The shielding base portion B3 of the first lower shield pattern 14a may surround the redistribution base portion RB3 of the first lower redistribution pattern 12a. The shielding via portion V3 of the first lower shield pattern 14a may surround the redistribution via portion RV3 of the first lower redistribution pattern 12a.

[0101] The second lower shield pattern 14b includes a shield via portion V4 and a shield base portion B4. The shield via portion V4 of the second lower shield pattern 14b may be disposed on the shield base portion B4 of the second lower shield pattern 14b.

[0102] Similar to the shielding via portion V1 of the second upper shield pattern 24b, the shielding via portion V4 of the second lower shield pattern 14b may have a quadrilateral ring shape. The shielding via portion V4 of the second lower shield pattern 14b may include a first portion extending in the first direction D1 and a second portion VP42 extending in the second direction D2.

[0103] Similar to the shielding base portion B1 of the second upper shielding pattern 24b, the shielding base portion B4 of the second lower shielding pattern 14b may have a quadrangular ring shape. The shielding base portion B4 of the second lower shielding pattern 14b may include a first portion extending in the first direction D1 and a second portion BP42 extending in the second direction D2.

[0104] The second lower redistribution pattern 12b includes a redistribution via portion RV4 and a redistribution base portion RB4. The redistribution via portion RV4 of the second lower redistribution pattern 12b may be disposed on the redistribution base portion RB4 of the second lower redistribution pattern 12b.

[0105] The redistribution via portion RV4 of each second lower redistribution pattern 12b may be located at the same level as the shielding via portion V4 of the second lower shield pattern 14b. The redistribution base bottom RB4 of each second lower redistribution pattern 12b may be located at the same level as the shielding base bottom B4 of the second lower shield pattern 14b.

[0106] The shielding base portion B4 of the second lower shield pattern 14b may surround the redistribution base portion RB4 of the second lower redistribution pattern 12b. The shielding via portion V4 of the second lower shield pattern 14b may surround the redistribution via portion RV4 of the second lower redistribution pattern 12b.

[0107] Each of the third lower shield patterns 14c includes a shielding via portion V5 and a shielding base portion B5. The shielding via portion V5 of the third lower shield pattern 14c may be disposed on the shielding base portion B5 of the third lower shield pattern 14c.

[0108] Similar to the shielding via portion V1 of the second upper shield pattern 24b, the shielding via portion V5 of the third lower shield pattern 14c may have a quadrilateral ring shape. The shielding via portion V5 of the third lower shield pattern 14c may include a first portion extending in the first direction D1 and a second portion VP52 extending in the second direction D2.

[0109] Similar to the shielding base portion B1 of the second upper shielding pattern 24b, the shielding base portion B5 of the third lower shielding pattern 14c may have a quadrangular ring shape. The shielding base portion B5 of the third lower shielding pattern 14c may include a first portion extending in the first direction D1 and a second portion BP52 extending in the second direction D2.

[0110] Each of the third lower redistribution patterns 12c includes a redistribution via portion RV5 and a redistribution base portion RB5. The redistribution via portion RV5 of the third lower redistribution pattern 12c may be disposed on the redistribution base portion RB5 of the third lower redistribution pattern 12c.

[0111] The redistribution via portion RV5 of each third lower redistribution pattern 12c may be located at the same level as the shielding via portion V5 of the third lower shield pattern 14c. The redistribution base bottom RB5 of each third lower redistribution pattern 12c may be located at the same level as the shielding base bottom B5 of the third lower shield pattern 14c.

[0112] The shielding base portion B5 of the third lower shield pattern 14c may surround the redistribution base portion RB5 of the third lower redistribution pattern 12c. The shielding via portion V5 of the third lower shield pattern 14c may surround the redistribution via portion RV5 of the third lower redistribution pattern 12c.

[0113] The shielding via portion V3 of each first lower shield pattern 14a, the shielding via portion V4 of each second lower shield pattern 14b, and the shielding via portion V5 of each third lower shield pattern 14c may overlap with each other in the third direction D3. The second portion VP32 of the shielding via portion V3 included in the first lower shield pattern 14a, the second portion VP42 of the shielding via portion V4 included in the second lower shield pattern 14b, and the second portion VP52 of the shielding via portion V5 included in the third lower shield pattern 14c may overlap with each other in the third direction D3.

[0114] In some embodiments, the shielding passage portion V3 of the first lower shielding pattern 14a, the shielding passage portion V4 of the second lower shielding pattern 14b, and the shielding passage portion V5 of the third lower shielding pattern 14c may overlap with the shielding passage V2 of the first upper shielding pattern 24a and the shielding passage V1 of the second upper shielding pattern 24b in the third direction D3.

[0115] The second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d each include an inner portion IN surrounded by the lower shield structure 14 and an outer portion OU surrounding the lower shield structure 14. The lower shield structure 14 can separate the inner portion IN and the outer portion OU of each of the second lower dielectric layer 11b, the third lower dielectric layer 11c, and the fourth lower dielectric layer 11d from each other. The inner portion IN and the outer portion OU of the second lower dielectric layer 11b can be separated from each other by the shielding passage portion V3 of the first lower shield pattern 14a and the shielding base portion B4 of the second lower shield pattern 14b. The inner portion IN and the outer portion OU of the third lower dielectric layer 11c can be separated from each other by the shielding passage portion V4 of the second lower shield pattern 14b and the shielding base portion B5 of the third lower shield pattern 14c. The inner portion IN and the outer portion OU of the fourth lower dielectric layer 11d can be separated from each other by the shielding passage portion V5 of the third lower shield pattern 14c.

[0116] The lower shield structure 14 may have a quadrilateral ring shape. The lower shield structure 14 may include a first portion extending in the first direction D1 and a second portion extending in the second direction D2. The first portion of the lower shield structure 14 may include a first portion of the shielding path portion V3 and a first portion of the shielding base portion B3 included in the first lower shield pattern 14a, a first portion of the shielding path portion V4 and a first portion of the shielding base portion B4 included in the second lower shield pattern 14b, and a first portion of the shielding path portion V5 and a first portion of the shielding base portion B5 included in the third lower shield pattern 14c. The second portion of the lower shield structure 14 may include a second portion VP32 of the shielding path portion V3 and a second portion BP32 of the shielding base portion B3 included in the first lower shield pattern 14a, a second portion VP42 of the shielding path portion V4 and a second portion BP42 of the shielding base portion B4 included in the second lower shield pattern 14b, and a second portion VP52 of the shielding path portion V5 and a second portion BP52 of the shielding base portion B5 included in the third lower shield pattern 14c.

[0117] The first, second, and third lower redistribution patterns 12a, 12b, and 12c may be disposed between first portions of the lower shield structures 14. The first, second, and third lower redistribution patterns 12a, 12b, and 12c may be disposed between second portions of the lower shield structures 14.

[0118] In the semiconductor package according to some embodiments, the lower shield structure 14 and the upper shield structure 24 may function as crack stoppers, and thus the rigidity of the semiconductor package may be improved, thereby being protected from damage by external force.

[0119] In the semiconductor package according to some embodiments, the lower shield structure 14 and the upper shield structure 24 may block electromagnetic waves.

[0120] In the semiconductor package according to some embodiments, the warpage of the lower redistribution substrate 10 may be changed according to the size of the lower shield structure 14, and the warpage of the upper redistribution substrate 20 may be changed according to the size of the upper shield structure 24. Therefore, the size of the lower shield structure 14 and the size of the upper shield structure 24 may be adjusted to minimize the warpage of the lower redistribution substrate 10 and the warpage of the upper redistribution substrate 20.

[0121] The semiconductor package according to some embodiments includes the lower shield structure 14 and the upper shield structure 24 , and thus may improve reduction in thickness of the lower dielectric structure 11 and reduction in thickness of the upper dielectric structure 21 in processes for forming the lower dielectric structure 11 and the upper dielectric structure 21 .

[0122] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E Illustrated are cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments.

[0123] refer to Figure 2A , a first semiconductor chip 30 , a connection dielectric layer 50 , and a connection conductive structure 55 may be formed on a support substrate 90 . A first mold layer 60 may be formed to cover the first semiconductor chip 30 .

[0124] refer to Figure 2B , the support substrate 90 may be removed. The first semiconductor chip 30, the connection dielectric layer 50, the connection conductive structure 55 and the first mold layer 60 may be turned upside down.

[0125] A fourth lower dielectric layer 11d may be formed on the first semiconductor chip 30 and the connection dielectric layer 50. An opening OP may be formed in the fourth lower dielectric layer 11d. The opening OP includes a hole HO and a trench TE surrounding the hole HO.

[0126] A conductive layer CL may be formed on the fourth lower dielectric layer 11d. The conductive layer CL may fill the opening OP. The conductive layer CL may include a conductive material. For example, the conductive layer CL may include copper.

[0127] refer to Figure 2C , the conductive layer CL may be patterned. The conductive layer CL may be patterned into a third lower redistribution pattern 12c and a third lower shielding pattern 14c. The third lower redistribution pattern 12c may fill the hole HO of the opening OP. The third lower shielding pattern 14c may fill the trench TE of the opening OP.

[0128] In some embodiments, after the conductive layer CL is separated into the third lower redistribution pattern 12c and the third lower shield pattern 14c, an etching process may be performed on the third lower shield pattern 14c. In this case, the height of the third lower shield pattern 14c may be less than that of the third lower redistribution pattern 12c.

[0129] refer to Figure 2D , the first lower dielectric layer 11a, the second lower dielectric layer 11b and the third lower dielectric layer 11c, the first lower redistribution pattern 12a and the second lower redistribution pattern 12b, and the first lower shield pattern 14a and the second lower shield pattern 14b may be formed. The first lower dielectric layer 11a, the second lower dielectric layer 11b and the third lower dielectric layer 11c, the first lower redistribution pattern 12a and the second lower redistribution pattern 12b, and the first lower shield pattern 14a and the second lower shield pattern 14b may be formed by a process similar to the process for forming the fourth lower dielectric layer 11d, the third lower redistribution pattern 12c and the third lower shield pattern 14c. The bump connection pattern 13 may be formed. Thus, the lower redistribution substrate 10 may be formed.

[0130] refer to Figure 2E , the lower redistribution substrate 10 may be inverted. The first upper dielectric layer 21a, the second upper dielectric layer 21b, and the third upper dielectric layer 21c, the first upper redistribution pattern 22a and the second upper redistribution pattern 22b, and the first upper shield pattern 24a and the second upper shield pattern 24b may be formed on the connection dielectric layer 50 and the first mold layer 60. The first upper dielectric layer 21a, the second upper dielectric layer 21b, and the third upper dielectric layer 21c, the first upper redistribution pattern 22a and the second upper redistribution pattern 22b, and the first upper shield pattern 24a and the second upper shield pattern 24b may be formed by a process similar to that for forming the fourth lower dielectric layer 11d, the third lower redistribution pattern 12c, and the third lower shield pattern 14c.

[0131] refer to Figure 1A , the first and second bumps 81 and 82 , the second semiconductor chip 40 , and the second mold layer 70 may be formed.

[0132] Figure 3 FIG. 1 is a perspective view partially illustrating an upper shield structure of a semiconductor package according to some embodiments. In addition to the following discussion, Figure 3 The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0133] refer to Figure 3 , the upper shield structure 24 of the semiconductor package includes a first upper shield pattern 24 a and a second upper shield pattern 24 b located on the first upper shield pattern 24 a .

[0134] The first upper shielding pattern 24a includes a shielding base portion B2 and a plurality of shielding passage portions V120 connected to the shielding base portion B2. The shielding passage portions V120 of the first upper shielding pattern 24a may be spaced apart from each other. The shielding passage portions V120 of the first upper shielding pattern 24a may be arranged along the extension direction of the shielding base portion B2 of the first upper shielding pattern 24a. For example, the shielding base portion B2 of the first upper shielding pattern 24a may include a portion extending in the second direction D2 and another portion extending in the first direction D1. The shielding passage portion V120 connected to a portion extending along the second direction D2 may be arranged along the second direction D2, and the shielding passage portion V120 connected to another portion extending along the first direction D1 may be arranged along the first direction D1.

[0135] The second upper shield pattern 24b includes a shield base portion B1 and a plurality of shielding via portions V110 connected to the shield base portion B1. The shielding via portions V110 of the second upper shield pattern 24b may be spaced apart from each other. The shielding via portions V110 of the second upper shield pattern 24b may be arranged along an extension direction of the shield base portion B1 of the second upper shield pattern 24b.

[0136] In some embodiments, similar to the upper shielding patterns 24 a and 24 b , the lower shielding pattern may include a plurality of shielding via portions.

[0137] Figure 4 An enlarged cross-sectional view of a semiconductor package according to some embodiments is illustrated. In addition to the following discussion, Figure 4 The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0138] refer to Figure 4 , the semiconductor package includes a conductive pattern CP connecting the second upper shield pattern 24b to the second upper redistribution pattern 22b. For convenience of discussion, the second upper shield pattern 24b, the second upper redistribution pattern 22b, and the conductive pattern CP are distinguished from each other, but the second upper shield pattern 24b, the second upper redistribution pattern 22b, and the conductive pattern CP may be connected into an integrated structure without a boundary therebetween.

[0139] The conductive pattern CP may be connected to the shield base bottom B1 of the second upper shield pattern 24b and the redistribution base bottom RB1 of the second upper redistribution pattern 22b. The upper shield structure 24 may be electrically connected to a ground voltage through the conductive pattern CP, the first and second upper redistribution patterns 22a and 22b, the connecting conductive pattern 56, and the lower redistribution substrate.

[0140] Since the upper shield structure 24 is electrically connected to the ground voltage, the upper shield structure 24 may have an electromagnetic wave blocking effect.

[0141] In some embodiments, a conductive pattern connecting the first upper shielding pattern 24 a to the first upper redistribution pattern 22 a may be provided.

[0142] In some embodiments, a conductive pattern connecting the lower shielding structure to the lower redistribution pattern may be provided.

[0143] Figure 5A An enlarged cross-sectional view showing a semiconductor package according to some embodiments is illustrated. Figure 5B The diagram shows Figure 5A In addition to the following discussion, Figure 5A and Figure 5B The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0144] refer to Figure 5A and Figure 5B , the semiconductor package includes a first exposure pattern EP1 and a second exposure pattern EP2. The first exposure pattern EP1 may be connected to the shielding base portion B1 of the second upper shielding pattern 24b. For convenience, the second upper shielding pattern 24b and the first exposure pattern EP1 are discussed separately from each other, but the second upper shielding pattern 24b and the first exposure pattern EP1 may be connected as an integrated structure without a boundary therebetween.

[0145] The second exposure pattern EP2 may be connected to the shielding base portion B2 of the first upper shielding pattern 24a. For convenience, the first upper shielding pattern 24a and the second exposure pattern EP2 are discussed separately from each other, but the first upper shielding pattern 24a and the second exposure pattern EP2 may be connected as an integrated structure without a boundary therebetween.

[0146] The first exposure pattern EP1 may be exposed outward through the sidewall 21c_S of the third upper dielectric layer 21c. The second exposure pattern EP2 may be exposed outward through the sidewall 21b_S of the second upper dielectric layer 21b.

[0147] In the semiconductor package according to some embodiments, when the first exposure pattern EP1 and the second exposure pattern EP2 are included, electromagnetic waves may be discharged through the first exposure pattern EP1 and the second exposure pattern EP2 , and the upper shielding structure 24 may have an improved electromagnetic wave blocking effect.

[0148] In some embodiments, the semiconductor package may include an exposure pattern connected to a lower shield structure.

[0149] Figure 6 FIG. 1 illustrates a plan view showing a planar structure of an upper shield structure in a semiconductor package according to some embodiments. In addition to the following discussion, Figure 6 The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0150] refer to Figure 6 , in the semiconductor package, the shielding base portion B210 of the second upper shielding pattern includes a first end EPO1 and a second end EPO2 facing each other. The first end EPO1 and the second end EPO2 may be spaced apart from each other.

[0151] The first test pattern TP1 may be connected to the first end EP01, and the second test pattern TP2 may be connected to the second end EP02. The width of the first test pattern TP1 and the width of the second test pattern TP2 may be greater than the width of the shielding base portion B210 of the second upper shielding pattern. The width of the first test pattern TP1 and the second test pattern TP2 may be greater than the width of the first end EP01 and the second end EP02 of the shielding base portion B210 included in the second upper shielding pattern.

[0152] The first test pattern TP1 and the second test pattern TP2 may be formed simultaneously with the second upper shielding pattern. After forming the first test pattern TP1 and the second test pattern TP2 and the second upper shielding pattern, a test device may be connected to the first test pattern TP1 and the second test pattern TP2 to test electrical characteristics of the upper shielding structure, and the occurrence of cracks in the upper shielding structure may be determined.

[0153] Figure 7 FIG. 1 illustrates a plan view showing a planar structure of an upper shield structure in a semiconductor package according to some embodiments. In addition to the following discussion, Figure 7 The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0154] refer to Figure 7 In the semiconductor package, the shielding base portion B310 of the second upper shielding pattern includes a first portion B311 adjacent to the first side wall 21_S1 of the upper dielectric structure 21, a second portion B312 adjacent to the second side wall 21_S2 of the upper dielectric structure 21, a third portion B313 adjacent to the third side wall 21_S3 of the upper dielectric structure 21, and a fourth portion B314 adjacent to the fourth side wall 21_S4 of the upper dielectric structure 21.

[0155] The first portion B311, the second portion B312, the third portion B313, and the fourth portion B314 of the shield base portion B310 included in the second upper shield pattern each include a first pattern portion PP1 extending in the first direction D1 and a second pattern portion PP2 extending in the second direction D2. The first pattern portion PP1 and the second pattern portion PP2 may be alternately connected to each other.

[0156] Similar to the shielding base portion B310 of the second upper shielding pattern, the shielding via portion of the second upper shielding pattern, the first upper shielding pattern, and the lower shielding structure may include a pattern portion.

[0157] Figure 8 FIG. 1 illustrates a plan view showing a planar structure of an upper shield structure in a semiconductor package according to some embodiments. In addition to the following discussion, Figure 8 The semiconductor package can be similar to Figure 7 semiconductor packages.

[0158] refer to Figure 8 In the semiconductor package, the shielding base portion B410 of the second upper shielding pattern includes a first portion B411 adjacent to the first side wall 21_S1 of the upper dielectric structure 21, a second portion B412 adjacent to the second side wall 21_S2 of the upper dielectric structure 21, a third portion B413 adjacent to the third side wall 21_S3 of the upper dielectric structure 21, and a fourth portion B414 adjacent to the fourth side wall 21_S4 of the upper dielectric structure 21.

[0159] Each of the first portion B411, the second portion B412, the third portion B413, and the fourth portion B414 of the shield base portion B410 included in the second upper shield pattern may have a zigzag shape.

[0160] The first part B411, the second part B412, the third part B413 and the fourth part B414 of the shielding base part B410 included in the second upper shielding pattern each include a first pattern part PP11 extending in the fourth direction D4 and a second pattern part PP22 extending in the fifth direction D5. The first pattern part PP11 and the second pattern part PP21 may be connected to each other alternately. The fourth direction D4 may intersect with the first direction D1, the second direction D2 and the third direction D3. For example, the fourth direction D4 may be a horizontal direction perpendicular to the third direction D3. The fifth direction D5 may intersect with the first direction D1, the second direction D2, the third direction D3 and the fourth direction D4. For example, the fifth direction D5 may be a horizontal direction perpendicular to the third direction D3.

[0161] Similar to the shielding base portion B410 of the second upper shield pattern, the shielding via portion of the second upper shield pattern, the first upper shield pattern, and the lower shield structure may have a zigzag shape.

[0162] Fig.9A Illustrated is a cross-sectional view showing a semiconductor package according to some embodiments. Fig. 9B The diagram shows Fig.9A In addition to the following discussion, Fig.9A and Fig. 9B The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0163] refer to Fig.9A and Fig. 9B The upper shield structure 524 includes a first upper shield pattern 524a, a second upper shield pattern 524b located on the first upper shield pattern 524a, and an upper dam pattern 524c located on the second upper shield pattern 524b.

[0164] The upper dam pattern 524c may include the same material as the first upper shield pattern 524a and the second upper shield pattern 524b. For example, the upper dam pattern 524c may include copper.

[0165] An underfill layer 590 may be disposed between the second semiconductor chip 40 and the upper redistribution substrate 20. The underfill layer 590 may include a dielectric material.

[0166] When in Fig. 9B The upper dam pattern 524c may have a quadrangular ring shape when viewed in the plan view shown. The upper dam pattern 524c may surround the underfill layer 590 and the second bump 82. The upper dam pattern 524c may serve as a dam to prevent the material of the underfill layer 590 from being discharged outward in a process for forming the underfill layer 590.

[0167] The upper dam pattern 524c may penetrate the top surface of the third upper dielectric layer 21c of the upper redistribution substrate 20. An upper portion of the upper dam pattern 524c may be covered by the second mold layer 70. An upper portion of the upper dam pattern 524c may be disposed in the second mold layer 70. A lower portion of the upper dam pattern 524c may be disposed in the third upper dielectric layer 21c of the upper dielectric structure 21.

[0168] The lower shield structure 514 includes a lower dam pattern 514d, a first lower shield pattern 514a on the lower dam pattern 514d, a second lower shield pattern 514b on the first lower shield pattern 514a, and a third lower shield pattern 514c on the second lower shield pattern 514b.

[0169] The lower dam pattern 514d may include the same material as the first lower shield pattern 514a, the second lower shield pattern 514b, and the third lower shield pattern 514c. For example, the lower dam pattern 514d may include copper.

[0170] The lower dam pattern 514d may have a quadrangular ring shape when viewed in a plan view. The lower dam pattern 514d may surround the bump connection pattern 13 and the first bump 81. The lower dam pattern 514d may function as a dam to prevent a material included in the underfill layer from being discharged outward in a process for forming the underfill layer.

[0171] The lower dam pattern 514d may penetrate the bottom surface of the first lower dielectric layer 11a of the lower redistribution substrate 10. An upper portion of the lower dam pattern 514d may be disposed in the first lower dielectric layer 11a of the lower dielectric structure 11.

[0172] Fig.10 The diagram illustrates a cross-sectional view of a semiconductor package according to some embodiments. In addition to the following discussion, Fig.10 The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0173] refer to Fig.10 , the connection dielectric layer 650 may be in contact with the top surface of the lower redistribution substrate 10 and the bottom surface of the upper redistribution substrate 20. The connection dielectric layer 650 may be in contact with the top surface and the sidewall of the first semiconductor chip 30. In some embodiments, the width of the connection dielectric layer 650 in the first direction D1 may be the same as the width of the lower redistribution substrate 10 in the first direction D1 and the width of the upper redistribution substrate 20 in the first direction D1.

[0174] In some embodiments, the connection dielectric layer 650 may include the same dielectric material as that of the second mold layer 70. For example, the connection dielectric layer 650 may include epoxy resin.

[0175] The connecting conductive structure 655 may have a pillar shape extending in the third direction D3 and penetrating the connecting dielectric layer 650. The connecting conductive structure 655 may contact the third lower redistribution pattern 12c and the first upper redistribution pattern 22a. The connecting conductive structure 655 may include a conductive material. For example, the connecting conductive structure 655 may include copper.

[0176] Fig.11 The diagram illustrates a cross-sectional view of a semiconductor package according to some embodiments. In addition to the following discussion, Fig.11 The semiconductor package can be similar to Figures 1A to 1G semiconductor packages.

[0177] refer to Fig.11 , the lower redistribution substrate 10 includes a pad pattern 715 on the bump connection pattern 13. The first lower redistribution pattern 712a may be disposed on the pad pattern 715. The pad pattern 715 may include a conductive material.

[0178] The first lower redistribution pattern 712a, the second lower redistribution pattern 712b, and the third lower redistribution pattern 712c may each include a redistribution path portion and a redistribution base portion located on the redistribution path portion. The first lower shielding pattern 714a, the second lower shielding pattern 714b, and the third lower shielding pattern 714c may each include a shielding path portion and a shielding base portion located on the shielding path portion.

[0179] A third bump 783 connecting the first pad 31 of the first semiconductor chip 30 to the third lower redistribution pattern 712c may be provided. The third bump 783 may include a conductive material.

[0180] After forming the lower redistribution substrate 10 , the first semiconductor chip 30 may be mounted on the lower redistribution substrate 10 .

[0181] Fig.12 The diagram illustrates a cross-sectional view of a semiconductor package according to some embodiments. In addition to the following discussion, Fig.12 The semiconductor package can be similar to Figures 1A to 1G Semiconductor packages or Fig.11 semiconductor packages.

[0182] refer to Fig.12 , the first semiconductor chip 30 includes a through via 833 located on the first pad 31 and a second pad 834 located on the through via 833. The through via 833 and the second pad 834 may include a conductive material.

[0183] The second semiconductor chip 840 may be mounted on the first semiconductor chip 30. The second semiconductor chip 840 includes a third pad 841. The third pad 841 may include a conductive material. The width of the second semiconductor chip 840 in the first direction D1 may be smaller than the width of the lower redistribution substrate 10 in the first direction D1.

[0184] A second bump 883 connecting the first pad 31 to the third lower redistribution pattern 712c may be provided. A third bump 884 connected to the third pad 841 may be provided. The second bump 883 and the third bump 884 may include a conductive material.

[0185] A connection via 855 connecting the third lower redistribution pattern 712c to the third bump 884 may be provided. The connection via 855 may include a conductive material. The second semiconductor chip 840 may be electrically connected to the lower redistribution substrate 10 through the third bump 884 and the connection via 855.

[0186] A mold layer 860 surrounding the first semiconductor chip 30 and the second semiconductor chip 840 may be provided. The mold layer 860 may include a dielectric material. The mold layer 860 may contact a sidewall of the second semiconductor chip 840.

[0187] Fig.13 The diagram illustrates a cross-sectional view of a semiconductor package according to some embodiments. In addition to the following discussion, Fig.13 The semiconductor package can be similar to Fig.12 semiconductor packages.

[0188] refer to Fig.13 , the width of the second semiconductor chip 940 in the first direction D1 may be the same as the width of the lower redistribution substrate 10 in the first direction D1. The mold layer 960 may be interposed between the second semiconductor chip 940 and the lower redistribution substrate 10. The lower redistribution substrate 10, the mold layer 960, and the second semiconductor chip 940 may have coplanar sidewalls.

[0189] In a semiconductor package according to some embodiments, a shielding structure may be included to improve rigidity of the semiconductor package and protect the semiconductor package from being damaged by external force.

[0190] In a semiconductor package according to some embodiments, a shielding structure may be included to block electromagnetic waves.

[0191] In a semiconductor package according to some embodiments, a size of a shielding structure may be adjusted to minimize warping of a redistribution substrate.

[0192] Although the present disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope that can be claimed. Certain features described in the present disclosure in the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even if initially recorded in the claims, in some cases, one or more features from the combination may be removed from the combination, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0193] Although the present invention has been described in conjunction with some embodiments shown in the accompanying drawings, it will be appreciated by those skilled in the art that changes can be made in form and detail without departing from the spirit and essential features of the present disclosure. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: a lower redistribution substrate; upper redistribution substrate; as well as a semiconductor chip, wherein the semiconductor chip is located between the lower redistribution substrate and the upper redistribution substrate, Wherein, the lower redistribution substrate comprises: Lower dielectric structure; a lower redistribution pattern surrounded by the lower dielectric structure; and a lower shielding structure surrounded by the lower dielectric structure and surrounding the lower redistribution pattern, and Wherein, the upper redistribution substrate comprises: upper dielectric structure; an upper redistribution pattern, the upper redistribution pattern being surrounded by the upper dielectric structure; and An upper shielding structure is surrounded by the upper dielectric structure and surrounds the upper redistribution pattern.

2. The semiconductor package according to claim 1, wherein: The upper shielding structure includes a first upper shielding pattern and a second upper shielding pattern located on the first upper shielding pattern, The first upper shielding pattern includes a first shielding via portion and a first shielding base portion, the first shielding base portion has a width greater than a width of the first shielding via portion, The second upper shield pattern includes a second shield via portion and a second shield base portion, the second shield base portion has a width greater than a width of the second shield via portion, and The first shielding via portion and the second shielding via portion overlap each other.

3. The semiconductor package according to claim 2, wherein: The second shielding path portion comprises: a plurality of first portions extending in a first direction; and a plurality of second portions extending in a second direction intersecting the first direction, The upper redistribution pattern includes a redistribution path portion and a redistribution base portion, and the width of the redistribution base portion is greater than the width of the redistribution path portion. wherein the redistribution path portion is located between two first portions of the plurality of first portions of the second shielding path portion, and Wherein, the redistribution path portion is located between two second portions of the plurality of second portions of the second shielding path portion.

4. The semiconductor package according to claim 2, wherein: The width of the first shielding via portion decreases as the distance from the lower redistribution substrate decreases, and the width of the second shielding via portion decreases as the distance from the lower redistribution substrate decreases.

5. The semiconductor package according to claim 2, wherein: The width of the first shielding via portion and the width of the second shielding via portion are in the range of 10 μm to 50 μm, and A width of the first shield base portion and a width of the second shield base portion are in a range of 20 μm to 100 μm.

6. The semiconductor package according to claim 1, wherein: The upper shielding structure comprises: a plurality of first portions extending in a first direction; and a plurality of second portions extending in a second direction intersecting the first direction, Wherein, a length of each of the plurality of first portions of the upper shielding structure in the first direction is greater than a length of the semiconductor chip in the first direction.

7. The semiconductor package according to claim 1, in, The upper redistribution substrate further includes a conductive pattern electrically connecting the upper shield structure to the upper redistribution pattern, and The upper shielding structure is electrically connected to a ground voltage through the conductive pattern and the upper redistribution pattern.

8. The semiconductor package according to claim 1, wherein: The upper shield structure further includes an exposure pattern that exposes a sidewall of the upper dielectric structure.

9. The semiconductor package according to claim 1, in, The upper shielding structure further includes an upper dam pattern that penetrates a top surface of the upper dielectric structure, and The lower shielding structure further includes a lower dam pattern, and the lower dam pattern penetrates the bottom surface of the lower dielectric structure.

10. A semiconductor package, comprising: a lower redistribution substrate; as well as a semiconductor chip mounted on the lower redistribution substrate, Wherein, the lower redistribution substrate comprises: Lower dielectric structure; a first lower redistribution pattern, the first lower redistribution pattern being surrounded by the lower dielectric structure; a second lower redistribution pattern, the second lower redistribution pattern being located on the first lower redistribution pattern; and a lower shielding structure surrounded by the lower dielectric structure and surrounding the first lower redistribution pattern and the second lower redistribution pattern, The lower shielding structure includes a first lower shielding pattern and a second lower shielding pattern located on the first lower shielding pattern. wherein the first lower shielding pattern is located at the same level as the first lower redistribution pattern, and Wherein, the second lower shielding pattern is located at the same level as that of the second lower redistribution pattern.

11. The semiconductor package according to claim 10, wherein: The first lower shield pattern includes a first shield base portion and a first shield via portion, the first shield via portion has a width smaller than a width of the first shield base portion, The first lower redistribution pattern includes a first redistribution base portion and a first redistribution path portion, the width of the first redistribution path portion is smaller than the width of the first redistribution base portion, A top surface of the first shielding via portion is located at the same level as a top surface of the first redistribution via portion, and A bottom surface of the first shielding substrate portion is located at the same level as a bottom surface of the first redistribution substrate portion.

12. The semiconductor package according to claim 11, wherein The lower dielectric structure includes a first lower dielectric layer and a second lower dielectric layer located on the first lower dielectric layer, and A top surface of the first shielding substrate portion and a top surface of the first redistribution substrate portion are in contact with a bottom surface of the second lower dielectric layer.

13. The semiconductor package according to claim 12, wherein: The second lower dielectric layer comprises: an inner portion surrounded by the lower shield structure; and An outer portion surrounds the lower shield structure.

14. The semiconductor package according to claim 10, wherein: The first lower shield pattern includes a first shield base portion and a plurality of first shield via portions connected to the first shield base portion, Wherein, the plurality of first shielding path portions are spaced apart from each other.

15. The semiconductor package according to claim 14, wherein: The plurality of first shield via portions are arranged along an extending direction of the first shield base portion.

16. The semiconductor package according to claim 10, further comprising: a connection dielectric layer, the connection dielectric layer being located on the lower redistribution substrate; a connecting conductive structure, the connecting conductive structure being located in the connecting dielectric layer; as well as an upper redistribution substrate, the upper redistribution substrate being located on the connection dielectric layer, Wherein, the distance between the lower shielding structure and the semiconductor chip is greater than the distance between the connecting conductive structure and the semiconductor chip.

17. The semiconductor package according to claim 16, wherein: The upper redistribution substrate comprises: upper dielectric structure; an upper redistribution pattern, the upper redistribution pattern being surrounded by the upper dielectric structure; and an upper shielding structure surrounded by the upper dielectric structure and surrounding the upper redistribution pattern, Wherein, the first lower shielding pattern, the second lower shielding pattern and the upper shielding structure overlap each other.

18. The semiconductor package according to claim 10, wherein: A distance between an outer sidewall of the lower dielectric structure and the first lower shielding pattern is smaller than a distance between an outer sidewall of the lower dielectric structure and the first lower redistribution pattern.

19. A semiconductor package, comprising: a lower redistribution substrate; a first semiconductor chip mounted on the lower redistribution substrate; a connecting dielectric layer, the connecting dielectric layer surrounding the first semiconductor chip; a connecting conductive structure, the connecting conductive structure being located in the connecting dielectric layer; an upper redistribution substrate, the upper redistribution substrate being located on the connection dielectric layer; a second semiconductor chip mounted on the upper redistribution substrate, Wherein, the lower redistribution substrate comprises: Lower dielectric structure; a lower redistribution pattern surrounded by a lower dielectric structure; and a lower shielding structure surrounded by the lower dielectric structure and surrounding the lower redistribution pattern, Wherein, the length of the lower shielding structure is greater than the length of the first semiconductor chip.

20. The semiconductor package according to claim 19, wherein The lower shielding structure comprises: a first portion extending in a first direction; and a second portion extending in a second direction intersecting the first direction, Wherein, a length of the first portion of the lower shielding structure in the first direction is greater than a length of the first semiconductor chip in the first direction.

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