Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package including a pad having high reliability and a method of manufacturing the same are provided. The semiconductor package includes a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a through pillar extending around the semiconductor chip and on the first redistribution substrate, and a second redistribution substrate on the semiconductor chip and the through pillar. A first pad region and a second pad region are defined on an upper surface of the second redistribution substrate, the first pad region is located at a central portion of the second redistribution substrate, and the second pad region extends around the first pad region, a first-type pad of a planar shape is located in the first opening, and a second-type pad of a planar shape is located in the second opening. A second type pad having an outer protruding portion is in the second opening.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0095615 filed on July 21, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates generally to a semiconductor package, and more particularly, to a semiconductor package including a redistribution substrate respectively located on an upper portion and a lower portion of a semiconductor chip and a method of manufacturing the semiconductor package. Background Art

[0003] With the rapid development of the electronics industry and user needs, the size and weight of electronic devices are further reduced. As the size and weight of electronic devices are reduced, the semiconductor packages used therein are also reduced in size and weight, and the semiconductor packages are also required to have high reliability as well as high performance and large capacity. As these semiconductor packages become more high-performance and high-capacity, the power consumption of the semiconductor packages has also increased. Therefore, the importance of the structure of the semiconductor package corresponding to the size / performance of the semiconductor package and providing a stable power supply for the semiconductor package has increased. Summary of the invention

[0004] The inventive concept provides a semiconductor package including a pad having high reliability and a method of manufacturing the semiconductor package.

[0005] According to one aspect of the present invention, there is provided a semiconductor package, comprising: a first redistribution substrate having multiple layers of first redistribution lines, a semiconductor chip on the first redistribution substrate, a through-pillar extending around the semiconductor chip and on the first redistribution line, and a second redistribution substrate on the semiconductor chip and the through-pillar and having multiple layers of second redistribution lines. A first pad area and a second pad area are defined on an upper surface of the second redistribution substrate, a first opening exposing a portion of the second redistribution line is arranged in the first pad area, and the first pad area is located at a central portion of the second redistribution substrate, and the second pad area surrounds the first pad area (i.e., extends around the first pad area), a second opening exposing a portion of the second redistribution line is arranged in the second pad area, a first type pad with a flat shape is arranged in the first opening on the second redistribution line, and a second type pad with an outer protruding portion is arranged in the second opening on the second redistribution line.

[0006] According to another aspect of the inventive concept, there is provided a semiconductor package, comprising: a first redistribution substrate having a plurality of first redistribution lines, a semiconductor chip on the first redistribution substrate, a sealing material on the first redistribution substrate to cover the semiconductor chip, a through-pillar extending around the semiconductor chip on the first redistribution substrate in a structure penetrating the sealing material, a second redistribution substrate on the sealing material and having a plurality of second redistribution lines, and an upper package on the second redistribution substrate through an inter-substrate connection terminal. An opening exposing a portion of the second redistribution line is on an upper surface of the second redistribution substrate, and the uppermost second redistribution line exposed from the opening has a multi-metal layer structure.

[0007] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a first redistribution substrate having a plurality of first redistribution lines, a semiconductor chip on the first redistribution substrate, a through-pillar extending around the semiconductor chip and on the first redistribution line, and a second redistribution substrate on the semiconductor chip and the through-pillar and having a plurality of second redistribution lines. An opening exposing a portion of the second redistribution line is on an upper surface of the second redistribution substrate, and the uppermost second redistribution line exposed from the opening comprises a lower metal layer of copper (Cu) and an upper metal layer of nickel (Ni).

[0008] According to another aspect of the inventive concept, a method for manufacturing a semiconductor package is provided, the method comprising: forming a first redistribution substrate on a carrier substrate; forming a through-pillar on the outside of the first redistribution substrate; mounting a semiconductor chip on a central portion of the first redistribution substrate; forming a sealing material covering the through-pillar and the semiconductor chip; exposing an upper surface of the through-pillar by grinding an upper portion of the sealing material; and forming a second redistribution substrate on the through-pillar and the sealing material. Forming the second redistribution substrate comprises: forming an uppermost redistribution line having a copper (Cu) lower metal layer and a nickel (Ni) upper metal layer by electroplating; forming a main body insulating layer covering the uppermost redistribution line; forming an opening penetrating the main body insulating layer to expose a portion of the uppermost redistribution line; and forming two types of pads on the uppermost redistribution line in the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) indicate corresponding elements in the several figures, and in which:

[0010] Figure 1A and Figure 1B are respectively a plan view and a cross-sectional view each schematically showing an example structure of a semiconductor package according to an embodiment of the present disclosure;

[0011] FIG. 2A to FIG. 2C It is shown Figure 1B A cross-sectional view of an enlarged region EP of a semiconductor package;

[0012] Figure 3 It shows Figure 2A A cross-sectional view of an enlarged area A;

[0013] Figure 4 is a partial cross-sectional view of a semiconductor package of a comparative example;

[0014] FIG. 5A to FIG. 5D are cross-sectional views each schematically showing an example structure of a semiconductor package according to an embodiment of the present disclosure;

[0015] Figure 6 is shown in more detail Figure 5A A cross-sectional view of an example structure of an upper package in a semiconductor package;

[0016] 7A to 7J is a schematic diagram showing the manufacturing Figure 1B A cross-sectional view of an intermediate process in an example operation of a semiconductor package of FIG. 1 ; and

[0017] FIG. 8A to FIG. 8D is shown in more detail to manufacture Figure 7J FIG. 5 is a cross-sectional view of an intermediate process in an example operation of a second redistribution substrate. DETAILED DESCRIPTION

[0018] The inventive concept will now be described more fully with reference to the accompanying drawings in which embodiments of the inventive concept are shown. As mentioned above, like reference numerals in the drawings represent like elements, and thus their description will be omitted.

[0019] Figure 1A and Figure 1B are respectively a plan view and a cross-sectional view each schematically showing an example structure of a semiconductor package according to an embodiment of the present disclosure, and FIG. 2A to FIG. 2C It shows Figure 1B A cross-sectional view of an enlarged region EP of a semiconductor package. Figure 3 It shows Figure 2A A cross-sectional view of an enlarged area A. Figure 4 is a partial cross-sectional view of a semiconductor package according to a comparative example.

[0020] Reference Figures 1A to 2A and Figure 3 , the semiconductor package 100 according to the embodiment may include a first redistribution substrate 110, a semiconductor chip 120, a through post 130, a second redistribution substrate 140, a sealing material (ie, sealant) 150, and external connection terminals 160. The semiconductor package 100 of the present embodiment may be a wafer level package (WLP).

[0021] The first redistribution substrate 110 may be disposed on a lower portion of the semiconductor chip 120 and used to redistribute electrical connections to the chip pads 122 of the semiconductor chip 120 to an outer region of the semiconductor chip 120. Specifically, the first redistribution substrate 110 may include a first body insulating layer 101, a first redistribution line 103, a first vertical through-hole 105, and a first substrate pad 107, the first substrate pad 107 including a first lower substrate pad 107d and a first upper substrate pad 107u.

[0022] The first body insulating layer 101 may include an insulating material such as a photo-imaging dielectric (PID) resin, and may further include an inorganic filler. However, the material of the first body insulating layer 101 is not limited to PID. The first body insulating layer 101 may have a multi-layer structure according to the multi-layer structure of the first redistribution line 103. However, in Figure 1B In the figure, for convenience, the first body insulating layer 101 is shown as a single-layer structure.

[0023] The first redistribution line 103 may be configured as a multi-layer structure within the first body insulation layer 101. The first redistribution lines 103 of different layers may be connected to each other through corresponding first vertical through-holes 105. In addition, the first redistribution line 103 may be connected to the first substrate pad 107 through the first vertical through-holes 105. The first substrate pad 107 may include a first lower substrate pad 107d on a lower surface of the first body insulation layer 101 and a first upper substrate pad 107u on an upper surface of the first body insulation layer 101.

[0024] The external connection terminal 160 may be located on the lower surface of the first body insulating layer 101. The external connection terminal 160 may be located on the first lower substrate pad 107d on the lower surface of the first body insulating layer 101. The external connection terminal 160 may be electrically connected to the semiconductor chip 120 through the first redistribution line 103 of the first redistribution substrate 110 and one or more bumps 125. The term "connection" (or "contact" or similar terms) as used herein is intended to refer to the physical and / or electrical connection between two or more elements, and may include other intermediate elements. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0025] The external connection terminals 160 may be located at a central lower surface portion of the first redistribution substrate 110 and an outer lower surface portion of the first redistribution substrate 110, the central lower surface portion corresponding to the lower surface of the semiconductor chip 120, and the outer lower surface portion extending from the central lower surface portion to the outside along a first direction (x direction) and a second direction (y direction), the first direction intersecting the second direction, and the first direction and the second direction being parallel to the upper surface of the first redistribution substrate 110. As a result, the first redistribution substrate 110 may be used to redistribute the electrical connection with the bump 125 of the semiconductor chip 120 to a portion wider than the lower surface of the semiconductor chip 120 through the first redistribution line 103 and the external connection terminal 160. In this way, a package structure in which the external connection terminal 160 is located in an area wider than the lower surface of the semiconductor chip 120 is referred to as a fan-out (FO) package structure. In contrast, a package structure in which the external connection terminal 160 is arranged only at a portion corresponding to the lower surface of the semiconductor chip 120 is referred to as a fan-in (FI) package structure.

[0026] The semiconductor chip 120 may be disposed on the first redistribution substrate 110 by one or more bumps 125. The semiconductor chip 120 may be located at the center portion of the first redistribution substrate 110 in the x direction. In addition, the semiconductor chip 120 may be arranged at the center portion of the first redistribution substrate 110 in the y direction. The bump 125 may include a metal column. In some embodiments, the bump 125 may include a metal column and solder. Here, the metal column may include, for example, copper (Cu). However, the material of the metal column is not limited to Cu.

[0027] The semiconductor chip 120 may be an analog chip. The semiconductor chip 120 may include a plurality of logic elements therein. Here, the logic element is an element that performs various logic processing and may include, for example, AND, OR, NOT, triggers, etc. The logic element may also include an element for supporting communication. In the semiconductor package 100 of the present embodiment, the semiconductor chip 120 may be, for example, an application processor (AP) chip. The semiconductor chip 120 may also be referred to as a control chip, a processing chip, a central processing unit (CPU) chip, etc., according to its function. In addition, in terms of integrated functions, the semiconductor chip 120 is also referred to as a system on chip (SoC). According to an embodiment, the elements for supporting communication may be separately provided in a modem chip, or may be arranged on a first redistribution substrate 110 in a structure coupled to the semiconductor chip 120.

[0028] The semiconductor chip 120 may include a substrate and a plurality of wiring layers. An integrated circuit layer may be formed on an active surface of the substrate. The integrated circuit layer may include a plurality of logic elements. A plurality of wiring layers may be arranged on the lower surface of the substrate and include multilayer lines. In the semiconductor chip 120, the lower surface may be the front side as an active surface, and the upper surface may be the back side as a passive surface. In other words, based on the substrate (and depending on the orientation of the semiconductor chip 120 in the semiconductor package 100), the lower surface of the substrate on which the plurality of wiring layers are arranged may correspond to the front side of the semiconductor chip 120, and the upper surface of the substrate may correspond to the back side of the semiconductor chip 120. The semiconductor chip 120 may be mounted on the first redistribution substrate 110 in a flip-chip structure by a chip pad 122 and a bump 125 arranged on the front side of the semiconductor chip 120.

[0029] The through-pillar 130 may extend in the z-direction between the first redistribution substrate 110 and the second redistribution substrate 140. The sealing material 150 may be disposed between the first redistribution substrate 110 and the second redistribution substrate 140. Therefore, the through-pillar 130 may have a structure extending through the sealing material 150. The through-pillar 130 may electrically connect the first redistribution substrate 110 to the second redistribution substrate 140. For example, the through-pillar 130 may be connected to the first redistribution line 103 of the first redistribution substrate 110, and may also be connected to the second redistribution line 143 of the second redistribution substrate 140.

[0030] The through-pillar 130 may include, for example, Cu. However, the material of the through-pillar 130 is not limited to Cu. The through-pillar 130 may be formed by electroplating using a seed metal. Therefore, the seed metal may be formed on the first redistribution substrate 110, and the through-pillar 130 may be formed on the seed metal. The seed metal may include, for example, various metal materials such as Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. In the semiconductor package 100 of this embodiment, the seed metal may be included as a part of the through-pillar 130. For example, the seed metal may include Cu, and the through-pillar 130 may also include Cu. Therefore, in Figure 1B In the examples, the seed metal is not separately indicated.

[0031] The sealing material 150 may cover and seal the side surfaces and the top surface of the semiconductor chip 120. In addition, the sealing material 150 may surround the side surfaces of the through pillars 130. The term "covering" (or similar terms) as may be used herein is intended to broadly refer to an element, structure or layer being on or over another element, structure or layer, either directly or with one or more other intermediate elements, structures or layers located therebetween. The term "surrounding" (or similar terms) as may be used herein is intended to broadly refer to an element, structure or layer extending around, encapsulating, surrounding or enclosing another element, structure or layer on all sides, although breaks or gaps may also be present. Thus, for example, a layer of material having voids or gaps therein may still "surround" another layer that it surrounds. As Figure 1B As shown, the sealing material 150 may also be located between the upper surface of the semiconductor chip 120 and the lower surface of the second redistribution substrate 140. However, according to an embodiment, the sealing material 150 may not be located between the upper surface of the semiconductor chip 120 and the lower surface of the second redistribution substrate 140. That is, according to an embodiment, the upper surface of the semiconductor chip 120 may be in direct contact with the lower surface of the second redistribution substrate 140 (i.e., without an intermediate element).

[0032] like Figure 1B As shown, the sealing material 150 can fill the space between the first redistribution substrate 110 and the semiconductor chip 120 and between the bumps 125 on the lower surface of the semiconductor chip 120. However, in some embodiments, the bottom filler is filled between the bumps 125 on the lower surface of the semiconductor chip 120, and the sealing material 150 can cover the semiconductor chip 120 and the bottom filler. The term "fill" (or similar terms) that may be used herein is intended to broadly refer to completely filling a defined space (e.g., the space between the first redistribution substrate 110 and the semiconductor chip 120) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have gaps or other spaces in the entire space.

[0033] The sealing material 150 may include an insulating material, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin including a reinforcing material in the above resin. For example, the sealing material 150 may include ABF, FR-4, BT resin, etc. In addition, the sealing material 150 may include a photosensitive material such as a photo imaging encapsulant (PIE). The material of the sealing material 150 is not limited to the above materials.

[0034] The second redistribution substrate 140 may be located on the through-pillar 130 and the sealing material 150. The second redistribution substrate 140 may have a structure similar to that of the first redistribution substrate 110. For example, the second redistribution substrate 140 may include a second body insulation layer 141, a second redistribution line 143, a second vertical through hole 145, and a second substrate pad 147. The second body insulation layer 141, the second redistribution line 143, and the second vertical through hole 145 are respectively as described for the first body insulation layer 101, the first redistribution line 103, and the first vertical through hole 105 of the first redistribution substrate 110. However, the second body insulation layer 141 may be thinner than the first body insulation layer 101. Moreover, the number of layers of the second redistribution line 143 may be less than the number of layers of the first redistribution line 103. For example, in the semiconductor package 100 of the present embodiment, the first redistribution line 103 may have three or more layers, and the second redistribution line 143 may have two layers. However, the number of layers of the first redistribution lines 103 and the second redistribution lines 143 is not limited to the above values.

[0035] In the second redistribution substrate 140, the second substrate pads 147 may be located on the upper surface of the second body insulating layer 141. However, according to some embodiments, the second substrate pads 147 may also be arranged on the lower surface of the second body insulating layer 141. For example, the second substrate pads 147 may be formed on the through-pillars 130, and the second redistribution lines 143 may be connected to the second substrate pads 147 through the second vertical through-holes 145.

[0036] In the semiconductor package 100 of the embodiment, the second substrate pad 147 may include two or more types of pads. For example, the second substrate pad 147 may include a first type pad 147a and a second type pad 147b. The first type pad 147a may be located in a first pad region A in a central portion of the second redistribution substrate 140. The second type pad 147b may be located in a second pad region B in an outer portion of the second redistribution substrate 140. Figure 1A As shown, the second pad area B may surround the first pad area A. For reference, the first pad area A may be referred to as a marking pad area, which means that a mark for packaging information is formed therein. In addition, the second pad area B may be referred to as a coupling pad area, which means that it is coupled to a through column.

[0037] like Figure 2AAs shown, in the semiconductor package 100 of the present embodiment, a first opening (i.e., opening) OP1 may be formed in the first pad area A. The first opening OP1 may penetrate (i.e., at least partially extend to) the upper portion of the second body insulating layer 141 to expose a portion of the uppermost second redistribution line 143T in the second redistribution line 143. The term "exposed" (or similar terms) may be used to describe the relationship between elements and / or to relate to an intermediate process for manufacturing a semiconductor device, but may not require that a specific element in the completed device be exposed. Similarly, the term "unexposed" may be used to describe the relationship between elements and / or to relate to an intermediate process for manufacturing a semiconductor device, but may not require that a specific element be not exposed in the completed device. In addition, a second opening (i.e., opening) OP2 may be formed in the second pad area B. The second opening OP2 may penetrate the upper portion of the second body insulating layer 141 to expose a portion of the uppermost second redistribution line 143T. Typically, the size of the first opening OP1 in the first pad area A may be larger than the size of the second opening OP2 in the second pad area B.

[0038] The first type pad 147a may be located on the uppermost second redistribution line 143T in the first opening OP1. The first type pad 147a may have a plate shape, such as Figure 2A As shown. In addition, the first type pad 147a may have a size smaller than the size of the portion of the uppermost second redistribution line 143T exposed in the first opening OP1. That is, the horizontal cross-sectional area of ​​the first type pad 147a may be equal to or smaller than the horizontal cross-sectional area of ​​the exposed portion of the uppermost second redistribution line 143T. Therefore, the uppermost second redistribution line 143T may be exposed to the outside of the first type pad 147a; that is, the uppermost second redistribution line 143T may extend beyond the first type pad 147a in the x direction. Figure 3 The sizes of the first opening OP1 , the uppermost second redistribution line 143T, and the first type pad 147 a are described in more detail.

[0039] The second type pad 147b may be located on the uppermost second redistribution line 143T in the second opening OP2. The second type pad 147b may include an outer protrusion portion OP such as Figure 2A As shown. That is, the second type pad 147b may include a central pad portion CP and an outer protrusion portion OP at a central portion thereof. The central pad portion CP may contact the uppermost second redistribution line 143T. The outer protrusion portion OP may have a structure extending from the central pad portion CP to protrude on the upper surface of the second body insulating layer 141. The second type pad 147b may fill the inside of the second opening OP2. Therefore, in the second opening OP2, the uppermost second redistribution line 143T may not be exposed.

[0040] In the semiconductor package 100 of the present embodiment, the top second redistribution line 143T may have a double metal layer structure. For example, the top second redistribution line 143T may include a lower metal layer 143d and an upper metal layer 143u. In the semiconductor package 100 of the embodiment, the lower metal layer 143d may include Cu and the upper metal layer 143u may include nickel (Ni). However, the material of the upper metal layer 143u is not limited to Ni. For example, in some embodiments, the upper metal layer 143u may include Ti, TiN, etc. In addition, in some embodiments, the upper metal layer 143u may have a multilayer structure. For example, the upper metal layer 143u may include Ni / Ti, Ni / TiN, Ti / TiN, etc.

[0041] In the semiconductor package 100 of the present embodiment, since the uppermost second redistribution line 143T has a double metal layer structure, defects such as discoloration of the first pad region A and the second pad region B, peeling of the second body insulating layer 141 from the metal layer (e.g., the uppermost second redistribution line 143T), and cracks in the uppermost second redistribution line 143T can be prevented from occurring. Figure 4 Prevention of defects of the semiconductor package 100 of the embodiment is described in more detail.

[0042] The second redistribution lines 143 of the second redistribution substrate 140 may be electrically connected to the semiconductor chip 120 and / or the external connection terminals 160 through the through-pillars 130 and the first redistribution lines 103 of the first redistribution substrate 110. Figure 5A ) is located on the second redistribution substrate 140, the upper package 200 may be electrically connected to the semiconductor chip 120 and / or the external connection terminals 160 through the second redistribution substrate 140, the through-pillars 130 and the first redistribution substrate 110.

[0043] The external connection terminal 160 may be located on the first lower substrate pad 107d on the lower surface of the first redistribution substrate 110, and electrically connected to the first redistribution line 103 through the first lower substrate pad 107d. The external connection terminal 160 may connect the semiconductor package 100 to a package substrate of an external system or a main board (not explicitly shown) of an electronic device such as a mobile device, etc. The external connection terminal 160 may include a conductive material, such as at least one of solder, tin (Sn), silver (Ag), Cu, and aluminum (Al).

[0044] The upper package 200 including the memory chip (refer to Figure 5A ) can be stacked on the upper surface of the second redistribution substrate 140, and connected through the inter-substrate connection terminals 250 (refer to Figure 5A) is electrically connected to the second redistribution substrate 140. A structure of a semiconductor package in which an upper package is stacked on the second redistribution substrate 140 may correspond to a package-on-package (POP) structure. FIG. 5A to FIG. 5D The description of the semiconductor package of the POP structure is described in more detail. According to an embodiment, the heat dissipation structure 300 (see Figure 5B ) may also be stacked on the upper surface of the second redistribution substrate 140. FIG. 5B to FIG. 5D The description of the semiconductor package structure is described in more detail.

[0045] Reference Figure 3 In the semiconductor package 100 of the present embodiment, the sizes of the first opening OP1, the uppermost second redistribution line 143T, and the first type pad 147a may have the following relationship. For example, the horizontal cross-sectional area of ​​the first opening OP1 may be smaller than the horizontal cross-sectional area of ​​the uppermost second redistribution line 143T. For example, the first width W1 of the first opening OP1 in the x-direction may be smaller than the second width W2 of the uppermost second redistribution line 143T in the x-direction. Therefore, the outer portion of the uppermost second redistribution line 143T may be covered by the second body insulating layer 141. The first width W1 of the first opening OP1 may be defined as the width of the bottom surface of the first opening OP1 in the x-direction. The first width W1 of the first opening OP1 may be greater than the third width W3 of the first type pad 147a in the x-direction. Therefore, the first type pad 147a may have a non-solder mask defined (NSMD) pad structure.

[0046] For reference, the pad structure can be divided into a solder mask defined (SMD) pad structure and a NSMD pad structure. The SMD structure may refer to a structure in which the outside of the pad is covered by a solder mask or a main insulating layer. In contrast, the NSMD pad structure may refer to a structure in which the pad is separated from the solder mask or the main insulating layer and is completely exposed. In the NSMD pad structure, the redistribution line may be exposed around the pad.

[0047] In the semiconductor package 100 of the embodiment, the upper metal layer 143u of the uppermost second redistribution line 143T may have a first cross-sectional thickness D1 (along the z direction) of about 0.1 micrometers (μm) or more. The upper metal layer 143u may be used as a barrier film. When the upper metal layer 143u has a cross-sectional thickness less than about 0.1 μm, the upper metal layer 143u may not be sufficient to serve as a barrier film. In addition, in the semiconductor package 100 of the present embodiment, the first thickness D1 of the upper metal layer 143u of the uppermost second redistribution line 143T may be equal to or less than the second cross-sectional thickness D2 (in the z direction) of the lower metal layer 143d.

[0048] In the semiconductor package 100 of the present embodiment, the second substrate pads 147 are arranged on the second redistribution substrate 140, but the second substrate pads 147 may include two types of pads. Specifically, the second substrate pads 147 may include first type pads 147a arranged in the first pad region A of the second redistribution substrate 140 and second type pads 147b arranged in the second pad region B of the second redistribution substrate 140 (see FIG. 2A to FIG. 2B ). For example, the first type pad 147a may have a NSMD pad structure, and the second type pad 147b may have a SMD pad structure. In addition, the second type pad 147b may be classified as an SMD pad structure in that it is not spaced apart from the second body insulating layer 141. However, when considering that the outside of the second type pad 147b is not covered by the second body insulating layer 141, according to an embodiment, the second type pad 147b may also be classified as a NSMD pad structure.

[0049] In addition, in the semiconductor package 100 of the present embodiment, the top second redistribution line 143T of the second redistribution substrate 140 may have a double metal layer structure. For example, the top second redistribution line 143T may include a lower metal layer 143d containing Cu and an upper metal layer 143u containing Ni. In this way, since the top second redistribution line 143T of the second redistribution substrate 140 has a double metal layer structure, defects such as discoloration of the first pad area A and the second pad area B, peeling of the second main body insulating layer 141 from the metal layer (e.g., the top second redistribution line 143T), and cracks in the metal layer of the top second redistribution line 143T can be prevented. In addition, the double metal layer of the top second redistribution line 143T is formed by a one-step electroplating process, and the process conditions can be optimized. Here, the one-step electroplating process may refer to performing an electroplating process by the same equipment. That is, the double metal layer can be formed from different materials by an electroplating process using the same equipment.

[0050] Reference Figure 1A , Figure 1B and Figure 2B The semiconductor package 100a of the embodiment can be Figure 1B The difference of the semiconductor package 100 of the embodiment is that the second substrate pad 147' is located in the second redistribution substrate 140a. Specifically, in the semiconductor package 100a of the embodiment, the second substrate pad 147' may include only the first type pad 147a. Therefore, the first type pad 147a may be located in both the first pad area A and the second pad area B of the second redistribution substrate 140a.

[0051] Even in the semiconductor package 100a of the embodiment, the uppermost second redistribution line 143T exposed through the first opening OP1 and the second opening OP2 may have a double metal layer structure in each of the first pad area A and the second pad area B. For example, the uppermost second redistribution line 143T may include a lower metal layer 143d and an upper metal layer 143u. In the semiconductor package 100a of the embodiment, the lower metal layer 143d may include Cu and the upper metal layer 143u may include nickel (Ni). However, the material of the upper metal layer 143u is not limited to Ni.

[0052] Reference Figure 1A , Figure 1B and Figure 2C The semiconductor package 100b of the embodiment can be Figure 1B The semiconductor package 100 of the embodiment is different in that the uppermost second redistribution line 143T1 has a single metal layer structure. Specifically, in the semiconductor package 100b of the embodiment, the uppermost second redistribution line 143T1 may have a single metal layer structure of Cu.

[0053] In addition, in the semiconductor package 100b of the embodiment, the first type pad 147a may be arranged in the first pad region A, and the second type pad 147b may be arranged in the second pad region B. Therefore, in the first pad region A, a portion of the uppermost second redistribution line 143T1 may be exposed through the first opening OP1. In addition, in the second pad region B, the second type pad 147b may completely fill the second opening OP2, and the uppermost second redistribution line 143T1 may not be exposed.

[0054] Reference Figure 4 , in the semiconductor package Com. of the comparative example, the NSMD pad PAD may be located in both the first pad area A and the second pad area B. In addition, the topmost redistribution line RDL on which the pad PAD is arranged may have a single-layer structure. Hereinafter, in the semiconductor package Com. having a structure of the topmost redistribution line RDL and the pad PAD, defects such as peeling, cracks, and the like may occur. Specifically, since the Cu of the topmost redistribution line RDL is exposed through the opening, defects such as discoloration and peeling may occur due to oxidation of Cu. Here, peeling may refer to a phenomenon in which the main insulating layer PID falls off from a metal layer such as the pad PAD and / or the topmost redistribution line RDL. In addition, when a welding process is performed on the pad PAD, cracks may occur in the metal layer of the pad PAD and / or the topmost redistribution line RDL due to stress caused by excessive growth of intermetallic compounds (IMC).

[0055] On the contrary, Figure 1A and Figure 1BIn the semiconductor package 100 of the illustrative embodiment, since the uppermost second redistribution line 143T includes an upper metal layer 143u of Ni and a lower metal layer 143d of Cu, and the types of pads in the first pad area A and the second pad area B are doubled, the above-mentioned problems can be solved. For example, in the first pad area A, the first type pad 147a can be formed in a flat shape on the upper metal layer 143u of Ni, and merged with the uppermost second redistribution line 143T through the upper metal layer 143u. Therefore, the defects of discoloration and peeling (De-La) caused by oxidation of Cu can be solved. In addition, since the types of pads in the first pad area A and the second pad area B can be doubled and arranged, in the case of the first pad area A, the peeling defect can be improved and the amount of the second main insulating layer 141 can be minimized. In addition, in the case of the second pad area B, since the second type pad 147b is located on the upper metal layer 143u of Ni and has a structure including the outer protrusion portion OP, excessive growth of ICM may be suppressed during the welding process. Therefore, crack defects in the metal layer such as the second redistribution line 143 can be prevented.

[0056] FIG. 5A to FIG. 5D are cross-sectional views each schematically showing at least a portion of an example structure of a semiconductor package according to an embodiment. Figures 1A to 4 Description given.

[0057] Reference Figure 5A , the semiconductor package 1000 of the embodiment may be different from the semiconductor package 100 of FIG. 1 in that it further includes an upper package 200. Specifically, the semiconductor package 1000 of the embodiment may include a lower package 100 and an upper package 200. The lower package 100 may be different from the semiconductor package 100 of FIG. 1. Figure 1B However, the lower package 100 is not limited to Figure 1B For example, the lower package 100 may also be Figure 2B The semiconductor package 100a or Figure 2C Semiconductor package 100b.

[0058] The upper package 200 may have a structure including, for example, a package substrate, an upper semiconductor chip, an upper sealing material, etc. The package substrate may include, for example, a ceramic substrate, a printed circuit board (PCB), an organic substrate, an interposer substrate, etc. In the semiconductor package 1000 of the present embodiment, the package substrate may be a PCB. Inter-substrate connection terminals 250 such as bumps or solder balls may be located on the lower surface of the package substrate. The upper package 200 may be mounted on the second redistribution substrate 140 through the inter-substrate connection terminals 250.

[0059] The upper semiconductor chip may be a memory chip, but the embodiment is not limited thereto. For example, the upper semiconductor chip may include a volatile memory element such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a nonvolatile memory element such as a flash memory.

[0060] The upper package 200 may have a structure in which one upper semiconductor chip is mounted on a package substrate or may have a structure in which a plurality of upper semiconductor chips are stacked on a package substrate. The plurality of upper semiconductor chips may be mounted on the package substrate by an adhesive layer and bonding wires, or may be mounted on the package substrate by using bumps and through silicon vias (TSVs). For example, in the semiconductor package 1000, the upper package 200 may be a high bandwidth memory (HBM) package. Figure 6 The description of FIG. 1 describes the HBM package in more detail. According to an embodiment, a single chip may be stacked on the second redistribution substrate 140 instead of the upper package 200 .

[0061] The upper sealing material can protect the upper semiconductor chip from external physical or chemical damage by sealing the upper semiconductor chip. The upper sealing material may include an insulating material, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin including a reinforcing material in the above resin. For example, the upper sealing material may include an Ajinomoto accumulation film ( Ajinomoto Fine-Techno Co., Ltd. (registered trademark), FR-4 (epoxy resin), bismaleimide triazine (BT) resin, etc. However, the material of the upper sealing material is not limited to the above-mentioned materials.

[0062] Reference Figure 5B The semiconductor package 1000a of the embodiment can be Figure 5A The difference of the semiconductor package 1000 is that the heat dissipation structure 300 is also stacked on the upper surface of the semiconductor chip 120. Specifically, in the lower package 100c of the semiconductor package 1000a of the present embodiment, the semiconductor chip 120 may be located on the first redistribution substrate 110, but may be arranged to be offset to the right in the x-direction. In addition, the upper surface of the semiconductor chip 120 may be exposed from the sealing material 150.

[0063] The second redistribution substrate 140b may cover the through pillars 130 and the sealing material 150, and may cover a portion of the upper surface of the semiconductor chip 120. In other words, on the upper surface of the semiconductor chip 120, the second redistribution substrate 140b and the heat dissipation structure 300 may be arranged laterally adjacent to each other with a certain spacing therebetween in the x-direction. The upper package 200 may be stacked on the second redistribution substrate 140b. The upper package 200 may be as shown in FIG. Figure 5A The semiconductor package 1000 is described in the description.

[0064] The heat dissipation structure 300 may be stacked on the semiconductor chip 120 by an adhesive layer 320 (e.g., conductive epoxy) or an alternative attachment means. The heat dissipation structure 300 may be, for example, a heat sink or a heat sink. In order to effectively transfer heat from the semiconductor chip 120 to the heat dissipation structure 300, the adhesive layer 320 may include a material with high thermal conductivity. For example, the adhesive layer 320 may include a thermal interface material (TIM), a thermally conductive resin, a thermally conductive polymer, silicon oxide or silicon nitride (e.g., SiO 2 or SiCN), etc. Here, the TIM may include materials with high thermal conductivity, i.e., grease, tape, elastomer filling pad, phase change material, etc., which are materials with low thermal resistance. In the semiconductor package 1000a of the present embodiment, since the upper surface of the semiconductor chip 120 is exposed and the heat dissipation structure 300 is directly stacked on the semiconductor chip 120 through the adhesive layer 320, the heat dissipation efficiency of the semiconductor chip 120 can be greatly improved.

[0065] Reference Figure 5C The semiconductor package 1000b of the embodiment can be Figure 5B The semiconductor package 1000a of the present embodiment is different in that the heat dissipation structure 300 can be stacked on at least a portion of the upper surface of the semiconductor chip 120 along the z direction, and the two upper packages 200-1 and 200-2 can be stacked on the upper surface of the second redistribution substrate 140c. Specifically, in the lower package 100d of the semiconductor package 1000b of the present embodiment, the second redistribution substrate 140c can be divided into two parts, and the upper packages 200-1 and 200-2 can be stacked on the corresponding parts of the second redistribution substrate 140c.

[0066] The heat dissipation structure 300 may be arranged between the two upper packages 200-1 and 200-2 along the x direction. In addition, the heat dissipation structure 300 may be directly stacked on the upper surface of the semiconductor chip 120 through the adhesive layer 320. The heat dissipation structure 300 and the adhesive layer 320 are as shown in FIG. Figure 5B The semiconductor package 1000a is described as described above.

[0067] According to an embodiment, when viewed in a plan view, the second redistribution substrate 140c may have a rectangular ring shape with only a central portion removed. In the structure of the second redistribution substrate 140c, four upper packages may be arranged on each side of the rectangular ring shape.

[0068] Reference Figure 5D The semiconductor package 1000c of the embodiment can be used with Figure 5CThe semiconductor package 1000b is different in that it also includes a passive component 170. In particular, in the lower package 100e of the semiconductor package 1000c of the present embodiment, the passive component 170 may be located on the lower surface of the first redistribution substrate 110. According to some embodiments, the passive component 170 may be alternatively or additionally arranged on the upper surface of the first redistribution substrate 110 and / or inside the first redistribution substrate 110. In addition, the passive component 170 may be located on the lower surface, on the upper surface and / or inside the second redistribution substrate 140c. The passive component 170 may include a two-terminal component, such as a resistor, an inductor, or a capacitor. In the semiconductor package 1000c of the present embodiment, the passive component 170 may include a multilayer ceramic capacitor (MLCC) 172 and a silicon capacitor 174.

[0069] Figure 6 is shown in more detail Figure 5A FIG. 1 is a cross-sectional view of the structure of the upper package in the semiconductor package 1000, and for the sake of convenience, the second redistribution substrate 140 is schematically shown. Figure 5A Describe and briefly give or omit references FIG. 1A to FIG. 5D Description given.

[0070] Reference Figure 6 , as mentioned above, in Figure 5A In the semiconductor package 1000, the upper package 200 may be an HBM package. More specifically, the upper package 200 may include a base chip 210 and a plurality of core chips 220-1, 220-2, 220-3, and 220-4 (collectively referred to as 220) on the base chip 210. In addition, the base chip 210 and the plurality of core chips 220 may include a through electrode 230. The uppermost core chip 220-4 among the plurality of core chips 220 may not include the through electrode 230.

[0071] The base chip 210 may include logic elements, but the embodiment is not limited thereto. Therefore, the base chip 210 may be a logic chip. The base chip 210 may be located below the multiple core chips 220 to integrate signals from the multiple core chips 220 and send the integrated signals to the outside, and may also send signals and power from the outside to the multiple core chips 220. Therefore, the base chip 210 may be referred to as a buffer chip or a control chip. Each of the multiple core chips 220 may be a memory chip. For example, each of the multiple core chips 220 may be a DRAM chip. The core chips may be stacked on the base chip 210 or on the core chip 220 below it by pad-to-pad bonding, hybrid bonding, bonding using a bonding member, bonding using anisotropic conductive film (ACF), and the like. In Figure 6In FIG. 2 , four core chips 220 - 1 to 220 - 4 are stacked, but the number of core chips 220 is not limited to four. For example, three or less or five or more core chips 220 may be stacked.

[0072] The inter-substrate connection terminal 250 may be located on the lower surface of the base chip 210. The inter-substrate connection terminal 250 may include, for example, a column and a solder, or may include only a solder (e.g., a solder bump). The inter-substrate connection terminal 250 may be connected to the through-electrode 230. The upper package 200 may be disposed on the second redistribution substrate 140 via the inter-substrate connection terminal 250. The core chip 220 on the base chip 210 may be sealed by an upper sealing material (e.g., a sealant) 240. However, the uppermost core chip 220-4 among the plurality of core chips 220 may not be covered by the upper sealing material 240. However, in other embodiments, the upper surface of the uppermost core chip 220-4 may also be covered by the upper sealing material 240.

[0073] 7A to 7J is a schematic diagram showing the manufacturing Figure 1B FIG. 1 is a cross-sectional view of an intermediate process in an exemplary operation of the semiconductor package 100. Figure 1B Describe and briefly give or omit references Figures 1A to 6 Description given.

[0074] Reference Fig. 7A In the method of manufacturing the semiconductor package 100 of the embodiment, first, a first redistribution substrate 110 is formed. The first redistribution substrate 110 may include a first body insulating layer 101, a first redistribution line 103, a first vertical through hole 105, and a first substrate pad 107, as described above (see Figure 1B ). The first redistribution substrate 110 may be located on the carrier substrate 2000. The carrier substrate 2000 may be a large-sized substrate, such as a wafer. In addition, a large redistribution substrate including a plurality of first redistribution substrates 110 may be formed on the carrier substrate 2000. After subsequent components are formed on the large redistribution substrate, the semiconductor package individualized (i.e., cut) by a sawing process is referred to as WLP (wafer level packaging). However, for ease of description, the following Fig. 7A and FIG. 7B to FIG. 7J Only one first redistribution substrate 110 and its corresponding components are shown.

[0075] Thereafter, a seed metal 132 is formed on the first redistribution substrate 110. The seed metal 132 may be used in a subsequent electroplating process to form the through-pillar 130. The seed metal 132 may include one or more of various metal materials, such as Cu, Ti, Ta, TiN, TaN, etc. In the method of manufacturing a semiconductor package of an embodiment, the seed metal 132 may include Cu.

[0076] Reference Figure 7B , a photoresist (PR) 1500 is coated on the seed metal 132 of the first redistribution substrate 110. For example, the PR 1500 may be coated by a spin coating method using a spin coater. The PR 1500 may be formed to have a uniform thickness with the through pillar 130 ( Figure 1B ) corresponds to the cross-sectional thickness (along the z direction).

[0077] Reference Figure 7C After coating PR1500 on the seed metal 132 of the first redistribution substrate 110, an exposure process is performed. The exposure process may be performed by using a mask including a specific pattern. For example, light may pass through a transparent portion of a transparent mask, and the light may be irradiated on a specific portion of PR1500. The chemical properties of the portion of PR1500 irradiated with light may be changed. For example, after the exposure process, PR1500a may be divided into an unexposed portion 1510 and an exposed portion 1520. Figure 7C As can be seen in FIG. 1 , the exposure portion 1520 may be located outside (ie, at the periphery) of the first redistribution substrate 110 .

[0078] Reference Fig.7D , after the exposure process, a development process is performed on PR1500a. In the development process, for example, the exposed portion 1520 may be removed. For example, PR1500a may be a positive PR. According to an embodiment, a negative PR may also be used, and when a negative PR is used, an unexposed portion of PR1500a may be removed.

[0079] When the exposed portion 1520 is removed by the development process, a PR pattern 1500b may be formed on the seed metal 132. The PR pattern 1500b may include a plurality of through holes H. The seed metal 132 may be exposed from the bottom surface of the plurality of through holes H. After the development process, byproducts such as PR scum may remain in the plurality of through holes H. Therefore, the byproducts are removed by a cleaning process. For reference, a process of removing PR scum is referred to as a PR descum process. The PR descum process may be included in the cleaning process.

[0080] Reference Fig. 7EAfter a cleaning process, through-pillars 130a are formed inside the plurality of through-holes H by electroplating. The through-pillars 130a may include, for example, Cu. Although not shown in the drawings, the through-pillars 130a may also be formed on a portion of the upper surface of the PR pattern 1500b adjacent to the through-holes H.

[0081] Reference Figure 7F After forming the through pillar 130a, the PR pattern 1500b is removed (see Fig. 7E ). The PR pattern 1500b may be removed by an ashing / stripping process. After removing the PR pattern 1500b, the seed metal 132 may be exposed between the through-pillars 130a. Subsequently, the seed metal 132 exposed between the through-pillars 130a is removed by an etching process. By removing the exposed seed metal 132, the upper surface of the first redistribution substrate 110 may be exposed between the through-pillars 130a. The seed metal 132 on the lower surface of the through-pillar 130a may remain as the seed metal 132. The seed metal 132 and the through-pillar 130a may include the same Cu. Therefore, the seed metal 132 and the through-pillar 130a are collectively referred to as the through-pillar 130, and the following Figure 7G to Figure 7J The seed metal 132 is omitted.

[0082] Reference Figure 7G , Figure 1B The semiconductor chip 120 is disposed on the first redistribution substrate 110. The semiconductor chip 120 may be attached to the first redistribution substrate 110 in a flip chip structure by using bumps 125. The bumps 125 may contact corresponding pads 122 on the front surface of the semiconductor chip 120 turned upside down. According to an embodiment, an underfill may fill the space between the first redistribution substrate 110 and the semiconductor chip 120 and between the bumps 125.

[0083] Reference Figure 7H After the semiconductor chip 120 is disposed on the first redistribution substrate 110, a sealing material 150a (i.e., a sealant) covering the semiconductor chip 120 and the through-pillar 130 is formed on the first redistribution substrate 110. The sealing material 150a may cover the side surface and the upper surface of the semiconductor chip 120 and the side surface and the upper surface of the through-pillar 130. The material of the sealing material 150a is as shown in FIG. Figure 1B The sealing material 150 of the semiconductor package 100 is as described above.

[0084] Reference Fig.7I, a planarization process is performed to remove the upper portion of the sealing material 150a. The planarization process may be performed by grinding and / or a chemical mechanical polishing (CMP) process. By the planarization process performed on the sealing material 150a, the upper surface of the through-pillar 130 may be exposed through the sealing material 150. After the planarization process is performed on the sealing material 150a, the upper surface of the through-pillar 130 and the upper surface of the sealing material 150 may be substantially coplanar in the z direction. Fig.7I As shown, the sealing material 150 having a certain thickness in the z-direction may remain on the upper portion of the semiconductor chip 120 .

[0085] Reference Figure 7J After the planarization process, a second redistribution substrate 140 is formed on the through-pillars 130 and the sealing material 150. The second redistribution substrate 140 may include a second body insulating layer 141, a second redistribution line 143, a second vertical through hole 145, and a second substrate pad 147 (see Figure 1B ). The second redistribution line 143 of the second redistribution substrate 140 may be connected to the through-pillar 130. In addition, the second redistribution substrate 140 is as shown in FIG. Figure 1B The second redistribution substrate 140 of the semiconductor package 100 is as described above.

[0086] Thereafter, the carrier substrate 2000 is separated from the first redistribution substrate 110, and the external connection terminals 160 are arranged on the lower surface of the first redistribution substrate 110, as shown in FIG. Figure 1B shown. Figure 1B The semiconductor package 100 can be supplemented by the arrangement of the external connection terminals 160. As described above, because 7A to 7J The process is formed at the wafer level, so Figure 1B The semiconductor package 100 may be substantially completed by a dicing process of separating the semiconductor package into individual semiconductor packages.

[0087] FIG. 8A to FIG. 8D is shown in more detail to manufacture Figure 7J A cross-sectional view of an intermediate process in an exemplary method of a second redistribution substrate 140, which may correspond to Figure 2A Refer to the cross-sectional view of Figure 2A Describe and briefly give or omit references Figures 1A to 7J Description given.

[0088] Reference Fig. 8AThe process of forming the second redistribution substrate 140 includes coating a seed metal and coating a second body insulating layer 141 of the PID on the seed metal. Thereafter, after the second body insulating layer 141 is patterned by an exposure process, the second redistribution line 143 and / or the second vertical through hole 145 may be formed by an electroplating process. Such a process may also be performed on each layer. Fig. 8A A state in which a seed metal 143 s is formed on the second body insulating layer 141 and the second vertical via 145 after forming the lower-layer second redistribution line 143 and the second vertical via 145 is shown.

[0089] Reference Figure 8B , the second main body insulating layer 141 of the PID is coated on the seed metal 143s, and the second main body insulating layer 141 is patterned by an optical process to expose the seed metal 143s. Subsequently, an electroplating process is performed on the seed metal 143s to form the uppermost second redistribution line 143T on the second vertical through hole 145. Thereafter, the second main body insulating layer 141 is removed to expose the seed metal 143s. Subsequently, the exposed seed metal 143s is removed. The uppermost second redistribution line 143T may include, for example, a lower metal layer 143d of Cu and an upper metal layer 143u of Ni. At the same time, the lower metal layer 143d may include a seed metal located at the bottom. The uppermost second redistribution line 143T may be formed by a one-step electroplating process.

[0090] Reference Figure 8C , after forming the uppermost second redistribution line 143T, the uppermost portion of the second body insulating layer 141 covering the uppermost second redistribution line 143T is formed. Thereafter, a first opening (i.e., opening) OP1 and a second opening OP2, each exposing a portion of the upper surface of the uppermost second redistribution line 143T, are formed by an optical process. For example, the first opening OP1 may be formed in the first pad area A, and the second opening OP2 may be formed in the second pad area B. As shown in the figure, the first opening OP1 may be formed to be relatively larger than the second opening OP2 in width. For example, the first opening OP1 and the second opening OP2, each exposing the uppermost second redistribution line 143T, may be duplexed and formed according to the pad area.

[0091] Reference Fig.8D, after forming the first opening OP1 and the second opening OP2, a seed metal is formed on the upper surface and inner wall of the second body insulating layer 141 and on the exposed uppermost second redistribution line 143T. Subsequently, the portion where the pad is to be formed is defined by PR coating and patterning. Thereafter, the second substrate pad 147 is formed by electroplating. As described above, the second substrate pad 147 may include a first type pad 147a in the first opening OP1 in the first pad area A and a second type pad 147b in the second opening OP2 in the second pad area B. As shown in the figure, the first type pad 147a may have a flat shape, and the second type pad 147b may have a structure including an outer protrusion OP, which extends to the upper surface of the second body insulating layer 141 close to the sidewall defining the second opening OP2.

[0092] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: A first redistribution substrate having a plurality of layers of first redistribution lines; a semiconductor chip on the first redistribution substrate; a through-pillar extending vertically on the first redistribution substrate and laterally spaced apart from the semiconductor chip; as well as a second redistribution substrate, on the semiconductor chip and the through-pillar, and having at least one second redistribution line, wherein a first pad area and a second pad area are defined on an upper surface of the second redistribution substrate, the first pad area includes a first opening exposing a first portion of the at least one second redistribution line and is located at a central portion of the second redistribution substrate, and the second pad area extends around the first pad area and includes a second opening exposing a second portion of the at least one second redistribution line, A first type pad having a planar shape is on the at least one second redistribution line in the first opening, and a second type pad having an outer protruding portion is on the at least one second redistribution line in the second opening.

2. The semiconductor package according to claim 1, wherein An uppermost second redistribution line exposed from the first opening and the second opening among the at least one second redistribution line has a multi-metal layer structure, The uppermost second redistribution line includes a lower metal layer of copper Cu and an upper metal layer of nickel Ni and / or an upper metal layer of titanium Ti, and The first type pads and the second type pads are on the upper metal layer.

3. The semiconductor package according to claim 2, wherein: The uppermost second redistribution line includes the lower metal layer of Cu and the upper metal layer of Ni, The first cross-sectional thickness of the upper metal layer is 0.1 μm or greater, and The second cross-sectional thickness of the lower metal layer is equal to or greater than the first cross-sectional thickness of the upper metal layer.

4. The semiconductor package according to claim 1, wherein: The first type pad is on an uppermost second redistribution line among the at least one second redistribution line in the first opening, and The uppermost second redistribution line is exposed around the first type pad.

5. The semiconductor package according to claim 4, wherein: The second redistribution substrate includes a body insulating layer over the at least one second redistribution line, The first opening has a structure vertically extending into a portion of an upper portion of the body insulating layer to expose a portion of the uppermost second redistribution line, The entirety of the uppermost second redistribution line has a first width in a first direction parallel to the upper surface of the first redistribution substrate, A portion of the uppermost second redistribution line exposed by the first opening has a second width in the first direction that is smaller than the first width, and The body insulating layer is on an outer portion of the uppermost second redistribution line.

6. The semiconductor package according to claim 1, wherein The second type pad is on an uppermost second redistribution line among the at least one second redistribution line in the second opening, and The uppermost second redistribution line is not exposed around the second type pad.

7. The semiconductor package according to claim 6, wherein: The second redistribution substrate includes a body insulating layer over the at least one second redistribution line, The second opening has a structure vertically extending into a portion of an upper portion of the body insulating layer, and the structure has a bottom surface of the uppermost second redistribution line and a side surface of the body insulating layer, and The second type pad has a structure extending from the uppermost second redistribution line to the side surface and the upper surface of the body insulating layer.

8. The semiconductor package according to claim 1, further comprising: The upper package, on the second redistribution substrate, Wherein, the semiconductor chip includes an application processor AP chip, and The upper package includes at least one memory chip.

9. A semiconductor package, comprising: A first redistribution substrate having a plurality of layers of first redistribution lines; a semiconductor chip on the first redistribution substrate; a sealing material on the first redistribution substrate and over the semiconductor chip; a through-pillar, on the first redistribution substrate, extending into the sealing material and laterally spaced apart from the semiconductor chip; a second redistribution substrate on the sealing material and having at least one second redistribution line; and an upper package on the second redistribution substrate and electrically connected to the second redistribution substrate through an inter-substrate connection terminal, wherein an opening exposing a portion of the at least one second redistribution line is located on an upper surface of the second redistribution substrate, and An uppermost second redistribution line exposed through the opening among the at least one second redistribution line has a multi-metal layer structure.

10. The semiconductor package according to claim 9, wherein A first pad area and a second pad area are defined on an upper surface of the second redistribution substrate, the first pad area is located at a central portion of the second redistribution substrate, and the second pad area extends around the first pad area, The opening includes a first opening in the first pad area and a second opening in the second pad area, a first type pad having a planar shape is on an uppermost second redistribution line among the at least one second redistribution line in the first opening, and A second type pad having an outer protruding portion is on an uppermost second redistribution line among the at least one second redistribution line in the second opening.

11. The semiconductor package according to claim 10, wherein: The uppermost second redistribution line of the at least one second redistribution line comprises a lower metal layer of copper Cu and an upper metal layer of nickel Ni, The first type pad is on the upper metal layer in the first opening, and The upper metal layer is exposed around the first type pad.

12. The semiconductor package according to claim 10, wherein: The uppermost second redistribution line of the at least one second redistribution line comprises a lower metal layer of copper Cu and an upper metal layer of nickel Ni, The second type pad is on the upper metal layer in the second opening, and The upper metal layer is not exposed around the second type pad.

13. A semiconductor package, comprising: A first redistribution substrate having a plurality of layers of first redistribution lines; a semiconductor chip on the first redistribution substrate; a through-pillar on the first redistribution substrate and laterally spaced apart from the semiconductor chip; as well as a second redistribution substrate, on the semiconductor chip and the through-pillar, and having at least one second redistribution line, wherein an opening exposing a portion of the at least one second redistribution line is located on an upper surface of the second redistribution substrate, and An uppermost second redistribution line exposed through the opening among the at least one second redistribution line includes a lower metal layer of copper Cu and an upper metal layer of nickel Ni.

14. The semiconductor package according to claim 13, wherein: A first pad area and a second pad area are defined on an upper surface of the second redistribution substrate, the first pad area being at a central portion of the second redistribution substrate, and the The second pad area extends around the first pad area, The opening includes a first opening in the first pad area and a second opening in the second pad area, a first type pad having a planar shape is on an uppermost second redistribution line among the at least one second redistribution line in the first opening, and A second type pad having an outer protruding portion is on an uppermost second redistribution line among the at least one second redistribution line in the second opening.

15. The semiconductor package according to claim 14, wherein: The first type pad is on the upper metal layer in the first opening, and The upper metal layer is exposed around the first type pad.

16. The semiconductor package according to claim 14, wherein: The second type pad is on the upper metal layer in the second opening, The second redistribution substrate includes a body insulating layer above the at least one second redistribution line, The second opening has a structure vertically extending into a portion of an upper portion of the body insulating layer, and the structure is defined by a bottom surface of the upper metal layer and a side surface of the body insulating layer, and The second type pad has a structure extending from the upper metal layer to the side surface and the upper surface of the body insulating layer.

17. A method for manufacturing a semiconductor package, the method comprising: providing a first redistribution substrate on a carrier substrate; forming a through-pillar outside the first redistribution substrate; providing a semiconductor chip on a central portion of the first redistribution substrate; forming a sealing material on the through-pillar and the semiconductor chip; exposing an upper surface of the through-pillar by grinding an upper portion of the sealing material; as well as providing a second redistribution substrate on the through-pillars and the sealing material, Wherein, providing the second redistribution substrate comprises: forming an uppermost redistribution line by electroplating, the uppermost redistribution line having a lower metal layer of copper Cu and an upper metal layer of nickel Ni; forming a body insulating layer on the uppermost redistribution line; forming an opening extending into an upper portion of the body insulating layer to expose a portion of the uppermost redistribution line; and Two types of pads having different shapes are formed on the uppermost redistribution line in the opening.

18. The method according to claim 17, wherein: A first pad area and a second pad area are defined on an upper surface of the second redistribution substrate, the first pad area is at a central portion of the second redistribution substrate, and the second pad area extends around the first pad area, Forming the opening includes: forming a first opening in the first pad region and forming a second opening in the second pad region, and Forming the two types of pads includes: forming a first type pad having a planar shape in the first opening; and A second type pad having an outer protruding portion is formed in the second opening.

19. The method according to claim 18, wherein: The first type pad is on the upper metal layer of the uppermost redistribution line in the first opening, The upper metal layer is exposed around the first type pad, The second type pad is arranged on the upper metal layer of the uppermost redistribution line in the second opening, and The upper metal layer is not exposed around the second type pad.

20. The method according to claim 18, wherein: The second opening has a structure vertically extending into a portion of an upper portion of the body insulating layer, and the structure is defined by a bottom surface of the upper metal layer of the uppermost redistribution line and a side surface of the body insulating layer, and The second type pad has a structure extending from the upper metal layer of the uppermost redistribution line to the side surface and the upper surface of the body insulating layer.

Images