Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a capacitor region and an inductor region which are adjacent to each other; forming a plurality of layers of capacitance plates stacked from bottom to top on the substrate of the capacitance region and a dielectric layer located between two adjacent layers of capacitance plates; multiple layers of inductance coils stacked from bottom to top and dielectric layers located between every two adjacent layers of inductance coils are formed on the substrate of the inductance area, every two adjacent layers of inductance coils are electrically connected to form a spiral inductor, the inductance coils correspond to the capacitance plates one to one, and the inductance coils and the capacitance plates which are in one-to-one correspondence are located on the same layer; wherein one end of the spiral inductor is electrically connected with any layer of capacitor plate. According to the invention, the power supply circuit can obtain relatively high inductance while having relatively high capacitance, so that the performance of the power supply circuit is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Nowadays, many electronic devices require DC voltage power supply, and the DC power supply voltage usually comes from an adapter. The adapter obtains AC voltage from the wall socket (power grid), converts the AC voltage into an uncontrolled DC voltage through a rectifier bridge, and converts the uncontrolled DC voltage into the required DC power supply voltage through a switching power supply.

[0003] Switching power supplies usually use transformers or inductors as energy storage elements. For example, in a flyback converter, a transformer is used as an energy storage element. A switch is electrically coupled to the primary side of the transformer, and a control circuit controls the on and off of the switch so that energy is alternately stored in the transformer or transferred to the secondary side of the transformer. The secondary side of the transformer passes through a filter to generate an output voltage across the output capacitor, which is the DC output voltage of the flyback converter. The increase and decrease of the DC output voltage are opposite to the power delivered to the load. An increase in load will cause the DC output voltage to decrease, while a decrease in load will cause the DC output voltage to increase. Normally, the DC output voltage is fed back to the control circuit so that the switching power supply can compensate for changes in the load.

[0004] Current high-performance computing power supply solutions require the provision of high-quality inductors and capacitors. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of a power supply circuit.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a capacitor region and an inductor region arranged adjacent to each other; a multilayer capacitor plate stacked from bottom to top, located on the substrate of the capacitor region; a multilayer inductor coil stacked from bottom to top, located on the substrate of the inductor region, two adjacent layers of inductor coils are electrically connected to form a spiral inductor, the inductor coils correspond to the capacitor plates one by one, and the one-to-one corresponding inductor coils and capacitor plates are located on the same layer; wherein one end of the spiral inductor is electrically connected to any layer of capacitor plates; a dielectric layer, located between two adjacent layers of capacitor plates and between two adjacent layers of inductor coils.

[0007] Optionally, in the multilayer capacitor plates, two adjacent layers of capacitor plates partially overlap, and the non-overlapping portions serve as extensions, and the extensions of adjacent capacitor plates are stacked in sequence from bottom to top.

[0008] Optionally, the semiconductor structure further includes: a first electrical connection structure, which penetrates through the extension of the capacitor plate of the even-numbered layers and is electrically connected thereto; and a second electrical connection structure, which penetrates through the extension of the capacitor plate of the odd-numbered layers and is electrically connected thereto.

[0009] Optionally, when the number of layers of the multilayer capacitor plate is an odd number, the semiconductor structure further includes: a pseudo capacitor plate located on an extension of the topmost even-numbered capacitor plate; and the first electrical connection structure also passes through the pseudo capacitor plate.

[0010] Optionally, one end of the inductor coil located at the bottom layer extends into the capacitor region and is connected to the capacitor plate at the bottom layer to form an integrated structure.

[0011] Optionally, each layer of inductor coils is a spiral structure rotating in the same direction from the head end to the tail end, and the head ends and tail ends of two adjacent layers of inductor coils are longitudinally connected, so that the stacked multiple layers of inductor coils constitute a spiral inductor.

[0012] Optionally, the point where the head ends and tail ends of two adjacent layers of inductor coils are longitudinally connected is used as the connection position, and the two adjacent layers of inductor coils are longitudinally staggered with other layers of inductor coils at the connection position; the semiconductor structure also includes: a third electrical connection structure, which is located at the connection position, passes through the two adjacent layers of inductor coils at the connection position, and is electrically connected to the two adjacent layers of inductor coils.

[0013] Optionally, the shape of each layer of the inductor coil includes square, hexagon, octagon or circle.

[0014] Optionally, the material of the dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; the material of the capacitor plate includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; the material of the inductor coil includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0015] Optionally, the capacitor plate and the inductor coil located on the same layer have the same thickness and are made of the same material.

[0016] Optionally, the thickness of the capacitor plate is to The thickness of the inductor coil is to

[0018] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, including a capacitor region and an inductor region arranged adjacent to each other; forming a plurality of capacitor plates stacked from bottom to top and a dielectric layer located between two adjacent capacitor plates on the substrate of the capacitor region; forming a plurality of inductor coils stacked from bottom to top and a dielectric layer located between two adjacent inductor coils on the substrate of the inductor region, the two adjacent inductor coils are electrically connected to form a spiral inductor, the inductor coils correspond one-to-one to the capacitor plates, and the one-to-one corresponding inductor coils and capacitor plates are located on the same layer; wherein one end of the spiral inductor is electrically connected to any layer of capacitor plates.

[0019] Optionally, in the step of forming a plurality of layers of capacitor plates stacked from bottom to top on the substrate of the capacitor region, two adjacent layers of capacitor plates partially overlap, and the non-overlapping portions serve as extensions, and the extensions of adjacent capacitor plates are stacked in sequence from bottom to top.

[0020] Optionally, the forming method further includes: forming a first electrical connection structure that penetrates through the extension of the capacitor plate of the even-numbered layers and is electrically connected thereto; and forming a second electrical connection structure that penetrates through the extension of the capacitor plate of the odd-numbered layers and is electrically connected thereto.

[0021] Optionally, when the number of layers of the multilayer capacitor plate is odd, the formation method also includes: forming a pseudo capacitor plate on the extension of the topmost even-layer capacitor plate; in the step of forming the first electrical connection structure, the first electrical connection structure also passes through the pseudo capacitor plate.

[0022] Optionally, in the step of forming the inductor coil and the capacitor plate, one end of the inductor coil located at the bottom layer extends into the capacitor region and is connected to the capacitor plate at the bottom layer to form an integrated structure.

[0023] Optionally, in the step of forming a plurality of layers of inductor coils stacked from bottom to top on the substrate of the inductor region, each layer of the inductor coil is a spiral structure rotating in the same direction from the head end to the tail end, and the head end and the tail end of two adjacent layers of the inductor coils are longitudinally connected so that the stacked plurality of layers of the inductor coils constitute a spiral inductor.

[0024] Optionally, in the step of forming a plurality of layers of inductor coils stacked from bottom to top on the substrate of the inductor region, the point where the head ends and the tail ends of two adjacent layers of inductor coils are longitudinally connected is used as the connection position, and the two adjacent layers of inductor coils are longitudinally staggered from the other layers of inductor coils at the connection position; the formation method also includes: at the connection position, forming a third electrical connection structure that penetrates the two adjacent layers of inductor coils at the connection position and is electrically connected to them.

[0025] Optionally, in the step of forming a plurality of layers of inductor coils stacked from bottom to top on the substrate of the inductor region, the shape of each layer of the inductor coils includes square, hexagon, octagon or circle.

[0026] Optionally, the steps of forming capacitor plates and forming inductor coils include: performing multiple patterning processes and performing a dielectric layer forming process between two adjacent patterning processes until the number of layers of the capacitor plates reaches a preset number of layers; the patterning process includes: forming an electrode material layer on a substrate; patterning the electrode material layer to form a plate-shaped electrode material layer in the capacitor area as a capacitor plate, and forming a coil-shaped electrode material layer in the inductor area as an inductor coil; the dielectric layer forming process includes: forming a dielectric layer covering the capacitor plates and the inductor coil.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0028] In the semiconductor structure provided by the embodiment of the present invention, the multi-layer capacitor plates stacked from bottom to top are located on the substrate of the capacitor region, the multi-layer inductor coils stacked from bottom to top are located on the substrate of the inductor region, two adjacent layers of inductor coils are electrically connected to form a spiral inductor, the inductor coils correspond one-to-one to the capacitor plates, and the one-to-one corresponding inductor coils and capacitor plates are located in the same layer, wherein one end of the spiral inductor is electrically connected to any layer of the capacitor plates; in the embodiment of the present invention, the multi-layer capacitor plates constitute a capacitor, the multi-layer inductor coils constitute a spiral inductor, and one end of the spiral inductor formed by the stacked multi-layer inductor coils is connected to any The layered capacitor plates are electrically connected, and the capacitor in the capacitor area is connected to the spiral inductor in the inductor area to form a power supply circuit. The capacitor plates in the capacitor usually have more layers, and the inductor coil corresponds to the capacitor plates one by one. The one-to-one corresponding inductor coil and capacitor plate are located in the same layer. It is possible to utilize the fact that the capacitor plates in the capacitor usually have more layers, and simultaneously form an inductor coil with a correspondingly large number of layers. The inductance strength is proportional to the number of windings. Therefore, the number of layers of the inductor coil is increased, and the inductance strength can be correspondingly increased, so that the power supply circuit can obtain a higher inductance while having a higher capacitance, thereby improving the performance of the power supply circuit.

[0029] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a multilayer capacitor plate stacked from bottom to top and a dielectric layer located between two adjacent layers of capacitor plates are formed on a substrate in a capacitor region, a multilayer inductor coil stacked from bottom to top and a dielectric layer located between two adjacent layers of inductor coils are formed on a substrate in an inductor region, the two adjacent layers of inductor coils are electrically connected to form a spiral inductor, the inductor coils correspond to the capacitor plates one by one, and the one-to-one corresponding inductor coils and capacitor plates are located in the same layer, wherein one end of the spiral inductor is electrically connected to any layer of capacitor plates; in the embodiment of the present invention, the multilayer capacitor plates constitute a capacitor, the multilayer inductor coils constitute a spiral inductor, and the stacking One end of the spiral inductor formed by stacked multi-layer inductor coils is electrically connected to any layer of capacitor plates, and the capacitor in the capacitor area is connected to the spiral inductor in the inductor area to form a power supply circuit. The capacitor plates in the capacitor usually have more layers, and the inductor coil corresponds to the capacitor plates one by one. The one-to-one corresponding inductor coils and capacitor plates are located in the same layer. It is possible to utilize the fact that the capacitor plates in the capacitor usually have more layers to form a correspondingly larger number of inductor coils at the same time. The inductance strength is proportional to the number of windings. Therefore, the number of layers of the inductor coil is increased, and the inductance strength can be increased accordingly, so that the power supply circuit can obtain a higher inductance while having a higher capacitance, thereby improving the performance of the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 3 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0031] Figures 4 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0032] As can be seen from the background art, a high-performance computing power supply solution needs to provide high-quality inductors and capacitors at the same time, but it is currently difficult to obtain a power supply circuit with both high capacitance and high inductance.

[0033] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a capacitor region and an inductor region arranged adjacent to each other; a multilayer capacitor plate stacked from bottom to top, located on the substrate of the capacitor region; a multilayer inductor coil stacked from bottom to top, located on the substrate of the inductor region, two adjacent layers of inductor coils are electrically connected to form a spiral inductor, the inductor coils correspond to the capacitor plates one by one, and the one-to-one corresponding inductor coils and capacitor plates are located on the same layer; wherein one end of the spiral inductor is electrically connected to any layer of capacitor plates; a dielectric layer, located between two adjacent layers of capacitor plates and between two adjacent layers of inductor coils.

[0034] In an embodiment of the present invention, a multilayer capacitor plate constitutes a capacitor, and a multilayer inductor coil constitutes a spiral inductor. One end of the spiral inductor formed by stacking the multilayer inductor coils is electrically connected to any layer of the capacitor plate, and the capacitor in the capacitor area is connected to the spiral inductor in the inductor area to form a power supply circuit. The capacitor plates in the capacitor usually have more layers, and the inductor coil corresponds to the capacitor plates one by one. The one-to-one corresponding inductor coils and capacitor plates are located on the same layer. The characteristic that the capacitor plates in the capacitor usually have more layers can be utilized to form a correspondingly larger number of inductor coils at the same time. The inductance strength is proportional to the number of windings. Therefore, the number of layers of the inductor coil is increased, and the inductance strength can be correspondingly increased, so that the power supply circuit can obtain a higher inductance while having a higher capacitance, thereby improving the performance of the power supply circuit.

[0035] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 1 to 3 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0036] Combined with reference Figures 1 to 3 , Figure 2 for Figure 1 A top view of Figure 3 for Figure 1 The circuit diagram of the present invention comprises a semiconductor structure including: a substrate 100, including a capacitor region 100C and an inductor region 100I arranged adjacent to each other; a multilayer capacitor plate 200 stacked from bottom to top, located on the substrate 100 in the capacitor region 100C; a multilayer inductor coil 240 stacked from bottom to top, located on the substrate 100 in the inductor region 100I, two adjacent layers of inductor coils 240 are electrically connected to form a spiral inductor, the inductor coils 240 correspond to the capacitor plates 200 one by one, and the one-to-one corresponding inductor coils 240 and capacitor plates 200 are located in the same layer; wherein one end of the spiral inductor is electrically connected to any layer of the capacitor plate 200; a dielectric layer 230, located between two adjacent layers of the capacitor plates 200, and between two adjacent layers of the inductor coils 240.

[0037] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0038] In this embodiment, the substrate 100 includes a capacitor region 100C and an inductor region 100I which are adjacently arranged.

[0039] The capacitor region 100C is used to form a MIM capacitor structure, and the inductor region 100I is used to form a spiral inductor structure.

[0040] In this embodiment, a positioning structure (not shown) is further formed in the substrate 100 for positioning the electrical connection structure.

[0041] The multilayer capacitor plates 200 are alternately stacked from bottom to top to serve as electrode plates of the MIM capacitor structure.

[0042] In this embodiment, in the multilayer capacitor plates 200, two adjacent layers of capacitor plates 200 partially overlap, and the non-overlapping portion serves as an extension portion 200e, and the extension portions 200e of adjacent capacitor plates 200 are stacked sequentially from bottom to top.

[0043] Two adjacent layers of capacitor plates 200 are partially overlapped, and the overlapping portions of the capacitor plates 200 face each other to form a capacitor structure. The non-overlapping portions serve as extension portions 200e, and the extension portions 200e are used to electrically connect to the outside, thereby loading electrical signals for each layer of capacitor plates 200. The extension portions 200e of the adjacent capacitor plates 200 are stacked in sequence from bottom to top, and the adjacent capacitor plates 200 can be loaded with electrical signals at the same time through the extension portions 200e of the adjacent capacitor plates 200, which is beneficial to simplifying the structure, simplifying the process flow, and improving the integration of the semiconductor structure.

[0044] In this embodiment, the material of the capacitor plate 200 is a conductive material. As an example, the material of the capacitor plate 200 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0045] It should be noted that in this embodiment, the thickness of the capacitor plate 200 should not be too large or too small. If the thickness of the capacitor plate 200 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the capacitor plate 200 is too small, it is easy to cause the resistance of the capacitor plate 200 to be too large, affecting the performance of the capacitor structure. For this reason, in this embodiment, the thickness of the capacitor plate 200 is to

[0046] Multiple layers of inductor coils 240 are alternately stacked from bottom to top to form the coils of the inductor structure.

[0047] In this embodiment, the multilayer capacitor plates 200 constitute a capacitor, and the multilayer inductor coil 240 constitutes a spiral inductor. One end of the spiral inductor formed by the stacked multilayer inductor coil 240 is electrically connected to any layer of the capacitor plate 200, and the capacitor in the capacitor area 100C is connected to the spiral inductor in the inductor area 100I to form a power supply circuit. The capacitor plates 200 in the capacitor usually have more layers, and the inductor coil 240 corresponds to the capacitor plates 200 one by one, and the one-to-one corresponding inductor coil 240 and capacitor plate 200 are located in the same layer. It is possible to utilize the fact that the capacitor plates 200 in the capacitor usually have more layers, and simultaneously form a correspondingly larger number of inductor coils 240. The inductance strength is proportional to the number of windings. Therefore, the number of layers of the inductor coil 240 is increased, and the inductance strength can be correspondingly increased, so that the power supply circuit can obtain a higher inductance while having a higher capacitance, thereby improving the performance of the power supply circuit.

[0048] The one-to-one corresponding inductor coil 240 and capacitor plate 200 are located in the same layer, which means that the one-to-one corresponding inductor coil 240 and capacitor plate 200 are obtained by patterning the same electrode material layer.

[0049] It should be noted that by utilizing the characteristic that the capacitor plates 200 in the capacitor usually have more layers and simultaneously forming the inductor coil 240 with correspondingly more layers, it is beneficial to avoid as much as possible the use of other metal wires to form multi-layer inductor coils, and the problem of the inductor coil having a larger number of layers due to the limitations of the design rules of different layers of metal wires, and it is beneficial to simplify the formation process of the multi-layer inductor coil 240.

[0050] Correspondingly, in this embodiment, the capacitor plate 200 and the inductor coil 240 located in the same layer have the same thickness and are made of the same material.

[0051] In this embodiment, one end of the spiral inductor is electrically connected to any layer of capacitor plate 200, thereby achieving the following Figure 3 The circuit diagram shows the electrical connection of the spiral inductor and capacitor structure.

[0052] Specifically, in this embodiment, one end of the inductor coil 240 located at the bottom layer extends into the capacitor region 100C and is connected to the capacitor plate 200 at the bottom layer to form an integrated structure.

[0053] One end of the inductor coil 240 located at the bottom layer extends into the capacitor area 100C and is connected to the bottom layer capacitor plate 200 as an integrated structure. That is to say, the bottom layer inductor coil 240 is electrically connected to the bottom layer capacitor plate 200 to realize the electrical connection between the spiral inductor and the capacitor structure, so that the electrical connection structure between the spiral inductor and the capacitor structure is relatively simple and easy to realize. Moreover, the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 are an integrated structure, that is to say, the same electrode material layer is used for patterning, and the portion where the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 are connected is retained in the patterning step without being removed. After patterning, the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 are directly obtained as an integrated structure, thereby directly realizing the electrical connection between the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 without the need to add an additional structure to electrically connect the two, which is conducive to simplifying the structure, simplifying the process flow, improving the process efficiency, and reducing costs.

[0054] In this embodiment, each layer of inductor coils 240 is a spiral structure rotating in the same direction from the head end to the tail end, and the head ends and tail ends of two adjacent layers of inductor coils 240 are longitudinally connected, so that the stacked multiple layers of inductor coils 240 constitute a spiral inductor.

[0055] As an example, Figure 2 The beginning S and the end E of the spiral structure of the topmost inductor coil 240 are shown in FIG.

[0056] It should be noted that for the sake of clarity, Figure 2 Different filling patterns are used for the inductor coils 240 in different layers.

[0057] Each layer of the inductor coil 240 is a spiral structure rotating in the same direction from the head end to the tail end, and the head end and the tail end of two adjacent layers of the inductor coil 240 are longitudinally connected, so that the longitudinally stacked multiple layers of the inductor coil 240 are connected in sequence to form a spiral coil structure, thereby realizing the function of the multiple layers of the inductor coil 240 constituting a spiral inductor.

[0058] In this embodiment, the longitudinal connection point between the head end and the tail end of two adjacent layers of inductor coils 240 is used as the connection position (eg Figure 2 The two adjacent layers of inductor coils 240 are at the connection position and are staggered with the other layers of inductor coils 240 in the longitudinal direction.

[0059] In this embodiment, two adjacent layers of inductor coils 240 are longitudinally connected at the connection position through a third electrical connection structure that penetrates the film layer. The two adjacent layers of inductor coils 240 are longitudinally staggered from other layers of inductor coils 240 at the connection position, so that the third electrical connection structure will not mistakenly connect to other film layers in the longitudinal direction, thereby providing a spatial position for the formation of the third electrical connection structure.

[0060] In this embodiment, the shape of each layer of the inductor coil 240 includes square, hexagon, octagon or circle.

[0061] This embodiment does not limit the morphology of each layer of the inductor coil 240 , and the morphology can be set according to actual process requirements.

[0062] In this embodiment, the material of the inductor 240 is a conductive material. As an example, the material of the inductor 240 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0063] It should be noted that in this embodiment, the thickness of the capacitor coil 240 should not be too large or too small. If the thickness of the capacitor coil 240 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the capacitor coil 240 is too small, it is easy to cause the resistance of the capacitor coil 240 to be too large, affecting the performance of the inductor structure. For this reason, in this embodiment, the thickness of the capacitor coil 240 is to

[0064] The dielectric layer 230 is used as an insulating layer in the MIM capacitor to isolate the capacitor plates 200 of adjacent layers and to isolate the inductor coils 240 of adjacent layers.

[0065] In this embodiment, the material of the dielectric layer 230 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of high-k dielectric materials is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0066] Specifically, the dielectric layer 230 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 230 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 230 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0067] In this embodiment, the dielectric layer 230 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked together. In other embodiments, according to process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0068] In this embodiment, when the number of layers of the multi-layer capacitor plate 200 is an odd number, the semiconductor structure further includes: a pseudo capacitor plate 250 located on the extension portion 200 e of the capacitor plate 220 of the topmost even-numbered layer.

[0069] like Figure 1 As shown, in the multi-layer capacitor plate 200 , odd-numbered layers are labeled 210 , and even-numbered layers are labeled 220 .

[0070] In this embodiment, two adjacent layers of capacitor plates 200 are partially overlapped, and the non-overlapping portion is used as an extension portion 200e. The extension portions 200e of the adjacent capacitor plates 200 are stacked from bottom to top in sequence, so that the electrical signal can be simultaneously loaded for the adjacent capacitor plates 200 through the extension portions 200e of the adjacent capacitor plates 200. When the number of layers of the capacitor plates 200 is an odd number, the number of stacked layers of the extension portions 200e of the capacitor plates 210 of the odd number layers is one more than the number of stacked layers of the extension portions 200e of the capacitor plates 220 of the even number layers. Therefore, in this embodiment, a pseudo capacitor plate 250 is formed on the extension portion 200e of the topmost even number layer capacitor plate 220, so that the capacitor plates of the odd number layers are stacked. The number of metal film layers at the extension portion 200e of the electrode 210 is equal to the number of metal film layers at the extension portion 200e of the capacitor electrode 220 with an even number of layers, so that when the second electrical connection structure for loading electrical signals on the capacitor electrode 210 with odd numbers of layers is formed and the first electrical connection structure for loading electrical signals on the capacitor electrode 220 with even numbers of layers is formed, the number of etched metal film layers is consistent, and the thickness of the etched metal film layers tends to be consistent accordingly, so that the etching process for forming the first electrical connection structure and the etching process for forming the second electrical connection structure can be performed using the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0071] In the present embodiment, in order to make the thickness of the etched metal film layer tend to be consistent when the second electrical connection structure for loading electrical signals on the capacitor plates 210 formed as odd layers and the first electrical connection structure for loading electrical signals on the capacitor plates 220 formed as even layers are formed, the topmost odd-numbered layer capacitor plates 210 and the pseudo capacitor plates 250 are patterned through the same electrode material layer, so that the topmost odd-numbered layer capacitor plates 210 and the pseudo capacitor plates 250 have the same thickness, which is beneficial to simplify the process flow and improve process efficiency.

[0072] In this embodiment, the semiconductor structure further includes: a first electrical connection structure 310 that penetrates through the extension portion 200 e of the even-layer capacitor plate 220 and is electrically connected thereto.

[0073] The first electrical connection structure 310 is used to electrically connect the even-numbered capacitor plates 220 , so as to load electrical signals to the even-numbered capacitor plates 220 .

[0074] Specifically, in the present embodiment, in the step of forming the first electrical connection structure 310, the positioning structure corresponding to the first electrical connection structure 310 is used as the formation position to form the first electrical connection structure 310 that penetrates the even-layer capacitor plate 220. The first electrical connection structure 310 penetrates the even-layer capacitor plate 220 and is in full contact with the even-layer capacitor plate 220, thereby being able to better achieve electrical connection performance.

[0075] In this embodiment, the material of the first electrical connection structure 310 is a conductive material. As an example, the material of the first electrical connection structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0076] Accordingly, in the present embodiment, when the number of layers of the multilayer capacitor plate 200 is an odd number, the first electrical connection structure 310 also penetrates the pseudo capacitor plate 250, so that when the second electrical connection structure for loading electrical signals on the capacitor plate 210 formed as an odd number of layers and the first electrical connection structure for loading electrical signals on the capacitor plate 220 formed as an even number of layers are formed, the number of etched metal film layers is consistent, and accordingly the thickness of the etched metal film layers tends to be consistent, so that the etching process when forming the first electrical connection structure and the etching process when forming the second electrical connection structure can be performed using the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0077] In this embodiment, the semiconductor structure further includes: a second electrical connection structure 320 that penetrates through the extension portion 200 e of the odd-numbered capacitor plate 210 and is electrically connected thereto.

[0078] The second electrical connection structure 320 is used to electrically connect the odd-numbered capacitor plates 210 , so as to load electrical signals to the odd-numbered capacitor plates 210 .

[0079] Specifically, in the present embodiment, in the step of forming the second electrical connection structure 320, the positioning structure corresponding to the second electrical connection structure 320 is used as the formation position to form the second electrical connection structure 320 that penetrates the odd-numbered capacitor plates 210. The second electrical connection structure 320 penetrates the odd-numbered capacitor plates 210 and is in full contact with the odd-numbered capacitor plates 210, thereby being able to better achieve electrical connection performance.

[0080] In this embodiment, the material of the second electrical connection structure 320 is a conductive material. As an example, the material of the second electrical connection structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0081] In this embodiment, the semiconductor structure further includes: a third electrical connection structure 330 , which is located at the connection position, penetrates through two adjacent layers of inductor coils 240 at the connection position, and is electrically connected to the two adjacent layers of inductor coils 240 .

[0082] The third electrical connection structure 330 is used to electrically connect two adjacent layers of inductor coils 240 at a connection position, so that multiple layers of inductor coils 240 are connected to form a spiral inductor structure.

[0083] Specifically, in this embodiment, in the step of forming the third electrical connection structure 330, the positioning structure corresponding to the third electrical connection structure 330 is used as the formation position to form the third electrical connection structure 330 that penetrates the two adjacent layers of inductor coils 240 at the connection position. The third electrical connection structure 330 penetrates the two adjacent layers of inductor coils 240 at the connection position and is in full contact with them, thereby being able to better achieve electrical connection performance.

[0084] In this embodiment, the material of the third electrical connection structure 330 is a conductive material. As an example, the material of the third electrical connection structure 330 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0085] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 4 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0086] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0087] refer to Figure 4 , providing a substrate 100, including a capacitor region 100C and an inductor region 100I that are adjacently arranged.

[0088] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0089] In this embodiment, the substrate 100 includes a capacitor region 100C and an inductor region 100I which are adjacently arranged.

[0090] The capacitor region 100C is used to form a MIM capacitor structure, and the inductor region 100I is used to form a spiral inductor structure.

[0091] In this embodiment, a positioning structure (not shown) is further formed in the substrate 100 for positioning the electrical connection structure.

[0092] Combined with reference Figures 5 to 11, a plurality of capacitor plates 200 stacked from bottom to top and a dielectric layer 230 located between two adjacent capacitor plates 200 are formed on the substrate 100 of the capacitor region 100C; a plurality of inductor coils 240 stacked from bottom to top and a dielectric layer 230 located between two adjacent inductor coils 240 are formed on the substrate 100 of the inductor region 100I, the two adjacent inductor coils 240 are electrically connected to form a spiral inductor, the inductor coils 240 correspond one-to-one to the capacitor plates 200, and the one-to-one corresponding inductor coils 240 and capacitor plates 200 are located in the same layer; wherein one end of the spiral inductor is electrically connected to any layer of the capacitor plates 200.

[0093] The multilayer capacitor plates 200 are alternately stacked from bottom to top and are used as electrode plates of the MIM capacitor structure.

[0094] In the present embodiment, in the step of forming a multilayer capacitor plate 200 stacked from bottom to top on the substrate 100 of the capacitor region 100C, two adjacent layers of capacitor plates 200 are partially overlapped, and the non-overlapping portion serves as an extension portion 200e, and the extension portions 200e of the adjacent capacitor plates 200 are stacked in sequence from bottom to top.

[0095] Two adjacent layers of capacitor plates 200 are partially overlapped, and the overlapping portions of the capacitor plates 200 face each other to form a capacitor structure. The non-overlapping portions serve as extension portions 200e, and the extension portions 200e are used to electrically connect to the outside, thereby loading electrical signals for each layer of capacitor plates 200. The extension portions 200e of the adjacent capacitor plates 200 are stacked in sequence from bottom to top, and the adjacent capacitor plates 200 can be loaded with electrical signals at the same time through the extension portions 200e of the adjacent capacitor plates 200, which is beneficial to simplifying the structure, simplifying the process flow, and improving the integration of the semiconductor structure.

[0096] In the present embodiment, in the step of forming a multilayer capacitor plate 200 stacked from bottom to top on the substrate 100 of the capacitor region 100C, the material of the capacitor plate 200 is a conductive material. As an example, the material of the capacitor plate 200 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0097] It should be noted that, in the present embodiment, in the step of forming a multilayer capacitor plate 200 stacked from bottom to top on the substrate 100 of the capacitor region 100C, the thickness of the capacitor plate 200 should not be too large or too small. If the thickness of the capacitor plate 200 is too large, it is easy to occupy too much space, affecting the integration of the semiconductor structure; if the thickness of the capacitor plate 200 is too small, it is easy to cause the resistance of the capacitor plate 200 to be too large, affecting the performance of the capacitor structure. For this reason, in the present embodiment, in the step of forming a multilayer capacitor plate 200 stacked from bottom to top on the substrate 100 of the capacitor region 100C, the thickness of the capacitor plate 200 is to

[0099] Multiple layers of inductor coils 240 are alternately stacked from bottom to top to form the coils of the inductor structure.

[0100] In this embodiment, the multilayer capacitor plates 200 constitute a capacitor, and the multilayer inductor coil 240 constitutes a spiral inductor. One end of the spiral inductor formed by the stacked multilayer inductor coil 240 is electrically connected to any layer of the capacitor plate 200, and the capacitor in the capacitor area 100C is connected to the spiral inductor in the inductor area 100I to form a power supply circuit. The capacitor plates 200 in the capacitor usually have more layers, and the inductor coil 240 corresponds to the capacitor plates 200 one by one, and the one-to-one corresponding inductor coil 240 and capacitor plate 200 are located in the same layer. It is possible to utilize the fact that the capacitor plates 200 in the capacitor usually have more layers, and simultaneously form a correspondingly larger number of inductor coils 240. The inductance strength is proportional to the number of windings. Therefore, the number of layers of the inductor coil 240 is increased, and the inductance strength can be correspondingly increased, so that the power supply circuit can obtain a higher inductance while having a higher capacitance, thereby improving the performance of the power supply circuit.

[0101] The one-to-one corresponding inductor coil 240 and capacitor plate 200 are located in the same layer, which means that the one-to-one corresponding inductor coil 240 and capacitor plate 200 are obtained by patterning the same electrode material layer.

[0102] It should be noted that by utilizing the characteristic that the capacitor plates 200 in the capacitor usually have more layers and simultaneously forming the inductor coil 240 with correspondingly more layers, it is beneficial to avoid as much as possible the use of other metal wires to form multi-layer inductor coils, and the problem of the inductor coil having a larger number of layers due to the limitations of the design rules of different layers of metal wires, and it is beneficial to simplify the formation process of the multi-layer inductor coil 240.

[0103] Accordingly, in the present embodiment, in the steps of forming the inductor coil 240 and forming the capacitor plate 200 , the capacitor plate 200 and the inductor coil 240 located in the same layer have the same thickness and are made of the same material.

[0104] In this embodiment, one end of the spiral inductor is electrically connected to any layer of capacitor plate 200, thereby achieving the following Fig.11 The circuit diagram shows the electrical connection of the spiral inductor and capacitor structure.

[0105] Specifically, in the step of forming the inductor coil 240 and the capacitor plate 200 in this embodiment, one end of the inductor coil 240 at the bottom layer extends into the capacitor region 100C and is connected to the capacitor plate 200 at the bottom layer to form an integrated structure.

[0106] One end of the inductor coil 240 located at the bottom layer extends into the capacitor area 100C and is connected to the bottom layer capacitor plate 200 as an integrated structure. That is to say, the bottom layer inductor coil 240 is electrically connected to the bottom layer capacitor plate 200 to realize the electrical connection between the spiral inductor and the capacitor structure, so that the electrical connection structure between the spiral inductor and the capacitor structure is relatively simple and easy to realize. Moreover, the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 are an integrated structure, that is to say, the same electrode material layer is used for patterning, and the portion where the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 are connected is retained in the patterning step without being removed. After patterning, the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 are directly obtained as an integrated structure, thereby directly realizing the electrical connection between the bottom layer inductor coil 240 and the bottom layer capacitor plate 200 without the need to add an additional structure to electrically connect the two, which is conducive to simplifying the structure, simplifying the process flow, improving the process efficiency, and reducing costs.

[0107] In this embodiment, in the step of forming a plurality of layers of inductor coils 240 stacked from bottom to top on the substrate 100 of the inductor region 100I, each layer of the inductor coils 240 is a spiral structure rotating in the same direction from the head end to the tail end, and the head end and the tail end of two adjacent layers of the inductor coils 240 are longitudinally connected so that the stacked plurality of layers of the inductor coils 240 constitute a spiral inductor.

[0108] As an example, Fig.10 The beginning S and the end E of the spiral structure of the topmost inductor coil 240 are shown in FIG.

[0109] It should be noted that for the sake of clarity, Fig.10 Different filling patterns are used for the inductor coils 240 in different layers.

[0110] Each layer of the inductor coil 240 is a spiral structure rotating in the same direction from the head end to the tail end, and the head end and the tail end of two adjacent layers of the inductor coil 240 are longitudinally connected, so that the longitudinally stacked multiple layers of the inductor coil 240 are connected in sequence to form a spiral coil structure, thereby realizing the function of the multiple layers of the inductor coil 240 constituting a spiral inductor.

[0111] In the present embodiment, in the step of forming the multi-layer inductor coils 240 stacked from bottom to top on the substrate 100 of the inductor region 100I, the longitudinal connection point between the head end and the tail end of two adjacent layers of inductor coils 240 is used as the connection position (eg Fig.10 The two adjacent layers of inductor coils 240 are at the connection position and are staggered with the other layers of inductor coils 240 in the longitudinal direction.

[0112] In this embodiment, two subsequent adjacent layers of inductor coils 240 are longitudinally connected at the connection position through a third electrical connection structure that penetrates the film layer. The two adjacent layers of inductor coils 240 are longitudinally staggered from other layers of inductor coils 240 at the connection position, so that the third electrical connection structure will not mistakenly connect to other film layers in the longitudinal direction, thereby providing a spatial position for the formation of the third electrical connection structure.

[0113] In this embodiment, in the step of forming a plurality of layers of inductor coils 240 stacked from bottom to top on the substrate 100 in the inductor region 100I, the shape of each layer of inductor coils 240 includes a square, a hexagon, an octagon or a circle.

[0114] This embodiment does not limit the morphology of each layer of the inductor coil 240 , and the morphology can be set according to actual process requirements.

[0115] In this embodiment, the material of the inductor 240 is a conductive material. As an example, the material of the inductor 240 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0116] It should be noted that, in the present embodiment, in the step of forming a multilayer inductor coil 240 stacked from bottom to top on the substrate 100 of the inductor region 100I, the thickness of the capacitor coil 240 should not be too large or too small. If the thickness of the capacitor coil 240 is too large, it is easy to occupy too much space and affect the integration of the semiconductor structure; if the thickness of the capacitor coil 240 is too small, it is easy to cause the resistance of the capacitor coil 240 to be too large, affecting the performance of the inductor structure. For this reason, in the present embodiment, in the step of forming a multilayer inductor coil 240 stacked from bottom to top on the substrate 100 of the inductor region 100I, the thickness of the capacitor coil 240 is to

[0117] The dielectric layer 230 is used as an insulating layer in the MIM capacitor to isolate the capacitor plates 200 of adjacent layers and to isolate the inductor coils 240 of adjacent layers.

[0118] In this embodiment, the material of the dielectric layer 230 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of high-k dielectric materials is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0119] Specifically, the dielectric layer 230 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 230 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 230 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0120] In this embodiment, the dielectric layer 230 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked together. In other embodiments, according to process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0121] In this embodiment, the steps of forming the capacitor plate 200 and forming the inductor coil 240 include: performing multiple patterning processes and forming a dielectric layer 230 between two adjacent patterning processes until the number of layers of the capacitor plate 200 reaches a preset number of layers; the patterning process includes: forming an electrode material layer 260 on the substrate 100; patterning the electrode material layer 260, forming a plate-shaped electrode material layer 260 in the capacitor area 100C as the capacitor plate 200, and forming a coil-shaped electrode material layer 260 in the inductor area 100I as the inductor coil 240; the dielectric layer 230 formation process includes: forming a dielectric layer 230 covering the capacitor plate 200 and the inductor coil 240.

[0122] Multiple patterning processes and dielectric layer 230 formation processes are performed between two adjacent patterning processes until the number of layers of capacitor plates 200 reaches a preset number of layers, so that the capacitor plates 200 and the inductor coil 240 on the same layer are patterned through the same electrode material layer 260 .

[0123] Specifically, Figure 5 and Figure 6 For a graphical treatment, refer to Figure 5 , forming an electrode material layer 260 on the substrate 100; referring to Figure 6, a patterned electrode material layer 260 is formed, a plate-shaped electrode material layer 260 is formed in the capacitor area 100C as the bottom capacitor plate 200, and a coil-shaped electrode material layer 260 is formed in the inductor area 100I as the bottom inductor coil 240. The lowest capacitor plate 200 and the bottom inductor coil 240 are an integrated structure.

[0124] Figure 7 and Figure 8 The diagram illustrates a process of multiple patterning processes and a process of forming the dielectric layer 230 between two adjacent patterning processes.

[0125] Continue to refer Figure 8 When the number of layers of the multilayer capacitor plate 200 is an odd number, the forming method further includes: forming a pseudo capacitor plate 250 on the extension portion 200e of the capacitor plate 220 of the topmost even layer.

[0126] like Fig. 9 As shown, in the multi-layer capacitor plate 200 , odd-numbered layers are labeled 210 , and even-numbered layers are labeled 220 .

[0127] In this embodiment, two adjacent layers of capacitor plates 200 are partially overlapped, and the non-overlapping portion is used as an extension portion 200e. The extension portions 200e of the adjacent capacitor plates 200 are stacked from bottom to top in sequence, so that the electrical signal can be simultaneously loaded for the adjacent capacitor plates 200 through the extension portions 200e of the adjacent capacitor plates 200. When the number of layers of the capacitor plates 200 is an odd number, the number of stacked layers of the extension portions 200e of the capacitor plates 210 of the odd number layers is one more than the number of stacked layers of the extension portions 200e of the capacitor plates 220 of the even number layers. Therefore, in this embodiment, a pseudo capacitor plate 250 is formed on the extension portion 200e of the topmost even number layer capacitor plate 220, so that the capacitor plates of the odd number layers are stacked. The number of metal film layers at the extension portion 200e of the electrode 210 is equal to the number of metal film layers at the extension portion 200e of the capacitor electrode 220 with an even number of layers, so that when the second electrical connection structure for loading electrical signals on the capacitor electrode 210 with odd numbers of layers is formed and the first electrical connection structure for loading electrical signals on the capacitor electrode 220 with even numbers of layers is formed, the number of etched metal film layers is consistent, and the thickness of the etched metal film layers tends to be consistent accordingly, so that the etching process for forming the first electrical connection structure and the etching process for forming the second electrical connection structure can be performed using the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0128] In the present embodiment, in order to make the thickness of the etched metal film layer tend to be consistent when the second electrical connection structure for loading electrical signals on the capacitor plates 210 formed as odd layers and the first electrical connection structure for loading electrical signals on the capacitor plates 220 formed as even layers are formed, the topmost odd-numbered layer capacitor plates 210 and the pseudo capacitor plates 250 are patterned through the same electrode material layer, so that the topmost odd-numbered layer capacitor plates 210 and the pseudo capacitor plates 250 have the same thickness, which is beneficial to simplify the process flow and improve process efficiency.

[0129] In this embodiment, the forming method further includes: forming a first electrical connection structure 310 that penetrates through the extension portion 200 e of the even-layer capacitor plate 220 and is electrically connected thereto.

[0130] The first electrical connection structure 310 is used to electrically connect the even-numbered capacitor plates 220 , so as to load electrical signals to the even-numbered capacitor plates 220 .

[0131] Specifically, in the present embodiment, in the step of forming the first electrical connection structure 310, the positioning structure corresponding to the first electrical connection structure 310 is used as the formation position to form the first electrical connection structure 310 that penetrates the even-layer capacitor plate 220. The first electrical connection structure 310 penetrates the even-layer capacitor plate 220 and is in full contact with the even-layer capacitor plate 220, thereby being able to better achieve electrical connection performance.

[0132] In this embodiment, in the step of forming the first electrical connection structure 310, the material of the first electrical connection structure 310 is a conductive material. As an example, the material of the first electrical connection structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0133] Accordingly, in the present embodiment, when the number of layers of the multilayer capacitor plate 200 is an odd number, in the step of forming the first electrical connection structure 310, the first electrical connection structure 310 also penetrates the pseudo capacitor plate 250, so that when the second electrical connection structure for loading electrical signals on the capacitor plate 210 with odd layers is formed and the first electrical connection structure for loading electrical signals on the capacitor plate 220 with even layers is formed, the number of etched metal film layers is consistent, and accordingly the thickness of the etched metal film layers tends to be consistent, so that the etching process when forming the first electrical connection structure and the etching process when forming the second electrical connection structure can be performed using the same etching process parameters, that is, the first electrical connection structure and the second electrical connection structure can be formed in the same step, thereby improving the process efficiency.

[0134] In this embodiment, the forming method further includes: forming a second electrical connection structure 320 that penetrates through the extension portion 200 e of the odd-numbered capacitor plate 210 and is electrically connected thereto.

[0135] The second electrical connection structure 320 is used to electrically connect the odd-numbered capacitor plates 210 , so as to load electrical signals to the odd-numbered capacitor plates 210 .

[0136] Specifically, in the present embodiment, in the step of forming the second electrical connection structure 320, the positioning structure corresponding to the second electrical connection structure 320 is used as the formation position to form the second electrical connection structure 320 that penetrates the odd-numbered capacitor plates 210. The second electrical connection structure 320 penetrates the odd-numbered capacitor plates 210 and is in full contact with the odd-numbered capacitor plates 210, thereby being able to better achieve electrical connection performance.

[0137] In this embodiment, in the step of forming the second electrical connection structure 320, the material of the second electrical connection structure 320 is a conductive material. As an example, the material of the second electrical connection structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0138] In this embodiment, the forming method further includes: forming, at the connection position, a third electrical connection structure 330 that penetrates through two adjacent layers of inductor coils 240 at the connection position and is electrically connected to the two adjacent layers of inductor coils 240 .

[0139] The third electrical connection structure 330 is used to electrically connect two adjacent layers of inductor coils 240 at a connection position, so that multiple layers of inductor coils 240 are connected to form a spiral inductor structure.

[0140] Specifically, in this embodiment, in the step of forming the third electrical connection structure 330, the positioning structure corresponding to the third electrical connection structure 330 is used as the formation position to form the third electrical connection structure 330 that penetrates the two adjacent layers of inductor coils 240 at the connection position. The third electrical connection structure 330 penetrates the two adjacent layers of inductor coils 240 at the connection position and is in full contact with them, thereby being able to better achieve electrical connection performance.

[0141] In this embodiment, in the step of forming the third electrical connection structure 330, the material of the third electrical connection structure 330 is a conductive material. As an example, the material of the third electrical connection structure 330 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, including a capacitor region and an inductor region disposed adjacent to each other; A multilayer capacitor plate stacked from bottom to top is located on the substrate of the capacitor region; A plurality of layers of inductor coils stacked from bottom to top are located on the substrate of the inductor region, two adjacent layers of the inductor coils are electrically connected to form a spiral inductor, the inductor coils correspond to the capacitor plates one by one, and the one-to-one corresponding inductor coils and capacitor plates are located in the same layer; Wherein, one end of the spiral inductor is electrically connected to any layer of the capacitor plate; The dielectric layer is located between two adjacent layers of capacitor plates and between two adjacent layers of inductor coils.

2. The semiconductor structure according to claim 1, wherein: In the multi-layer capacitor plates, two adjacent layers of capacitor plates are partially overlapped, and the non-overlapping parts serve as extensions, and the extensions of the adjacent capacitor plates are stacked in sequence from bottom to top.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: a first electrical connection structure, penetrating through the extensions of the capacitor plates of the even-numbered layers and electrically connected thereto; The second electrical connection structure penetrates through the extension portions of the capacitor plates of the odd-numbered layers and is electrically connected thereto.

4. The semiconductor structure according to claim 3, characterized in that When the number of layers of the multilayer capacitor plates is an odd number, the semiconductor structure further comprises: a pseudo capacitor plate, located on an extension of the capacitor plate of the topmost even-numbered layer; The first electrical connection structure also passes through the pseudo capacitor plate.

5. The semiconductor structure according to claim 1, wherein: One end of the inductor coil located at the bottom layer extends into the capacitor region and is connected to the capacitor plate at the bottom layer to form an integrated structure.

6. The semiconductor structure according to claim 1, wherein: Each layer of the inductor coils is a spiral structure rotating in the same direction from the head end to the tail end, and the head ends and tail ends of two adjacent layers of inductor coils are longitudinally connected so that the stacked multiple layers of inductor coils form a spiral inductor.

7. The semiconductor structure according to claim 6, wherein: The longitudinal connection point between the head end and the tail end of two adjacent layers of inductor coils is used as the connection position, and the two adjacent layers of inductor coils are staggered with the other layers of inductor coils in the longitudinal direction at the connection position; The semiconductor structure further includes: a third electrical connection structure, which is located at the connection position, penetrates through the two adjacent layers of inductor coils at the connection position, and is electrically connected to the two adjacent layers of inductor coils.

8. The semiconductor structure according to claim 1, wherein: The shape of each layer of the inductor coil includes square, hexagon, octagon or circle.

9. The semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; The material of the capacitor plate includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; The material of the inductor coil includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

10. The semiconductor structure according to claim 1, wherein: The capacitor plate and the inductor coil located on the same layer have the same thickness and are made of the same material.

11. The semiconductor structure according to claim 1, wherein: The thickness of the capacitor plate is to The thickness of the inductor coil is to 12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate including a capacitor region and an inductor region disposed adjacent to each other; Forming a plurality of capacitor plates stacked from bottom to top on the substrate of the capacitor region, and a dielectric layer located between two adjacent capacitor plates; A plurality of inductor coils stacked from bottom to top and a dielectric layer located between two adjacent layers of inductor coils are formed on the substrate of the inductor region, the two adjacent layers of inductor coils are electrically connected to form a spiral inductor, the inductor coils correspond to the capacitor plates one by one, and the one-to-one corresponding inductor coils and capacitor plates are located in the same layer; Wherein, one end of the spiral inductor is electrically connected to any layer of the capacitor plate.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming a plurality of layers of capacitor plates stacked from bottom to top on the substrate of the capacitor region, two adjacent layers of capacitor plates are partially overlapped, and the non-overlapping parts are used as extensions, and the extensions of the adjacent capacitor plates are stacked in sequence from bottom to top.

14. The method for forming a semiconductor structure according to claim 13, wherein: The forming method further comprises: forming a first electrical connection structure penetrating through the extension of the capacitor plate of the even-numbered layers and electrically connected thereto; A second electrical connection structure is formed which penetrates through the extensions of the capacitor plates of the odd-numbered layers and is electrically connected thereto.

15. The method for forming a semiconductor structure according to claim 14, wherein: When the number of layers of the multilayer capacitor plates is an odd number, the forming method further comprises: forming a pseudo capacitor plate on the extension of the capacitor plate of the topmost even layer; In the step of forming the first electrical connection structure, the first electrical connection structure also penetrates the pseudo capacitor plate.

16. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the inductor coil and the capacitor plate, one end of the inductor coil located at the bottom layer extends into the capacitor region and is connected to the capacitor plate at the bottom layer to form an integrated structure.

17. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming a plurality of layers of inductor coils stacked from bottom to top on the substrate of the inductor region, each layer of the inductor coils is a spiral structure rotating in the same direction from the head end to the tail end, and the head end and the tail end of two adjacent layers of inductor coils are longitudinally connected so that the stacked plurality of layers of inductor coils constitute a spiral inductor.

18. The method for forming a semiconductor structure according to claim 17, wherein: In the step of forming a plurality of layers of inductor coils stacked from bottom to top on the substrate of the inductor region, the longitudinal connection point between the head ends and the tail ends of two adjacent layers of inductor coils is used as the connection position, and the two adjacent layers of inductor coils are staggered with the other layers of inductor coils in the longitudinal direction at the connection position; The forming method further includes: forming a third electrical connection structure at the connection position, which penetrates through two adjacent layers of inductor coils at the connection position and is electrically connected to the two adjacent layers of inductor coils.

19. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming a plurality of layers of inductor coils stacked from bottom to top on the substrate of the inductor region, the shape of each layer of the inductor coils includes square, hexagon, octagon or circle.

20. The method for forming a semiconductor structure according to claim 12, wherein: The steps of forming the capacitor plate and the inductor coil include: performing multiple patterning processes and dielectric layer forming processes between two adjacent patterning processes until the number of layers of the capacitor plate reaches a preset number of layers; The patterning process includes: forming an electrode material layer on the substrate; patterning the electrode material layer to form a plate-shaped electrode material layer in the capacitor region as the capacitor plate, and forming a coil-shaped electrode material layer in the inductor region as the inductor coil; The dielectric layer forming process includes: forming a dielectric layer covering the capacitor plates and the inductor coil.

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