Apparatus, system and method for adaptive burst mode control

Abstract

The invention relates to an apparatus, system and method for adaptive burst mode control. In described examples, an apparatus includes a pulse width modulation (PWM) control circuit (136) and a burst mode logic circuit (144). An input of the burst mode logic circuit (144) is coupled to an output of the PWM control circuit (136). The burst mode logic circuit (144) is configured to receive a feedback signal from a secondary side (116) of a power conversion circuit (102). The burst mode logic circuit (144) is configured to suppress a sleep cycle of a burst mode in response to a magnitude of the feedback signal exceeding a nominal load threshold voltage. The PWM control circuit (136) continues to operate in the burst mode while the burst mode logic circuit (144) suppresses the sleep cycle.

Description

Technical Field

[0001] The present application relates generally to pulse width modulation (PWM) control of power converters, and more particularly to burst mode PWM control of power converters under no load or light load conditions. Background Art

[0002] In some examples, PWM signals are used to control switching devices, such as power converters. In some examples, the power converter operates at relatively high efficiency under normal load. However, under no load or light load conditions, providing continuous inductor current may result in reduced converter efficiency. Therefore, under no load or light load conditions, a burst mode is used, in which the PWM signal is delivered to the switching device during relatively brief burst periods, rather than during the intervals between burst periods. Summary of the invention

[0003] In the described example, a device includes a pulse width modulation (PWM) control circuit and a burst mode logic circuit. An input of the burst mode logic circuit is coupled to an output of the PWM control circuit. The burst mode logic circuit is configured to receive a feedback signal from a secondary side of a power conversion circuit. The burst mode logic circuit is configured to suppress a sleep cycle of the burst mode in response to a magnitude of the feedback signal exceeding a nominal load threshold voltage. After the burst mode logic circuit begins suppressing the sleep cycle, the PWM control circuit continues to operate in the burst mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a functional block diagram and circuit diagram of an exemplary power converter system.

[0005] Figure 2 yes Figure 1 A collection of exemplary burst mode signals for a power converter system.

[0006] Figure 3 yes Figure 1 Logic gate and functional block diagram of a burst mode logic circuit.

[0007] Figure 4 is a timing diagram showing an example of applying a burst mask to a PWM control signal to generate a burst mode PWM signal.

[0008] Figure 5A is shown for generating Figure 4 A timing diagram of an exemplary process of burst masking.

[0009] Figure 5B is used to generate Figure 4 An exemplary process of burst masking is as follows: Figure 5A As shown in .

[0010] Figure 6 Is for use without Figure 3 The comparator burst mode logic circuit, from Figure 1 The no-load or low-load condition of the power converter system is transformed to Figure 1 A timing diagram of an exemplary process for normal load conditions of a power converter system.

[0011] Figure 7 Is used for Figure 3 The burst mode logic circuit, from Figure 1 The no-load or low-load condition of the power converter system is transformed to Figure 1 A timing diagram of an exemplary process for normal load conditions of a power converter system.

[0012] Figure 8 Is the process used to transition a power converter system from burst mode to normal mode in response to nominal load conditions. DETAILED DESCRIPTION

[0013] Figure 1 1 is a functional block diagram and circuit diagram of an exemplary power converter system 100. The power converter system 100 includes an inductor-inductor-capacitor (LLC) converter 102, a load 104, a voltage sensor 106, a current sensor 108, a control integrated circuit (IC) 110, and a gate driver circuit 112.

[0014] LLC converter 102 includes a primary side 114 and a secondary side 116. Primary side 114 includes a voltage source 118, a high-side transistor 120, a low-side transistor 122, a capacitor 124, an inductor 126, and a primary winding 128. Inductor 126, the magnetizing inductance of primary winding 128, and capacitor 124 together form a resonant tank circuit. Therefore, LLC converter 102 is referred to as a resonant power converter. Secondary side 116 includes a secondary winding 130, a first rectifier transistor 132, and a second rectifier transistor 134. Primary winding 128 and secondary winding 130 together form a transformer 131. Inductor 126 can be, for example, an external inductor or leakage inductance of transformer 131.

[0015] Control IC 110 includes pulse width modulation (PWM) circuit 136, processor 138, memory 140, clock circuit 142, and burst mode logic circuit 144. Figure 3The burst mode logic circuit 144 is further described. The memory 140 includes a memory circuit storing instructions for executing an interrupt service routine (ISR) 146 for switching between a burst mode for operating the LLC converter 102 and a normal mode for operating the LLC converter 102. In some examples, the ISR 146 is stored in a flash memory bank of the memory 140.

[0016] On the primary side 114, a positive terminal of a voltage source 118 is connected to a first terminal of a high-side transistor 120. A second terminal of the high-side transistor 120 is connected to a first terminal of a low-side transistor 122 and a first terminal of an inductor 126. A second terminal of the inductor 126 is connected to a first terminal of a primary winding 128. The primary winding 128 is magnetically coupled to a secondary winding 130. A second terminal of the primary winding 128 is connected to a first terminal of a capacitor 124. A second terminal of the capacitor 124 is connected to a second terminal of the low-side transistor 122 and a negative terminal of the voltage source 118.

[0017] On the secondary side 116, a first terminal of the secondary winding 130 is connected to a first terminal of a first transistor 132. A second terminal of the secondary winding 130 is connected to a first terminal of a second transistor 134. A center tap of the secondary winding 130 is connected to an input of the current sensor 108 and a first terminal of the load 104 via a first output terminal 148. A second terminal of the load 104 is connected to second terminals of the first transistor 132 and the second transistor 134 via a second output terminal 150. The output voltage V of the LLC converter 102 is OUT is the voltage between the first output terminal 148 and the second output terminal 150, i.e., the voltage across the load 104. The second output terminal 150 is connected to the input of the voltage sensor 106. The first transistor 132 and the second transistor 134 are controlled using respective control terminals such that the first transistor 132 and the second transistor 134 form a rectifier that rectifies the current on the secondary side 116.

[0018] The control terminals of the first transistor 132 and the second transistor 134 are, for example, gates of corresponding metal oxide semiconductor field effect transistors (MOSFETs). In some examples, the first transistor 132 and the second transistor 134 are n-channel MOSFETs. The source of the first transistor 132 is connected to the positive terminal of the voltage source 118. The drain of the first transistor 132 is connected to the drain of the second transistor 134 and the first terminal of the inductor 126. The drain of the second transistor 134 is connected to the second terminal of the capacitor 124 and the negative terminal of the voltage source 118. The first transistor 132 and the second transistor 134 provide a switching function for the LLC converter 102, thereby controlling the current flowing through the primary coil 128, and therefore, controlling the transmission of energy from the primary coil 128 to the secondary coil 130.

[0019] The output of the voltage sensor 106 is connected to an input of the PWM circuit 136 (e.g., through a first optocoupler). The output of the PWM circuit 136 is connected to a first input of the burst mode logic circuit 144. The first output of the current sensor 108 is connected to a second input of the burst mode logic circuit 144 and a first input of the processor 138 (e.g., through a second optocoupler). The processor 138 is connected to communicate with the memory 140, and a second output of the processor 138 is connected to a third input of the burst mode logic circuit 144. The output of the burst mode logic circuit 144 is connected to an input of the gate driver 112. The first output of the gate driver 112 is connected to the control terminal of the high-side transistor 120. The second output of the gate driver 112 is connected to the control terminal of the low-side transistor 122.

[0020] When the high-side transistor 120 is turned on and the low-side transistor 122 is turned off, the current flowing from the positive terminal of the voltage source 118 through the inductor 126 and through the primary winding 128 increases. When the current flows through the primary winding 128 to the capacitor 124, the capacitor 124 is charged and the primary winding 128 generates a magnetic flux, which causes the magnetic core (not shown) to store magnetic energy having a first polarity. When the high-side transistor 120 is turned off and the low-side transistor 122 is turned on, the current flowing from the capacitor 124 through the primary winding 128, through the inductor 126 toward the negative terminal of the voltage source 118 increases. When the current flows through the primary winding 128 to the negative terminal of the voltage source 118, the capacitor 124 is discharged and the primary winding 128 generates a magnetic flux, which causes the magnetic core to store magnetic energy having a second polarity. The magnetic flux generated by the primary winding 128 induces a current in the secondary winding 130 , which is rectified by the first transistor 132 and the second transistor 134 to provide direct current (DC) power to the load 104 .

[0021] In some resonant power converters, as the output current demand (the current demand of the load 104) decreases, the switching frequency of the transistors that control the power delivery is increased to reduce the power output. In the LLC converter 102, this corresponds to increasing the switching frequency of the high-side transistor 120 and the low-side transistor 122. However, in low load conditions, the high switching frequency and reduced power output may result in reduced efficiency due to increased switching losses. In some instances, a burst mode is used to maintain the target output voltage level within a hysteresis range and maintain relatively high efficiency while the LLC converter 102 operates in low load conditions. About Figures 2 to 5B The burst mode is further described.

[0022] Figure 2 yes Figure 11. A diagram 200 of exemplary burst mode signals of a power converter system 100 of FIG. 1 is shown. The same reference numerals or other reference designators are used in the drawings to represent the same or similar features (structurally and / or functionally). The diagram 200 includes a first diagram 202 and a second diagram 204. The first diagram 202 shows the output signal of the PWM circuit 136, which is referred to herein as the PWM switching signal 206. The second diagram 204 shows the voltage (V VLO ). VLO ISR 146 is used to regulate V OUT The control loop voltage. V VLO Given by Equation 1:

[0023] V VLO =(V REF -V OUT )×Compensator Equation 1

[0024] In Equation 1, V REF is the reference voltage (not shown), V OUT The PWM circuit 136 uses V VLO To determine the switching frequency, to regulate the output voltage to the reference voltage, and the control IC 110 uses the compensator value to adjust V VLO to facilitate this function.

[0025] The PWM switching signal 206 includes a period corresponding to normal operation 210 and a period corresponding to burst mode operation 212. The burst mode 212 has a burst period 214 during which the high-side transistor 120 and the low-side transistor 122 are alternately turned on and off by the gate driver 112 to generate a pulse burst, thereby starting the oscillation of the resonant converter at a level sufficient to recharge the output capacitor. A burst interval period 216 is located between the burst periods 214. During the burst interval period 216, the high-side transistor 120 and the low-side transistor 122 are turned off. Therefore, given the off state, the burst interval period 216 can also be referred to as a sleep period 216.

[0026] During the period when the PWM switching signal 206 switches between voltages corresponding to logic one and logic zero—that is, throughout normal operation 210, and during burst periods 214 of burst mode operation 212—the gate driver circuit 112 drives the high-side transistor 120 and the low-side transistor 122 alternately on and off. These periods of active switching operation are represented as eye diagrams. The sleep period 216 is represented as a constant value (straight line).

[0027] During normal operation 210, V VLO 208 is maintained at a substantially constant level. At T1, the load is removed (suddenly or gradually), which causes V VLO 208 decreases. At time T2, the ISR 146 executed by the processor 138 detects a no load or low load condition (also referred to herein as an underload condition) and signals the PWM circuit 136 and the burst mode logic circuit 144 to initiate a burst mode 212. The underload condition may correspond, for example, to an average current demand of the load 104 being less than an average current that the high-side transistor 120 and the low-side transistor 122 can effectively induce in the secondary coil by the primary coil 128 during normal operation 210.

[0028] During the burst mode 212, the PWM switching signal 206 provides a higher frequency pulse (compared to the higher frequency of the normal mode 210) to control the high-side transistor 120 and the low-side transistor 122 to switch more frequently. The higher switching rate enables a higher rate of power transfer from the primary coil 128 to the secondary coil 130. This enables the LLC converter 102 to regulate V VLO 208, and thus, regulates the output voltage while significantly reducing the total power transferred across transformer 131 by providing power transfer cycles having a relatively high frequency but a relatively short duration. It should be noted that during sleep cycle 216, V OUT As the output capacitor (not shown) discharges, it decreases, which causes V VLO 208 increases (see Equation 1).

[0029] At T3, V VLO 208 reaches (or rises above) a high threshold 218, which reflects that the voltage sensor 106 detects that V OUT In response, the PWM circuit 136 and the burst mode logic circuit 144 start a burst cycle 214 to transfer energy from the primary coil 128 to the secondary coil 130 to increase V OUT and (correspondingly) reduce V VLO 208. At T4, V VLO 208 reaches (or falls below) the low threshold 220, which reflects that the voltage sensor 106 detects that V OUT In response, PWM circuit 136 and burst mode logic circuit 144 end burst cycle 214, allowing sleep cycle 216 to begin. VLOWhen the ISR 146 executed by the processor 138 ends the burst mode 212 when the high threshold 218 and the low threshold 220 during the burst mode 212 indicate a normal load condition. In some examples, the voltage swing between the high threshold 218 and the low threshold 220 during the burst mode 212 is greater than the corresponding voltage swing during the normal operation 210 (not in Figure 2 (shown in the).

[0030] Figure 3 yes Figure 1 1. The burst mode logic circuit 144 of the embodiment of the present invention is a logic gate and functional block diagram of the burst mode logic circuit 144. The burst mode logic circuit 144 includes a comparator 302, a burst mask generator 304, or a logic gate 306, and an AND logic gate 308. A first input of the comparator 302 is connected to the output of the current sensor 108 (e.g., via an optocoupler) to receive an output current signal indicating the output current of the LLC converter 102. The output current signal may correspond to, for example, an instantaneous voltage across a resistor connected in series with the load 104. The voltage across the resistor is captured by a capacitor using a monostable multivibrator. In response to the trigger signal, the monostable multivibrator provides a short duration pulse to quickly close the switch and then open the switch (resistors, capacitors, multivibrators, and switches are not shown). A second input of the comparator 302 receives a nominal load threshold voltage, which is used to indicate a return from an underload condition to a normal load condition.

[0031] The output of comparator 302 is connected to a first input of an OR logic gate 306. A second input of OR logic gate 306 receives a burst mode flag that indicates whether power converter system 100 is currently operating in normal mode 210 or in burst mode 212. A burst mode flag having a voltage corresponding to a logic one indicates operation in normal mode 210, and a burst mode flag having a voltage corresponding to a logic zero indicates operation in burst mode 212. An input of burst mask generator 304 receives a PWM control signal from PWM circuit 136. An output of burst mask generator 304 is connected to a third input of OR logic gate 306.

[0032] The output of the OR logic gate 306 is connected to a first input of an AND logic gate 308. A second input of the AND logic gate 308 receives the PWM control signal. The output of the AND logic gate 308 is connected to the gate driver circuit 112 and provides a gate driver control signal.

[0033] As described above, the nominal load threshold voltage is used to indicate whether the power converter system 100 is in a normal load condition or in an underload condition. If the output current signal is greater than the nominal load threshold voltage, a normal load condition is indicated. Therefore, in response to the voltage of the output current signal being less than the nominal load threshold voltage (which indicates an underload condition), the comparator 302 outputs a voltage corresponding to a logic zero (e.g., a relatively low voltage). In response to the voltage of the output current signal exceeding the nominal load threshold voltage (which indicates a normal load condition), the comparator 302 transitions to outputting a voltage corresponding to a logic one (e.g., a relatively high voltage). In some instances, the comparator 302 also includes a hysteresis of its threshold voltage, thereby avoiding the comparator 302 from outputting a logic one to outputting a logic zero due to a random or transient event such as line noise. In some instances, in response to the output current signal and the nominal load threshold voltage, different types of comparators are used to determine the transition from an underload condition to a normal load condition.

[0034] Comparator 302 is used to inhibit sleep cycle 216 in response to detecting the nominal load condition while power converter system 100 continues to operate in burst mode. Inhibition of sleep cycle 216 corresponds to the output of comparator 302 being a logic one and may occur (completely or partially) during burst cycle 214. While comparator 302 is inhibiting sleep cycle 216, ISR 146 (executed by processor 138) processes signal information indicating the nominal load condition and, after completing the processing, returns power converter system 100 to normal mode 210. Figure 7 The suppression of the sleep cycle 216 by the comparator 302 is discussed further.

[0035] Figure 4 4 is a timing diagram 400 showing an example of applying a burst mask 402 to a PWM control signal 404 to generate a burst mode PWM signal 406. The burst mask 402 is, for example, a square wave in which a logic portion corresponding to the duration of a corresponding burst period 214 alternates with a logic zero portion corresponding to the duration of a corresponding sleep period 216. The burst mode PWM signal 406 corresponds to the PWM switching signal 206 during the burst mode 212. The burst mode PWM signal 406 is the output of an AND logic gate 308 that receives the PWM control signal 404 and the burst mask 402 as inputs. That is, during the burst mode 212, the burst mode PWM signal 406 output by the AND logic gate 308 corresponds to the PWM control signal 404 during the burst period 214 and has a logic zero value otherwise. In response to V VLO 208 to determine the duration of the pulse 408 of the burst mask 402—and accordingly, to determine that the output capacitor is recharged during the burst period 214 to increase V OUT degree.

[0036] Back to Figure 3 , if the burst mode flag has a logic value of one (normal operation) or the output of the comparator 302 has a logic value of one (a nominal load condition is detected), the OR logic gate 306 outputs a logic value of one, regardless of the output of the burst mask generator 304. If both the burst mode flag and the output of the comparator 302 have a logic value of zero, the OR logic gate 306 outputs the burst mask 402 generated by the burst mask generator 304. Therefore, if either the burst mode flag or the output of the comparator 302 has a logic value of one, the AND logic gate 308 outputs the PWM control signal 404. If both the burst mode flag and the output of the comparator 302 have a logic value of zero, the AND logic gate 308 outputs the burst mode PWM signal 406. In other words, the AND logic gate 308 outputs the burst mode PWM signal 406 only when both conditions are met, namely, the burst mode flag indicates a burst mode and the comparator 302 does not detect a normal load condition.

[0037] Figure 5A is shown for generating Figure 4 A timing diagram 500 of an exemplary process 501 of burst masking 402 of FIG. Figure 5B is an exemplary process 501. Corresponding to Figure 5B The corresponding process 501 steps Figure 5A Portions of the timing diagram 500 are labeled with corresponding step identification numbers.

[0038] In step 502, the PWM circuit 136 generates the PWM control signal 404. In some examples, steps 504 and 508 to 512 are performed using the burst mask generator 304, and step 514 is performed using the burst mode logic circuit 144. In step 504, a timing window 506 is determined. The timing window 506 has a duration of one burst mode cycle, i.e., the burst period 214 and the subsequent (next / subsequent) sleep period 216. In some examples, the timing window 506 is selected so that the frequency of the burst period 214 is at least 20 kilohertz (kHz) (or other frequencies above audible frequencies) so that the burst mode switching will not generate audible noise. A frequency of 20 kHz corresponds to a burst mode cycle duration of 50 microseconds.

[0039] In step 508, a portion of each burst mode cycle that will be the burst period 214 is determined. In some examples, this portion is selected to reduce output voltage ripple.

[0040] In step 510, the start and end times of the burst period 214 are determined. In some examples, the duration of the burst period 214 is determined as a plurality of the PWM control signal 404 duty cycles. In some examples, the start time of the timing window 506 is used as the start time of the burst period 214. In some examples, the start time of the timing window 506 falls at a random time relative to the duty cycle of the PWM control signal 404. The start time of the burst period 214 may be adjusted so that the first PWM pulse of the burst period 214 has a duty cycle selected to reduce output voltage ripple. In some examples, a 25% duty cycle is selected for the first PWM pulse of the burst period 214 of the PWM control signal 404 having a 50% duty cycle. (In some examples, other PWM control signal 404 duty cycles and / or first PWM pulse duty cycles are used.) The start of the burst period 214 may be determined using an internal count of the PWM circuit 136 for determining the rising and falling edges of the PWM pulse to ensure that the first PWM pulse has a 25% duty cycle. In the example shown, the burst period 214 begins with a count corresponding to a rising edge of the PWM pulse plus a count corresponding to half the duty cycle of the PWM control signal 404 and ends with a count corresponding to a falling edge of the PWM pulse.

[0041] In step 512 , the burst mask generator 304 generates a burst mask using the determined burst period 214 and the timing window 506 . In step 514 , the burst mode logic circuit 144 generates a burst mode PWM signal 406 using the PWM control signal 404 , the burst mask 402 , and the AND logic gate 308 .

[0042] Figure 6 Is for use without Figure 3 The burst mode logic circuit 144 of the comparator 302, from Figure 1 The underload condition of the power converter system 100 transitions to Figure 1 6. A timing diagram 600 of an exemplary process for a normal load condition of a power converter system of FIG. 6. A PWM control signal 602 is applied to the burst mode logic circuit 144 to generate a gate driver control signal 604. An output current signal 606 shows a voltage indicative of the current measured by the current sensor 108. A voltage loop output signal (V VLO )608 and the output voltage signal (V OUT )610.

[0043] As about Figure 2 As described, during the burst mode 212, the PWM circuit 136, the burst mode logic circuit 144, and the gate driver circuit 112 together control the high-side transistor 120 and the low-side transistor 122 so that V VLO608 is maintained between the upper threshold 218 and the lower threshold 220. This causes V OUT 610 is maintained close to the corresponding average value V OUT 612.

[0044] At time T1, the output current signal 606 has a rising edge 614, changing from a value indicating an underload condition to a value indicating a normal load condition. The control loop interval 616 of the ISR 146 refers to the processor 138 executing the instructions of the ISR 146 in response to the output current signal 606 transition to set the burst mode flag (see Figure 3 ) changes from zero to one and switches the PWM circuit 136 from burst mode operation to normal mode operation. In some examples, the delay represented by the control loop interval 616 also includes the time it takes for the control loop regulation function to start providing the compensator value (see equation 1).

[0045] In some examples, the control loop interval 616 of the ISR 146 has a duration (e.g., 20 microseconds) that can substantially overlap with the burst cycle interval 216. This allows V VLO 608 is not controlled during periods of high current demand by the load 104. In response, V VLO 608 increases outside the hysteresis interval defined by the upper threshold 218 and the lower threshold 220, causing V OUT 610 has a relatively large undershoot. In other words, V OUT 610 has the expected average V OUT 612. After the control loop interval 616 of ISR 146 ends, V OUT Normal mode control of 610 resumes at T2, after which V VLO 608 and V OUT 610 returns toward the corresponding expected range.

[0046] Figure 7 is used Figure 3 The burst mode logic 144, from Figure 1 The underload condition of the power converter system 100 transitions to Figure 1 6. As the output current signal 606 increases along its rising edge 614, the output current signal 606 exceeds the nominal load threshold. This causes the output of the comparator 302 to transition to a logic one. Therefore, the output of the OR logic gate 306 becomes a constant logic one, causing the output of the gate driver control signal 308 to be equal to the PWM control signal 602. In other words, in response to the comparator 302 detecting the transition to a normal load condition, the sleep cycle 216 is inhibited.

[0047] Suppressing the sleep cycle 216 at T1 means that in response to the rising edge 614, Figure 7 The gate driver control signal 604 continues to provide continuous burst cycle 214 control to the high-side transistor 120 and the low-side transistor 122. Figure 6 In contrast to the method Figure 6 In the method of , there is a delay after T1 during which the sleep cycle 216 persists. This enables the primary side 114 to transfer energy to the secondary side 116 while the control loop interval 616 of the ISR 146 is ongoing, regardless of the normal timing of the sleep cycle 216. In some examples, the hardware delay 702 (of the burst mode logic circuit 144) for inhibiting the sleep cycle 216 is much shorter than the software delay for completing the control loop interval 616 of the ISR 146. In one example, this hardware delay 702 is 60 nanoseconds. Therefore, when the power converter system 100 transitions to normal mode operation, V OUT 610 undershoot is reduced and V OUT 610 remains closer to the expected average V OUT 612 till T2.

[0048] After T1, PWM control circuit 136 continues to operate in burst mode 212 because processor 138 has not yet signaled PWM control circuit 136 to transition to normal mode 210. After T2, after the operation of ISR control loop 146 to detect normal load conditions is completed, power converter system 100 returns to V OUT 610 Normal mode 210 regulation.

[0049] Figure 88 is a process 800 for transitioning a power converter system 100 from a burst mode 210 to a normal mode 212 in response to a nominal load condition. In step 802, the power converter system 100 operates in the burst mode 212 in response to an underload condition. In step 804, the burst mode logic circuit 144 compares a feedback signal in response to the load condition of the power converter with a nominal load threshold. In an example, the feedback signal may be a voltage of the output current signal 606, which indicates an output current of the LLC converter 102 measured by the current sensor 106. In step 806, the burst mode logic circuit 144 inhibits a sleep cycle of the burst mode in response to the voltage of the feedback signal exceeding the nominal load threshold voltage, while the PWM control circuit 136 continues to operate in the burst mode 212 (i.e., the control loop of the ISR 146 has not yet been completed, and therefore, the PWM control circuit 136 remains in the burst mode 212). The voltage of the feedback signal exceeding the nominal load threshold voltage indicates a nominal load condition. In step 808 , the control loop of ISR 146 is completed, and processor 138 signals power converter system 100 to transition to operating in normal mode 210 in response to ISR 146 detecting the nominal load condition.

[0050] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

[0051] In some instances, the burst control circuits and processes described herein may be used to control PWM controlled devices other than half-bridge LLC converters, such as buck, boost, or buck-boost converters, half-bridge or full-bridge devices, DC or AC input devices, DC or AC output devices, or other devices that include power across an inductor or transformer or that otherwise provide or regulate power.

[0052] In some examples, normal load conditions are applied during the burst period 214 , or after the sleep period 216 begins.

[0053] In some examples, the sentence “the burst mode logic circuit is configured to inhibit a sleep cycle of the burst mode in response to the magnitude of the feedback signal exceeding the nominal load threshold voltage while the PWM control circuit continues to operate in the burst mode” refers to the following example. Figure 3 and 7 The behavior of the burst mode logic circuit 144 is described.

[0054] The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that achieve a functional relationship consistent with the description. For example, if device A provides a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal provided by device A.

[0055] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, for example: (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. Moreover, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0056] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0057] As used herein, the terms "terminal", "node", "interconnect", "pin", "solder ball", and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their terminals.

[0058] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0059] The functionality of the present disclosure is attributed to the control IC 110, the PWM circuit 136, the processor 138, and the burst mode logic circuit 144. The control IC 110, the PWM circuit 136, the processor 138, and / or the burst mode logic circuit 144 may include one or more processors. The control IC 110, the PWM circuit 136, the processor 138, and / or the burst mode logic circuit 144 may include any combination of integrated circuit systems, discrete logic circuit systems, analog circuit systems, such as one or more microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, central processing units, graphics processing units, field programmable gate arrays, and / or any other processing resources. In some examples, the control IC 110, the PWM circuit 136, the processor 138, and the burst mode logic circuit 144 may include multiple components, such as any combination of the processing resources listed above and other discrete or integrated logic circuit systems and / or analog circuit systems.

[0060] The techniques described in this disclosure may also be embodied or encoded in an article of manufacture that includes a non-transitory computer-readable storage medium, such as memory 140. Exemplary non-transitory computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable ROM, erasable programmable ROM, electronically erasable programmable ROM, flash memory, solid state drive, hard disk, magnetic media, optical media, or any other computer-readable storage device or tangible computer-readable medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. In some examples, the non-transitory storage medium may store data that may change over time (e.g., in RAM or cache memory).

[0061] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the remaining circuitry. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs (nMOSFETs), or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, such as NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0062] The circuits described herein may be reconfigured to include replaced components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0063] Although certain elements of the described examples may be included in the integrated circuit and other elements are external to the integrated circuit, in other exemplary embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0064] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the value, or if the value is zero, means a reasonable range of values ​​around zero.

Claims

1. A device comprising: A pulse width modulation (PWM) control circuit comprises an output; as well as a burst mode logic circuit comprising an input and an output, the input of the burst mode logic circuit being coupled to the output of the PWM control circuit, and the burst mode logic circuit being configured to receive a feedback signal from a secondary side of a power conversion circuit; Wherein the burst mode logic circuit is configured to inhibit a sleep cycle of a burst mode in response to a magnitude of the feedback signal exceeding a nominal load threshold voltage while the PWM control circuit continues to operate in the burst mode.

2. The device of claim 1 , wherein the burst mode logic circuit comprises a comparator comprising a first input and a second input, the comparator being configured to receive the feedback signal at its first input, and the comparator being configured to receive the nominal load threshold voltage at its second input.

3. The apparatus of claim 2, wherein the burst mode logic circuit comprises: a burst mask generator comprising an input and an output, the input of the burst mask generator being coupled to the output of the PWM control circuit; An OR logic gate having a first input, a second input and a third input, the first input of the OR logic gate being coupled to the output of the comparator, the second input of the OR logic gate being coupled to the output of the burst mask generator, and the OR logic gate being configured to receive a burst mode flag at its third input.

4. The apparatus of claim 3 , wherein the burst mode logic circuit comprises an AND logic gate having a first input, a second input, and an output, the first input of the AND logic gate being coupled to the output of the OR logic gate, and the second input of the AND logic gate being coupled to the output of the PWM control circuit.

5. The apparatus of claim 1 , wherein the PWM control circuit comprises an input, the input of the burst mode logic circuit is a first input of the burst mode logic circuit, the feedback signal is a first feedback signal, and the burst mode logic circuit comprises a second input; The device further comprises: a memory circuit storing instructions that, when executed, are configured to execute an interrupt service routine for determining a load state of the power conversion circuit; as well as a processor coupled to executablely communicate with the memory circuit, the processor comprising an input, a first output, and a second output, the processor being configured to receive a second feedback signal at its first input, the first output of the processor being coupled to the input of the PWM control circuit, and the second output of the processor being coupled to the second input of the burst mode logic circuit.

6. A system comprising: a current sensor having an input and an output; a pulse width modulation (PWM) control circuit having an input and an output, wherein the input of the PWM control circuit is coupled to the output of the current sensor; a burst mode logic circuit having a first input, a second input, and an output, the first input of the burst mode logic circuit being coupled to the output of the PWM control circuit and the second input of the burst mode logic circuit being coupled to the output of the current sensor; a gate driver circuit having an input and an output, the input of the gate driver circuit being coupled to the output of the burst mode logic circuit; as well as a switch having a first terminal, a second terminal, and a control terminal, the control terminal of the switch being coupled to the output of the gate driver circuit; Wherein the burst mode logic circuit is configured to inhibit a sleep cycle of a burst mode in response to a voltage of the first input of the burst mode logic circuit exceeding a nominal load threshold voltage while the PWM control circuit continues to operate in the burst mode.

7. The system according to claim 6, wherein the switch is a first switch, and wherein the output of the gate driver circuit is a first output of the gate driver circuit, the gate driver circuit having a second output; The system further includes a second switch having a first terminal, a second terminal, and a control terminal, the first terminal of the first switch being coupled to the first terminal of the second switch, and the control terminal of the second switch being coupled to the second output of the gate driver circuit.

8. The system of claim 7, further comprising an inductor-inductor-capacitor (LLC) power converter, the LLC power converter comprising the first switch and the second switch, and the current sensor is configured to measure an output current of the LLC power converter.

9. The system of claim 6, wherein the switch is a first switch, the output of the gate driver circuit is a first output of the gate driver circuit, the gate driver circuit has a second output, the input of the PWM control circuit is a first input of the PWM control circuit, and the PWM control circuit has a second input, the system further comprising: a capacitor comprising a first terminal and a second terminal; Inductors; a voltage sensor comprising an input and an output, the input of the voltage sensor being coupled to the inductor and the output of the voltage sensor being coupled to the second input of the PWM control circuit; as well as a second switch having a first terminal, a second terminal, and a control terminal, the first terminal of the first switch being coupled to the first terminal of the second switch, the second terminal of the second switch being coupled to the second terminal of the capacitor, and the control terminal of the second switch being coupled to the second output of the gate driver circuit.

10. The system according to claim 9, wherein the inductor is a secondary coil; The system further comprises a primary coil; Wherein the first switch and the second switch are coupled to control power transfer from the primary coil to the secondary coil.

11. The system of claim 6, wherein the burst mode logic circuit comprises a comparator comprising a first input and a second input, the first input of the comparator being coupled to the second input of the burst mode logic circuit, and the comparator being configured to receive the nominal load threshold voltage at its second input.

12. The system of claim 11, wherein the burst mode logic circuit comprises: a burst mask generator comprising an input and an output, the input of the burst mask generator being coupled to the first input of the burst mode logic circuit; An OR logic gate having a first input, a second input and a third input, the first input of the OR logic gate being coupled to the output of the comparator, the second input of the OR logic gate being coupled to the output of the burst mask generator, and the OR logic gate being configured to receive a burst mode flag at its third input.

13. The system of claim 12, wherein the burst mode logic circuit comprises an AND logic gate having a first input, a second input, and an output, the first input of the AND logic gate being coupled to the output of the OR logic gate, and the second input of the AND logic gate being coupled to the output of the PWM control circuit.

14. The system of claim 6, wherein the PWM control circuit includes an input, the input to the burst mode logic circuit is a first input to the burst mode logic circuit, and the burst mode logic circuit includes a second input; The system further comprises: a memory circuit storing instructions that, when executed, are configured to execute an interrupt service routine for determining a load state of the switch; as well as a processor coupled to executablely communicate with the memory circuit, the processor comprising an input, a first output, and a second output, the processor being configured to receive a feedback signal at its first input, the first output of the processor being coupled to the input of the PWM control circuit, and the second output of the processor being coupled to the second input of the burst mode logic circuit.

15. A method of operating a pulse width modulation control (PWM control) system, the method comprising: controlling a switch using a PWM control signal generated by a PWM control circuit operating in a burst mode corresponding to an underload condition of the PWM control system such that burst periods of the PWM control signal alternate with sleep periods of the PWM control signal; determining that the PWM control system has transitioned to a normal load condition in response to a feedback signal exceeding a nominal load threshold; In response to the determining that the PWM control system has transitioned to the normal load condition, the sleep cycle of the PWM control signal is suppressed while the PWM control circuit continues to operate in the burst mode.

16. The method of claim 15, further comprising transitioning from a burst mode to a normal mode after the inhibiting begins.

17. The method of claim 15, wherein the feedback signal is responsive to an output current of the PWM control system.

18. The method of claim 15, wherein the feedback signal is a first feedback signal; The method further includes transitioning the PWM control circuit to operate in a normal mode corresponding to the normal load condition of the PWM control system; wherein said transforming said PWM control circuit is performed in response to an interrupt service routine determining that a second feedback signal indicates said normal load condition; and Wherein said determining that said second feedback signal indicates said normal load condition is completed after said determining that said PWM control system has transitioned to said normal load condition is completed.

19. The method of claim 18, wherein the first feedback signal is responsive to an output current of the PWM control system and the second feedback signal is responsive to an output voltage of the PWM control system.

20. The method of claim 15, wherein the controlling is performed in response to a burst mode flag, an output of a comparator performing the determining, a burst mask, and the PWM control signal.

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