Buffer circuit design method based on high-frequency SiC half-bridge inverter

Abstract

The invention discloses a buffer circuit design method based on a high-frequency SiC half-bridge inverter, and the method comprises the steps: building a high-frequency SiC half-bridge inverter test circuit based on the half-bridge topology of a voltage type inverter; parasitic parameters of the high-frequency SiC half-bridge inverter test circuit are obtained; establishing a circuit model corresponding to the experimental circuit according to an equivalent circuit and parasitic parameters when a switch S1 in the high-frequency half-bridge test circuit is in a turn-off transient state; and calculating equivalent resistance under the turn-off transient resonant frequency, simplifying a circuit model, carrying out complex frequency domain analysis on an equivalent series second-order circuit, solving a transfer function of output voltage, constraining a solution of a characteristic equation, obtaining resistance and capacitance values of the buffer circuit, and completing the design of the buffer circuit. According to the invention, test conditions are simplified, and acquisition of parasitic parameters is more scientific, accurate and simple.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic electric energy conversion, and in particular to a buffer circuit design method based on a high-frequency SiC half-bridge inverter. Background Art

[0002] In the process of designing high switching frequency power electronic converters, wide bandgap semiconductors such as silicon carbide (SiC) are often used as switching devices. Such devices have high electron drift velocity, faster speed, lower on-resistance and higher junction temperature, which makes it possible for inverters to work at high switching frequencies. However, high switching frequency means high dv / dt and di / dt in the circuit, which will resonate between the parasitic inductance loop of the high-frequency circuit and the parasitic capacitance of the switch tube and the parasitic parameters of the main circuit components, causing spike overvoltage at both ends of the switch tube during the switching transient, especially the shutdown overvoltage often exceeds 1 times of the DC power supply, which will not only cause distortion of the output waveform and reduce the accuracy, but also because the voltage resistance of the switch tube is limited, SiC in high-power and high-voltage applications will cause the switch tube to be broken down due to excessive spike oscillation.

[0003] In order to solve the above problems, a buffer circuit is generally connected in parallel at both ends of the switch tube. The buffer circuit is composed of a buffer capacitor and a buffer resistor. There are currently three methods for designing the parameters of these two components: the first is to build a double-pulse test platform circuit, analyze the oscillation frequency of a single switch tube, and then perform modeling analysis on it, and continuously adjust the parameters of the buffer circuit to optimize the value. This method starts with a double-pulse experimental platform, but in the process of building the experimental circuit, a lot of experience is required to select suitable diodes, capacitors, and inductors. The requirements are relatively strict, the process is relatively complicated, and it is not targeted at common bridge circuits, but only targeted at them. The first method is to calculate the state of a single tube; the second method is to calculate the total parasitic capacitance and parasitic inductance in the circuit according to the oscillation frequency of the waveform before and after the parallel buffer circuit, and then add the buffer circuit to optimize the analysis circuit. This method relies on the accuracy of the formula calculation and the calculation process is relatively complicated and not suitable for forward design parameters; the third method is to reverse the cause of the oscillation frequency of the waveform to calculate the total parasitic capacitance and parasitic inductance in the circuit. This method mathematically models the mechanism of oscillation of the inductance and capacitance of the main circuit, thereby solving the inductance parameters of the main circuit from the perspective of oscillation. It does not consider the impact of the parasitic parameters of the switch tube in the oscillation and the calculation is complicated. Most of the above design methods involve complex calculation processes, building complex dual-pulse circuits and considering the switching state of a single switch tube. It is of great significance to propose a design for a high-frequency SiC device buffer circuit in a bridge circuit for the most commonly used bridge structure. Summary of the invention

[0004] The purpose of the present invention is to provide a buffer circuit design method based on a high-frequency SiC half-bridge inverter, which adopts a half-bridge inverter topology to test the peak oscillation and perform mathematical modeling on it, so that the experimental circuit design is simpler and more targeted to the widely used bridge structure, and can avoid the complex problems of device parameter selection and the complex analysis process of working mode when building a double-pulse circuit, so that the test circuit is simpler and more applicable.

[0005] The present invention adopts the following technical solution: a buffer circuit design method based on a high-frequency SiC half-bridge inverter, comprising the following steps:

[0006] Step 1: Based on the half-bridge topology of the voltage source inverter, a high-frequency SiC half-bridge inverter test circuit is established by using the stacking design and welding technology of the printed circuit board. The circuit includes a discrete high-frequency SiC Mosfet low-side switch tube S1, a discrete high-frequency SiC Mosfet high-side switch tube S2, and a DC power supply V dc , drive circuit, first to fourth Schottky diodes D1 to D4, first to fourth buffer capacitors C1 to C4, first buffer resistor R1, second buffer resistor R2, wiring inductance L con and parasitic inductance L loop ;

[0007] Among them, the low-side switch tube S1 and the high-side switch tube S2 have the same structure; the drive circuit is designed using an isolated half-bridge driver chip, the driver chip is powered by a DSP control module, and provides two complementary control signals with dead time, and the auxiliary power supply is provided by an isolated power supply.

[0008] Step 2: Obtain parasitic parameters of the high-frequency SiC half-bridge inverter test circuit.

[0009] Step 3: Based on the equivalent circuit and parasitic parameters of the switch S1 in the high-frequency half-bridge test circuit during the turn-off transient, establish a circuit model corresponding to the experimental circuit.

[0010] Step 4: Calculate the equivalent resistance at the turn-off transient resonant frequency, simplify the circuit model in step 3, and perform complex frequency domain analysis on the equivalent series second-order circuit to solve the transfer function of the output voltage.

[0011] Step 5: Based on the transfer function, obtain the resistance and capacitance values ​​of the buffer circuit to complete the design of the buffer circuit.

[0012] Furthermore, in step 1, the structure of the high-frequency SiC half-bridge inverter test circuit is:

[0013] The discrete high-frequency SiC Mosfet low-side switch S1 includes a first gate inductor L G1 , the first drain inductance L D1, the first source gate inductance L S1 , the first gate input resistor R G1(int) , the first on-resistance R DS1 , the first gate-source capacitance C GS1 , the first drain-source capacitance C DS1 , the first drain-gate capacitance C DG1 , the first internal body diode D S1 and the first diode junction capacitance C J1 ; The discrete high-frequency SiC Mosfet high-side switch S2 includes a second gate inductor L G2 , the second drain inductance L D2 , the second source gate inductance L S2 , the second gate input resistor R G2(int) , the second on-resistance R DS2 , the second gate-source capacitance C GS2 , the second drain-source capacitance C DS2 , the second drain-gate capacitance C DG2 , the second internal body diode D S2 and the second diode junction capacitance C J2 .

[0014] The driving circuit of the low-side switch tube S1 includes a first driving voltage V gs1 , the first driving resistor R g1 and the first driving inductor L g1 .

[0015] The driving circuit of the high-side switch tube S2 includes a second driving voltage V gs2 , the second driving resistor R g2 and the second driving inductor L g2 .

[0016] The first buffer resistor R1 and the second buffer capacitor C2 are connected in parallel to form a first buffer branch, and the second buffer resistor R2 and the fourth buffer capacitor C4 are connected in parallel to form a second buffer branch; the first on-resistance R DS1 、The first body diode junction capacitance C J1 and the first diode D S1 To form a parallel branch, the parallel branch is D S1 The equivalent model of the second on-resistance R DS2 , the second body diode junction capacitance C J2 and the second diode D S2 To form a parallel branch, the parallel branch is D S2 The equivalent model of .

[0017] The cathode of the first Schottky diode D1 is respectively connected to the second drain inductor L D2 One end of the parasitic inductance L loopThe first end of the first Schottky diode D1 is connected to the first branch of the second buffer branch, the anode of the first Schottky diode D1 is connected to one end of the first buffer capacitor C1, and the parasitic inductance L loop The other end is connected to the DC voltage source V dc The other end of the first buffer capacitor C1 is connected to the anode of the second Schottky diode D2 and the first fulcrum of the first buffer branch, and the cathode of the second Schottky diode D2 is connected to the second driving power supply V gs2 The negative electrode, the second source gate inductor L s2 One end and wiring inductance L con The second branch of the first buffer branch is connected to the DC voltage source V dc The cathode of the fourth Schottky diode D4 and the anode of the second driving power supply V gs2 The negative electrode of the second source gate inductor L s2 The other end is connected to the second gate-source capacitor C GS2 One end of the second diode junction capacitance C J2 One end and the second drain-source capacitor C DS2 One end of the second gate-source capacitor C GS2 The other end is connected to the second drain-gate capacitor C DG2 One end and the second gate input resistor R G2(int) One end of the second diode is connected to the junction capacitance C J2 The other end is connected to the second drain-source capacitor C DS2 The other end of the second drain inductor L D2 The other end of the second drain-gate capacitor C DG2 The other end of the second gate input resistor R G2(int) The other end of the second gate inductor L G2 One end of the second gate inductor L G2 The other end is connected to the second driving resistor R g2 One end of the second drive resistor R g2 The other end is connected to the second driving inductor L g2 One end of the second drive inductor L g2 The other end is connected to the second driving power supply V gs2 positive connection.

[0018] Wiring inductance L con The other end is connected to the first drain inductor L D1 One end of the first drain inductor L is connected to the anode of the third Schottky diode D3, the cathode of the third Schottky diode D3 is connected to one end of the third buffer capacitor C3, the other end of the third buffer capacitor C3 is connected to the cathode of the fourth Schottky diode D4 and the second branch of the second buffer branch respectively, and the first drain inductor L D1 The other end is connected to the first drain-gate capacitor CDG1 One end of the first diode junction capacitance C J1 One end and the first drain-source capacitor C DS1 One end of the first drain-source capacitor C DS1 The other end is connected to the first diode junction capacitance C J1 The other end of the first source gate inductor L S1 One end of the first gate-source capacitor C GS1 One end of the first source-gate inductor L S1 The other end of the first gate-source capacitor C GS1 The other end is connected to the first drain-gate capacitor C DG1 The other end and the first gate input resistor R G1(int) One end of the first gate input resistor R G1(int) The other end of the first gate inductor L G1 One end of the first gate inductor L G1 The other end is connected to the first driving resistor R g1 One end of the first drive resistor R g1 The other end is connected to the first driving inductor L g1 One end of the first drive inductor L g1 The other end is connected to the first driving power supply V gs1 positive connection.

[0019] Furthermore, in step 1, the driving circuit is used to provide positive and negative pulse periodic driving voltage, and the driving voltage adjusts the current through the driving resistor connected in series, wherein the driving resistor of the upper tube is R g2 , the driving resistance of the lower tube is R g1 , the driving voltage provided turns on the switch tube in the positive half cycle and turns off the switch tube in the negative half cycle; the driving inductor corresponding to the discrete high-frequency SiC Mosfet low-side switch tube S1 is L g1 , the corresponding driving voltage source V gs1 ; The driving inductor corresponding to the discrete high-frequency SiC Mosfet high-side switch S2 is L g2 , the corresponding driving voltage source V gs2 .

[0020] Furthermore, in step 1, all driving inductors and wiring inductors L con All are generated through PCB wiring.

[0021] Furthermore, in step 2, obtaining the parasitic parameters includes:

[0022] (1) Consult the relevant data sheet of the selected SiC Mosfet to obtain the parameters of gate-source capacitance, drain-source capacitance, drain-gate capacitance, and diode junction capacitance.

[0023] (2) Download the source file of the official simulation file corresponding to SiC Mosfet and obtain the parasitic inductance parameters of each pin.

[0024] (3) Use the LCR digital bridge to obtain the DC bus inductance, and obtain the driving inductance and wiring inductance through calculation.

[0025] Furthermore, in step 3, establishing a circuit model corresponding to the experimental circuit includes the following contents:

[0026] When the discrete high-frequency SiC Mosfet high-side switch S2 is in the on state, the second internal body diode D is ignored. S2 The second on-resistance R DS2 Placed outside the switch tube, all parasitic parameters except the drain and source inductance are bypassed; when the discrete high-frequency SiC Mosfet low-side switch tube S1 is in the off state, it is regarded as an internal open circuit, and the first diode junction capacitance C J1 and the first drain-source capacitance C DS1 After being connected in parallel with the first drain-gate capacitor C DG1 , the first gate-source capacitance C GS1 Form a triangle connection, wiring inductance L con and the first drain inductance L D1 Connect in series to get the inductance L' D , inductance L' D The parasitic capacitor connected in series with the triangle, the first drive resistor R g1 and the first gate input resistor R G1(int) The total resistance R of the first drive circuit is obtained by connecting them in series G1 , the first driving inductor L g1 and the first gate inductor L G1 Equivalent to the total driving inductance L' G The gate parasitic parameters of the switch tube S1 and the parameters in the drive circuit are combined with the first gate-source capacitance C GS1 and the first source-gate inductance L S1 After parallel connection, it is connected to the negative pole of the DC voltage source, and then the circuit model corresponding to the experimental circuit is obtained.

[0027] Furthermore, in step 4, solving the transfer function of the output voltage includes the following:

[0028] The calculation formula for PCB (Printed Circuit Board) trace inductance is:

[0029]

[0030] Among them, L represents the PCB trace inductance; l represents the PCB trace inductance length; W represents the PCB trace inductance width; H represents the copper thickness.

[0031] According to the star-delta impedance transformation and the circuit model in step 3, the circuit parameters are transformed into the complex frequency domain for series-parallel simplification. The specific expression is:

[0032]

[0033] Where s represents the Laplace operator, L' loop represents the simplified DC loop inductance, L' G represents the simplified total driver inductance, ω off Represents the circuit resonant frequency when turned off, R eq_G Represents the gate-source equivalent resistance, C G Represents the gate capacitance after star-delta transformation, C S Represents the source capacitance after star-delta transformation, R eq_S Represents the source equivalent resistance, R eq_D Represents the drain equivalent resistance, R eq Represents the total equivalent resistance, C D It represents the drain equivalent capacitance after star-delta transformation, L S represents the source-gate inductance, L D is the leakage inductance, R G(int) Represents the gate input resistance, R g Represents the driving resistance, L G Represents the gate inductance, L g Represents the driving inductance, C GS Represents the gate-source capacitance, C GD is the drain-gate capacitance, C DS represents the drain-source capacitance, C J Represents the diode junction capacitance, R DS Represents the on-resistance.

[0034] According to formulas (5) and (6), the equivalent RLC (Resistor Inductor Capacitor) series second-order circuit model of the low-side switch tube S1 in the high-frequency circuit is obtained, and its turn-off voltage transfer function G(s) is:

[0035]

[0036] According to formula (7), the Bode diagram is drawn to predict the oscillation frequency of the circuit model and the voltage gain at the oscillation frequency. At the same time, the buffer circuit of the high-frequency SiC half-bridge inverter test circuit is equivalent to the parallel form of RC (Resistor-Capacitance circuit) branches. For the test circuit of the low-side switch tube S1, it is connected in parallel to the total equivalent resistance and drain capacitance to obtain the output voltage transfer function with the buffer circuit added. The specific formula is:

[0037]

[0038] Among them, V DS Represents DC voltage, R SN Represents the buffer resistor, C SN Represents the buffer capacitor.

[0039] Furthermore, in step 5, the value of the buffer circuit is obtained according to the transfer function, including two methods:

[0040] (1) Taking the values ​​of buffer capacitance and buffer resistance as unknown quantities and amplitude gain as the target, a three-dimensional graph is established using Matlab mathematical tools. The matching point of buffer resistance and buffer capacitance when the amplitude gain is less than 1.1 times the DC voltage is the optimal matching point, which is the value of the buffer circuit.

[0041] (2) According to the zeros and poles corresponding to the characteristic equation in the transfer function, the values ​​of resistance and capacitance are adjusted so that the real part of the pole under the influence of the mode is on the negative half axis. When the real root of the negative half axis is restricted, the values ​​of resistance and capacitance are constrained. At this time, the commonly used C0G material capacitors and commonly used resistance values ​​within the constraint range are substituted into the transfer function to observe the oscillation frequency and gain, and then the values ​​of the buffer resistor and buffer capacitor are obtained.

[0042] Furthermore, the present invention also proposes an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the buffer circuit design method based on a high-frequency SiC half-bridge inverter when executing the computer program.

[0043] Furthermore, the present invention also proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is run by a processor, the buffer circuit design method based on the high-frequency SiC half-bridge inverter is executed.

[0044] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0045] (1) The method proposed in the present invention only requires two identical silicon carbide switching tubes and the application of other passive components and active components in the buffer circuit, thereby simplifying the test conditions.

[0046] (2) The method proposed in the present invention is more scientific, accurate and simple for obtaining parasitic parameters. Starting from the constructed circuit, the parasitic parameters of each part of the high-frequency circuit are comprehensively considered.

[0047] (3) The method proposed in the present invention observes the form of oscillation from an experimental perspective, which is similar to the second-order oscillation problem. The Bode diagram of the transfer function of the shutdown transient is analyzed from the perspective of the complex frequency domain, which can avoid the risks during the experiment and prevent the tube from being over-voltage-broken. At the same time, the influence of the two parameters of resistance and capacitance are comprehensively considered during the design, and the oscillation peak value and oscillation frequency are taken as the suppression targets for comprehensive consideration of the values, thereby avoiding iterative trial and error and multiple complex calculations of a single resistance or capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is an overall implementation flow chart of the present invention.

[0049] Figure 2 It is a test circuit diagram of the high-frequency SiC half-bridge inverter of the present invention.

[0050] Figure 3 It is a transient equivalent circuit diagram of S2 being turned off when the half-bridge circuit of the present invention is working.

[0051] Figure 4 It is a simplified equivalent circuit diagram of the transient state when S2 is turned off when the half-bridge circuit of the present invention is working.

[0052] Figure 5 It is a simplified frequency domain RLC equivalent circuit diagram of the switch S2 of the present invention when it is turned off.

[0053] Figure 6 It is a simplified frequency domain equivalent circuit diagram of the S2 turn-off transient adding buffer circuit of the present invention.

[0054] Figure 7 It is the simulation verification circuit and waveform diagram of the present invention. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0056] To achieve the above object, the present invention proposes a buffer circuit design method based on a high-frequency SiC half-bridge inverter, such as Figure 1 As shown, the specific steps are as follows:

[0057] Step 1: Based on the half-bridge topology of the voltage source inverter, use the stacking design and welding technology of the printed circuit board to establish a high-frequency SiC half-bridge inverter test circuit, such as Figure 2 As shown, the circuit includes a discrete high-frequency SiC Mosfet low-side switch tube S1, a discrete high-frequency SiC Mosfet high-side switch tube S2, and a DC power supply V dc, drive circuit, first to fourth Schottky diodes D1 to D4, first to fourth buffer capacitors C1 to C4, first buffer resistor R1, second buffer resistor R2, wiring inductance L con and parasitic inductance L loop The freewheeling Schottky diode has the characteristics of high-speed turn-off and turn-on and is used to provide a current channel in the snubber circuit. The high-frequency oscillating current absorbs the peak energy through the parallel branch of the snubber capacitor and the snubber resistor, and also increases the damping effect in the current path to suppress the oscillation.

[0058] Among them, when selecting the switch tube, in order to ensure the requirement of high-speed turn-on and turn-off, the gate-source charge Q g and R G(int) As small as possible, select two identical SiC Mosfet switch tubes to connect the two tubes in series; use an isolated half-bridge driver chip to design the drive circuit, the driver chip is powered by a DSP control module, and provides two complementary control signals with dead time, and the auxiliary power supply is provided by an isolated power supply; the specific contents are as follows:

[0059] The discrete high-frequency SiC Mosfet low-side switch S1 includes a first gate inductor L G1 , the first drain inductance L D1 , the first source gate inductance L S1 , the first gate input resistor R G1(int) , the first on-resistance R DS1 , the first gate-source capacitance C GS1 , the first drain-source capacitance C DS1 , the first drain-gate capacitance C DG1 , the first internal body diode D S1 and the first diode junction capacitance C J1 ; The discrete high-frequency SiC Mosfet high-side switch S2 includes a second gate inductor L G2 , the second drain inductance L D2 , the second source gate inductance L S2 , the second gate input resistor R G2(int) , the second on-resistance R DS2 , the second gate-source capacitance C GS2 , the second drain-source capacitance C DS2 , the second drain-gate capacitance C DG2 , the second internal body diode D S2 and the second diode junction capacitance C J2 .

[0060] The driving circuit of the low-side switch tube S1 includes a first driving voltage V gs1 , the first driving resistor R g1 and the first driving inductor L g1 .

[0061] The driving circuit of the high-side switch tube S2 includes a second driving voltage V gs2 , the second driving resistor R g2 and the second driving inductor L g2 .

[0062] The first buffer resistor R1 and the second buffer capacitor C2 are connected in parallel to form a first buffer branch, and the second buffer resistor R2 and the fourth buffer capacitor C4 are connected in parallel to form a second buffer branch; the first on-resistance R DS1 、The first body diode junction capacitance C J1 and the first diode D S1 To form a parallel branch, the parallel branch is D S1 The equivalent model of the second on-resistance R DS2 , the second body diode junction capacitance C J2 and the second diode D S2 To form a parallel branch, the parallel branch is D S2 The equivalent model of .

[0063] The cathode of the first Schottky diode D1 is respectively connected to the second drain inductor L D2 One end of the parasitic inductance L loop The first end of the first Schottky diode D1 is connected to the first branch of the second buffer branch, the anode of the first Schottky diode D1 is connected to one end of the first buffer capacitor C1, and the parasitic inductance L loop The other end is connected to the DC voltage source V dc The other end of the first buffer capacitor C1 is connected to the anode of the second Schottky diode D2 and the first fulcrum of the first buffer branch, and the cathode of the second Schottky diode D2 is connected to the second driving power supply V gs2 The negative electrode, the second source gate inductor L s2 One end and wiring inductance L con The second branch of the first buffer branch is connected to the DC voltage source V dc The cathode of the fourth Schottky diode D4 and the anode of the second driving power supply V gs2 The negative electrode of the second source gate inductor L s2 The other end is connected to the second gate-source capacitor C GS2 One end of the second diode junction capacitance C J2 One end and the second drain-source capacitor C DS2 One end of the second gate-source capacitor C GS2 The other end is connected to the second drain-gate capacitor C DG2 One end and the second gate input resistor R G2(int) One end of the second diode is connected to the junction capacitance C J2 The other end is connected to the second drain-source capacitor C DS2 The other end of the second drain inductor LD2 The other end of the second drain-gate capacitor C DG2 The other end of the second gate input resistor R G2(int) The other end of the second gate inductor L G2 One end of the second gate inductor L G2 The other end is connected to the second driving resistor R g2 One end of the second drive resistor R g2 The other end is connected to the second driving inductor L g2 One end of the second drive inductor L g2 The other end is connected to the second driving power supply V gs2 positive connection.

[0064] Wiring inductance L con The other end is connected to the first drain inductor L D1 One end of the first drain inductor L is connected to the anode of the third Schottky diode D3, the cathode of the third Schottky diode D3 is connected to one end of the third buffer capacitor C3, the other end of the third buffer capacitor C3 is connected to the cathode of the fourth Schottky diode D4 and the second branch of the second buffer branch respectively, and the first drain inductor L D1 The other end is connected to the first drain-gate capacitor C DG1 One end of the first diode junction capacitance C J1 One end and the first drain-source capacitor C DS1 One end of the first drain-source capacitor C DS1 The other end is connected to the first diode junction capacitance C J1 The other end of the first source gate inductor L S1 One end of the first gate-source capacitor C GS1 One end of the first source-gate inductor L S1 The other end of the first gate-source capacitor C GS1 The other end is connected to the first drain-gate capacitor C DG1 The other end and the first gate input resistor R G1(int) One end of the first gate input resistor R G1(int) The other end of the first gate inductor L G1 One end of the first gate inductor L G1 The other end is connected to the first driving resistor R g1 One end of the first drive resistor R g1 The other end is connected to the first driving inductor L g1 One end of the first drive inductor L g1 The other end is connected to the first driving power supply V gs1 positive connection.

[0065] The driving circuit is used to provide positive and negative pulse periodic driving voltage. The driving voltage adjusts the current through the series driving resistor, where the driving resistor of the upper tube is R g2 , the driving resistance of the lower tube is R g1 The driving voltage provided turns on the switch tube in the positive half cycle and turns off the switch tube in the negative half cycle. Due to the isolation effect inside the chip, the entire driving circuit can be regarded as a series connection of a square wave voltage source that emits periodic positive and negative alternations and a driving resistor and a driving inductor. The driving inductor corresponding to the discrete high-frequency SiCMosfet low-side switch tube S1 is L g1 , the corresponding driving voltage source V gs1 ; The driving inductor corresponding to the discrete high-frequency SiC Mosfet high-side switch S2 is L g2 , the corresponding driving voltage source V gs2 .

[0066] Wiring inductance L con And all driving inductances are generated through PCB wiring.

[0067] Step 2: Obtain the parasitic parameters of the high-frequency SiC half-bridge inverter test circuit; the acquisition method is:

[0068] (1) Consult the relevant data sheet of the selected SiC Mosfet to obtain the parameters of gate-source capacitance, drain-source capacitance, drain-gate capacitance, and diode junction capacitance.

[0069] (2) Download the source file of the official simulation file corresponding to SiC Mosfet and obtain the parasitic inductance parameters of each pin. Since the two switches in the half-bridge circuit are the same, the corresponding pin parasitic parameters are also the same, that is, L D1 =L D2 =L D , L S1 =L S2 , L G1 =L G2 .

[0070] (3) Use the LCR digital bridge to obtain the DC bus inductance, and get the drive circuit inductance and wiring inductance. The collective formula is:

[0071]

[0072] Among them, L g Indicates loop inductance; l g and l con Respectively represent the PCB wiring distance between the drive circuit and the switch tube, W g and W con They are wiring widths, both in centimeters.

[0073] Step 3: Based on the equivalent circuit and parasitic parameters of the switch S1 in the high-frequency half-bridge test circuit when it is turned off transiently, establish a circuit model corresponding to the experimental circuit; Figure 3 The specific contents are as follows:

[0074] When the discrete high-frequency SiC Mosfet high-side switch S2 is in the on state, its internal on-resistance is extremely small. The internal body diode is regarded as an extremely small DC voltage source under the state of bearing forward voltage, which can be ignored compared with the DC power supply. The drain-source capacitance and the diode junction capacitance are bypassed. In order to simplify the circuit, the on-resistance is placed outside. Except for the drain-source inductance, all other parasitic parameters of S2 are bypassed. For the off state of S1, it is regarded as an internal open circuit. The external diode junction capacitance and the drain-source capacitance are connected in parallel to form a triangle connection with the drain-gate capacitance and the gate-source capacitance. The series connection of S2 and the wiring inductance and the pin inductance connected to S1 are unified as the pin inductance L' D , and then the internal parasitic capacitance of the triangle-connected switch tube is connected in series, and the driving resistor and the equivalent gate input resistor in the driving circuit are connected in series to form the total driving resistance R G , the gate pin and driver parasitic wiring inductance is equivalent to the driver inductance L' G , driving circuit and parasitic gate-source capacitance C GS and the inductance L of the SOURCE pin S The series branches are connected in parallel and then connected to the negative pole of the DC power supply.

[0075] Step 4: Calculate the equivalent resistance at the turn-off transient resonant frequency, simplify the circuit model in step 3, and perform complex frequency domain analysis on the equivalent series second-order circuit to solve the transfer function of the output voltage; the specific contents are:

[0076] The calculation formula for PCB (Printed Circuit Board) trace inductance is:

[0077]

[0078] Among them, L represents the PCB trace inductance, the unit is nanofarad; l represents the PCB trace inductance length, the unit is centimeter; W represents the PCB trace inductance width, the unit is centimeter; H represents the copper thickness, the unit is ounce.

[0079] According to the star-delta impedance transformation and the circuit model in step 3, the circuit parameters in the circuit model are transformed into the complex frequency domain for series-parallel simplification, such as Figure 4 As shown, the specific expression is:

[0080]

[0081] Where s represents the Laplace operator, L' looprepresents the simplified DC loop inductance, L' G represents the simplified total driver inductance, ω off Represents the circuit resonant frequency when turned off, R eq_G Represents the gate-source equivalent resistance, C G Represents the gate capacitance after star-delta transformation, C S Represents the source capacitance after star-delta transformation, R eq_S Represents the source equivalent resistance, R eq_D Represents the drain equivalent resistance, R eq Represents the total equivalent resistance, C D It represents the drain equivalent capacitance after star-delta transformation, L S represents the source-gate inductance, L D is the leakage inductance, R G(int) Represents the gate input resistance, R g Represents the driving resistance, L G Represents the gate inductance, L g Represents the driving inductance, C GS Represents the gate-source capacitance, C GD is the drain-gate capacitance, C DS represents the drain-source capacitance, C J Represents the diode junction capacitance, R DS Represents the on-resistance.

[0082] Figure 4 (a) shows the simplification of the transient circuit of S1 turning off. It can be seen from the figure that S2 is equivalent to a series connection of an on-resistance, a drain inductance and a source inductance. When S1 is turned off, it is equivalent to a mixed connection of multiple capacitors. Figure 4 (b) The equivalent circuit model of S1 in (a) when it is turned off uses a star-delta variation to simplify each capacitor branch; Figure 4 (c) represents the connection model of the equivalent resistance of each branch in (b) at the turn-off resonant frequency.

[0083] According to formulas (10) and (11), the equivalent RLC (Resistor Inductor Capacitor) series second-order circuit model of the low-side switch tube S1 in the high-frequency circuit when it is turned off transiently is obtained, as follows: Figure 5 As shown, relative to Figure 4 The parallel branch is simplified, and the transfer function G(s) of the turn-off voltage of the circuit model is:

[0084]

[0085] According to formula (12), the Bode plot is drawn to predict the oscillation frequency of the circuit model and the voltage gain at the oscillation frequency. At the same time, the high-frequency SiC half-bridge inverter test circuit is equivalent to the parallel form of RC (Resistor-Capacitance circuit) branches, as shown in Figure 6 As shown, relative to Figure 2 The freewheeling diode, switch tube model and drive circuit of the buffer circuit are simplified. The test circuit of the low-side switch tube S1 is connected in parallel to the total equivalent resistance and drain capacitance, and the output voltage transfer function with the buffer circuit is obtained. The specific formula is:

[0086]

[0087] Among them, V DS Represents DC voltage, R SN Represents the buffer resistor, C SN Represents the buffer capacitor.

[0088] Step 5: Based on the transfer function, obtain the resistance and capacitance values ​​of the buffer circuit to complete the design of the buffer circuit. The specific contents are:

[0089] (1) Taking the values ​​of the buffer capacitor and the buffer resistor as unknown quantities, selecting common parameters of film capacitors or MLCC capacitors, and taking the amplitude gain as the target, a three-dimensional graph is established using Matlab mathematical tools. The matching point of the buffer resistor and the buffer capacitor when the amplitude gain is less than 1.1 times the DC voltage is the optimal matching point, which is the value of the buffer circuit.

[0090] (2) According to the zero poles corresponding to the characteristic equation in the transfer function, adjust the resistance and capacitance values ​​so that the real part of the pole under the modal influence is on the negative half axis. When limiting the real root of the negative half axis, the resistance and capacitance values ​​are constrained. At this time, the commonly used C0G material capacitors and commonly used resistance values ​​within the constraint range are substituted into the transfer function to observe the oscillation frequency and gain, and then the values ​​of the buffer resistor and buffer capacitor are obtained. When selecting Schottky diodes, larger recovery current and smaller on-state voltage drop can achieve better oscillation spike suppression.

[0091] When the commonly used 10nF capacitor and 100 ohm resistor are selected through the transfer function, the oscillation amplitude presented by the transfer function is small and the oscillation frequency is low. Therefore, this value is selected and substituted into the LTspice simulation for verification, such as Figure 7 As shown in (a). Figure 7 (b) shows the voltage oscillation waveform without the designed snubber circuit. Figure 7 (c) shows the voltage waveform after using the designed buffer circuit. By comparison, it can be seen that the buffer circuit designed in the present invention effectively suppresses the peak oscillation during the shutdown overvoltage and improves the output voltage.

[0092] The embodiment of the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. It should be noted that when the processor executes the computer program, the specific steps of the method provided in the embodiment of the present invention are corresponding to the specific steps of the method provided in the embodiment of the present invention, and the processor has the functional modules and beneficial effects corresponding to the execution method. For technical details not described in detail in this embodiment, please refer to the method provided in the embodiment of the present invention.

[0093] The embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. It should be noted that when the computer program is executed by the processor, it corresponds to the specific steps of the method provided in the embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not described in detail in this embodiment, please refer to the method provided in the embodiment of the present invention.

[0094] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A buffer circuit design method based on a high-frequency SiC half-bridge inverter, characterized in that: include: Step 1: Based on the half-bridge topology of the voltage source inverter, a high-frequency SiC half-bridge inverter test circuit is established by using the stacking design and welding technology of the printed circuit board. The circuit includes a discrete high-frequency SiC Mosfet low-side switch tube S1, a discrete high-frequency SiC Mosfet high-side switch tube S2, and a DC power supply V dc , drive circuit, first to fourth Schottky diodes D1 to D4, first to fourth buffer capacitors C1 to C4, first buffer resistor R1, second buffer resistor R2, wiring inductance L con and parasitic inductance L loop ; Among them, the low-side switch tube S1 and the high-side switch tube S2 have the same structure; Step 2, obtaining parasitic parameters of a high-frequency SiC half-bridge inverter test circuit; Step 3, according to the equivalent circuit and parasitic parameters of the switch S1 in the high-frequency half-bridge test circuit when it is turned off transiently, establish a circuit model corresponding to the experimental circuit; Step 4: Calculate the equivalent resistance at the turn-off transient resonant frequency, simplify the circuit model in step 3, and perform complex frequency domain analysis on the equivalent series second-order circuit to solve the transfer function of the output voltage; Step 5: Based on the third-order output voltage transfer function after adding the equivalent buffer circuit, constrain the poles of the characteristic root equation to obtain the resistance and capacitance values ​​of the buffer circuit, and complete the design of the buffer circuit.

2. The buffer circuit design method based on high-frequency SiC half-bridge inverter according to claim 1 is characterized in that: In step 1, the structure of the high-frequency SiC half-bridge inverter test circuit is: The discrete high-frequency SiC Mosfet low-side switch S1 includes a first gate inductor L G1 , the first drain inductance L D1 , the first source gate inductance L S1 , the first gate input resistor R G1(int) , the first on-resistance R DS1 , the first gate-source capacitance C GS1 , the first drain-source capacitance C DS1 , the first drain-gate capacitance C DG1 , the first internal body diode D S1 and the first diode junction capacitance C J1 ; The discrete high-frequency SiC Mosfet high-side switch S2 includes a second gate inductor L G2 , the second drain inductance L D2 , the second source gate inductance L S2 , the second gate input resistor R G2(int) , the second on-resistance R DS2 , the second gate-source capacitance C GS2 , the second drain-source capacitance C DS2 , the second drain-gate capacitance C DG2 , the second internal body diode D S2 and the second diode junction capacitance C J2 ; The driving circuit of the low-side switch tube S1 includes a first driving voltage V gs1 , the first driving resistor R g1 and the first driving inductor L g1 ; The driving circuit of the high-side switch tube S2 includes a second driving voltage V gs2 , the second driving resistor R g2 and the second drive circuit inductor L g2 ; The first buffer resistor R1 and the second buffer capacitor C2 are connected in parallel to form a first buffer branch, and the second buffer resistor R2 and the fourth buffer capacitor C4 are connected in parallel to form a second buffer branch; the first on-resistance R DS1 、The first body diode junction capacitance C J1 and the first diode D S1 To form a parallel branch, the parallel branch is D S1 The equivalent model of the second on-resistance R DS2 , the second body diode junction capacitance C J2 and the second diode D S2 To form a parallel branch, the parallel branch is D S2 Equivalent model of The cathode of the first Schottky diode D1 is respectively connected to the second drain inductor L D2 One end of the parasitic inductance L loop The first end of the first Schottky diode D1 is connected to the first branch of the second buffer branch, the anode of the first Schottky diode D1 is connected to one end of the first buffer capacitor C1, and the parasitic inductance L loop The other end is connected to the DC voltage source V dc The other end of the first buffer capacitor C1 is connected to the anode of the second Schottky diode D2 and the first fulcrum of the first buffer branch, and the cathode of the second Schottky diode D2 is connected to the second driving power supply V gs2 The negative electrode, the second source gate inductor L s2 One end and wiring inductance L con The second branch of the first buffer branch is connected to the DC voltage source V dc The cathode of the fourth Schottky diode D4 and the anode of the second driving power supply V gs2 The negative electrode of the second source gate inductor L s2 The other end is connected to the second gate-source capacitor C GS2 One end of the second diode junction capacitance C J2 One end and the second drain-source capacitor C DS2 One end of the second gate-source capacitor C GS2 The other end is connected to the second drain-gate capacitor C DG2 One end and the second gate input resistor R G2(int) One end of the second diode is connected to the junction capacitance C J2 The other end is connected to the second drain-source capacitor C DS2 The other end of the second drain inductor L D2 The other end of the second drain-gate capacitor C DG2 The other end of the second gate input resistor R G2(int) The other end of the second gate inductor L G2 One end of the second gate inductor L G2 The other end is connected to the second driving resistor R g2 One end of the second drive resistor R g2 The other end is connected to the second driving inductor L g2 One end of the second drive inductor L g2 The other end is connected to the second driving power supply V gs2 The positive connection of Wiring inductance L con The other end is connected to the first drain inductor L D1 One end of the first drain inductor L is connected to the anode of the third Schottky diode D3, the cathode of the third Schottky diode D3 is connected to one end of the third buffer capacitor C3, the other end of the third buffer capacitor C3 is connected to the cathode of the fourth Schottky diode D4 and the second branch of the second buffer branch respectively, and the first drain inductor L D1 The other end is connected to the first drain-gate capacitor C DG1 One end of the first diode junction capacitance C J1 One end and the first drain-source capacitor C DS1 One end of the first drain-source capacitor C DS1 The other end is connected to the first diode junction capacitance C J1 The other end of the first source gate inductor L S1 One end of the first gate-source capacitor C GS1 One end of the first source-gate inductor L S1 The other end of the first gate-source capacitor C GS1 The other end is connected to the first drain-gate capacitor C DG1 The other end and the first gate input resistor R G1(int) One end of the first gate input resistor R G1(int) The other end of the first gate inductor L G1 One end of the first gate inductor L G1 The other end is connected to the first driving resistor R g1 One end of the first drive resistor R g1 The other end is connected to the first driving inductor L g1 One end of the first drive inductor L g1 The other end is connected to the first driving power supply V gs1 positive connection.

3. The buffer circuit design method based on high-frequency SiC half-bridge inverter according to claim 1 is characterized in that: In step 1, an isolated half-bridge driver chip is used to design a drive circuit. The driver chip is powered by a DSP control module and provides two complementary control signals with dead time. The auxiliary power supply is provided by an isolated power supply. The driving circuit is used to provide positive and negative pulse periodic driving voltage. The driving voltage adjusts the current through the series driving resistor, where the driving resistor of the upper tube is R g2 , the driving resistance of the lower tube is R g1 , the driving voltage provided turns on the switch tube in the positive half cycle and turns off the switch tube in the negative half cycle; the driving inductor corresponding to the discrete high-frequency SiC Mosfet low-side switch tube S1 is L g1 , the corresponding driving voltage source V gs1 ; The driving inductor corresponding to the discrete high-frequency SiC Mosfet high-side switch S2 is L g2 , the corresponding driving voltage source V gs2 .

4. The buffer circuit design method based on high-frequency SiC half-bridge inverter according to claim 2 is characterized in that: In step 1, the wiring inductance L con And all driving inductances are generated through PCB wiring.

5. The buffer circuit design method based on high-frequency SiC half-bridge inverter according to claim 1, characterized in that: In step 2, obtaining the parasitic parameters includes: (1) Consult the relevant data sheet of the selected SiC Mosfet to obtain the parameters of gate-source capacitance, drain-source capacitance, drain-gate capacitance, and diode junction capacitance; (2) Download the source file of the official simulation file corresponding to SiC Mosfet and obtain the parasitic inductance parameters of each pin; (3) Use the LCR digital bridge to obtain the DC bus inductance and obtain the driving inductance and wiring inductance.

6. The buffer circuit design method based on high-frequency SiC half-bridge inverter according to claim 2 is characterized in that: In step 3, the circuit model corresponding to the experimental circuit is established, including the following contents: When the discrete high-frequency SiC Mosfet high-side switch S2 is in the on state, the second internal body diode D is ignored. S2 The second on-resistance R DS2 Placed outside the switch tube, all parasitic parameters except the drain and source inductance are bypassed; when the discrete high-frequency SiC Mosfet low-side switch tube S1 is in the off state, it is regarded as an internal open circuit, and the first diode junction capacitance C J1 and the first drain-source capacitance C DS1 After being connected in parallel with the first drain-gate capacitor C DG1 , the first gate-source capacitance C GS1 Form a triangle connection, wiring inductance L con and the first drain inductance L D1 Connect in series to get the inductance L' D , inductance L' D The parasitic capacitor connected in series with the triangle, the first drive resistor R g1 and the first gate input resistor R G1(int) The total resistance R of the first drive circuit is obtained by connecting them in series G1 , the first driving inductor L g1 and the first gate inductor L G1 Equivalent to the total driving inductance L' G The gate parasitic parameters of the switch tube S1 and the parameters in the drive circuit are combined with the first gate-source capacitance C GS1 and the first source-gate inductance L S1 After parallel connection, it is connected to the negative pole of the DC voltage source, and then the circuit model corresponding to the experimental circuit is obtained.

7. The buffer circuit design method based on high-frequency SiC half-bridge inverter according to claim 1, characterized in that: In step 4, solving the transfer function for the output voltage includes the following: The calculation formula for PCB trace inductance is: Among them, L represents the PCB trace inductance; l represents the PCB trace length; W represents the PCB trace inductance width; H represents the copper thickness; According to the star-delta impedance transformation and the circuit model in step 3, the circuit parameters are transformed into the complex frequency domain for series-parallel simplification. The specific expression is: Where s represents the Laplace operator, L' loop represents the simplified DC loop inductance, L' G represents the simplified total driver inductance, ω off Represents the circuit resonant frequency when turned off, R eq_G Represents the gate-source equivalent resistance, C G Represents the gate capacitance after star-delta transformation, C S Represents the source capacitance after star-delta transformation, R eq_S Represents the source equivalent resistance, R eq_D Represents the drain equivalent resistance, R eq Represents the total equivalent resistance, C D It represents the drain equivalent capacitance after star-delta transformation, L S represents the source-gate inductance, L D Represents the leakage inductance, R G Represents the total drive resistance, R G(int) Represents the gate input resistance, R g Represents the driving resistance, L G Represents the gate inductance, L g Represents the driving inductance, C GS Represents the gate-source capacitance, C GD is the drain-gate capacitance, C DS represents the drain-source capacitance, C J Represents the diode junction capacitance, R DS represents the on-resistance; According to formulas (1) and (2), the equivalent RLC series second-order circuit model of the low-side switch tube S1 in the high-frequency circuit when it is turned off is obtained, and its turn-off voltage transfer function G(s) is: According to formula (3), the Bode diagram is drawn to predict the oscillation frequency of the circuit model and the voltage gain at the oscillation frequency. At the same time, the buffer circuit of the high-frequency SiC half-bridge inverter test circuit is equivalent to the parallel form of RC branches. For the test circuit of the low-side switch tube S1, it is connected in parallel to the total equivalent resistance and drain capacitance to obtain the output voltage transfer function with the buffer circuit added. The specific formula is: Among them, V DS Represents DC voltage, R SN Represents the buffer resistor, C SN Represents the buffer capacitor.

8. The buffer circuit design method based on high-frequency SiC half-bridge inverter according to claim 1, characterized in that: In step 5, the value of the buffer circuit is obtained according to the transfer function, including two methods: (1) Taking the values ​​of the buffer capacitor and the buffer resistor as unknown quantities and the amplitude gain as the target, a three-dimensional graph is established using Matlab mathematical tools. The matching point of the buffer resistor and the buffer capacitor when the amplitude gain is less than 1.1 times the DC voltage is the optimal matching point, which is the value of the buffer circuit; (2) According to the zeros and poles corresponding to the characteristic equation in the transfer function, the values ​​of the resistors and capacitors are adjusted so that the real part of the poles under the influence of the mode is on the negative half axis. The real roots of the negative half axis are restricted to constrain the values ​​of the resistors and capacitors. The capacitor and resistor values ​​within the constraint interval are substituted into the transfer function to obtain the values ​​of the buffer resistor and the buffer capacitor.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method for designing a snubber circuit based on a high-frequency SiC half-bridge inverter according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for designing a snubber circuit based on a high-frequency SiC half-bridge inverter according to any one of claims 1 to 8 is executed.

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