Multi-level controller with lookup table

Abstract

The invention provides a multi-level controller with a lookup table. A controller for a multi-stage power converter utilizes a lookup table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement a complex set of control states for the multi-stage power converter. Since the set of control states can be pre-processed, the LUT is well suited to so select such control states. This technique can be fast because the delay is only LUT access time, rather than propagation delay through a complex combinatorial logic network. A fast flash ADC is designed to achieve all of the following properties: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements to properly balance flying capacitor voltages in a multi-stage converter cell.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and more particularly to controllers for multi-level power converters. Background Art

[0002] Many electronic products, especially mobile computing and / or communication products and components (e.g., notebook computers, ultrabook computers, tablet devices, LCD and LED displays) require multiple voltage levels. For example, a radio frequency (RF) transmitter power amplifier may require a relatively high voltage (e.g., 12V or higher), while logic circuit systems may require low voltage levels (e.g., 1V to 3V). Still other circuit systems may require intermediate voltage levels (e.g., 5V to 10V).

[0003] DC power converters are commonly used to generate lower or higher voltages from common power sources such as batteries, solar cells, and rectified AC sources. Power converters that generate lower output voltage levels from higher input voltage sources are often called buck converters because the output voltage V OUT Less than the input voltage V IN , so the converter "steps down" the input voltage. Power converters that generate higher output voltage levels from lower input voltage supplies are often called boost converters because V OUT Greater than V IN Some power converters may be buck converters or boost converters, depending on which terminals are used for input and output. Some power converters may provide an inverting output. Some power converters may output a current that is a function of a generated voltage derived from an input voltage.

[0004] One type of DC power converter, known as a multi-level power converter, includes a charge transfer capacitor as an energy storage element coupled by a controlled power switch to transfer charge from V IN Transfer to V OUT . Such charge transfer capacitors are often called "fly capacitors" or "pump capacitors". Each time a flying capacitor is used (i.e., not bypassed), the electrical energy flowing through it typically charges or discharges the flying capacitor. This creates a control problem: in what configuration and sequence can the flying capacitors be switched while maintaining the average voltage across the flying capacitors? This is a charge balancing problem introduced by multi-level converter circuits - proper multi-level power converter operation requires that the flying capacitor voltages be continuously balanced with the corresponding target voltages.

[0005] As the complexity of multi-level converter circuits increases, determining a suitable charge balancing method may become extremely difficult. In particular, the complexity of the algorithm for flying capacitor voltage balancing increases dramatically with the number of flying capacitors due to priority requirements and the interdependent and restrictive capacitor voltage control that exists due to the limited options for power switch configurations for specific target levels. Most conventional control methods rely on large and complex combinational logic networks to establish a series of associated state changes in an attempt to achieve charge balance. Control systems based on long sequences of power switch states typically assume that all system variables, such as input voltage and output current, are constant during the sequence. This is unrealistic for real-world environments, where all system variables are often dynamic. In addition, the charge balancing calculation should be completed very quickly on a cycle-by-cycle basis, especially when the load current on the power converter is very high. High load current changes the flying capacitor voltage very quickly depending on the capacitor value.

[0006] Therefore, there is a need for circuits and methods for more effectively and efficiently balancing the voltage across each flying capacitor of a multi-level converter circuit. The present invention addresses this need and others. Summary of the invention

[0007] The present invention comprises a controller for a multi-level power converter that utilizes a lookup table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement an algorithm that includes a complex set of control states for the multi-level power converter. The LUT is well suited for selecting such control states because the algorithm can be pre-processed. This technique can be fast because the delay is only the LUT access time, not the propagation delay through a complex combinational logic network. The fast flash ADC is designed to achieve all of the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements of properly balancing the flying capacitor voltages in the multi-level converter cells.

[0008] The algorithm for balancing the flying capacitor voltages may need to adapt to changes in conditions and / or configurations - however fixed combinational logic does not have the flexibility for such a task. In particular, the voltage across each flying capacitor is a dynamic variable whose value is a useful and often necessary factor in determining the charge balance across the flying capacitors of a multi-stage converter circuit. For example, the voltage of some flying capacitors may change faster than the voltage of other flying capacitors, and such rapidly changing flying capacitors may require a higher priority to balance their voltages. The present invention is able to flexibly adapt to such dynamic conditions and / or configurations.

[0009] One embodiment includes a controller for an M-class power converter unit having one or more flying capacitors coupled to a set of power switches, where M≥3, the controller comprising: a voltage level selector configured to generate and output a first set of address bits; a set of one or more analog-to-digital converters, each member of the set configured to couple to an associated flying capacitor of the one or more flying capacitors and output a first bit indicating whether a voltage on the associated flying capacitor is above or below a reference target level, and a second bit indicating whether the voltage on the associated flying capacitor is within or outside a target window; two bits, wherein the first bit and the second bit of the group of one or more analog-to-digital converters together constitute a second group of address bits; a lookup table, which is coupled to the voltage level selector and the group of one or more analog-to-digital converters, the lookup table stores a group of switch state selector values ​​and outputs the selected switch state selector value in response to receiving an address that includes a cascade of the first group of address bits and the second group of address bits; and an M-level switch state selector, which is configured to be coupled to the M-level power converter unit to receive at least a portion of the selected switch state selector value from the lookup table and generate a group of power switch state settings based on the received portion of the selected switch state selector value.

[0010] The details of one or more embodiments of the invention are set forth in the following drawings and description. Other features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of a circuit including a prior art power converter.

[0012] Figure 2 Can be used as Figure 1 Schematic diagram of a general prior art M-level multi-level converter unit.

[0013] Figure 3 Is from Figure 2 Schematic diagram of a flying capacitor Cx, showing the corresponding "controlled" power switch group.

[0014] Figure 4 is a block diagram of one embodiment of control circuitry for an M-stage converter cell coupled to an output block including an inductor L and an output capacitor COUT.

[0015] Figure 5A is a block diagram of a first embodiment of an improved controller circuit for an M-class converter cell according to the present invention.

[0016] Figure 5B is a table showing the effect of switch state selector values ​​on the power switches of an example 5-level converter cell when the inductor L current is positive.

[0017] Figure 5C is a table showing the effect of switch state selector values ​​on the power switches of an example 5-level converter cell when the inductor L current is negative.

[0018] Figure 5D is a block diagram of a second embodiment of an improved controller circuit for an M-class converter cell according to the present invention.

[0019] Figure 5E is a block diagram of a third embodiment of an improved controller circuit for an M-class converter cell according to the present invention.

[0020] Figure 6 is a block diagram showing details of another version of the improved controller of level 5.

[0021] Figure 7 It is particularly suitable for Figure 6 A schematic diagram of an embodiment of a circuit for use with a 2-bit fast flash ADC circuit.

[0022] Figure 8 is the indication for V HI 、V TARGET 、V LO and V CxIN An example voltage is a graph of voltage versus time.

[0023] Fig. 9 is a top view of a substrate which may be, for example, a printed circuit board or a chip module substrate (eg, a thin film sheet).

[0024] Fig.10 is a process flow diagram illustrating one method for controlling M-level power converter cells having one or more flying capacitors coupled to a set of power switches, where M≥3.

[0025] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0026] The present invention includes a controller for a multi-level power converter that utilizes a lookup table (LUT) in conjunction with a fast flash analog-to-digital converter (ADC) circuit to implement an algorithm that includes a set of complex control states for the multi-level power converter. Since the algorithm can be pre-processed, the LUT is well suited for selecting such control states. The technique can be fast because the delay is only the LUT access time, not the propagation delay through a complex combinational logic network. The fast flash ADC includes a 2-bit implementation that is designed to achieve all of the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing the flying capacitor voltages in the multi-level converter cells.

[0027] The algorithm for balancing the flying capacitor voltages may need to adapt to changes in conditions and / or configurations - however fixed combinational logic does not have the flexibility for such a task. In particular, the voltage across each flying capacitor is a dynamic variable whose value is a useful and often necessary factor in determining the charge balance across the flying capacitors of a multi-stage converter circuit. For example, the voltage of some flying capacitors may change faster than the voltage of other flying capacitors, and such rapidly changing flying capacitors may require a higher priority to balance their voltages. The present invention is able to flexibly adapt to such dynamic conditions and / or configurations.

[0028] Figure 1 1 is a block diagram of a circuit including a prior art power converter 100. In the example shown, the power converter 100 includes a converter unit 102 and a controller 104. The converter unit 102 is configured to receive an input voltage V across terminals N1 and N3 (common) from a voltage source 106 (e.g., a battery). IN , and the input voltage V IN Transformed into an output voltage V across terminals N2 and N3 (common) OUT . Output voltage V OUT Usually coupled to the output capacitor C OUT The output capacitor C OUT A load represented by an equivalent resistance R may be connected across the two terminals. In some embodiments of the power converter 100 , auxiliary circuitry (not shown) such as a bias voltage generator, a clock generator, a voltage control circuit, etc. may also be present and coupled to the converter unit 102 and the controller 104 .

[0029] The controller 104 receives a set of input signals and generates a set of output signals. Some of these input signals arrive along a signal path 110 connected to the converter unit 102. Some of the input signals carry information indicating the operating state of the converter unit 102. The controller 104 also typically receives at least a clock / timing signal CLK and one or more external input / output signals I / O, which may be analog, digital (encoded or direct signal lines), or a combination of the two. Based on the received input signals, the controller 104 generates a set of control signals that are returned to the converter unit 102 on the signal path 110, which control the internal components of the converter unit 102 (e.g., internal integrated or external discrete switches, such as FETs, especially MOSFETs) so that the converter unit 102 switches V IN Convert to V OUT .

[0030] In some power converter designs, the converter unit 102 may include a multi-level converter circuit. For example, Figure 2 Can be used as Figure 1 A schematic diagram of a general prior art M-level multi-level converter unit 400 of the converter unit 102 of FIG. 1 is shown. A set of power switches S1 to S[2*(M-1)] are coupled in series at V IN and circuit ground, where M ≥ 3. The group of power switches is organized into switch pairs: S1 & S2, S3 & S4, ... S[2*(M-2)+1] & S[2*(M-1)]. A group of M-2 flying capacitors Cx are coupled in series with a particular corresponding power switch (see Figure 3 ), and are coupled in parallel with the power switches between these specific power switches. In terms of switch pairs, there are M-1 pairs of power switches, or one more than the number of flying capacitors. The corresponding target average voltage across each flying capacitor Cx in the M-level multi-level converter unit 400 is given by the formula V Cx =(M-2)*V IN / (M-1) gives [note that a 2-level converter cell has no capacitors]. Thus, for example, for a 5-level converter cell (M=5), there are 3 flying capacitors C1 to C3 and 4 pairs of power switches S1 to S8, and the corresponding target average voltage across the 3 flying capacitors C1 to C3 is V C1 =1 / 4V IN 、V C2 =1 / 2V IN and V C3 =3 / 4V IN .

[0031] The optional inductor L is coupled to the output capacitor C OUT and coupled to a node L between power switches S1 and S2 X. Output shunt capacitor C OUT The voltage across the two ends is V OUT The inductor L doubles as a virtual current source, which moves all the charge between the flying capacitor Cx. This produces a very efficient form of charge transfer, but since the current may be in the positive direction (to V OUT ) or negative direction (away from V OUT ) flows on the flying capacitor Cx, exacerbating the charge balance problem.

[0032] Figure 3 Is from Figure 2 300 of a flying capacitor Cx, showing the corresponding "controlled" power switch group. Each flying capacitor Cx has a first terminal coupled between an external high-side power switch S[2*x+1] and an internal high-side power switch S[2*x-1], where "high side" refers to the V IN side. Each flying capacitor Cx has a second terminal coupled between an external low-side power switch S[2*x+2] and an internal low-side power switch S[2*x], where "low side" refers to the reference potential side of the converter circuit (usually the circuit ground GND). Therefore, for a multi-stage converter unit 200 with M=3, the first terminal of a single flying capacitor C1 (i.e., x=1) will be coupled between the external high-side power switch S3 and the internal high-side power switch S1, and the second terminal of the capacitor C1 will be coupled between the internal low-side power switch S2 and the external low-side power switch S4. Therefore, each flying capacitor Cx within the multi-stage converter unit 200 has four associated power switches, which can affect the current flowing through the flying capacitor Cx and most of the power switches are shared between adjacent flying capacitors Cx (for example, Figure 2 , S3, S5, S4 and S6 in the circuit).

[0033] Control circuitry for four associated power switches that can affect the current flowing through a particular flying capacitor Cx sets the states of those associated power switches based in part on the voltage across the flying capacitor Cx.

[0034] Flying capacitor Cx voltage V Cx should be balanced quickly (on a cycle-by-cycle time scale or shorter, where each cycle may be on the order of about 1 μs) to reach the correct target voltage level (e.g., 1 / 4 V IN , 1 / 2V INetc.). One sign that the flying capacitors are starting to lose balance is that the expected internal voltage level will deviate more and more from the target voltage level over time, which will force the control loop to adjust the duty cycle of the power converter to compensate and introduce subharmonic behavior; ultimately, if not checked, the power converter may become unregulated. One way to digitize the voltage information of the flying capacitors Cx is to convert the voltage across each associated capacitor into a digital signal using a conventional flash ADC coupled to the corresponding capacitors. Conventional flash ADCs (also known as direct conversion ADCs) use a linear voltage ladder with a comparator at each "rung" of the ladder to compare the input voltage to a continuous reference voltage. The output of these comparators is typically fed into a digital encoder, which converts the input into a binary value. In order to obtain the capacitor voltage with sufficient resolution to achieve the specified voltage balance tolerance, a large number of bits is typically required. For example, for V IN =48V, an 8-bit flash ADC will have a resolution of 1 / 2LSB, which is 0.5*48 / 256=94mV. If the voltage balance is specified to be within 100mV, an 8-bit ADC is required, but such an ADC requires 255 comparators and therefore has the problem of high cost in terms of integrated circuit (IC) area and power consumption. Using conventional design methods, the three flying capacitors C1, C2, C3 of a 5-level multi-level converter unit require a total of three 8-bit flash ADCs, resulting in 768 comparators and even higher IC area and power consumption.

[0035] The multi-stage converter circuit couples the flying capacitors Cx in different combinations to lower or raise L X As described above, each time a flying capacitor is used (i.e., not bypassed), the power flowing through it typically charges or discharges the flying capacitor, which raises the following control problem: in what configuration and sequence can the flying capacitors be switched while maintaining their average voltage?

[0036] It is relatively easy to solve the charge balancing problem in a 3-level converter circuit to maintain an average voltage across a single flying capacitor (again, a 2-level converter circuit lacks a flying capacitor). For example, in a 3-level converter circuit, there is only one way to X Level 1 (GND) and Level 3 (V IN ) Voltage level (see Figure 2 )——For these L X voltage level does not use a single flying capacitor C1. However, for node L X Level 2 (1 / 2V IN) voltage level, two independent power switch states can be used: one power switch state charges capacitor C1 (S3 and S2 are closed, S1 and S4 are open), and the other power switch state discharges the capacitor (S3 and S2 are open, S1 and S4 are closed). Therefore, the control of the 3-level converter circuit is quite simple: each time the power converter unit switches state to level 2, the controller can alternate between charging and discharging the single capacitor C1 to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help decide the charging state or the discharging state. For example, if the capacitor voltage is below 1 / 2V IN , the controller will choose to charge, and if the capacitor voltage is higher than 1 / 2V IN , the controller will choose to discharge.

[0037] Higher level converter circuits (M ≥ 4) reveal the charge balancing difficulties when there are more flying capacitors. For example, in a 4-level converter unit, L X The level 1 voltage level (GND) and level 4 voltage level (V IN ) are each determined by a single switch state. However, L X Level 2 voltage level (1 / 3V IN ) and Level 3 voltage levels (2 / 3V IN ) can each be implemented in any of three different switching states. At even higher order multi-level converter circuits, there may be more switching states for generating V IN and GND. Therefore, the problem is more serious in the case of a 5-level converter circuit. X The level 1 voltage level (GND) and level 5 voltage level (V IN ) are each determined by a single switch state. However, L X Level 2 voltage level (1 / 4V IN ) and Level 4 voltage levels (3 / 4V IN ) can each be realized in any of four different switching states, and L X Level 3 voltage level (1 / 2V IN ) can each be implemented in any of six different switching states.

[0038] It is clear from these examples that determining an appropriate charge balancing approach can become extremely difficult as the complexity of multi-level converter circuits increases. As mentioned previously, most conventional control approaches rely on establishing a sequence of linked state changes to attempt to achieve charge balancing. Control systems based on long sequences of switching states typically assume that all system variables—such as input voltage and output current—are constant during the sequence. This is unrealistic for real-world environments, where all system variables are often dynamic.

[0039] Figure 4 is used to couple to the inductor L and output capacitor C OUT 4 is a block diagram of one embodiment of a control circuit system 400 for an M-level converter unit 402 having an output block 404 (conceptually, the inductor L may also be considered to be included within the M-level converter unit 402). The example control circuit system 400 is adapted according to the teachings set forth in U.S. patent application serial number 17 / 560,767, entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter,” filed on December 23, 2021, which is assigned to the assignee of the present invention, and the contents of which are incorporated by reference. However, the present invention may be used in conjunction with other types of control circuit systems for the M-level converter unit 402.

[0040] The control circuit system 400 is used as a control loop coupled to the output of the M-level converter unit 402 and to the power switch control input of the M-level converter unit 402. In general, the control circuit system 400 is configured to monitor the output (e.g., voltage and / or current) of the M-level converter unit 402 and take into account V INA set of power switch control inputs to the M-level converter unit 402 is dynamically generated according to changes in the output load, and the set of power switch control inputs attempts to stabilize the output voltage and / or current at a specified value. In an alternative embodiment, the control circuit system 400 can be configured to monitor the input (e.g., voltage and / or current) of the M-level converter unit 402 and / or one or more internal nodes of the M-level converter unit 402 (e.g., the voltage across one or more flying capacitors Cx or the current through one or more power switches). Therefore, most generally, the control circuit system 400 can be configured to monitor the voltage and / or current of the nodes (e.g., input terminals, internal nodes, or output terminals) of the M-level converter unit 402. The control circuit system 400 can be incorporated into the overall controller 104 of the power converter 100 for implementing the M-level converter unit 402 or separated from the overall controller 104, and a portion of the control circuit system 400 can be implemented with a digital microcontroller.

[0041] The first block includes a feedback controller 406, which can be a controller such as a fixed frequency voltage mode or current mode controller, a constant on-time controller, a hysteretic controller, or any other variation. The feedback controller 406 is shown coupled to V from the M-stage converter unit 402. OUT In an alternative embodiment, feedback controller 406 may be configured to monitor the input of M-level converter unit 402 and / or internal nodes of M-level converter unit 402. Feedback controller 406 generates a signal directly or indirectly indicating V OUT The signal of the voltage at the M-stage converter unit 402 generally determines which of the following needs to be done in order to maintain V OUT The expected value of: charging, discharging, or tri-state (i.e., open circuit, in which no current flows).

[0042] In the example shown, the feedback controller 406 includes a feedback circuit 408, a compensation circuit 410, and a pulse width modulation (PWM) generator 412. The feedback circuit 408 may, for example, include a feedback loop voltage detector that converts V OUT (or V OUT The attenuated version of V OUT The target voltage (which can be dynamic) is compared to a reference voltage and the output is used to indicate V OUT A control signal is used to determine whether the voltage is above or below the target voltage. A feedback loop voltage detector can be implemented using a comparison device such as an operational amplifier (op-amp) or a transconductance amplifier (gm amplifier).

[0043] The compensation circuit 410 is configured to stabilize the closed-loop response of the feedback controller 406 by avoiding unintentional generation of positive feedback that may cause oscillations and controlling overshoot and ringing in the step response of the feedback controller 406. The compensation circuit 410 may be implemented in a known manner and may include LC and / or RC circuits.

[0044] PWM generator 412 generates the actual PWM control signal that ultimately sets the duty cycle of the power switches of M-stage converter unit 402. In some embodiments, PWM generator 412 may deliver an additional optional control signal CTRL, which indicates, for example, V OUT The magnitude of the difference from the reference voltage (thus indicating that some levels of the M-stage converter unit 402 should be bypassed to achieve a higher or lower level) and the direction of the difference (e.g., V OUT In other embodiments, the optional control signal CTRL may be provided from the output of the compensation circuit 410, or from the output of the feedback circuit 408, or from a signal coupled to, for example, V OUT A separate comparator (not shown) is used to obtain the selectable control signal CTRL. One purpose of the selectable control signal CTRL is to know V OUT How close to the target output voltage is that this may be useful for advanced control algorithms, allowing OUT Faster charging of the inductor L in case of severe under-regulation.

[0045] The second block includes an M-level controller 414, the main function of which is to select the desired V OUT The power switching state of the charge balance state on the flying capacitor within the M-stage converter unit 402 is simultaneously maintained regardless of which power switching state or power switching states were used in the past.

[0046] The M-level controller 414 includes a voltage level selector 416 that receives the PWM control signal and an additional control signal CTRL (if available). In addition, the voltage level selector 416 can be coupled to V OUT and / or V IN The function of the voltage level selector 416 is to convert the received signal to a target output voltage level (eg, on a cycle-by-cycle basis). The voltage level selector 416 will typically take into account at least V OUT and V IN to determine which target level should charge or discharge the output of the M-stage converter unit 402 at the desired rate.

[0047] The output of the voltage level selector 416 is coupled to an M-level switch state selector 418. The M-level switch state selector 418 determines which power switch state should be preferred for capacitor charge balancing for the desired output level, given the target level generated by the voltage level selector 416. The output of the M-level switch state selector 418 is coupled to the power switches of the M-level converter unit 402 (through appropriate level shifter circuits and driver circuits, as may be required for a particular converter unit), and includes the power switch state settings determined by the M-level switch state selector 418 (which selects the configuration of the power switches within the M-level converter unit 402 corresponding to the selected target level).

[0048] Typically (but not always), the voltage level selector 416 and the M-level switch state selector 418 change their states only when the PWM signal changes. For example, when the PWM signal goes high, the voltage level selector 416 selects which level causes the charging of the inductor L, and the M-level switch state selector 418 sets which version of the switch setting is used for that level. Then, when the PWM signal goes low, the voltage level selector 416 selects which level should discharge the inductor L, and the M-level switch state selector 418 sets which version of the level is used. Therefore, the voltage level selector 416 and the M-level switch state selector 418 usually change states only when the PWM signal changes (the PWM signal is actually their clock signal). However, there may be situations or events where the CTRL signal is expected to change the state of the voltage level selector 416. In some embodiments, it may be useful to include the following timing function: the timing function forces the M-level switch state selector 418 to periodically re-evaluate the best version of the power switch state, for example, in order to avoid being "stuck" at one level for a long time, which may cause charge imbalance. Another situation is when the inductor current changes polarity - at this instant, the M-stage switch state selector 418 can change the switch state to continue to properly charge or discharge the flying capacitor.

[0049] In an implementation utilizing the teachings set forth in the above-referenced patent application entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter,” the M-level controller 414 implements a control method for the M-level converter unit 402 that selects L at each X The voltage level at the node selects the substantially optimal power switch state that moves the flying capacitor Cx to the charge balance state, regardless of which power switch state or states were used in the past. Therefore, such a multi-level converter circuit freely selects different power switch states or states in each switching cycle. Xvoltage level without tracking any previous power switch state or sequence of power switch states.

[0050] In some embodiments, the M-level switch state selector 418 can take into account the current I flowing through the inductor L by means of an optional current measurement input 420. L This can be achieved in a conventional manner.

[0051] Figure 4 One significant benefit of the control circuitry shown is that it enables the generation of voltages in the boundary region between voltage levels which represents an unattainable output voltage for conventional multi-level DC to DC converter circuits in which switching is limited to two adjacent voltage levels.

[0052] Although Figure 4 A specific embodiment of a control circuit system for an M-class converter unit modified according to the present invention is shown, but it should be understood that other control circuits can be adjusted or designed while still being able to use embodiments of the present invention to provide appropriate switching signals for the power switches within the converter unit.

[0053] Figure 5A is a block diagram of a first embodiment of an improved controller circuit 500 for an M-level converter unit 402 according to the present invention. Figure 4 Similar in most aspects to the control circuit system 400 of the improved controller circuit 500, the improved controller circuit 500 includes a lookup table (LUT) 502 and a multiplexer (MUX) 504 coupled in series between a voltage level selector 416 and an M-level switch state selector 418. The voltage level selector 416 provides a level signal that includes a portion of the address within the LUT 502. An additional portion of the address within the LUT 502 is provided by multiple sets of two bits B0 and B1 from multiple 2-bit fast flash ADCs, which will be described in detail below. In the example shown, the LUT 502 outputs 8 bits of data per address, and the 8 bits of data are respectively corresponding to the positive inductor current +I L and negative inductor current -I L The two 4-bit switch state selector values ​​of are coupled to MUX 504. MUX 504 selects one of the two switch state selector values, and M-level switch state selector 418 converts the selected switch state selector value into a corresponding switch state applied to the power switch within M-level converter unit 402. In the example shown, current measurement input 420 provides the current I flowing through inductor L to voltage level selector 416. L In an alternative embodiment, the current polarity represented by the current measurement input 420 can be used to directly select the output of the MUX 504 so as to select a switch state suitable for the corresponding current polarity of the inductor L.

[0054] Figure 5B is a table showing the effect of switch state selector values ​​on the power switches of an example 5-level converter cell when the inductor L current is positive. A 4-bit pattern (e.g., "0000", "1111") indicates that the upper four switches (S1, S3, S5, S7 - see Figure 2 ) switch positions; the lower four switches of the 5-level converter unit (S2, S4, S6, S8 - see Figure 2 ) will receive the complementary 4-bit switch position pattern generated within the M-level switch state selector 418. Figure 5B The values ​​in the table represent the results on the three flying capacitors C1, C2, C3 due to each set of switch positions: the value "-1" indicates that the flying capacitor is discharging, the value "0" indicates that there is no change in the charge of the flying capacitor, and the value "1" indicates that the flying capacitor is charging. It is worth noting that when level 1 or level 5 are selected, the flying capacitor is not involved, and therefore no charge change occurs due to the switch position. In addition, levels 2, 3 and 4 provide multiple ways to achieve the desired target voltage, but have different charging / discharging effects on the flying capacitors C1 to C3, and there are complex interdependencies. For example, in level 2, it is impossible to discharge the flying capacitor C3 without also charging the flying capacitor C2 (switch state selector mode "0100"), so if the result is that the flying capacitor C2 is overcharged, then in subsequent cycles, the discharging flying capacitor C2 should be discharged to achieve balance.

[0055] Figure 5C is a table showing the effect of the switch state selector values ​​on the power switches of an example 5-level converter cell when the inductor L current is negative. Figure 5B Same as, but all table values ​​are reversed (i.e., Figure 5B The "1" in becomes Figure 5C The "-1" in Figure 5B The "-1" in becomes Figure 5C ”1” in the figure).

[0056] LUT 502 is accessed by a 9-bit address. The 3 MSBs of the 9-bit address are provided by voltage level selector 416 and can be considered a "page" address that indicates the voltage level that is determined to provide a regulated output V OUT The selected level (L1 to L5) required. Note that although 3 bits can address up to 8 pages, in the example shown, only 5 pages are used, and in some applications as few as 3 pages may be used.

[0057] In the example shown, the 6 LSBs of the 9-bit address are provided by three 2-bit fast flash ADCs, each of which outputs a B0, B1 binary value pair (described in detail below). The B0 value indicates whether the voltage on the associated flying capacitor is below a reference target level (B0=0) and therefore the flying capacitor should be charged, or above a reference target level (B0=1) and therefore the flying capacitor should be discharged. The B1 value indicates whether the voltage on the associated flying capacitor is within a target window (B1=0) or outside the target window (B1=1). Note that in some embodiments, the fast flash ADC can output more than 2 bits for increased accuracy (finer granularity).

[0058] Figure 5A The LUT 502 in the example circuit shown in FIG. 5 contains a set of up to 64 switch state selector values ​​in 5 pages (320 values ​​in total) of data cells, each data cell including 8 bits (4 bits for positive inductor current values ​​and 4 bits for negative inductor current values). The 8-bit data cells of the LUT 502 are addressed by a 9-bit address, which is generated by the concatenation of the 3 MSBs provided by the voltage level selector 416 and the 6 LSBs provided by the three 2-bit fast flash ADCs. Table 1 is an example of a set of switch state selector values ​​that can be stored as addressable data values ​​within the LUT 502. In order to save space in the present disclosure, only the 8-bit data cells for the positive inductor current +I are shown. L 4-bit switch state selector value, thus omitting the negative inductor current -I L however, when connected together, the two groups of 4 bits form the 8-bit data output from LUT 502. Furthermore, to save space in this disclosure, only 16 groups (80 total 8-bit values) are shown, rather than the full range of 64 groups (320 total 8-bit values).

[0059]

[0060] Table 1

[0061] Considering the current I flowing through the inductor L L The polarity of the level (L1 to L5) is selected by an algorithm such as described in the above-referenced U.S. patent application Ser. No. 17 / 560,767. Looking at row #0, the 6 LSBs (3 sets of B0, B1 pairs) generated by the 2-bit fast flash ADCs (ADC1 to ADC3) associated with the flying capacitors C1 to C3 in the 9-bit LUT address indicate the corresponding voltage V of all 3 flying capacitors. C1 To V C3Within its corresponding window (B1=0), but below its corresponding target voltage (B0=0). When selecting the 3 MSBs of the 9-bit LUT address, the voltage level selector 416 can be configured to preferably select any level that will not cause discharge (because all flying capacitors Cx are below their corresponding target voltages). For example, if L2 is the selected operating level of the converter cell 402, the voltage level selector 416 can output "001", which combined with the 6 LSBs of "000000", addresses the LUT 502 cell containing the positive current switch state selector value "1000" (see row #0 of Table 1). This value, along with the negative current corresponding value, will be output to MUX 504, which will select a value to pass to the M-level switch state selector 418. As Figure 5B As shown in the table in , a positive current switch state selector value of "1000" causes the flying capacitor C3 to be charged, and there is no change in the flying capacitors C1 and C2.

[0062] Conversely, if L3 is the selected operating level for converter unit 402, voltage level selector 416 may output "010", which combined with the 6 LSBs of "000000", results in LUT 502 outputting a positive current switch state selector value of "1100", which causes flying capacitor C2 to be charged and flying capacitors C1 and C3 to remain unchanged.

[0063] Row #1 is the following situation: ADC indicates V C2 and V C3 is within its corresponding window and below its corresponding target voltage, while V C1 is within its window and above its corresponding target voltage (LSBs = "000001"). Row #2 is the case where the ADC indicates V C2 and V C3 is within its corresponding window and below its corresponding target voltage, while V C1 is outside its window and below its corresponding target voltage (LSBs="000010"). Row #3 is the case where the ADC indicates V C2 and V C3 within their respective windows and below their respective target voltages, while V C1 Outside its window and above its corresponding target voltage (LSBs="000011").

[0064] The selected switch state selector values ​​inside the LUT 502 may be predetermined and loaded before operation begins. The switch state selector values ​​to be stored in the LUT 502 may be selected heuristically taking into account the M size of the multi-level converter (e.g., 4-level, 5-level) and the voltage and capacitance of the corresponding flying capacitors. Typically, the switch state selector values ​​may be weighted toward balancing the highest voltage flying capacitor first, since the actual capacitance of the highest voltage flying capacitor is relatively small compared to the lower voltage flying capacitors due to derating.

[0065] As will be appreciated, the size of the LUT will need to be larger to accommodate all possible switch state selector values ​​for converter cells larger than 5-level converter cells (e.g., 6-level or 7-level converter cells). Each additional flying capacitor will require an associated 2-bit fast flash ADC, each ADC adding two bits to the address of the LUT 502.

[0066] Figure 5D is a block diagram of a second embodiment of an improved controller circuit 550 for an M-level converter unit 402 according to the present invention. Figure 5A 502, with one key difference being that the PWM signal from the PWM generator 412 is applied to the LUT 502 rather than the voltage level selector 416. Thus, the voltage level selector 416 can be clocked at a slower rate, but must output two signals, PWM high and PWM low, to the LUT 502. In the illustrated embodiment, the current measurement input 420 provides polarity information for directly selecting the output of the MUX 504, so as to select a switch state appropriate for the corresponding current polarity of the inductor L.

[0067] Figure 5E is a block diagram of a third embodiment of an improved controller circuit 560 for an M-level converter unit 402 according to the present invention. Figure 5A The control circuit system 500 of FIG. 5 is similar in most aspects to that of FIG. 5 , with one key difference being that the PWM signal from the PWM generator 412 is applied to the M-level switch state selector 418 rather than the voltage level selector 416. In the illustrated embodiment, the current measurement input 420 provides polarity information for directly selecting the output of the M-level switch state selector 418 so as to select a switch state appropriate for the corresponding current polarity of the inductor L. Thus, the LUT 502 can output a low (discharging) current (I L +), low current with negative polarity (I L -), high (charging) current with positive polarity (I H +) and a high current with negative polarity (I HThe output from LUT 502 can be directly applied to the M-level switch state selector 418, where the selection is made by the PWM signal and the current measurement input 420.

[0068] Note that if the PWM signal is applied to the multi-level switch state selector 418, the system can react to the charge state of the flying capacitor at each PWM edge. If the PWM signal is not applied at these stages and the LUT 502 is controlled by a slower clock, the flying capacitor cannot change as quickly and therefore its size should be larger for the same ripple voltage. From a different perspective, using the PWM signal at the voltage level selector 416 or at the LUT 502 rather than at the multi-level switch state selector 418 has a greater likelihood that voltage deviations will occur on the flying capacitor due to signal propagation delays (thus requiring a large flying capacitor). It is desirable to have a large number of flying capacitors from the PWM generator 412 to the LUT 502. X The shortest propagation delay at the node to select the correct level; longer delays may increase errors and may result in the selection of the wrong level. Therefore, applying the PWM signal to the multi-level switch state selector 418 generally results in the shortest propagation delay and generally allows the use of a smaller flying capacitor.

[0069] Figure 6 is a block diagram of the details of another version of the improved controller 600 at level 5. The improved controller 600 can be considered as Figure 5A , Figure 5D or Figure 5E The voltage level selector 416 may be implemented as part of the microcontroller 602, which may include the RAM 604 and / or the ROM 606 (the ROM 606 may be a reprogrammable type of ROM). As described above, the voltage level selector 416 outputs the 3 MSBs [2:0] of the 9-bit address [8:0] to the LUT 502. The three 2-bit fast flash ADCs of block 608 provide the 6 LSBs [5:0] of the 9-bit address to the LUT 502. The LUT 502 provides two 4-bit switch state selector values ​​(corresponding to the positive inductor current +1 L and negative inductor current -I L), MUX 504 selects a set of 4-bit switch state selector values ​​to be passed to gate driver circuit 610. Gate driver 610 is coupled to converter cell 402 (a 5-level converter cell in this example) and passes the output from MUX 504 and the complementary version of the output, which are applied to the power switches within converter cell 402. For example, if MUX 504 outputs binary 0010, gate driver 610 will output both binary 0010 and binary 1101.

[0070] In some embodiments, the current polarity measurement can be used to directly select the output of MUX 504 to select a switch state appropriate for the corresponding current polarity of inductor L. Microcontroller 602 can also be coupled to the data input port of LUT 502 to allow initial programming and reprogramming of data cells within LUT 502.

[0071] The use of LUT 502 supports the need for a PWM period that is longer than the PWM generator 412 (see Figure 5A ) operation with faster response time, particularly because the inductor current polarity can change at least twice within a PWM cycle, and the flying capacitor voltage detected by the dedicated 2-bit fast flash ADC can change asynchronously and continuously at any time. The intra-cycle change of the above two values ​​can update the address presented to the LUT 502, which can change the output of the switch state selector value (after a short LUT memory access time delay) to reconfigure the state of the power switch.

[0072] As mentioned above Figure 5D and Figure 5E In some embodiments, the generation of the PWM signal may occur at Figure 5A 4. The LUT 502 may be configured to provide a plurality of outputs, each of which may be at different points as depicted. For example, moving the generation of the PWM signal after the voltage level selector 416 means that the voltage selector 416 can be a slower component (but must output two outputs - PWM_high and PWM_low). Similarly, the generation of the PWM signal can be moved to the MUX 504, in which case the LUT 502 will provide four outputs - PWM_high+ for positive current, PWM_high- for negative current, PWM_low+ for positive current, and PWM_low- for negative current. Such a configuration can relax how fast the LUT 502 needs to execute.

[0073] Implementing voltage level selector 416 as part of microcontroller 602 enables many other useful functions that do not require cycle-by-cycle update speeds, such as using V IN and V OUTvoltage determines the optimal levels L1 to L5 to be selected to determine the 3 MSBs output to LUT 502; fault response (e.g., timeout, over-temperature, over-voltage and / or over-current faults); and selectively updates (reprograms) the switch state selector values ​​stored in LUT 502 based on dynamic conditions.

[0074] Referring back to Table 1 above, for the positive inductor current case, the switch state selector value for L1 is always "0000" (and similarly for the negative inductor current case), and for the positive inductor current case, the switch state selector value for L5 is always "1111" (and similarly for the negative inductor current case). Therefore, in an alternative embodiment, the size of LUT 502 can be reduced from 5 pages of 64 rows (a total of 320 8-bit values) to 3 pages of 64 rows (a total of 192 8-bit values) by adding additional "L1, L5" logic 612 to intercept all "000" and "100" MSB outputs from voltage level selector 416 and provide the corresponding 4-bit value "0000" or "1111" to M-level switch state selector 418.

[0075] Advantages of using a lookup table as disclosed above include:

[0076] - Capable of providing fast switch state updates for converter cell power switches based on real-time flying capacitor voltage measurements to balance the flying capacitor voltage at a cycle-by-cycle rate or even faster (intra-cycle);

[0077] - Flexibly adjust the voltage balancing algorithm as needed by reprogramming the LUT 502 to customize the switch state selector values ​​according to the actual flying capacitor characteristics; for example, the voltage of a particular flying capacitor may change faster than the voltage of other flying capacitors, and such a fast-changing flying capacitor may require a higher priority to balance its voltage;

[0078] -The lookup table data can also be updated by the microcontroller during operation when fast updates are not required or when the memory location is not actively used. An example is when V OUT When in low voltage operation between levels 1 and 2, other higher levels (pages), such as level 3, can be updated without interrupting operation as long as the dual port memory is used.

[0079] In considering the characteristics of multi-level converters and the control algorithms required to balance the flying capacitor voltage to a specific target, the inventors realized that a full 8-bit, 255 comparator ADC is not required to indicate the flying capacitor voltage. In a 3-level converter with a single flying capacitor, the balancing algorithm uses one information bit to indicate whether the flying capacitor voltage is too high or too low compared to the specified target voltage. However, for higher-level multi-level converters with multiple capacitors (e.g., a 4-level power converter with 3 flying capacitors), additional bits of voltage range / window information are required so that the priority of which flying capacitor to balance first can be determined. Therefore, one aspect of the present invention is a 2-bit fast flash ADC circuit designed to be used with a multi-level converter to achieve all of the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements of properly balancing the flying capacitor voltages in the multi-level converter cells.

[0080] Figure 7 It is particularly suitable for Figure 6 Schematic diagram of an embodiment of a 2-bit flash ADC circuit 700 used in conjunction with a circuit of FIG. An instance of the 2-bit flash ADC circuit 700 may be coupled across corresponding flying capacitors Cx in a multi-stage converter cell.

[0081] In the example shown, the voltage V across the plates of the flying capacitor Cx is represented by Cx The voltage V CxIN is applied to the first terminal of the first comparator 702, the first terminal of the second comparator 704, and the first terminal of the third comparator 706. The voltage V CxIN Can be equal to V Cx Or it can be V Cx A scaled version of 702 to accommodate the input range of comparators 702 , 704 , and 706 .

[0082] The second input of the first comparator 702 is coupled to a specified upper window voltage threshold V HI , which can be a universal reference voltage V REF Similarly, the second input of the third comparator 706 is coupled to the specified lower window voltage threshold V LO , which can be a universal reference voltage V REF The reference voltage V TARGET is coupled to the second input of the second comparator 704 and may be a common reference voltage V REF Therefore, the 2-bit fast flash ADC circuit 700 uses only 3 comparators, resulting in a much smaller layout area than a conventional 8-bit ADC. The output of the second comparator 704 is the first bit B0.

[0083] In all cases, manipulating the voltage to obtain the scaled voltage can be accomplished by a number of known circuits including resistor dividers.

[0084] In the example shown, the output of the first comparator 702 is coupled to the inverting input of the NAND gate 708, and the output of the third comparator 706 is coupled to the non-inverting input of the NAND gate 708. The output of the output of the NAND gate 708 is the second bit B1. It should be understood that different combinations of logic elements can be used to implement the functionality of the NAND gate 708. Therefore, the combination of the first comparator 702, the third comparator 706 and the NAND gate 708 can be viewed as a circuit that provides a second binary output B1, which indicates the input voltage V CxIN The reference voltage V HI and reference voltage input V LO Inside or outside the defined voltage window.

[0085] The first bit B0 indicates the voltage V of a particular capacitor Cx. Cx (By V CxIN indicates) is at the corresponding target voltage (e.g., 1 / 4V IN , 1 / 2V IN For example, B0=0 can be used to indicate the voltage V Cx Below the target voltage of the corresponding capacitor Cx, B0=1 can be taken to indicate the voltage V Cx Above the target voltage of the corresponding capacitor Cx.

[0086] The second bit B1 indicates the voltage V of a particular capacitor Cx. Cx (By V CxIN ) is within or outside a predetermined target window, which is a voltage range around the target voltage of the capacitor Cx (see also Figure 4 ). For example, B1=0 can be taken to indicate the voltage V Cx Within the specified window (voltage range) of the corresponding capacitor Cx, B1 = 1 can be taken to indicate that the voltage V Cx is outside the designated window for the corresponding capacitor Cx. Therefore, the B1 bit provides an additional bit of voltage range / window information needed so that priority can be determined as to which flying capacitor Cx to balance first.

[0087] Once the B1, B0 bit pairs are generated for each flying capacitor Cx, this information can be provided to the control system (eg, Figure 6 An improved controller circuit is provided to balance the charge across the flying capacitor Cx by selecting switch states for the group of associated power switches S1 to S[2*(M-1)].

[0088] Figure 8 is the indication for V HI 、V TARGET 、V LO and V CxIN An example voltage graph of voltage versus time. V HI With V LO The voltage span between V TARGET Window 802 (note that window 802 does not need to surround V TARGET symmetrical positioning, although it is generally preferred to have a symmetrical window 802). Plot 804 shows V in different time periods indicated by tick marks 806a to 806d on the time dimension of graph 800. CxIN (Indicates V Cx ) for several different values. CxIN The bracketed values ​​adjacent to different portions of the plot 804 indicate corresponding pairs of bits B1 (MSB) and B0 (LSB) that may be generated by the 2-bit flash ADC circuit 500 of FIG. 5 .

[0089] For example, at tick mark 806a, the B1, B0 pair is

[00] , indicating that V CxIN Lower than V TARGET Again within window 802; at tick mark 806b, the pair B1 and B0 is

[11] , indicating V CxIN Higher than V TARGET Again outside window 802; at scale mark 806c, B1, B0 pair is

[01] , indicating V CxIN Higher than V TARGET Again within window 802; and at tick mark 806d, the B1, B0 pair is

[10] , indicating V CxIN Lower than V TARGET Again outside window 802.

[0090] Return to reference Figure 7 , the 2-bit fast flash ADC circuit 700 may include a scalar circuit 710 for converting the V of a particular flying capacitor Cx to Cx Scaled down to the appropriate input voltage V for comparators 702 to 706 CxIN For example, V Cx can be about 48V, and the corresponding scaled V CxIN It can be about 2.4V.

[0091] The 2-bit flash ADC circuit 700 may further include a resistor divider 712, which includes a resistor divider 712 connected in series to a common reference voltage V REFA set of resistors R0 to R3 are connected between a reference potential 714 (e.g., about 2.4V) and a reference potential 714 (e.g., circuit ground). Some or all of the set of resistors R0 to R3 may be fixed or variable (variable examples of the set of resistors R0 to R3 are shown in FIG. Figure 7 In the case of variable resistors R0 to R3, the corresponding control signal CTRL R0 To control signal CTRL R3 Resistors R0 through R3 may be provided by controller 716 and coupled to the variable resistors to set the associated resistance values.

[0092] The ratios of each subset of the resistors R0 to R3 provide different scaled voltages at nodes A, B, and C of the voltage divider 512. For example, a scaled voltage V HI , where V HI =V REF ×(R1+R2+R3) / (R0+R1+R2+R3). The scaled voltage V can be obtained at node B. TARGET , where V TARGET =V REF ×(R2+R3) / (R0+R1+R2+R3). The scaled voltage V can be obtained at node C. LO , where V LO =V REF ×(R3) / (R0+R1+R2+R3). Therefore, V HI >V TARGET >V LO The respective values ​​of resistors R0 through R3 may be settable (eg, by laser trimming during manufacturing) or adjustable (eg, when assembled in a circuit module) or variable (eg, by a programming control signal from controller 716).

[0093] The values ​​of the resistors R0 to R3 can be selected so that V HI >V TARGET and V TARGET >V LO The amount of voltage ripple at the output of the associated power converter is sufficient to exceed the amount of voltage ripple at the output of the associated power converter in order to prevent the voltage ripple from causing an erroneous indication that the capacitor is outside the upper window voltage threshold or the lower window voltage threshold. The voltage ripple on the flying capacitor Cx is at least a function of the capacitance of the capacitor, the switching frequency of the associated power switch, and the load current of the power converter. It is not desirable to set the window size to be less than the steady-state voltage ripple so that the representative capacitor voltage V CxIN Constantly exceeding the target window. Since the voltage ripple is a function of the load current, the controller 716 can adjust the window size based on the load current.

[0094] The values ​​of the group of resistors R0 to R3 should also not be set so that the voltage range window defined by the high window voltage threshold and the low window voltage threshold is too wide, which may result in no flying capacitor being given priority for voltage balancing. Therefore, window size adjustment can be performed to better optimize the flying capacitor voltage balancing priority. For example, if multiple flying capacitor voltages frequently fall outside the window at the same time, priority information cannot be obtained because all flying capacitors are unbalanced. In this case, the value of the voltage range window defined by the high window voltage threshold and the low window voltage threshold may be increased. Figure 8 The size of the window 802 in 802 is adjusted to allow certain flying capacitor voltages to be within the window 802 while other flying capacitor voltages fall outside the window 802 so that priority can be given to those flying capacitors that fall outside the window 802. The window size adjustment can be done dynamically by the controller 716 to better optimize the flying capacitor voltage balance.

[0095] Note that in a preferred embodiment, the window sizes of all capacitors are adjusted together because the voltage balancing algorithm is usually based on a specific target. For example, for the case where all flying capacitors Cx have equal voltage ripples (e.g., the same capacitance at the target voltage of each capacitor), it may be desirable to set the window size to be the same for all flying capacitors Cx. When the window size needs to be increased when all flying capacitors Cx are outside the window, the window sizes of all flying capacitors Cx can be increased by the same amount, and vice versa. This will allow the controller to achieve voltage balance within the same voltage increment of each flying capacitor Cx. For the case of different capacitances of each flying capacitor Cx, the window can be scaled by the ratio of the capacitance, but again, all capacitor windows will be adjusted at the same time. In other embodiments, it may be desirable to adjust the size of one or more windows individually. In some embodiments, the minimum window size can be dynamically set based on the voltage ripple plus some incremental values, which mainly depends on the load current because the frequency and capacitance are fixed in most cases.

[0096] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for processing, manufacturing and / or improved performance. In particular, IC embodiments including the present invention are often used in modules, where one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components and possible additional ICs) into a package. Then, ICs and / or modules are usually combined with other components often on printed circuit boards to form a part of a final product such as a cellular phone, a laptop computer or an electronic tablet, or to form a more advanced module that can be used in a variety of products such as vehicles, test equipment, medical equipment, etc. Through various configurations of modules and components, such ICs usually support modes of communication (often wireless communication).

[0097] As an example of further integration of embodiments of the present invention with other components, Fig. 9 900, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin film sheet). In the example shown, substrate 900 includes a plurality of ICs 902A to 902D having terminal pads 904 that are interconnected by conductive vias and / or traces on and / or within substrate 900 or on an opposing (rear) surface of substrate 900 (to avoid clutter, surface conductive traces are not shown and not all terminal pads are labeled). ICs 902a to 902d may be implemented, for example, as signal switches, active filters, amplifiers (including one or more LNAs), and other circuit systems. For example, IC 902b may incorporate a similar Figure 5A , Figure 6 and Figure 7 One or more examples of circuits of the type shown in FIG.

[0098] The substrate 900 may also include one or more passive devices 906 embedded in, formed on, and / or secured to the substrate 900. Although shown as a generally rectangular shape, the passive devices 906 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., which are interconnected to other passive devices 906 and / or the respective ICs 902a to 902d via conductive traces on or in the substrate 900. The front or back surface of the substrate 900 may be used as a location for forming other structures.

[0099] Another aspect of the present invention includes a method for controlling an M-level power converter unit. For example, Fig.10is a process flow diagram illustrating a method for controlling M-class power converter units having one or more flying capacitors coupled to a set of power switches, where M≥3. The method includes: configuring a voltage level selector to generate and output a first set of address bits (block 1002); generating, for an associated one of the one or more flying capacitors, a first bit indicating whether a voltage across the associated flying capacitor is above or below a reference target level (block 1004); generating, for an associated one of the one or more flying capacitors, a second bit indicating whether a voltage across the associated flying capacitor is within a target window or outside the target window (block 1006); applying the first set of address bits and a set of the first and second bits as a cascade address to a lookup table that stores a set of switch state selector values ​​and outputs a selected switch state selector value in response to receiving the cascade address (block 1008); generating a set of power switch state settings based on a received portion of the selected switch state selector value (block 1010); and applying the generated set of power switch state settings to power switches of the M-class power converter units (block 1012).

[0100] Additional aspects of the above method may include one or more of the following: wherein the switch state selector values ​​stored in the lookup table are dynamically changeable; wherein the M-level power converter unit includes an output inductor, and the switch state selector values ​​each include a cascade of a first switch state selector value corresponding to a positive current through the inductor and a second switch state selector value corresponding to a negative current through the inductor; and / or selectively providing one of the first switch state selector value or the second switch state selector value as a received portion of the selected switch state selector value.

[0101] It may be desirable to provide additional control and operating circuitry (or one or more shutdown procedures) that enables reliable and efficient operation of a power converter utilizing a multi-stage converter unit designed according to the present disclosure. For example, in a step-down power converter, the output voltage of the converter unit is less than the input voltage of the converter unit. When the output load current is non-zero, shutting down or disabling (e.g., due to a fault event, such as a short circuit) a converter unit having a designed inductor connected to the output generally requires some means of releasing the inductor current. In some embodiments, a bypass switch may be connected in parallel with the designed inductor connected to the output of the converter unit, and the bypass switch may be controlled to be disconnected during normal operation and closed when the converter unit is shut down or in the event of a fault. Ideally, in order to prevent transient ringing and provide a safe discharge of the inductor current, the bypass switch may be closed before disabling the converter unit switching. In an alternative embodiment where a MOSFET is used for the main power switch of the converter, an inherent body diode connected between the body and drain terminals of each MOSFET may also release the inductor current. Details of these solutions and alternative shutdown solutions are taught in U.S. Patent No. 10,686,367, entitled “Apparatus and Method for Efficient Shutdown of Adiabatic Charge Pumps,” published on June 16, 2020, which is assigned to the assignee of the present invention and is incorporated by reference.

[0102] Another consideration when combining converter units in parallel is to control multiple parallel power converters to avoid inrush current (e.g., during a soft start period of the power converter) and / or overstress of power switches when all power converters are not fully operational (e.g., during startup) or when a fault condition occurs. Conditional control can be achieved by monitoring voltage and / or current using node state detectors coupled to selected nodes within the parallel connected power converters. In some embodiments, such node state detectors can be configured to work in parallel with output state detectors that measure the output voltage of the associated power converter during startup. The node state detector ensures that the voltage across important components (e.g., flying capacitors and / or power switches) within the converter unit of the power converter is within the desired range before achieving full power steady-state operation of the parallel power converter, otherwise full power steady-state operation will be prevented. The node state detector can be coupled to a master controller that uses one or more common control signals to control one or more of the parallel power converters. In a further implementation of the master controller configuration, the parallel power converters can each report a power good signal (Pgood) when preparing to leave the startup phase for full power steady-state operation. The master controller may substantially AND all such Pgood signals, possibly along with one or more status signals from other circuits, such that the master controller does not enable full power steady-state operation of any parallel power converter unless all parallel power converters are ready for that state. In essence, the Pgood signals from each parallel power converter are all tied together such that the parallel power converters may not transition out of the startup phase until all Pgood signals indicate that they are ready to transition to stable operation. In addition, if the Pgood signal changes due to a fault condition in one or more of the parallel power converters, the parallel power converters may transition from steady-state operation to automatic restart or shutdown operation. Details of these solutions and alternative shutdown solutions are taught in U.S. Patent No. 10,992,226, entitled “Startup Detection for Parallel Power Converters,” issued on April 27, 2021, which has been assigned to the assignee of the present invention, and the contents of which are incorporated by reference.

[0103] Another consideration in operating a multi-level converter unit is to obtain (i.e., pre-charge) and maintain a substantially fully proportionally balanced flying capacitor voltage so that all power switches are subject to similar voltage stresses, because unbalanced flying capacitors may cause power switches (particularly FET power switches) to breakdown due to exposure to high voltage. One solution to both pre-charging capacitor voltages and operating balance of capacitor voltages in a multi-level DC to DC converter circuit is to provide parallel "shadow" circuits that conditionally couple a flying capacitor to a voltage source or other circuit to pre-charge the capacitor, or conditionally couple two or more flying capacitors together to transfer charge from a higher voltage capacitor to a lower voltage capacitor, or conditionally couple a flying capacitor to a voltage sink to discharge the capacitor, all under control of real-time capacitor voltage measurements. Each parallel "shadow" circuit may include a switch and resistor coupled in parallel with a main power switch that is part of a multi-level converter unit (in some cases, one switch-resistor pair may span two series-connected power switches). This particular solution for precharging and / or balancing the charge on the flying capacitor is very fast, provides a slow precharging of the flying capacitor during the precharging period, protects the power switches from inrush current, and provides a stable voltage for the converter unit power switches. Details of this solution and alternative precharging and charge balancing solutions are taught in U.S. Patent No. 10,720,843, entitled “Multi-Level DC-DC Converter with Lossy Voltage Balancing,” issued on July 21, 2020, which is assigned to the assignee of the present invention and is incorporated by reference.

[0104] Another solution to balancing capacitor voltages in a multi-level DC-to-DC converter circuit is to provide a lossless voltage balancing solution in which disordered state transitions of the multi-level DC-to-DC converter units are allowed to occur during normal operation. The net effect of the disordered state transitions is to increase or decrease the voltage across a particular flying capacitor, thereby preventing voltage overstress on the main power switch of the DC-to-DC converter. In some embodiments, the overall sequence of state transitions is restricted to reduce or avoid transition state switching, thereby allowing each capacitor the opportunity to have its voltage manipulated as needed, rather than allowing voltage balancing of one capacitor and then another capacitor. Details of this solution and alternative charge balancing solutions are taught in U.S. Patent No. 10,770,974, entitled “Multi-Level DC-DC Converter with Lossless Voltage Balancing,” published on September 8, 2020, which is assigned to the assignee of the present invention and the contents of which are incorporated by reference.

[0105] An additional consideration of some embodiments is to implement the operation of a multi-level converter unit so that a voltage can be generated in a boundary region between voltage levels. "Boundary region" means an output voltage that cannot be obtained by a conventional multi-level DC to DC converter circuit. In order to generate an output voltage in a boundary region, some embodiments basically alternate (switch) between adjacent (or even nearby) regions by setting the state of the converter unit power switch in a boundary region transition mode. For example, a 3-level DC to DC converter circuit can operate in region 1 for a selected time and in adjacent region 2 for a selected time. Therefore, region 1 and region 2 are considered as a single "super region". More generally, in some cases, it may be useful to create a super region using non-adjacent regions or using more than two regions (adjacent and / or non-adjacent). The details of this solution are taught in U.S. Patent No. 10,720,842, entitled "Multi-Level DC-DC Converter with Boundary Transition Control", published on July 21, 2020, which has been assigned to the assignee of the present invention and its contents are incorporated by reference.

[0106] Yet another consideration of some embodiments is to protect the main power switches and other components within the power converter from stress conditions, particularly from voltages exceeding the breakdown voltage of such power switches, particularly FET switches. One approach for protecting a multi-level power converter uses at least one high voltage FET power switch while allowing all or most other main power switches to be low voltage FET switches.

[0107] In power converters, especially multi-level power converters, power switches can be implemented with FETs, especially MOSFETs. For each power FET, a driver circuit is usually required. In addition, for some power FETs, a level shifter may be required to convert a low voltage logic on / off signal referenced to ground from an analog or digital controller into a signal with the same voltage swing but referenced to the source voltage of the power FET, which drives the power FET to charge or discharge the gate of the power FET, thereby controlling the on or blocking state of the power FET. In some applications, the functions of the level shifter and the driver circuit can be incorporated into one circuit.

[0108] It should be apparent that the multi-level power converter embodiments described in this disclosure may be synergistically combined with the teachings of one or more of the additional control and operating circuits and methods described in this section.

[0109] Embodiments of the present invention improve power density and / or power efficiency of combined circuits and circuit modules or blocks. As will be appreciated by those skilled in the art, utilizing embodiments of the present invention beneficially impacts system architecture in key ways, including lower power and / or longer battery life. Thus, the present invention specifically includes system-level embodiments that are creatively implemented through inclusion in large system designs and applications.

[0110] More specifically, multi-level power converters provide or achieve many benefits and advantages, including:

[0111] Adaptability to applications where the input and / or output voltages may have a wide dynamic range (e.g., different battery input voltage levels, different output voltages);

[0112] Improved efficiency in the operating time of devices running on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0113] Efficiency improvements where efficiency is important for thermal management, especially protecting other components (e.g., display, nearby ICs) from overheating;

[0114] Achieving design optimization of power efficiency, power density, and form factor of power converters—for example, a smaller size multi-level power converter may allow the power converter to be placed closer to the load, thereby improving efficiency and / or reducing overall material costs;

[0115] the ability to exploit the performance of smaller, low-voltage transistors;

[0116] Adaptability to applications where the power source can vary widely, such as batteries, other power converters, generators, or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, Power over Ethernet, etc.);

[0117] Adaptability to applications where the loads can vary widely, such as general ICs (including microprocessors and memory ICs), motors and actuators, transducers, sensors, and displays (e.g., all types of LCDs and LEDs);

[0118] Capabilities implemented in multiple IC technologies (e.g., MOSFET, GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chip, ball grid array, wafer-level chip packaging, wide fan-out packaging, and embedded packaging).

[0119] The advantages and benefits of multi-level power converters enable use in a wide range of applications. For example, applications of multi-level power converters include portable and mobile computing and / or communication products and components (e.g., notebook computers, ultrabook computers, tablet devices and phones), displays (e.g., LCD, LED), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z-Wave and GPS-based devices), wired network devices and systems, data centers (e.g., for battery backup systems and / or power conversion for processing systems and / or electronic / optical networking systems), Internet of Things (IOT) devices (e.g., smart switches and lights, security sensors and security camera devices), home appliances and electronic products (e.g., set-top boxes, battery-powered vacuum cleaners, appliances with built-in radio transceivers such as washing machines, dryers and refrigerators), AC / DC power converters, all types of electric vehicles (e.g., for drivetrains, control systems and / or infotainment systems), and other devices and systems that use portable power generation sources and / or require power conversion.

[0120] Radio system uses include wireless RF systems (including base stations, repeater stations, and handheld transceivers) using various technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing (“OFDM”), Quadrature Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Time Division Multiple Access (“TDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 4G and WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11ac, 802.11ax), and other radio communication standards and protocols.

[0121] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor and includes insulated gates having metal or metalloid, insulator and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal or heavily doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0122] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or the frequency of an alternating voltage or current in an electrical circuit.

[0123] With respect to the drawings cited in this disclosure, the dimensions of the various elements are not drawn to scale; some dimensions may be significantly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0124] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or in a hybrid circuit form or a discrete circuit form. Any suitable substrate and process (including but not limited to standard body silicon, high resistance body CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS)) can be used to manufacture integrated circuit embodiments. Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when manufactured using a process based on SOI or SOS or when manufactured using a process with similar characteristics. The manufacture performed in CMOS using SOI or SOS processes enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Since parasitic capacitance can usually be kept low (or minimal, or uniform across all cells, thereby allowing compensation for parasitic capacitance) by careful design, a monolithic IC implementation is particularly useful.

[0125] Depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS and enhancement mode or depletion mode transistor devices), voltage levels may be adjusted and / or voltage and / or logic signal polarity may be inverted. Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0126] A number of embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and therefore may be performed in an order different from that described. In addition, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial and / or parallel manner.

[0127] It should be understood that the foregoing description is intended to illustrate rather than limit the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that parenthetical markings used for claim elements are for convenience of reference to such elements and do not, by themselves, indicate a specific required order or enumeration of elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being considered as starting a conflicting marking sequence).

Claims

1. A controller for an M-level power converter unit having one or more flying capacitors coupled to a set of power switches, wherein M≥3, the controller comprising: (a) a voltage level selector configured to generate and output a first set of address bits; (b) a set of one or more analog-to-digital converters, each member of the set configured to be coupled to an associated one of the one or more flying capacitors and configured to output a set of bits indicative of a voltage across the associated flying capacitor compared to at least one voltage level, wherein at least a first bit and a second bit of the set of bits corresponding to each of the one or more analog-to-digital converters together comprise a second set of address bits; as well as (c) a lookup table coupled to the voltage level selector and to the group of one or more analog-to-digital converters, the lookup table storing a set of switch state selector values ​​and outputting selected switch state selector values ​​to the M-stage power converter unit in response to receiving an address comprising a cascade of the first group of address bits and the second group of address bits.

2. The controller according to claim 1, wherein: The first bit indicates whether the voltage across the associated flying capacitor is above or below a reference target level, and the second bit indicates whether the voltage across the associated flying capacitor is within or outside a target window.

3. The controller according to claim 1 further includes an M-level switch state selector, which is coupled to the lookup table and is configured to be coupled to the M-level power converter unit to receive at least a portion of the selected switch state selector value from the lookup table and generate a set of power switch state settings based at least in part on the received portion of the selected switch state selector value.

4. The controller according to claim 1, wherein: The switch state selector values ​​stored in the lookup table are dynamically changeable. 5 . The controller of claim 1 , further comprising a microcontroller coupled to the lookup table and configured to dynamically load a changed switch state selector value into the lookup table.

6. The controller according to claim 1, wherein: The M-level power converter unit includes an output inductor, and the switch state selector values ​​each include a cascade of a first switch state selector value corresponding to a positive current through the inductor and a second switch state selector value corresponding to a negative current through the inductor.

7. The controller of claim 6, further comprising a multiplexer connected between the lookup table and the M-level power converter unit and configured to provide one of the first switch state selector value or the second switch state selector value to the M-level power converter unit.

8. The controller according to claim 1, wherein: Each of the one or more analog-to-digital converters is a 2-bit analog-to-digital converter, the 2-bit analog-to-digital converter comprising: (a) a voltage input configured to be coupled to a voltage from the associated flying capacitor; (b) a comparator having a first input coupled to the voltage input and a second input coupled to a first reference voltage input, the second comparator outputting a first bit; and (c) a circuit coupled to the voltage input, a second reference voltage input, and a third reference voltage input, the circuit being configured to output a second bit, wherein the target window is defined by respective voltages on the second reference voltage input and the third reference voltage input.

9. The controller according to claim 8, wherein: The voltage from the associated flying capacitor is scaled before being coupled to the voltage input.

10. The controller according to claim 8, wherein: The first reference voltage input, the second reference voltage input and the third reference voltage input receive a first reference voltage, a second reference voltage and a third reference voltage respectively, wherein the second reference voltage is greater than the first reference voltage and the third reference voltage is less than the first reference voltage.

11. The controller of claim 10, further comprising a resistor divider configured to be coupled to a reference voltage source and configured to provide: (a) coupling the first reference voltage at a first node to the first reference voltage input; (b) coupling the second reference voltage at a second node of the second reference voltage input; as well as (c) The third reference voltage at a third node coupled to the third reference voltage input.

12. The controller according to claim 11, wherein: The resistor divider includes at least one adjustable resistor element configured to adjust at least one of the first reference voltage, the second reference voltage, and / or the third reference voltage.

13. An M-class power converter, comprising: (a) an M-level converter unit having one or more flying capacitors coupled to a set of power switches, where M ≥ 3, and configured to generate an output voltage or current according to an input voltage; (b) a first controller coupled to the M-stage converter unit and outputting a pulse width modulated signal in response to at least an output of the M-stage converter unit; (c) a second controller, the second controller being coupled to the first controller to receive the pulse width modulation signal, the M-level controller comprising: (1) a voltage level selector configured to generate and output a first set of address bits; (2) a group of one or more analog-to-digital converters, each member of the group being configured to be coupled to an associated one of the one or more flying capacitors, and outputting a set of bits indicative of a voltage on the associated flying capacitor compared to at least one voltage level, wherein at least a first bit and a second bit of the set of bits corresponding to each of the set of one or more analog-to-digital converters together comprise a second set of address bits; and (3) a lookup table coupled to the voltage level selector and the group of one or more analog-to-digital converters, the lookup table storing a group of switch state selector values ​​and outputting selected switch state selector values ​​to the M-stage power converter unit in response to receiving an address comprising a cascade of the first group of address bits and the second group of address bits.

14. The M-class power converter according to claim 13, wherein: The first bit indicates whether the voltage across the associated flying capacitor is above or below a reference target level, and the second bit indicates whether the voltage across the associated flying capacitor is within or outside a target window.

15. The M-level power converter according to claim 13 further includes an M-level switch state selector, which is coupled to the lookup table and is configured to be coupled to the M-level power converter unit to receive at least a portion of the selected switch state selector value from the lookup table and generate a set of power switch state settings based at least in part on the received portion of the selected switch state selector value.

16. The M-class power converter according to claim 13, wherein: The switch state selector values ​​stored in the lookup table are dynamically changeable.

17. The M-class power converter of claim 13, further comprising a microcontroller coupled to the lookup table and configured to dynamically load the changed switch state selector value into the lookup table.

18. The M-class power converter according to claim 13, wherein: The M-level power converter unit includes an output inductor, and the switch state selector values ​​each include a cascade of a first switch state selector value corresponding to a positive current through the inductor and a second switch state selector value corresponding to a negative current through the inductor.

19. The M-class power converter of claim 18, further comprising a multiplexer connected between the lookup table and the M-class switch state selector and configured to provide one of the first switch state selector value or the second switch state selector value to the M-class switch state selector.

20. The M-class power converter according to claim 13, wherein: Each of the one or more analog-to-digital converters is a 2-bit analog-to-digital converter, the 2-bit analog-to-digital converter comprising: (a) a voltage input configured to be coupled to a voltage from the associated flying capacitor; (b) a comparator having a first input coupled to the voltage input and a second input coupled to a first reference voltage input, the second comparator outputting a first bit; and (c) a circuit coupled to the voltage input, a second reference voltage input, and a third reference voltage input, the circuit being configured to output a second bit, wherein the target window is defined by respective voltages on the second reference voltage input and the third reference voltage input.

21. The M-class power converter according to claim 20, wherein: The voltage from the associated flying capacitor is scaled before being coupled to the voltage input.

22. The M-class power converter of claim 20, wherein: The first reference voltage input, the second reference voltage input and the third reference voltage input receive a first reference voltage, a second reference voltage and a third reference voltage respectively, wherein the second reference voltage is greater than the first reference voltage and the third reference voltage is less than the first reference voltage.

23. The M-class power converter of claim 22, further comprising a resistor divider configured to be coupled to a reference voltage source and configured to provide: (a) coupling the first reference voltage at a first node to the first reference voltage input; (b) coupling the second reference voltage at a second node of the second reference voltage input; as well as (c) The third reference voltage at a third node coupled to the third reference voltage input.

24. The M-class power converter of claim 23, wherein: The resistor divider includes at least one adjustable resistor element configured to adjust at least one of the first reference voltage, the second reference voltage, and / or the third reference voltage.

25. A method for controlling M-level power converter units having one or more flying capacitors coupled to a set of power switches, wherein M≥3, the method comprising: (a) configuring a voltage level selector to generate and output a first set of address bits; (b) generating, for an associated flying capacitor of the one or more flying capacitors, at least a first bit indicating whether a voltage across the associated flying capacitor is above or below a reference target level; (c) generating, for the associated flying capacitor of the one or more flying capacitors, at least a second bit indicating whether a voltage across the associated flying capacitor is within a target window or outside a target window; (d) applying the first set of address bits and the set of at least the first and second bits as a concatenated address to a lookup table that stores a set of switch state selector values ​​and outputs a selected switch state selector value in response to receiving the concatenated address; (e) generating a set of power switch state settings based on the received portion of the selected switch state selector value; as well as (f) applying the generated set of power switch state settings to the power switches of the M-stage power converter units.

26. The method according to claim 25, wherein: The switch state selector values ​​stored in the lookup table are selectively updateable.

27. The method according to claim 25, wherein: The M-level power converter unit includes an output inductor, and the switch state selector values ​​each include a cascade of a first switch state selector value corresponding to a positive current through the inductor and a second switch state selector value corresponding to a negative current through the inductor.

28. The method of claim 27, further comprising selectively providing one of the first switch state selector value or the second switch state selector value as the received portion of the selected switch state selector value.

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