Voltage conversion circuit

Abstract

The present invention discloses a voltage conversion circuit. The voltage conversion circuit includes a charge and discharge control unit, a charge and discharge unit, a clock signal generating unit and a logic control unit; the clock signal generating unit is used to generate multiple clock signals according to the output voltage and reference voltage of the voltage conversion circuit; the logic control unit is used to form a control signal according to multiple clock signals and a discharge stage control signal; the charge and discharge control unit is used to control the charging time of the charge and discharge unit according to the control signal; wherein the ratio of the periods of the multiple clock signals is an integer multiple of the base. The voltage conversion circuit provided by the embodiment of the present invention can not only improve the adjustment accuracy of the output voltage and ensure the adjustment range of the output voltage, but also reduce the control difficulty of the output voltage, simplify the circuit structure of the voltage conversion circuit, and reduce the cost of the voltage conversion circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of power electronics, and in particular to a voltage conversion circuit. Background Art

[0002] In electronic devices using a DC source, a voltage converter is required to convert the voltage of the power supply into the required operating voltage. Figure 1 The following is a schematic diagram of a voltage converter provided by the prior art. Figure 1 As shown, the voltage converter includes a control unit ( Figure 1 The control unit includes a control unit (not shown), a switching transistor M1, a charging inductor L1, a diode D1 and a discharging capacitor C1. The working process of the voltage converter includes a charging stage and a discharging stage. In the charging stage of the voltage converter, the control unit outputs a high potential, controls the switching transistor M1 to be turned on, and the current on the charging inductor L1 rises for charging, and the current on the charging inductor L1 mostly passes through the switching transistor M1. At this time, the discharging capacitor C1 is discharged, and the output voltage of the voltage converter decreases. In the discharging stage of the voltage converter, the control unit outputs a low potential, controls the switching transistor M1 to be turned off, and the current on the charging inductor L1 flows through the diode D1 to charge the discharging capacitor C1, and the output voltage of the voltage converter increases. It can be seen from the above process that the output voltage of the voltage converter decreases in the charging stage and increases in the discharging stage. The change in the output voltage makes the circuit of the control unit controlling the state of the switching transistor M1 to adjust the output voltage complicated, thereby making the circuit of the voltage converter complicated and increasing the cost of the voltage converter. Summary of the invention

[0003] The present invention provides a voltage conversion circuit to simplify the circuit structure of the voltage conversion circuit and reduce the cost of the voltage conversion circuit.

[0004] In a first aspect, an embodiment of the present invention provides a voltage conversion circuit, including a charge and discharge control unit, a charge and discharge unit, a clock signal generating unit and a logic control unit;

[0005] The first input end of the clock signal generating unit is connected to the output end of the voltage conversion circuit, the second input end of the clock signal generating unit is used to input a reference voltage, the multiple output ends of the clock signal generating unit are connected to the multiple first input ends of the logic control unit, and the second input end of the logic control unit is used to input a discharge stage control signal; the output end of the logic control unit is connected to the control end of the charge and discharge control unit, the first end of the charge and discharge control unit is grounded, the second end of the charge and discharge control unit is connected to the second end of the charge and discharge unit, the first end of the charge and discharge unit is connected to the power input end, and the output end of the charge and discharge unit serves as the output end of the voltage conversion circuit;

[0006] The clock signal generating unit is used to generate multiple clock signals according to the output voltage of the voltage conversion circuit and the reference voltage; the logic control unit is used to form a control signal according to the multiple clock signals and the discharge stage control signal; the charge and discharge control unit is used to control the charging time of the charge and discharge unit according to the control signal; wherein the ratio of the periods of the multiple clock signals is an integer multiple of the base digit.

[0007] Optionally, the clock signal generating unit includes an analog-to-digital converter and a clock generator;

[0008] The first input terminal of the analog-to-digital converter is connected to the output terminal of the voltage conversion circuit, the second input terminal of the analog-to-digital converter is used to input a reference voltage, and the analog-to-digital converter is used to form an n-bit digital signal according to the difference between the output voltage and the reference voltage; wherein n is an integer greater than or equal to 1;

[0009] The input end of the clock generator is connected to the output end of the analog-to-digital converter in a one-to-one correspondence, and the multiple output ends of the clock generator are connected to the multiple first input ends of the logic control unit. The clock generator is used to form n clock signals according to the n-bit digital signal; wherein, from the low bit to the high bit of the n-bit digital signal, the period of the clock signal corresponding to the next bit of the digital signal is m times the period of the clock signal corresponding to the previous and next digital signals, and m is the value of the base bit.

[0010] Optionally, when the bit value of the n-bit digital signal is 1, the clock signal of the corresponding bit is valid, and when the bit value of the n-bit digital signal is 0, the clock signal of the corresponding bit is invalid.

[0011] Optionally, the logic control unit includes an OR gate and an AND gate; multiple input ends of the OR gate are connected to multiple output ends of the clock signal generating unit, the output end of the OR gate is connected to the first input end of the AND gate, the second input end of the AND gate is used to input the discharge stage control signal, and the output end of the AND gate is connected to the control end of the charge and discharge control unit.

[0012] Optionally, the voltage conversion circuit also includes a delay unit; the input end of the delay unit is connected to the output end of the logic control unit, the output end of the delay unit is connected to the control end of the charge and discharge control unit, and the delay unit is used to delay the control signal.

[0013] Optionally, the delay time of the delay unit is the time from the end of the discharge phase of the current charge and discharge cycle to the end of the last valid level of the control signal in the discharge phase.

[0014] Optionally, the delay unit includes an adjustable resistor and an adjustable capacitor;

[0015] The first end of the adjustable resistor is connected to the output end of the logic control unit, the second end of the adjustable resistor is connected to the first end of the adjustable capacitor and to the control end of the charge and discharge control unit, and the second end of the adjustable capacitor is grounded.

[0016] Optionally, the delay unit also includes a first inverter and a second inverter; the first inverter is connected in series between the first end of the adjustable resistor and the output end of the logic control unit, and the second inverter is connected in series between the second end of the adjustable resistor and the control end of the charge and discharge control unit.

[0017] Optionally, the charge and discharge control unit includes a first transistor;

[0018] The gate of the first transistor serves as a control terminal of the charge and discharge control unit, the first electrode of the first transistor serves as a first terminal of the charge and discharge control unit, and the second electrode of the first transistor serves as a second terminal of the charge and discharge control unit.

[0019] Optionally, the charging and discharging unit includes a first inductor, a diode and a first capacitor;

[0020] The first end of the first inductor is connected to the power input end, the second end of the first inductor is connected to the anode of the diode and to the second end of the charge and discharge control unit, the cathode of the diode is connected to the first pole of the first capacitor and serves as the output end of the voltage conversion circuit, and the second pole of the first capacitor is grounded.

[0021] The technical solution of the embodiment of the present invention generates multiple clock signals according to the current output voltage and reference voltage of the voltage conversion circuit by setting a clock signal generating unit. The ratio of the periods of the multiple clock signals is an integer multiple of the base. When the control signal is formed by multiple clock signals, the duty cycle of the control signal can be adjusted according to the minimum half-period of the multiple clock signals, so that the output voltage can be adjusted according to the minimum half-period of the multiple clock signals, thereby improving the adjustment accuracy of the output voltage. At the same time, the maximum period of the multiple clock signals can be used to ensure the adjustment range of the charging time of the charge-discharge unit, thereby ensuring the adjustment range of the output voltage. Moreover, the logic control unit can select the clock signal of the discharge phase according to the discharge phase control signal, and then control the charging time of the charge-discharge unit in the next charge-discharge cycle through the clock signal of the discharge phase, so that the output voltage of the next charge-discharge cycle can be directly adjusted according to the difference between the output voltage and the reference voltage, thereby reducing the difficulty of controlling the output voltage, simplifying the circuit structure of the voltage conversion circuit, and reducing the cost of the voltage conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a voltage converter provided by the prior art;

[0023] Figure 2 A schematic diagram of the structure of a voltage conversion circuit provided by an embodiment of the present invention;

[0024] Figure 3 A timing diagram of multiple clock signals provided by an embodiment of the present invention;

[0025] Figure 4 A schematic diagram of the structure of a partial voltage conversion circuit provided by an embodiment of the present invention;

[0026] Figure 5 A timing diagram of an n-bit digital signal provided by an embodiment of the present invention;

[0027] Figure 6 for Figure 5 A timing diagram of a clock signal corresponding to the provided digital signal;

[0028] Figure 7 A schematic diagram of the structure of another voltage conversion circuit provided by an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of the voltage and current timing during the operation of a voltage conversion circuit provided by an embodiment of the present invention;

[0030] Fig. 9 A schematic diagram of the structure of a delay unit provided by an embodiment of the present invention;

[0031] Fig.10 A schematic diagram of the structure of another voltage conversion circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0033] Figure 2 Schematic diagram of a voltage conversion circuit provided by an embodiment of the present invention. Figure 2As shown, the voltage conversion circuit includes a charge and discharge control unit 110, a charge and discharge unit 120, a clock signal generating unit 130 and a logic control unit 140; the first input terminal IN1 of the clock signal generating unit 130 is connected to the output terminal VOUT of the voltage conversion circuit, the second input terminal IN2 of the clock signal generating unit 130 is used to input a reference voltage, multiple output terminals of the clock signal generating unit 130 are connected to multiple first input terminals IN3 of the logic control unit 140, and the second input terminal IN4 of the logic control unit 140 is used to input a discharge stage control signal; the output terminal of the logic control unit 140 is connected to the control terminal CDT2 of the charge and discharge control unit 110, and the charge and discharge control The first end of the charge and discharge control unit 110 is grounded GND, the second end of the charge and discharge control unit 110 is connected to the second end N1 of the charge and discharge unit 120, the first end of the charge and discharge unit 120 is connected to the power input end VDD, and the output end of the charge and discharge unit 120 serves as the output end VOUT of the voltage conversion circuit; the clock signal generating unit 130 is used to generate a plurality of clock signals according to the output voltage of the voltage conversion circuit and the reference voltage; the logic control unit 140 is used to form a control signal according to the plurality of clock signals and the discharge stage control signal; the charge and discharge control unit 110 is used to control the charging time of the charge and discharge unit 120 according to the control signal; wherein the ratio of the periods of the plurality of clock signals is an integer multiple of the base digit.

[0034] Specifically, the working process of the voltage conversion circuit includes a charging stage and a discharging stage. The reference voltage can be set according to the preset output voltage of the voltage conversion circuit. When the current output voltage of the voltage conversion circuit is greater than the reference voltage, the clock signal generating unit 130 can perform analog-to-digital conversion according to the difference between the current output voltage of the voltage conversion circuit and the reference voltage, generate a digital signal with a certain number of digits in a certain system, and generate multiple clock signals according to the digital signal. At this time, the number of multiple clock signals is the same as the number of digits of the digital signal. The ratio of the periods of the multiple clock signals is an integer multiple of the system, so that each digit of the digital signal corresponds to a clock signal of one cycle, so that the multiple clock signals can represent the difference between the current output voltage and the reference voltage. Moreover, the periods of different clock signals are different. When a control signal is formed by multiple clock signals, the duty cycle of the control signal can be adjusted according to the minimum half cycle of the multiple clock signals. Then, when the charge and discharge control unit 110 controls the charging time of the charge and discharge unit 120 according to the control signal, the output voltage can be adjusted according to the minimum half cycle of the multiple clock signals, thereby improving the adjustment accuracy of the output voltage. At the same time, the maximum period of multiple clock signals can be used to ensure the adjustment range of the charging time of the charging and discharging unit 120, thereby ensuring the adjustment range of the output voltage. Figure 3 A timing diagram of multiple clock signals provided by an embodiment of the present invention. Figure 3As shown, when the base digit is 2 and the number of bits is 4, the clock signal generating unit 130 can generate 4 clock signals according to the difference between the output voltage and the reference voltage, which are CLK corresponding to the low bit and the high bit in sequence. <0> ,CLK <1> ,CLK <2> and CLK <3> .CLK <1> The period is CLK <0> 2 times, CLK <2> The period is CLK <1> 2 times, CLK <3> The period is CLK <2> 2 times of CLK <0> The clock cycle is relatively small. <0> to CLK <3> When the output voltage is adjusted by four clock signals, CLK <0> The high and low levels of CLK adjust the charging time of the charging and discharging unit 120, so that the charging time of the charging and discharging unit 120 is adjusted with an accuracy of CLK <0> half of the cycle, thereby improving the regulation accuracy of the output voltage. <3> The high and low potentials adjust the charging time of the charging and discharging unit 120, which can ensure the adjustment range of the charging time of the charging and discharging unit 120, and further ensure the adjustment range of the output voltage.

[0035] The discharge phase control signal can be used to characterize that the voltage conversion circuit is in the discharge phase. After determining multiple clock signals, the logic control unit 140 can select the clock signal of the discharge phase according to the discharge phase control signal, and then control the charging time of the next charge and discharge cycle of the charge and discharge unit 120 through the clock signal of the discharge phase, so that the output voltage of the next charge and discharge cycle can be directly adjusted according to the difference between the output voltage and the reference voltage, which reduces the difficulty of controlling the output voltage, simplifies the circuit structure of the voltage conversion circuit, and reduces the cost of the voltage conversion circuit.

[0036] The technical solution of this embodiment generates multiple clock signals according to the current output voltage and reference voltage of the voltage conversion circuit by setting a clock signal generating unit. The ratio of the periods of the multiple clock signals is an integer multiple of the base. When the control signal is formed by multiple clock signals, the duty cycle of the control signal can be adjusted according to the minimum half-period of the multiple clock signals, so that the output voltage can be adjusted according to the minimum half-period of the multiple clock signals, thereby improving the adjustment accuracy of the output voltage. At the same time, the maximum period of the multiple clock signals can be used to ensure the adjustment range of the charging time of the charge-discharge unit, thereby ensuring the adjustment range of the output voltage. Moreover, the logic control unit can select the clock signal of the discharge phase according to the discharge phase control signal, and then control the charging time of the charge-discharge unit in the next charge-discharge cycle through the clock signal of the discharge phase, so that the output voltage of the next charge-discharge cycle can be directly adjusted according to the difference between the output voltage and the reference voltage, thereby reducing the difficulty of controlling the output voltage, simplifying the circuit structure of the voltage conversion circuit, and reducing the cost of the voltage conversion circuit.

[0037] Figure 4 FIG. 1 is a schematic diagram of a partial voltage conversion circuit provided by an embodiment of the present invention. Figure 4 As shown, the clock signal generating unit 130 includes an analog-to-digital converter 131 and a clock generator 132; the first input terminal of the analog-to-digital converter 131 is connected to the output terminal VOUT of the voltage conversion circuit, the second input terminal of the analog-to-digital converter 131 is used to input a reference voltage, and the analog-to-digital converter 131 is used to form an n-bit digital signal Dout according to the difference between the output voltage and the reference voltage. <0> -Dout <n-1>Wherein, n is an integer greater than or equal to 1; the input end of the clock generator 132 is connected to the output end of the analog-to-digital converter 131 in a one-to-one correspondence, and the multiple output ends of the clock generator 132 are connected to the multiple first input ends IN3 of the logic control unit 140. The clock generator 132 is used to generate a digital signal according to the n-bit digital signal Dout <0> -Dout <n-1>Forming n clock signals CLK <0> -CLK <n-1>; Among them, the n-bit digital signal Dout <0> -Dout <n-1>From low to high, the next digital signal Dout <k>The corresponding clock signal CLK <k>The cycle of the previous digital signal Dout <k-1>The corresponding clock signal CLK <k-1>m times the period of , where m is the value of the base.

[0038] Specifically, the first input terminal of the analog-to-digital converter 131 serves as the first input terminal IN1 of the clock signal generating unit 130, and the second input terminal of the analog-to-digital converter 131 serves as the second input terminal IN2 of the clock signal generating unit 130. The analog-to-digital converter 131 has an n-bit serial output interface. The analog-to-digital converter 131 can compare the current output voltage of the voltage conversion circuit with the reference voltage, and form an n-bit digital signal Dout according to the difference between the current output voltage and the reference voltage. <0> -Dout <n-1>In the same base, the n-bit digital signal Dout <0> -Dout <n-1>The corresponding value is set corresponding to the difference between the current output voltage of the voltage conversion circuit and the reference voltage. <0> -Dout <n-1>The base number is binary, and the number of bits is 4. When the difference between the current output voltage of the voltage conversion circuit and the reference voltage is 1V, the n-bit digital signal Dout <0> -Dout <n-1>The corresponding binary value can be 1, that is, 0001. When the difference between the current output voltage of the voltage conversion circuit and the reference voltage is 5V, the n-bit digital signal Dout <0> -Dout <n-1>The corresponding binary value can be 5, that is, 0101.

[0039] The number of input terminals and the number of output terminals of the clock generator 132 are the same as the number of bits of the digital signal output by the analog-to-digital converter 131. <0> -Dout <n-1>After that, each digital signal is output to an input terminal of the clock generator 132, so that the clock generator 132 generates a clock signal of a corresponding period according to the digital signal. <0> -Dout <n-1>From low to high, the next digital signal Dout <k>The corresponding clock signal CLK <k>The cycle of the previous digital signal Dout <k-1>The corresponding clock signal CLK <k-1>The period of n clock signals CLK is m times, where m is the value of the base bit. <0> -CLK <n-1>The period of the n clock signal CLK is gradually increased. Different clock signal periods can correspond to different time adjustment precisions and time adjustment ranges of the charge and discharge unit 120. <0> -CLK <n-1>By adjusting the duty cycle of the control signal to control the charge and discharge control unit 110 to adjust the different charging times of the charge and discharge unit 120, the time adjustment accuracy of the charge and discharge unit 120 can be improved, and the time adjustment range can be guaranteed, thereby improving the adjustment accuracy of the output voltage and ensuring the adjustment range of the output voltage. Then the clock generator 132 converts the n clock signals CLK <0> -CLK <n-1>The output is sent to a plurality of first input terminals IN3 of the logic control unit 140. The logic control unit 140 selects n clock signals CLK according to the discharge phase control signal. <0> -CLK <n-1>The timing control of the charge and discharge unit 120 in the discharge stage controls the charging time in the next charge and discharge cycle, and the output voltage of the next charge and discharge cycle can be directly adjusted according to the difference between the output voltage and the reference voltage, which reduces the difficulty of controlling the output voltage, simplifies the circuit structure of the voltage conversion circuit, and reduces the cost of the voltage conversion circuit.

[0040] Based on the above technical solution, the n-bit digital signal Dout <0> -Dout <n-1>When the bit value of is 1, the clock signal of the corresponding bit is valid, and the n-bit digital signal Dout <0> -Dout <n-1>When the bit value is 0, the clock signal of the corresponding bit is invalid.

[0041] Specifically, the validity of the clock signal output by the clock generator 132 may match the value of the corresponding bit of the digital signal. <0> -Dout <n-1>The bit value of is the value of each bit in the digital signal, which can be 0 or 1. When the clock signal is valid, the clock signal has a certain duty cycle in the corresponding period. When the clock signal is invalid, the clock signal is low level in the corresponding period. <0> -Dout <n-1>The value of adjusts the validity of the clock signal, thereby adjusting the charging time of the charging and discharging unit 120. Figure 5 A timing diagram of an n-bit digital signal provided by an embodiment of the present invention, Figure 6 for Figure 5 The timing diagram of a clock signal corresponding to the digital signal provided. Figure 5 and Figure 6 As shown in the figure, when the digital signal is binary, the number of bits is 4, and the period of the digital signal is 8ns, within 4 periods, the 4-bit digital signal Dout <0> -Dout <3> From low to high, the value of the first digital signal can be 1101, that is, Dout <0> =1101, the value of the second digital signal can be 0101, that is, Dout <1> =0101, the value of the third digital signal can be 1010, that is, Dout <2> =1010, the value of the fourth digital signal can be 1001, that is, Dout <3> =1001. At this time, the 4-bit digital signal Dout <0> -Dout <3> From low to high, 4 clock signals CLK <0> ,CLK <1> ,CLK <2> and CLK <3> In, CLK <3> The period is 8ns, CLK <2> The period is 4ns, CLK <1> The period is 2ns, CLK <0> The period is 1ns. In the period of the first digital signal, the 4-bit digital signal is 1101, so the clock signal CLK corresponding to the first digital signal is <0> The first digital cycle is a clock signal with a period of 1ns, and the second digital signal corresponds to the clock signal CLK <1> The clock signal CLK corresponding to the third digital signal is low level in the first digital cycle. <2> The first digital cycle is a clock signal with a period of 4ns. The clock signal CLK corresponding to the fourth digital signal is <3> The first digital cycle is a clock signal with a period of 8 ns. Then the logic control unit 140 generates a clock signal according to CLK <0> ,CLK <1> ,CLK <2> and CLK <3> The four clock signals control the charge and discharge control unit 110 to adjust the charging time of the charge and discharge unit 120, thereby adjusting the output voltage of the voltage conversion circuit. Similarly, in the second digital signal cycle, the four digital signals are 0011, and the clock signal CLK corresponding to the first digital signal is <0> The second digital cycle is a clock signal with a period of 1ns. The clock signal CLK corresponding to the second digital signal <1> The second digital cycle is a clock signal with a period of 2ns. The clock signal CLK corresponding to the third digital signal is <2> In the second digital cycle, it is at a low level, and the clock signal CLK corresponding to the fourth digital signal <3> In the second digital cycle, it is low level. In the third digital signal cycle, 4 is the digital signal 0100, then the clock signal CLK corresponding to the first digital signal <0> In the third digital cycle, the clock signal CLK corresponding to the second digital signal is low. <1> The third digital cycle is low level, and the clock signal CLK corresponding to the third digital signal <2> The clock signal with a period of 4ns in the third digital cycle, the clock signal CLK corresponding to the fourth digital signal <3> It is low during the third digital cycle.In the fourth digital signal cycle, 4 is the digital signal 1011, then the clock signal CLK corresponding to the first digital signal is <0> The fourth digital cycle is a clock signal with a period of 1ns. The clock signal CLK corresponding to the second digital signal is <1> The fourth digital cycle is a clock signal with a period of 2ns. The clock signal CLK corresponding to the third digital signal is <2> In the fourth digital cycle, the clock signal CLK corresponding to the fourth digital signal is low. <3> The fourth digital cycle is a clock signal with a period of 8 ns.

[0042] Continue to refer Figure 4 and Figure 6 The logic control unit 140 includes an OR gate 141 and an AND gate 142; multiple input ends of the OR gate 141 are connected to multiple output ends of the clock signal generating unit 130, the output end of the OR gate 141 is connected to the first input end of the AND gate 142, the second input end of the AND gate 142 is used to input the discharge stage control signal, and the output end of the AND gate 142 is connected to the control end of the charge and discharge control unit 110.

[0043] Specifically, the multiple input terminals of the OR gate 141 are connected to the multiple output terminals of the clock signal generating unit 130 as the multiple first input terminals IN3 of the logic control unit 140, and are used to input a clock signal respectively, and perform a logic OR on the multiple clock signals to form the adjustment signal CDS, and then output the adjustment signal CDS to the first terminal of the AND gate 142. The second terminal of the AND gate 142 inputs the discharge stage control signal, and the discharge stage control signal is used to characterize the discharge stage of the voltage conversion circuit. When the discharge stage control signal is logic high, the AND gate 142 can output the adjustment signal CDS to the control terminal CDT2 of the charge and discharge control unit 110, so that the clock signal corresponding to the difference between the current output voltage and the reference voltage can be output in the discharge stage, so that the charge and discharge control unit 110 controls the charging time of the charge and discharge unit 120 according to the clock signal in the next charge and discharge cycle, thereby adjusting the output voltage.

[0044] Figure 7 FIG. 1 is a schematic diagram of another voltage conversion circuit provided by an embodiment of the present invention. Figure 7 As shown, the voltage conversion circuit also includes a delay unit 150; the input terminal IN5 of the delay unit 150 is connected to the output terminal of the logic control unit 140, and the output terminal of the delay unit 150 is connected to the control terminal CDT2 of the charge and discharge control unit 110. The delay unit 150 is used to delay the control signal.

[0045] Specifically, the delay unit 150 can delay the control signal output by the logic control unit 140, so that the charge and discharge control unit 110 controls the charging time of the charge and discharge unit 120 according to the clock signal in the next charge and discharge cycle, thereby adjusting the output voltage according to the clock signal in the next charge and discharge cycle.

[0046] Figure 8 The following is a schematic diagram of the voltage and current timing of a voltage conversion circuit during operation provided by an embodiment of the present invention. Figure 8 As shown, the delay time of the delay unit 150 is the time t1 from the end of the discharge phase of the current charge and discharge cycle to the end of the last valid level of the control signal in the discharge phase.

[0047] Specifically, Figure 8 exemplarily shows a timing diagram of the charging current I_COIL, the output voltage Vout and the control signal CDT of the voltage conversion circuit during two charging and discharging cycles. In the charging phase CHARGE, the charging and discharging unit 120 is charged, the charging current I_COIL in the charging and discharging unit 120 gradually increases, and the output voltage Vout gradually decreases. The output voltage Vout is less than the reference voltage V CM , the control signal CDT outputs a low level signal. In the discharge phase DISCHARGE, the charge-discharge unit 120 discharges, the charging current I_COIL in the charge-discharge unit 120 gradually decreases, and the output voltage Vout gradually increases. When the output voltage Vout is greater than the reference voltage V CM When the clock signal generating unit 130 generates a signal according to the output voltage Vout and the reference voltage V CM A plurality of clock signals are generated, and the logic control unit 140 forms a control signal according to the clock signal and the discharge stage control signal, and then delays the control signal by t1 through the delay unit 150, so that the control signal starts to be output in the charging stage CHARGE of the next charge and discharge cycle, and the charge and discharge control unit 110 controls the charging time of the charge and discharge unit 120 to be reduced according to the control signal, thereby reducing the output voltage.

[0048] Fig. 9 A schematic diagram of the structure of a delay unit provided by an embodiment of the present invention. Fig. 9 As shown, the delay unit 150 includes an adjustable resistor Rt1 and an adjustable capacitor Ct1; the first end of the adjustable resistor Rt1 is connected to the output end of the logic control unit 140, the second end of the adjustable resistor Rt1 is connected to the first end of the adjustable capacitor Ct1, and is connected to the control end CDT2 of the charge and discharge control unit 110, and the second end of the adjustable capacitor Ct1 is grounded GND.

[0049] Specifically, the delay time of the delay unit 150 is the product of the resistance value of the adjustable resistor Rt1 and the capacitance value of the adjustable capacitor Ct1. When different control signals correspond to different delay times, the resistance value of the adjustable resistor Rt1 and / or the capacitance value of the adjustable capacitor Ct1 can be adjusted according to demand, so that the delay time of the delay unit 150 can be adjusted, so that the charge and discharge control unit 110 controls the charging time of the charge and discharge unit 120 through the control signal in the next charge and discharge cycle to adjust the output voltage.

[0050] Continue to refer Fig. 9 The delay unit 150 also includes a first inverter F1 and a second inverter F2; the first inverter F1 is connected in series between the first end of the adjustable resistor Rt1 and the output end of the logic control unit 140, and the second inverter F2 is connected in series between the second end of the adjustable resistor Rt1 and the control end CDT2 of the charge and discharge control unit 110.

[0051] Specifically, the first inverter F1 and the second inverter F2 can shape the control signal and increase the driving capability of the control signal. At the same time, the first inverter F1 and the second inverter F2 have a reverse effect. Through the two inversions of the first inverter F1 and the second inverter F2, the phase of the control signal can be guaranteed to remain unchanged.

[0052] Fig.10 FIG. 1 is a schematic diagram of another voltage conversion circuit provided by an embodiment of the present invention. Fig.10 As shown, the charge and discharge control unit 110 includes a first transistor T1; the gate of the first transistor T1 serves as the control terminal CDT2 of the charge and discharge control unit 110, the first electrode of the first transistor T1 serves as the first terminal of the charge and discharge control unit 110, and the second electrode of the first transistor T1 serves as the second terminal of the charge and discharge control unit 110.

[0053] Specifically, Fig.10 exemplarily shows that the first transistor T1 is an N-type MOS tube. When the control signal is at a high level, the first transistor T1 is turned on to control the charge and discharge unit 120 to charge. When the control signal is at a low level, the first transistor T1 is turned off to control the charge and discharge unit 120 to discharge. Thus, the duty cycle of the control signal can be adjusted to adjust the charge and discharge time of the charge and discharge unit 120, thereby adjusting the output voltage.

[0054] Continue to refer Fig.10 The charge and discharge unit 120 includes a first inductor LT, a diode DT and a first capacitor CT; a first end of the first inductor LT is connected to the power input terminal VDD, a second end of the first inductor LT is connected to the anode of the diode DT, and is connected to the second end of the charge and discharge control unit 110, a cathode of the diode DT is connected to the first electrode of the first capacitor CT, and serves as the output terminal VOUT of the voltage conversion circuit, and a second electrode of the first capacitor CT is grounded GND.

[0055] Specifically, when the control signal is at a high level, the first transistor T1 is turned on, the input power provided by the power input terminal VDD, the first inductor LT and the first transistor T1 form a charging loop, the input power charges the first inductor LT, and the current on the first inductor LT increases. At this time, the first capacitor CT is discharged to provide power to the output terminal VOUT, and the output voltage of the output terminal VOUT decreases. When the control signal is at a low level, the first transistor T1 is turned off, the first inductor LT, the diode DT and the first capacitor CT form a discharge loop, the first inductor LT is discharged to provide power to the output terminal VOUT, and the current on the first inductor LT decreases. At this time, the first capacitor CT is charged, and the output voltage of the output terminal VOUT increases. After the clock signal generating unit 130 forms a plurality of clock signals according to the current output voltage and the reference voltage, the logic control unit 140 generates a control signal according to the plurality of clock signals, and after the delay unit 150 performs a delay, the first transistor T1 can control the charge and discharge time of the first inductor LT according to the duty cycle of the control signal, thereby adjusting the output voltage of the voltage conversion circuit.

[0056] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims. < / k> < / k> < / k> < / k>

Claims

1. A voltage conversion circuit, characterized in that: It includes a charge and discharge control unit, a charge and discharge unit, a clock signal generating unit and a logic control unit; The first input end of the clock signal generating unit is connected to the output end of the voltage conversion circuit, the second input end of the clock signal generating unit is used to input a reference voltage, the multiple output ends of the clock signal generating unit are connected to the multiple first input ends of the logic control unit, and the second input end of the logic control unit is used to input a discharge stage control signal; the output end of the logic control unit is connected to the control end of the charge and discharge control unit, the first end of the charge and discharge control unit is grounded, the second end of the charge and discharge control unit is connected to the second end of the charge and discharge unit, the first end of the charge and discharge unit is connected to the power input end, and the output end of the charge and discharge unit serves as the output end of the voltage conversion circuit; The clock signal generating unit is used to generate a plurality of clock signals according to the output voltage of the voltage conversion circuit and the reference voltage; the logic control unit is used to form a control signal according to the plurality of clock signals and the discharge stage control signal; the charge and discharge control unit is used to control the charging time of the charge and discharge unit according to the control signal; wherein the ratio of the periods of the plurality of clock signals is an integer multiple of the base digit; The logic control unit includes an OR gate and an AND gate; multiple input ends of the OR gate are connected to multiple output ends of the clock signal generating unit, the output end of the OR gate is connected to the first input end of the AND gate, the second input end of the AND gate is used to input the discharge stage control signal, and the output end of the AND gate is connected to the control end of the charge and discharge control unit.

2. The voltage conversion circuit according to claim 1, characterized in that: The clock signal generating unit includes an analog-to-digital converter and a clock generator; The first input terminal of the analog-to-digital converter is connected to the output terminal of the voltage conversion circuit, the second input terminal of the analog-to-digital converter is used to input a reference voltage, and the analog-to-digital converter is used to form an n-bit digital signal according to the difference between the output voltage and the reference voltage; wherein n is an integer greater than or equal to 1; The input end of the clock generator is connected to the output end of the analog-to-digital converter in a one-to-one correspondence, and the multiple output ends of the clock generator are connected to the multiple first input ends of the logic control unit. The clock generator is used to form n clock signals according to the n-bit digital signal; wherein, from the low bit to the high bit of the n-bit digital signal, the period of the clock signal corresponding to the next bit of the digital signal is m times the period of the clock signal corresponding to the previous and next digital signals, and m is the value of the base bit.

3. The voltage conversion circuit according to claim 2, characterized in that: When the bit value of the n-bit digital signal is 1, the clock signal of the corresponding bit is valid, and when the bit value of the n-bit digital signal is 0, the clock signal of the corresponding bit is invalid.

4. The voltage conversion circuit according to any one of claims 1 to 3, characterized in that: It also includes a delay unit; the input end of the delay unit is connected to the output end of the logic control unit, the output end of the delay unit is connected to the control end of the charge and discharge control unit, and the delay unit is used to delay the control signal.

5. The voltage conversion circuit according to claim 4, characterized in that: The delay time of the delay unit is the time from the end of the discharge phase of the current charge and discharge cycle to the end of the last valid level of the control signal in the discharge phase.

6. The voltage conversion circuit according to claim 4, characterized in that: The delay unit includes an adjustable resistor and an adjustable capacitor; The first end of the adjustable resistor is connected to the output end of the logic control unit, the second end of the adjustable resistor is connected to the first end of the adjustable capacitor and to the control end of the charge and discharge control unit, and the second end of the adjustable capacitor is grounded.

7. The voltage conversion circuit according to claim 6, characterized in that: The delay unit also includes a first inverter and a second inverter; the first inverter is connected in series between the first end of the adjustable resistor and the output end of the logic control unit, and the second inverter is connected in series between the second end of the adjustable resistor and the control end of the charge and discharge control unit.

8. The voltage conversion circuit according to claim 1, characterized in that: The charge and discharge control unit includes a first transistor; The gate of the first transistor serves as a control terminal of the charge and discharge control unit, the first electrode of the first transistor serves as a first terminal of the charge and discharge control unit, and the second electrode of the first transistor serves as a second terminal of the charge and discharge control unit.

9. The voltage conversion circuit according to claim 1, characterized in that: The charging and discharging unit includes a first inductor, a diode and a first capacitor; The first end of the first inductor is connected to the power input end, the second end of the first inductor is connected to the anode of the diode and to the second end of the charge and discharge control unit, the cathode of the diode is connected to the first pole of the first capacitor and serves as the output end of the voltage conversion circuit, and the second pole of the first capacitor is grounded.

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