A rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision

Abstract

The present invention discloses a rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision, which relates to the field of integrated circuit technology. The amplifier circuit includes an input stage circuit, an intermediate stage circuit, a compensation circuit and an output stage circuit; the input stage circuit is used to achieve rail-to-rail input through a group of PMOS and NMOS differential pairs, the intermediate stage circuit is used to improve precision and stabilize the common mode through a pair of operational amplifier transistors, the compensation circuit is used to achieve voltage clamping of the circuit, and the output stage circuit is used to achieve rail-to-rail output and drive the load. The present invention enables the input and output signal swings to basically reach the positive and negative power supply rails. In the design of the input stage, the high current consumption caused by conventional designs is avoided. At the same time, the design of the intermediate stage can greatly increase the precision of the circuit, and it can be applied to high-precision signal processing circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a rail-to-rail operational amplifier circuit with low offset voltage, low noise, and high precision. Background Art

[0002] A rail-to-rail operational amplifier is an amplifier that can reach the limit of the power supply voltage range at both the input and output terminals. Conventional operational amplifiers usually cannot reach the power supply rail voltage at the input and output terminals, while the rail-to-rail operational amplifier realizes that its input voltage approaches the positive and negative power supply rails through a parallel complementary differential pair structure, and the output voltage can reach close to the power supply rail through a class-AB output structure, thereby greatly expanding the dynamic range of the input and output swing of the operational amplifier, enabling the input signal and output signal to cover the entire power supply voltage range, and thus improving the dynamic range and signal processing ability of the system. High-precision rail-to-rail operational amplifiers are widely used in fields such as sensor signal conditioning, power management, data acquisition systems, and medical devices. In sensor signal conditioning, the rail-to-rail operational amplifier can process weak signals and amplify them to a wider dynamic range; in power management, its high-precision characteristics can improve power efficiency and stability; in data acquisition systems, the rail-to-rail operational amplifier can improve sampling accuracy and signal quality; in medical devices, its high-precision and low-noise characteristics help improve the accuracy of detection and diagnosis. At the same time, in the application scenarios of operational amplifiers, offset is a key factor that cannot be ignored. The input offset voltage greatly affects the amplification accuracy of the operational amplifier, and reducing offset is an important part of the operational amplifier design. Therefore, the research on high-precision rail-to-rail operational amplifiers has become a hot topic in the current research field of operational amplifiers. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a rail-to-rail operational amplifier circuit with low offset voltage, low noise, and high precision.

[0004] The purpose of the present invention is achieved through the following technical solutions:

[0005] A rail-to-rail operational amplifier circuit with low offset voltage, low noise, and high precision includes an input stage circuit, an intermediate stage circuit, a compensation circuit, and an output stage circuit;

[0006] The first output terminal of the input stage circuit is connected to the first input terminal of the intermediate stage circuit, the second output terminal of the input stage circuit is connected to the second input terminal of the intermediate stage circuit, the first output terminal of the intermediate stage circuit is connected to the first input terminal of the compensation circuit and the first input terminal of the output stage circuit, and the second output terminal of the intermediate stage circuit is connected to the second input terminal of the compensation circuit and the second input terminal of the output stage circuit;

[0007] The input stage circuit is used to achieve rail-to-rail input through a set of PMOS and NMOS differential pairs. The intermediate stage circuit is used to improve accuracy and stabilize the common mode through a pair of operational amplifier transistors. The compensation circuit is used to achieve voltage clamping of the circuit. The output stage circuit is used to achieve rail-to-rail output and drive the load.

[0008] Further, the input stage circuit includes a DC current source I, a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a ninth NMOS transistor N9;

[0009] The first output terminal of the DC current source I is connected to the positive power supply voltage. The second output terminal of the DC current source I is connected to the drain of the seventh NMOS transistor N7, and the sources of the first and second PMOS transistors P1 and P2. The gate of the seventh NMOS transistor N7 is connected to the second output terminal of the fourth DC voltage source V4. The source of the seventh NMOS transistor N7 is connected to the gates of the eighth and ninth NMOS transistors N8 and N9, and the drain of the eighth NMOS transistor N8. The drain of the ninth NMOS transistor N9 is connected to the sources of the first and second NMOS transistors N1 and N2. The drain of the second NMOS transistor N2 is connected to the drain of the third PMOS transistor P3 and the source of the fifth PMOS transistor P5. The drain of the first NMOS transistor N1 is connected to the drain of the fourth PMOS transistor P4 and the source of the sixth PMOS transistor P6. The sources of the third and fourth PMOS transistors P3 and P4 are connected to the positive power supply voltage. The drain of the second PMOS transistor P2 is connected to the source of the fifth NMOS transistor N5 and the drain of the third NMOS transistor N3. The source of the first PMOS transistor P1 is connected to the source of the sixth NMOS transistor N6 and the drain of the fourth NMOS transistor N4. The gates of the third PMOS transistor P3 and the fourth NMOS transistor N4 are connected to the second output terminal of the first voltage source V1. The gates of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are connected to the second output terminal of the second voltage source V2. The gates of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to the second output terminal of the third voltage source V3. The sources of the eighth, ninth, third, and fourth NMOS transistors N8, N9, N3, and N4, and the first output terminals of the first, second, third, and fourth DC voltage sources V1, V2, V3, and V4 are connected to the negative power supply voltage. The first input terminal VP is connected to the gates of the first NMOS transistor N1 and the first PMOS transistor P1. The second input terminal VN is connected to the gates of the second NMOS transistor N2 and the second PMOS transistor P2. The first output terminal VO1 is connected to the drains of the fifth PMOS transistor P5 and the fifth NMOS transistor N5. The second output terminal VO2 is connected to the drains of the sixth PMOS transistor P6 and the sixth NMOS transistor N6, and the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4.

[0010] Further, the intermediate stage circuit includes a first operational amplifier and a second operational amplifier;

[0011] The inverting input terminal of the first operational amplifier is connected to the first output terminal VO1 of the input stage circuit. The non-inverting input terminal of the second operational amplifier is connected to the second output terminal VO2 of the input stage circuit. The non-inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are both grounded and connected to the negative power supply voltage of the input stage circuit.

[0012] Further, the output stage circuit includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4;

[0013] The gates of the seventh, eighth, ninth, and tenth PMOS transistors P7, P8, P9, and P10 are connected to the first input terminal VIN1 of the output stage circuit. The gates of the tenth, eleventh, twelfth, and thirteenth NMOS transistors N10, N11, N12, and N13 are connected to the second input terminal VIN2 of the output stage circuit. The sources of the seventh, eighth, ninth, and tenth PMOS transistors are connected to the positive power supply voltage. The sources of the tenth, eleventh, twelfth, and thirteenth NMOS transistors are connected to the negative power supply voltage. The first end of the first resistor R1 is connected to the drains of the seventh PMOS transistor P7 and the tenth NMOS transistor N10. The first end of the second resistor R2 is connected to the drains of the eighth PMOS transistor P8 and the eleventh NMOS transistor N11. The first end of the third resistor R3 is connected to the drains of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12. The first end of the fourth resistor R4 is connected to the drains of the tenth PMOS transistor P10 and the thirteenth NMOS transistor N13. The output terminal VOUT is connected to the second ends of the first, second, third, and fourth resistors R1, R2, R3, and R4;

[0014] The first input terminal VIN1 of the output stage circuit is connected to the output terminal of the first operational amplifier of the intermediate stage circuit. The second input terminal VIN2 is connected to the output terminal of the second operational amplifier of the intermediate stage circuit.

[0015] Further, the compensation circuit includes a second DC current source I2, a third DC current source I3, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, and a seventeenth NMOS transistor N17;

[0016] The source of the eleventh PMOS transistor P11 is connected to the positive power supply voltage. The drain of the eleventh PMOS transistor P11 is connected to the gate of the eleventh PMOS transistor P11, the source of the twelfth PMOS transistor P12, and the source of the fourteenth NMOS transistor N14. The drain of the twelfth PMOS transistor P12 is connected to the gate of the twelfth PMOS transistor P12 and the source of the thirteenth PMOS transistor P13. The gate of the thirteenth PMOS transistor P13 is connected to the gate of the fourteenth NMOS transistor N14, the drain of the fourteenth NMOS transistor N14, and the second output terminal of the second DC current source I2. The drain of the thirteenth PMOS transistor P13 is connected to the first output terminal of the second DC current source I2 and the negative power supply voltage.

[0017] The source of the fourteenth NMOS transistor N14 is connected to the negative power supply voltage. The drain of the fourteenth NMOS transistor N14 is connected to the gate of the fourteenth NMOS transistor N14, the source of the fifteenth NMOS transistor N15, and the source of the seventeenth NMOS transistor N17. The drain of the fifteenth NMOS transistor N15 is connected to the gate of the fifteenth NMOS transistor N15 and the source of the sixteenth NMOS transistor N16. The gate of the sixteenth NMOS transistor N16 is connected to the gate of the seventeenth NMOS transistor N17, the drain of the seventeenth NMOS transistor N17, and the second output terminal of the third DC current source I3. The drain of the sixteenth NMOS transistor N16 and the first output terminal of the third DC current source I3 are connected to the positive power supply voltage. The first input / output terminal IO1 is connected to the drain of the twelfth PMOS transistor P12. The second input / output terminal IO2 is connected to the drain of the fifteenth NMOS transistor N15.

[0018] The first input / output terminal IO1 of the compensation circuit is connected to the first input terminal VIN1 of the output stage circuit, and the second input / output terminal IO2 is connected to the second input terminal VIN2 of the output stage circuit.

[0019] The beneficial effects of the present invention are as follows: The present invention designs a rail-to-rail operational amplifier circuit with low noise, low offset, and high precision, enabling the input and output signal swings to basically reach the positive and negative power supply rails. In the design of the input stage, the higher current consumption caused by conventional designs is avoided, and at the same time, the design of the intermediate stage can greatly increase the precision of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is the circuit diagram of the overall circuit in the present invention;

[0021] Figure 2 is the circuit diagram of the input stage circuit in the present invention;

[0022] Figure 3 is the circuit diagram of the output stage circuit in the present invention;

[0023] Figure 4This is the structural block diagram of the compensation circuit in the present invention. Detailed implementation manners

[0024] Next, the technical solution of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

[0025] Refer to Figures 1-4 , the present invention provides a technical solution:

[0026] A rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision, as Figure 1 shown, includes an input stage circuit, an intermediate stage circuit, a compensation circuit and an output stage circuit connected in sequence;

[0027] The input stage circuit is used to achieve rail-to-rail input through a group of PMOS and NMOS differential pairs. The intermediate stage circuit is used to improve the precision and stabilize the common mode through a pair of five-transistor operational amplifiers. The compensation circuit is used to achieve voltage clamping of the circuit. The output stage circuit is used to achieve rail-to-rail output and drive the load.

[0028] Furthermore, the input stage circuit includes a DC current source I, a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a ninth NMOS transistor N9;

[0029] The first output terminal of the DC voltage source I is connected to the positive power supply voltage. The second output terminal is connected to the drain of the seventh NMOS transistor N7, and the sources of the first and second PMOS transistors P1 and P2. The gate of the seventh NMOS transistor N7 is connected to the second output terminal of the fourth DC voltage source V4. The source of the seventh NMOS transistor N7 is connected to the gates of the eighth and ninth NMOS transistors N8 and N9, and the drain of the eighth NMOS transistor N8. The drain of the ninth NMOS transistor N9 is connected to the sources of the first and second NMOS transistors N1 and N2. The drain of the second NMOS transistor N2 is connected to the drain of the third PMOS transistor P3 and the source of the fifth PMOS transistor P5. The drain of the first NMOS transistor N1 is connected to the drain of the fourth PMOS transistor P4 and the source of the sixth PMOS transistor P6. The sources of the third and fourth PMOS transistors P3 and P4 are connected to the power supply voltage. The drain of the second PMOS transistor P2 is connected to the source of the fifth NMOS transistor N5 and the drain of the third NMOS transistor N3. The source of the first PMOS transistor P1 is connected to the source of the sixth NMOS transistor N6 and the drain of the fourth NMOS transistor N4. The gates of the third PMOS transistor P3 and the fourth PMOS transistor N4 are connected to the second output terminal of the first voltage source V1. The gates of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are connected to the second output terminal of the second voltage source V2. The gates of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to the second output terminal of the third voltage source V3. The sources of the eighth, ninth, third, and fourth NMOS transistors N8, N9, N3, and N4, and the first output terminals of the first, second, third, and fourth DC voltage sources V1, V2, V3, and V4 are connected to the negative power supply voltage. The sources of the third and fourth PMOS transistors P3 and P4 are connected to the positive power supply voltage. The input terminal VP is connected to the gates of the first NMOS transistor N1 and the first PMOS transistor P1. The input terminal VN is connected to the gates of the second NMOS transistor N2 and the second PMOS transistor P2. The output terminal VO1 is connected to the drains of the fifth PMOS transistor P5 and the fifth NMOS transistor N5. The output terminal VO2 is connected to the drains of the sixth PMOS transistor P6 and the sixth NMOS transistor N6, and the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4.

[0030] In this embodiment, when the input voltage (i.e., the common-mode input voltage) applied across the input terminals VP and VN approaches the negative power supply voltage rail, the first NMOS transistor N1 and the second NMOS transistor N2 are turned off, and only the first PMOS transistor P1 and the second PMOS transistor P2 are operating. At this time, the signal flows through the first PMOS transistor P1, the second PMOS transistor P2, and the summing circuit composed of the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 to the subsequent circuit.

[0031] When the input voltage is near the mid - value between the positive and negative supply voltages, the first NMOS transistor N1, the second NMOS transistor N2, the first PMOS transistor P1, and the second PMOS transistor P2 are all in the on state. However, since the two differential pairs use the same DC current source I, by reasonably selecting the value of the fourth DC voltage source V4, the currents flowing through the PMOS differential pair and the NMOS differential pair are reasonably distributed to ensure that the transconductance of the input stage is in a relatively constant region;

[0032] When the input voltage approaches the positive power supply voltage rail, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, and only the first NMOS transistor N1 and the second NMOS transistor N2 are working. The current of the DC current source I flows through the first NMOS transistor N1 and the second NMOS transistor N2 through the current mirror composed of the seventh NMOS transistor N7, the eighth NMOS transistor N8, and the ninth NMOS transistor, and then flows to the subsequent circuit through the summing circuit composed of the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6.

[0033] In this embodiment, Figure 2 the input - stage circuit can satisfy the full - swing of the input level between the positive power supply voltage rail and the negative power supply voltage rail. And compared with the commonly used constant - transconductance structure, only one current source is used for biasing in this embodiment, reducing the power consumption of the input - stage circuit.

[0034] Further, the intermediate - stage circuit includes a first operational amplifier and a second operational amplifier;

[0035] The inverting input terminal of the first operational amplifier is connected to the first output terminal VO1 of the input - stage circuit, and the non - inverting input terminal of the second operational amplifier is connected to the second output terminal VO2 of the input - stage circuit; the non - inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are both grounded (connected to the negative power supply voltage of the input - stage circuit).

[0036] In this embodiment, when the entire operational amplifier is connected to a closed - loop system, after the intermediate - stage operational amplifier is connected, the voltages of the first output terminal VO1 and the second output terminal VO2 of the input - stage circuit tend to be equal, and the entire circuit has better symmetry, thus greatly improving the common - mode rejection ratio under DC input of the circuit and improving the accuracy of the overall circuit.

[0037] In a specific embodiment, such as Figure 3, the output stage circuit includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4;

[0038] The gates of the seventh, eighth, ninth, and tenth PMOS transistors P7, P8, P9, and P10 are connected to the first input terminal VIN1 of the output stage circuit. The gates of the tenth, eleventh, twelfth, and thirteenth NMOS transistors N10, N11, N12, and N13 are connected to the second input terminal VIN2 of the output stage circuit. The sources of the seventh, eighth, ninth, and tenth PMOS transistors are connected to the positive power supply voltage. The sources of the tenth, eleventh, twelfth, and thirteenth NMOS transistors are connected to the negative power supply voltage. The first end of the first resistor R1 is connected to the drains of the seventh PMOS transistor P7 and the tenth NMOS transistor N10. The first end of the second resistor R2 is connected to the drains of the eighth PMOS transistor P8 and the eleventh NMOS transistor N11. The first end of the third resistor R3 is connected to the drains of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12. The first end of the fourth resistor R4 is connected to the drains of the tenth PMOS transistor P10 and the thirteenth NMOS transistor N13. The output terminal VOUT is connected to the second ends of the first, second, third, and fourth resistors R1, R2, R3, and R4;

[0039] The first input terminal VIN1 of the output stage circuit is connected to the output terminal of the first operational amplifier in the intermediate stage circuit. The second input terminal VIN2 is connected to the output terminal of the second operational amplifier in the intermediate stage circuit.

[0040] In a specific embodiment, such as Figure 4 , the compensation circuit includes a second DC current source I2, a third DC current source I3, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, and a seventeenth NMOS transistor N17;

[0041] The source of the eleventh PMOS transistor P11 is connected to the positive power supply voltage. The drain of the eleventh PMOS transistor P11 is connected to the gate of the eleventh PMOS transistor P11, the source of the twelfth PMOS transistor P12, and the source of the fourteenth NMOS transistor N14. The drain of the twelfth PMOS transistor P12 is connected to the gate of the twelfth PMOS transistor P12 and the source of the thirteenth PMOS transistor P13. The gate of the thirteenth PMOS transistor P13 is connected to the gate of the fourteenth NMOS transistor N14, the drain of the fourteenth NMOS transistor N14, and the second output terminal of the second DC current source I2. The drain of the thirteenth PMOS transistor P13 and the first output terminal of the second DC current source I2 are connected to the negative power supply voltage;

[0042] The source of the fourteenth NMOS transistor N14 is connected to the negative power supply voltage. The drain of the fourteenth NMOS transistor N14 is connected to the gate of the fourteenth NMOS transistor N14, the source of the fifteenth NMOS transistor N15, and the source of the seventeenth NMOS transistor N17. The drain of the fifteenth NMOS transistor N15 is connected to the gate of the fifteenth NMOS transistor N15 and the source of the sixteenth NMOS transistor N16. The gate of the sixteenth NMOS transistor N16 is connected to the gate of the seventeenth NMOS transistor N17, the drain of the seventeenth NMOS transistor N17, and the second output terminal of the third DC current source I3. The drain of the sixteenth NMOS transistor N16 and the first output terminal of the third DC current source I3 are connected to the positive power supply voltage. The first input / output terminal IO1 is connected to the drain of the twelfth PMOS transistor P12. The second input / output terminal IO2 is connected to the drain of the fifteenth NMOS transistor N15;

[0043] The first input / output terminal IO1 of the compensation circuit is connected to the first input terminal VIN1 of the output stage circuit. The second input / output terminal IO2 is connected to the second input terminal VIN2 of the output stage circuit.

[0044] In this embodiment, in order to prevent the output stage current from increasing due to process variations, a compensation circuit is introduced to clamp the potential, thereby reducing the excessive current consumption caused by process errors. At the same time, a bias is provided for the MOS transistors in the output stage circuit. As Figure 4As shown, under normal circumstances, the twelfth PMOS transistor P12 and the second NMOS transistor N2 are turned off, and there are only two current paths: the eleventh PMOS transistor P11, the fourteenth PMOS transistor P14, the second DC current source I2, and the fourteenth NMOS transistor N14, the seventeenth NMOS transistor N17, and the third DC current source I3. When the potential of IO1 drops, the twelfth PMOS transistor P12 conducts. The circuit generates an additional current path. Since the gate potentials of the thirteenth PMOS transistor P13 and the fourteenth PMOS transistor P14 are the same and the source potential of the thirteenth PMOS transistor P13 is lower than that of the fourteenth PMOS transistor P14, the current flowing through the thirteenth PMOS transistor P13 is less than the current flowing through the fourteenth PMOS transistor P14. However, due to the large width-to-length ratio of the twelfth PMOS transistor P12, a large current will be generated. Therefore, the excess current will flow out through the path of the first operational amplifier OP1 in the intermediate-stage circuit, which will cause the current asymmetry between the left and right paths of the first operational amplifier OP1 in the intermediate-stage circuit. When all the current flows through one path of the first operational amplifier in the intermediate stage, the potential of IO1 at this time is the lowest potential that this point can reach. Similarly, for the input / output terminal IO2, when all the current flows through one path of the second operational amplifier in the intermediate stage, the potential of IO2 at this time is the highest potential that this point can reach.

[0045] In this example, in order to achieve low noise of the operational amplifier, according to the flicker noise expression, a relatively large value is set for the product of the width and length W*L of the first PMOS transistor P1 and the second PMOS transistor P2 in the input-stage circuit. At the same time, a relatively large value is also set for the product of the width and length W*L of the first NMOS transistor N1 and the second NMOS transistor N2 in the input stage, so that lower noise can be achieved. Since the operational amplifier in the intermediate stage of this example also generates a gain, the operational amplifier gain of this example is not particularly low.

[0046] In order to achieve low offset voltage of the operational amplifier, on the one hand, the sizes of the two pairs of transistors in the current mirror are increased proportionally to reduce the mismatch of the current mirror and thus achieve the purpose of low offset. On the other hand, by setting a Triming circuit in the circuit, after the chip is produced, the current flowing into the summing circuit of the input-stage pair of transistors is adjusted through trimming technology to further reduce the mismatch of the circuit.

[0047] The above description is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications, and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in related fields. And any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention should fall within the protection scope of the appended claims of the present invention.

Claims

1. A rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision, characterized in that: It includes an input stage circuit, an intermediate stage circuit, a compensation circuit, and an output stage circuit; The first output terminal of the input stage circuit is connected to the first input terminal of the intermediate stage circuit, and the second output terminal of the input stage circuit is connected to the second input terminal of the intermediate stage circuit. The first output terminal of the intermediate stage circuit is connected to the first input terminal of the compensation circuit and the first input terminal of the output stage circuit, and the second output terminal of the intermediate stage circuit is connected to the second input terminal of the compensation circuit and the second input terminal of the output stage circuit; The input stage circuit is used to achieve rail-to-rail input through a group of PMOS and NMOS differential pairs. The intermediate stage circuit is used to improve accuracy and stabilize the common mode through a pair of operational amplifier transistors. The compensation circuit is used to achieve voltage clamping of the circuit. The output stage circuit is used to achieve rail-to-rail output and drive the load; The input stage circuit includes a DC current source I, a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a ninth NMOS transistor N9; The first output terminal of the DC current source I is connected to the positive power supply voltage. The second output terminal of the DC current source I is connected to the drain of the seventh NMOS transistor N7, and the sources of the first and second PMOS transistors P1 and P2. The gate of the seventh NMOS transistor N7 is connected to the second output terminal of the fourth DC voltage source V4. The source of the seventh NMOS transistor N7 is connected to the gates of the eighth and ninth NMOS transistors N8 and N9, and the drain of the eighth NMOS transistor N8. The drain of the ninth NMOS transistor N9 is connected to the sources of the first and second NMOS transistors N1 and N2. The drain of the second NMOS transistor N2 is connected to the drain of the third PMOS transistor P3 and the source of the fifth PMOS transistor P5. The drain of the first NMOS transistor N1 is connected to the drain of the fourth PMOS transistor P4 and the source of the sixth PMOS transistor P6. The sources of the third and fourth PMOS transistors P3 and P4 are connected to the positive power supply voltage. The drain of the second PMOS transistor P2 is connected to the source of the fifth NMOS transistor N5 and the drain of the third NMOS transistor N3. The source of the first PMOS transistor P1 is connected to the source of the sixth NMOS transistor N6 and the drain of the fourth NMOS transistor N4. The gates of the third PMOS transistor P3 and the fourth PMOS transistor N4 are connected to the second output terminal of the first voltage source V1. The gates of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are connected to the second output terminal of the second voltage source V2. The gates of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to the second output terminal of the third voltage source V3. The sources of the eighth, ninth, third, and fourth NMOS transistors N8, N9, N3, and N4, and the first output terminals of the first, second, third, and fourth DC voltage sources V1, V2, V3, and V4 are connected to the negative power supply voltage. The first input terminal VP is connected to the gates of the first NMOS transistor N1 and the first PMOS transistor P1. The second input terminal VN is connected to the gates of the second NMOS transistor N2 and the second PMOS transistor P2. The first output terminal VO1 is connected to the drains of the fifth PMOS transistor P5 and the fifth NMOS transistor N5. The second output terminal VO2 is connected to the drains of the sixth PMOS transistor P6 and the sixth NMOS transistor N6, and the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4; The intermediate stage circuit includes a first operational amplifier and a second operational amplifier; The inverting input terminal of the first operational amplifier is connected to the first output terminal VO1 of the input stage circuit. The non-inverting input terminal of the second operational amplifier is connected to the second output terminal VO2 of the input stage circuit. The non-inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are both grounded and connected to the negative power supply voltage of the input stage circuit; The output stage circuit includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; The gates of the seventh, eighth, ninth, and tenth PMOS transistors P7, P8, P9, and P10 are connected to the first input terminal VIN1 of the output stage circuit. The gates of the tenth, eleventh, twelfth, and thirteenth NMOS transistors N10, N11, N12, and N13 are connected to the second input terminal VIN2 of the output stage circuit. The sources of the seventh, eighth, ninth, and tenth PMOS transistors are connected to the positive power supply voltage. The sources of the tenth, eleventh, twelfth, and thirteenth NMOS transistors are connected to the negative power supply voltage. The first end of the first resistor R1 is connected to the drains of the seventh PMOS transistor P7 and the tenth NMOS transistor N10. The first end of the second resistor R2 is connected to the drains of the eighth PMOS transistor P8 and the eleventh NMOS transistor N11. The first end of the third resistor R3 is connected to the drains of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12. The first end of the fourth resistor R4 is connected to the drains of the tenth PMOS transistor P10 and the thirteenth NMOS transistor N13. The output terminal VOUT is connected to the second ends of the first, second, third, and fourth resistors R1, R2, R3, and R4; The first input terminal VIN1 of the output stage circuit is connected to the output terminal of the first operational amplifier of the intermediate stage circuit. The second input terminal VIN2 is connected to the output terminal of the second operational amplifier of the intermediate stage circuit; The compensation circuit includes a second DC current source I2, a third DC current source I3, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, and a seventeenth NMOS transistor N17; The source of the eleventh PMOS transistor P11 is connected to the positive power supply voltage. The drain of the eleventh PMOS transistor P11 is connected to the gate of the eleventh PMOS transistor P11, the source of the twelfth PMOS transistor P12, and the source of the fourteenth NMOS transistor N14. The drain of the twelfth PMOS transistor P12 is connected to the gate of the twelfth PMOS transistor P12 and the source of the thirteenth PMOS transistor P13. The gate of the thirteenth PMOS transistor P13 is connected to the gate of the fourteenth NMOS transistor N14, the drain of the fourteenth NMOS transistor N14, and the second output terminal of the second DC current source I2. The drain of the thirteenth PMOS transistor P13 and the first output terminal of the second DC current source I2 and the negative power supply voltage are connected; The source of the fourteenth NMOS transistor N14 is connected to the negative power supply voltage. The drain of the fourteenth NMOS transistor N14 is connected to the gate of the fourteenth NMOS transistor N14, the source of the fifteenth NMOS transistor N15, and the source of the seventeenth NMOS transistor N17. The drain of the fifteenth NMOS transistor N15 is connected to the gate of the fifteenth NMOS transistor N15 and the source of the sixteenth NMOS transistor N16. The gate of the sixteenth NMOS transistor N16 is connected to the gate of the seventeenth NMOS transistor N17, the drain of the seventeenth NMOS transistor N17, and the second output terminal of the third DC current source I3. The drain of the sixteenth NMOS transistor N16 and the first output terminal of the third DC current source I3 are connected to the positive power supply voltage. The first input / output terminal IO1 is connected to the drain of the twelfth PMOS transistor P12. The second input / output terminal IO2 is connected to the drain of the fifteenth NMOS transistor N15; The first input / output terminal IO1 of the compensation circuit is connected to the first input terminal VIN1 of the output stage circuit, and the second input / output terminal IO2 is connected to the second input terminal VIN2 of the output stage circuit.

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