Duty cycle adjustment circuit, delay locked loop circuit and memory

Abstract

The present application discloses a duty cycle adjustment circuit, a delay locked loop circuit and a memory, wherein a duty cycle adjustment link in the duty cycle adjustment circuit receives an input clock signal and adjusts the duty cycle of the input clock signal to generate an output clock signal; a duty cycle detection circuit is coupled to the duty cycle adjustment link and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal; an initial state confirmation circuit is coupled to the duty cycle adjustment link and is used to detect the duty cycle of the output clock signal in the initial state of the duty cycle adjustment link and generate a corresponding second detection signal based on the duty cycle of the output clock signal; an adjustment circuit is coupled to the duty cycle detection circuit and the initial state confirmation circuit and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate an output clock signal.

Description

Technical Field

[0001] The present application relates to the technical field of duty cycle regulation, and in particular to a duty cycle adjustment circuit, a delay locked loop circuit and a memory. Background Art

[0002] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream random access memory and a typical semiconductor memory. DDR-type memory is designed to synchronously input or output data on both the rising and falling edges of the clock signal. Therefore, the clock signal's duty cycle must be precisely maintained at 50%. To this end, chips typically use a duty cycle adjustment circuit to adjust the clock signal's duty cycle, narrowing clock signals with a duty cycle above 50% and widening clock signals with a duty cycle below 50%. However, in existing duty cycle adjustment circuits, proper operation depends on establishing an accurate initial state, a problem that is largely overlooked in existing technologies. If the initial state is inaccurate, the duty cycle adjustment circuit will not only fail to adjust the duty cycle, but may also lose the clock signal, resulting in data transmission distortion. Summary of the Invention

[0003] In order to solve the above problems, the present application provides a duty cycle adjustment circuit, a delay phase-locked loop circuit and a memory to ensure the normal operation of the duty cycle adjustment link, avoid serious deviation of the duty cycle of the output clock signal and ensure the accuracy of data signal transmission.

[0004] To solve the above technical problems, a technical solution adopted in the present application is: providing a duty cycle adjustment circuit, which includes a duty cycle adjustment link, a duty cycle detection circuit, an initial state confirmation circuit and an adjustment circuit, wherein the duty cycle adjustment link receives an input clock signal and adjusts the duty cycle of the input clock signal to generate an output clock signal; the duty cycle detection circuit is coupled to the duty cycle adjustment link, and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal; the initial state confirmation circuit is coupled to the duty cycle adjustment link, and is used to detect the duty cycle of the output clock signal in the initial state of the duty cycle adjustment link, and generate a corresponding second detection signal based on the duty cycle of the output clock signal; the adjustment circuit is coupled to the duty cycle detection circuit and the initial state confirmation circuit, and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate an output clock signal.

[0005] The initial state confirmation circuit includes an inverter chain and a buffer unit. The inverter chain includes multiple inverter units connected in series. The input end of the inverter chain receives the output clock signal, the output end of the inverter chain is connected to the input end of the buffer unit, and the output end of the buffer unit is coupled to the adjustment circuit. The inverter chain generates a corresponding output voltage based on the output clock signal. The buffer unit is used to shape the output voltage to obtain a second detection signal.

[0006] Among them, the input end of the inverter unit at the head end of the inverter chain serves as the input end of the inverter chain to receive the output clock signal, the input end of each non-head end inverter unit is connected to the output end of the inverter unit of the previous level, and the output end of the inverter unit at the end of the inverter chain serves as the output end of the inverter chain and is connected to the input end of the buffer unit.

[0007] Each inverter unit includes a first transistor, a second transistor, and a capacitor; the control terminal of the first transistor is connected to the control terminal of the second transistor; and a first node between the control terminal of the first transistor and the control terminal of the second transistor serves as an input terminal of the inverter unit; a first channel terminal of the first transistor receives a reference voltage, a second channel terminal of the first transistor is connected to the first channel terminal of the second transistor, the second channel terminal of the second transistor is grounded, and a second node between the second channel terminal of the first transistor and the first channel terminal of the second transistor serves as an output terminal of the inverter unit; a first terminal of the capacitor is connected to the second node, and a second terminal of the capacitor is grounded.

[0008] Among them, the first transistor is a PMOS tube, and the second transistor is an NMOS tube. When the input signal of the input end of the inverter unit is at a high level, the second transistor is turned on and the capacitor performs a discharge operation; when the input signal of the input end of the inverter unit is at a low level, the first transistor is turned on and the capacitor performs a charging operation.

[0009] In which, in response to the duty cycle of the output clock signal being less than 0.5, the voltage at the output end of each inverter unit is less than the voltage at the input end of the inverter unit; the output voltage generated by the inverter chain approaches zero, and the second detection signal is shaped into a low-level signal; in response to the duty cycle of the output clock signal being greater than 0.5, the voltage at the output end of each inverter unit is greater than the voltage at the input end of the inverter unit, the output voltage generated by the inverter chain approaches the reference voltage, and the second detection signal is shaped into a high-level signal.

[0010] In which, the duty cycle adjustment circuit also includes: a logic circuit, the logic circuit is coupled to the duty cycle detection circuit, the initial state confirmation circuit and the adjustment circuit, the logic circuit is used to perform logical operations based on the first detection signal and the second detection signal to obtain a logic control signal, and send the logic control signal to the adjustment circuit; wherein, in response to being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the second detection signal; in response to not being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the first detection signal.

[0011] The logic circuit is any combination of a D flip-flop, a logic AND gate, a logic OR gate, and a logic NOT gate.

[0012] To solve the above technical problems, another technical solution adopted in this application is: providing a delay phase-locked loop circuit, which includes the above-mentioned duty cycle adjustment circuit and a control logic module, the control logic module is connected to the initial state confirmation circuit, and in response to the duty cycle adjustment link being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to a valid state; in response to the duty cycle adjustment link not being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to an invalid state.

[0013] In order to solve the above technical problem, another technical solution adopted in the present application is: providing a memory, which includes the above-mentioned delay locked loop circuit.

[0014] Different from the prior art, the duty cycle adjustment circuit of the present application includes a duty cycle adjustment link, a duty cycle detection circuit, an initial state confirmation circuit and an adjustment circuit. The duty cycle adjustment link receives an input clock signal and adjusts the duty cycle of the input clock signal to generate an output clock signal; the duty cycle detection circuit is coupled to the duty cycle adjustment link and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal; the initial state confirmation circuit is coupled to the duty cycle adjustment link and is used to detect the duty cycle of the output clock signal in the initial state of the duty cycle adjustment link and generate a corresponding second detection signal based on the duty cycle of the output clock signal; the adjustment circuit is coupled to the duty cycle detection circuit and the initial state confirmation circuit and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate an output clock signal. Through the above-described method, the duty cycle adjustment circuit of the present application can perform preliminary duty cycle detection on the output clock signal through the initial state confirmation circuit to determine the initial state of the duty cycle adjustment link, ensure the normal operation of the duty cycle adjustment link, avoid the uncertain state X of the duty cycle detection circuit when the duty cycle deviates significantly, ensure the correct transmission of data, and guarantee the accuracy of data signal transmission. In other words, for an output clock signal with a duty cycle that deviates significantly from 50%, when the clock link reaches the duty cycle detection circuit through a long routing, clock loss may occur, causing the entire loop to fail. However, the initial state confirmation circuit of the present application can detect a wider range of duty cycles, can detect output clock signals with a duty cycle that deviates significantly from 50%, and determine the correct loop state, so that the entire duty cycle adjustment circuit loop can normally adjust the clock signal duty cycle to approximately 50%, and ensure the normal operation of the duty cycle detection circuit and the entire loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0016] Figure 1 is a schematic diagram of a first embodiment of a duty cycle adjustment circuit provided by the present application;

[0017] Figure 2 1 is a schematic structural diagram of an embodiment of a duty cycle detection circuit;

[0018] Figure 3 It is a structural diagram of an embodiment of a duty cycle adjustment circuit in the prior art;

[0019] Figure 4 This is a circuit structure diagram of an embodiment of an initial state confirmation circuit provided by the present application;

[0020] Figure 5 This is a schematic diagram of the circuit structure of an inverter unit 1 provided by the present application;

[0021] Figure 6 This is a schematic diagram of the working principle of an inverter unit according to an embodiment of the present application;

[0022] Figure 7 is a schematic diagram of a second embodiment of a duty cycle adjustment circuit provided by the present application;

[0023] Figure 8 1 is a schematic structural diagram of an embodiment of a delay-locked loop circuit provided by the present application;

[0024] Figure 9 It is a structural diagram of an embodiment of the memory of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream random access memory and a typical semiconductor memory. DDR-type memory is designed to synchronously input or output data on both the rising and falling edges of the clock signal. Therefore, the clock signal's duty cycle must be precisely maintained at 50%. To this end, chips typically use a duty cycle adjustment circuit to adjust the clock signal's duty cycle, narrowing clock signals with a duty cycle above 50% and widening clock signals with a duty cycle below 50%. However, in existing duty cycle adjustment circuits, proper operation depends on establishing an accurate initial state, a problem that is largely overlooked in existing technologies. If the initial state is inaccurate, the duty cycle adjustment circuit will not only fail to adjust the duty cycle, but may also lose the clock signal, resulting in data transmission distortion.

[0028] In order to solve the above problems, this application first proposes a duty cycle adjustment circuit. Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the first embodiment of the duty cycle adjustment circuit provided by the present application. Figure 1 As shown, the duty cycle adjustment circuit 100 of this embodiment includes a duty cycle adjustment link 10 , a duty cycle detection circuit 20 , an initial state confirmation circuit 30 and an adjustment circuit 40 .

[0029] Among them, the duty cycle adjustment link 10 receives the input clock signal CLKIN and adjusts the duty cycle of the input clock signal CLKIN to generate the output clock signal CLKOUT; the duty cycle detection circuit 20 is coupled to the duty cycle adjustment link 10, and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal CLKOUT; the initial state confirmation circuit 30 is coupled to the duty cycle adjustment link 10, and is used to detect the duty cycle of the output clock signal CLKOUT in the initial state of the duty cycle adjustment link 10, and generate a corresponding second detection signal based on the duty cycle of the output clock signal CLKOUT; the adjustment circuit 40 is coupled to the duty cycle detection circuit 20 and the initial state confirmation circuit 30, and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link 10 adjusts the duty cycle of the input clock signal CLKIN to generate the output clock signal CLKOUT.

[0030] In this embodiment, the duty cycle detection circuit 20 is used to detect the duty cycle of the clock signal CLKOUT output by the duty cycle adjustment link 10. In response to the duty cycle of the output clock signal CLKOUT being greater than 50%, the first detection signal is a logic signal 1. In response to the duty cycle of the output clock signal CLKOUT being less than 50%, the first detection signal is a logic signal 0.

[0031] For example, see Figure 2 , Figure 2 FIG. 1 is a schematic diagram showing the structure of an embodiment of a duty cycle detection circuit. Figure 2 As shown, the duty cycle detection circuit 20 includes a single-ended to dual-ended converter circuit 21, a level detection circuit 22, and a comparator 23, which are connected in sequence. The duty cycle detection circuit 20 receives the output clock signal CLKOUT as input. The output clock signal CLKOUT is converted by the single-ended to dual-ended converter circuit 21 into a first differential clock signal LDCCR and a second differential clock signal LDCCF. The level detection circuit 22 detects the duration of the high and low levels of the first and second differential clock signals LDCCR and LDCCF, generating a first voltage analog signal LCMPR and a second voltage analog signal LCMPF representing the effective high and low levels. These signals are then sent to the comparator 23 for comparison, generating a first detection signal indicating whether the duty cycle is greater than 50%. In other embodiments, the duty cycle detection circuit 20 can also be implemented in other forms, which are not limited here.

[0032] In this embodiment, the adjustment circuit 40 may further include a state machine, for example, a finite state machine (FSM). When the state machine receives the control signal generated by the first detection signal of the duty cycle detection circuit 20 and the second detection signal of the initial state confirmation circuit 30, it generates a corresponding control code Code based on the control signal. <n:1>The duty cycle adjustment link 10 further includes a bias voltage generating module, which can receive a corresponding control code Code <n:1>Generate a corresponding bias voltage to act on the duty cycle adjustment link 10 to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT. In other embodiments, the adjustment circuit 40 can also be a controller or other form. The controller can receive the first detection signal of the duty cycle detection circuit 20 and the second detection signal of the initial state confirmation circuit 30 to generate a control signal, and obtain a corresponding control code based on the control signal through a logical operation in the controller to control the offset delay time of the rising edge and falling edge of the duty cycle adjustment link 10 to adjust the duty cycle of the output clock signal CLKOUT. In other embodiments, the bias voltage generation module can also be set in the adjustment circuit 40. In this embodiment, the bias voltage generation module in the adjustment circuit 40 outputs the bias voltage to the duty cycle adjustment link 10 to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT.

[0033] Also, see Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a structure of an embodiment of a duty cycle adjustment circuit in the prior art. Figure 3 As shown, in the existing technology, the initial state of the duty cycle regulation link 10 is not confirmed during the operation of the duty cycle regulation link 10, and the first detection signal output by the duty cycle detection circuit 20 is an unknown X state, which causes the duty cycle of the clock signal output by the duty cycle regulation link 10 to deviate seriously. For example, the duty cycle of the clock signal CLKIN input to the duty cycle adjustment link 10 is already greater than 50%. Under normal circumstances, the duty cycle adjustment link 10 should be adjusted in the direction of narrowing the duty cycle. However, since the first detection signal output by the duty cycle detection circuit 20 in the first cycle is unknown, if the first detection signal output in the first cycle controls the adjustment circuit 40 to increase the duty cycle of the output clock signal CLKOUT output by the duty cycle adjustment link 10, it will cause the duty cycle adjustment link 10 to be incorrectly adjusted, so that the duty cycle of the output clock signal CLKOUT is much greater than 50%, and the duty cycle seriously deviates from the clock signal of 50%. When the duty cycle adjustment link 10 reaches the duty cycle detection circuit 20 through a long wiring, the clock signal is easily lost, causing the entire loop to fail and normal data transmission to be impossible.

[0034] Therefore, in this embodiment, in order to determine the initial state of the duty cycle adjustment link 10, ensure that the duty cycle adjustment link 10 can operate normally and avoid serious deviation of the duty cycle, such as Figure 1 As shown, an initial state confirmation circuit 30 needs to be added to the duty cycle adjustment circuit 100. The initial state confirmation circuit 30 detects the duty cycle of the output clock signal CLKOUT in the initial state of the duty cycle adjustment link 10 and generates a corresponding second detection signal based on the duty cycle of the output clock signal CLKOUT. Here, the initial state of the duty cycle adjustment link 10 is the state before the first cycle in which the duty cycle detection circuit 20 outputs the first detection signal. During this period, the initial state confirmation circuit 30 needs to detect the duty cycle of the output clock signal CLKOUT to obtain the second detection signal to determine whether to adjust the duty cycle of the duty cycle adjustment link 10.

[0035] Different from the prior art, the duty cycle adjustment circuit 100 of the present application includes a duty cycle adjustment link 10, a duty cycle detection circuit 20, an initial state confirmation circuit 30 and an adjustment circuit 40. The duty cycle adjustment link 10 receives an input clock signal CLKIN and adjusts the duty cycle of the input clock signal CLKIN to generate an output clock signal CLKOUT; the duty cycle detection circuit 20 is coupled to the duty cycle adjustment link 10 and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal CLKOUT; the initial state confirmation circuit 30 is coupled to the duty cycle adjustment link 10 and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal CLKOUT; The duty cycle adjustment link 10 is coupled to the duty cycle detection circuit 20 and the initial state confirmation circuit 30, and is used to detect the duty cycle of the output clock signal CLKOUT in the initial state of the duty cycle adjustment link 10, and generate a corresponding second detection signal based on the duty cycle of the output clock signal CLKOUT; the adjustment circuit 40 is coupled to the duty cycle detection circuit 20 and the initial state confirmation circuit 30, and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link 10 adjusts the duty cycle of the input clock signal CLKIN to generate the output clock signal CLKOUT. In the above manner, the duty cycle adjustment circuit 100 of the present application can perform preliminary duty cycle detection on the output clock signal CLKOUT through the initial state confirmation circuit 30 to determine the initial state of the duty cycle adjustment link 10, ensure that the duty cycle adjustment link 10 can operate normally, avoid the uncertain state X of the duty cycle detection circuit 20 when the duty cycle deviates seriously, ensure the correct transmission of data, and ensure the accuracy of data signal transmission. That is to say, for the output clock signal CLKOUT whose duty cycle deviates seriously from 50%, when the clock link reaches the duty cycle detection circuit 20 through a long wiring, clock loss may occur, causing the entire loop to fail. The initial state confirmation circuit 30 of the present application can detect a wider range of duty cycles, and can detect the output clock signal CLKOUT whose duty cycle deviates seriously from 50%, and determine the correct loop state, so that the entire loop of the duty cycle adjustment circuit 100 can normally adjust the clock signal duty cycle to about 50%, and ensure the normal operation of the duty cycle detection circuit 20 and the entire loop.

[0036] Optionally, based on the above embodiment, please refer to Figure 4 , Figure 4 1 is a circuit diagram of an embodiment of the initial state confirmation circuit provided by this application. Figure 4 As shown, the initial state confirmation circuit 30 of this embodiment includes an inverter chain 31 and a buffer unit 32. The inverter chain 31 includes a plurality of inverter units 311 connected in series. The input end of the inverter chain 31 receives the output clock signal CLKOUT, the output end of the inverter chain 31 is connected to the input end of the buffer unit 32, and the output end of the buffer unit 32 is coupled to the adjustment circuit 40. The inverter chain 31 generates a corresponding output voltage based on the output clock signal CLKOUT. The buffer unit 32 is used to shape the output voltage to obtain a second detection signal.

[0037] In this embodiment, the following can be used: Figure 4 The inverter chain 31 shown filters the high-frequency output clock signal CLKOUT to obtain an output voltage, and then shapes the output voltage through a buffer to obtain a second detection signal. The second detection signal can also be represented by a logic signal 0 or 1 to indicate whether the duty cycle is greater than or less than 50%. If the duty cycle of the output clock signal CLKOUT is greater than 50%, the second detection signal is a logic signal 1, and if the duty cycle of the output clock signal CLKOUT is less than 50%, the second detection signal is a logic signal 0.

[0038] In addition, in this embodiment, the number of inverter units 311 in the inverter chain 31 can be set to 3 to 4. In other embodiments, the number of inverter units 311 can also be set based on actual conditions and is not limited here.

[0039] Optional, such as Figure 4 As shown, in this embodiment, the input end of the inverter unit 311 at the head end of the inverter chain 31 serves as the input end of the inverter chain 31 to receive the output clock signal CLKOUT, the input end of each non-head end inverter unit 311 is connected to the output end of the inverter unit 311 of the previous stage, and the output end of the inverter unit 311 at the end of the inverter chain 31 serves as the output end of the inverter chain 31 and is connected to the input end of the buffer unit 32.

[0040] Optionally, see Figure 5 , Figure 5 1 is a schematic diagram of the circuit structure of the inverter unit 1 provided by the present application. Figure 5 As shown, in this embodiment, each inverter unit 311 includes a first transistor M1, a second transistor M2 and a capacitor C; the control end of the first transistor M1 is connected to the control end of the second transistor M2; and a first node P between the control end of the first transistor M1 and the control end of the second transistor M2 serves as an input end of the inverter unit 311, a first pass end of the first transistor M1 receives a reference voltage, a second pass end of the first transistor M1 is connected to the first pass end of the second transistor M2, a second pass end of the second transistor M2 is grounded, and a second node Q between the second pass end of the first transistor M1 and the first pass end of the second transistor M2 serves as an output end of the inverter unit 311; a first end of the capacitor C is connected to the second node Q, and a second end of the capacitor C is grounded.

[0041] Optionally, based on Figure 5 In this embodiment, the first transistor M1 is a PMOS tube, and the second transistor M2 is an NMOS tube. In response to the input signal of the input end of the inverter unit 311 being a high level, the second transistor M2 is turned on, and the capacitor C performs a discharge operation; in response to the input signal of the input end of the inverter unit 311 being a low level, the first transistor M1 is turned on, and the capacitor C performs a charging operation.

[0042] In this embodiment, please refer to Figure 6 , Figure 6 This is a schematic diagram of the working principle of an embodiment of the inverter unit provided by this application. Assume that the duty cycle of the output clock signal CLKOUT is a, that is, within a period T of the output clock signal CLKOUT, the high level time is aT, and the low level time is (1-a)T. Figure 6 As shown in (a), when the input signal at the input terminal of the inverter unit 311 is at a high level, the second transistor M2 is turned on, and the capacitor C performs a discharge operation, that is, the charge on the upper plate of the capacitor C flows to the ground terminal. Assume that the conduction current at this time is I; Figure 6 As shown in (b), when the input signal at the input end of the inverter unit 311 is at a low level, the first transistor M1 is turned on, and the capacitor C performs a charging operation, that is, the reference voltage power supply injects charge into the upper plate of the capacitor C.

[0043] Optionally, based on Figure 2 and Figure 3 In the embodiment, in this embodiment, in response to the duty cycle of the output clock signal CLKOUT being less than 0.5, the voltage at the output end of each inverter unit 311 is less than the voltage at the input end of the inverter unit 311; the output voltage generated by the inverter chain 31 approaches zero, and the second detection signal is shaped into a low-level signal; in response to the duty cycle of the output clock signal CLKOUT being greater than 0.5, the voltage at the output end of each inverter unit 311 is greater than the voltage at the input end of the inverter unit 311, the output voltage generated by the inverter chain 31 approaches the reference voltage, and the second detection signal is shaped into a high-level signal.

[0044] Assume that the first transistor M1 and the second transistor M2 are completely matched, and the conduction current at this time is also I. Assume that the voltage at the input end of the inverter unit 311 is V0. After passing through one inverter unit 311, the voltage at the output end of the inverter unit 311 is V out =V0-aIT / C+(1-a)IT / C=V0+(1-2a)IT / C, where a is the duty cycle, I is the on-state current, T is the period of the input clock signal CLKIN, and C is the capacitance. After the output clock signal CLKOUT passes through the inverter chain 31, if the duty cycle a of the output clock signal CLKOUT is greater than 50%, the output voltage of the inverter chain 31 can approach zero, and the second detection signal after buffer shaping is a low-level signal. If the duty cycle a of the output clock signal CLKOUT is less than 50%, the output voltage of the inverter chain 31 can approach the reference voltage, and the second detection signal after buffer shaping is a high-level signal.

[0045] Based on the above embodiment, the initial state confirmation circuit 30 can be understood as a simple duty cycle detection circuit 20. The initial state confirmation circuit 30 and the duty cycle detection circuit 20 can both realize duty cycle detection at the same time. The initial state confirmation circuit 30 assists the duty cycle detection circuit 20 in completing the establishment of the initial state of the duty cycle adjustment link 10. Figure 2 Although the initial state confirmation circuit 30 of this embodiment does not have the same detection accuracy as the duty cycle detection circuit 20, the circuit structure of the initial state confirmation circuit 30 is simple, easy to implement, and small in size, making it sufficient to detect the initial state of the duty cycle adjustment link 10. For an output clock signal CLKOUT with a duty cycle that significantly deviates from 50%, the clock signal may be lost when the duty cycle adjustment link 10 passes through the long wiring to reach the duty cycle detection circuit 20, causing the entire loop to fail. However, the initial state confirmation circuit 30 can detect a wider duty cycle range and can detect output clock signals CLKOUT with a duty cycle that significantly deviates from 50%, helping the duty cycle adjustment circuit 100 determine the correct loop state. This allows the duty cycle adjustment circuit 100 to properly adjust the clock signal's duty cycle to approximately 50%, ensuring normal operation of the duty cycle adjustment circuit 100. In addition, in the present application, the duty cycle range detected by the initial state confirmation circuit 30 is wider than that of the duty cycle detection circuit 20 , and even the duty cycle of the output clock signal CLKOUT can be detected within a range up to 90%.

[0046] Optionally, see Figure 7 , Figure 7 FIG is a schematic diagram of the second embodiment of the duty cycle adjustment circuit provided by this application. Figure 7 As shown, in this embodiment, the duty cycle adjustment circuit 100 further includes a logic circuit 50, which is coupled to the duty cycle detection circuit 20, the initial state confirmation circuit 30 and the adjustment circuit 40. The logic circuit 50 is used to perform a logic operation based on the first detection signal and the second detection signal to obtain a logic control signal, and send the logic control signal to the adjustment circuit 40; wherein, in response to being in the initial state of the duty cycle adjustment link 10, the logic control signal of the logic circuit 50 is consistent with the level of the second detection signal; in response to not being in the initial state of the duty cycle adjustment link 10, the logic control signal of the logic circuit 50 is consistent with the level of the first detection signal.

[0047] In this embodiment, if the duty cycle adjustment link 10 is in the initial state, the logic control signal received by the adjustment circuit 40 is mainly based on the initial state confirmation circuit 30, that is, when the duty cycle adjustment link 10 is in the initial state, the logic control signal of the logic circuit 50 is consistent with the level of the second detection signal output by the initial state confirmation circuit 30; if the duty cycle adjustment link 10 is not in the initial state, that is, after the initial state, the logic control signal received by the adjustment circuit 40 is mainly based on the duty cycle detection circuit 20, and at this time, the logic control signal of the logic circuit 50 is consistent with the level of the first detection signal output by the duty cycle detection circuit 20.

[0048] Optionally, based on the above embodiment, the logic circuit 50 of this embodiment is any combination of a D flip-flop, a logic AND gate, a logic OR gate and a logic NOT gate, and only needs to meet the functions of the above logic circuit 50, which is not limited here.

[0049] Optionally, this application further proposes a delay phase-locked loop circuit, see Figure 8 , Figure 8 FIG. 1 is a schematic diagram of a structure of a delay phase-locked loop circuit according to an embodiment of the present invention. Figure 8 As shown, the delay locked loop circuit 200 of this embodiment includes the duty cycle adjustment circuit 100 of any of the above embodiments and a control logic module 210 .

[0050] Among them, the control logic module 210 is connected to the initial state confirmation circuit 30. In response to the duty cycle adjustment link 10 being in the initial state, the control logic module 210 converts the enable signal of the initial state confirmation circuit 30 to a valid state; in response to the duty cycle adjustment link 10 not being in the initial state, the control logic module 210 converts the enable signal of the initial state confirmation circuit 30 to an invalid state.

[0051] That is, in this embodiment, the control logic module 210 can be used to cause the initial state confirmation circuit 30 to operate only in the initial state of the duty cycle adjustment link 10. Specifically, when the duty cycle adjustment link 10 is enabled, the control logic module 210 converts the enable signal of the initial state confirmation circuit 30 to a valid state. After the duty cycle adjustment link 10 is established, the control logic module 210 sends a reset signal to convert the enable signal of the initial state confirmation circuit 30 to a deactivated state. In this manner, the control logic module 210 can be used to cause the initial state confirmation circuit 30 to operate only in the initial state of the duty cycle adjustment link 10, substantially without affecting the power consumption of the overall circuit.

[0052] Optionally, this application further proposes a memory, see Figure 9 , Figure 9 This is a schematic diagram of the structure of an embodiment of the memory of the present application. Figure 9 As shown, the memory 300 of this embodiment includes the delay locked loop circuit 200 of the above embodiment.

[0053] In this embodiment, the memory 300 may be a random access memory (DRAM), a static random access memory (SRAM), or a pseudo static random access memory (Pseudo SRAM, PSRAM), which is not limited here.

[0054] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A duty cycle adjustment circuit, characterized in that: include: A duty cycle adjustment link receives an input clock signal and adjusts the duty cycle of the input clock signal to generate an output clock signal; a duty cycle detection circuit coupled to the duty cycle adjustment link, and generating a corresponding first detection signal based on the detected duty cycle of the output clock signal; an initial state confirmation circuit, coupled to the duty cycle adjustment link, configured to detect the duty cycle of the output clock signal in an initial state of the duty cycle adjustment link, and generate a corresponding second detection signal based on the duty cycle of the output clock signal; an adjustment circuit, coupled to the duty cycle detection circuit and the initial state confirmation circuit, configured to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate the output clock signal; The initial state confirmation circuit filters the output clock signal in the initial state of the duty cycle adjustment link to obtain an output voltage, and shapes the output voltage to obtain the second detection signal indicating that the duty cycle of the output clock signal is greater than or less than 50%.

2. The duty cycle adjustment circuit according to claim 1, wherein: The initial state confirmation circuit includes an inverter chain and a buffer unit, wherein the inverter chain includes a plurality of inverter units connected in series, an input end of the inverter chain receives the output clock signal, an output end of the inverter chain is connected to an input end of the buffer unit, and an output end of the buffer unit is coupled to the adjustment circuit; The inverter chain generates the corresponding output voltage based on the output clock signal; and the buffer unit is used to shape the output voltage to obtain the second detection signal.

3. The duty cycle adjustment circuit according to claim 2, wherein: The input end of the inverter unit at the head end of the inverter chain serves as the input end of the inverter chain to receive the output clock signal, the input end of each non-head end inverter unit is connected to the output end of the inverter unit of the previous level, and the output end of the inverter unit at the end of the inverter chain serves as the output end of the inverter chain to be connected to the input end of the buffer unit.

4. The duty cycle adjustment circuit according to claim 2, wherein: Each of the inverter units includes a first transistor, a second transistor and a capacitor; The control terminal of the first transistor is connected to the control terminal of the second transistor; and a first node between the control terminal of the first transistor and the control terminal of the second transistor serves as an input terminal of the inverter unit; a first path terminal of the first transistor receives a reference voltage, a second path terminal of the first transistor is connected to the first path terminal of the second transistor, the second path terminal of the second transistor is grounded, and a second node between the second path terminal of the first transistor and the first path terminal of the second transistor serves as an output terminal of the inverter unit; a first terminal of the capacitor is connected to the second node, and a second terminal of the capacitor is grounded.

5. The duty cycle adjustment circuit according to claim 4, wherein: The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. In response to the input signal of the input end of the inverter unit being at a high level, the second transistor is turned on, and the capacitor performs a discharge operation; in response to the input signal of the input end of the inverter unit being at a low level, the first transistor is turned on, and the capacitor performs a charging operation.

6. The duty cycle adjustment circuit according to claim 4, wherein: In response to a duty cycle of the output clock signal being less than 0.5, a voltage at the output end of each inverter unit is less than a voltage at the input end of the inverter unit; the output voltage generated by the inverter chain approaches zero, and the second detection signal is shaped into a low-level signal; In response to a duty cycle of the output clock signal being greater than 0.5, a voltage at the output end of each inverter unit is greater than a voltage at the input end of the inverter unit, the output voltage generated by the inverter chain approaches the reference voltage, and the second detection signal is shaped into a high-level signal.

7. The duty cycle adjustment circuit according to claim 1, wherein: Also includes: a logic circuit, the logic circuit being coupled to the duty cycle detection circuit, the initial state confirmation circuit, and the adjustment circuit, the logic circuit being configured to perform a logic operation based on the first detection signal and the second detection signal to obtain a logic control signal, and send the logic control signal to the adjustment circuit; wherein, in response to being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the second detection signal; In response to not being in the initial state of the duty cycle adjustment link, the logic control signal of the logic circuit is consistent with the level of the first detection signal.

8. The duty cycle adjustment circuit according to claim 7, wherein: The logic circuit is any combination of a D flip-flop, a logic AND gate, a logic OR gate and a logic NOT gate.

9. A delay-locked loop circuit, characterized in that: The invention comprises a duty cycle adjustment circuit and a control logic module as described in any one of claims 1 to 8, wherein the control logic module is connected to the initial state confirmation circuit, and in response to the duty cycle adjustment link being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to a valid state; in response to the duty cycle adjustment link not being in the initial state, the control logic module converts the enable signal of the initial state confirmation circuit to an invalid state.

10. A memory, characterized in that: The delay-locked loop circuit according to claim 9 is included.

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