Analog signal digital remote transmission method and system based on CPLD (Complex Programmable Logic Device)

Abstract

The invention provides an analog signal digital remote transmission method and system based on a CPLD, and relates to the field of water depth power amplifier signal transmission, and the method comprises the steps: S1, starting data transmission, and carrying out the synchronous operation of a coding sending module and a decoding receiving module; and S2, the coding sending module sends the binary character string according to a preset period, and the decoding receiving module reads the binary character string according to the preset period. According to the invention, coding and decoding of binary character strings are carried out through CPLDs in the coding sending module and the decoding receiving module, and the accuracy of data transmission is improved. And high-efficiency and interference-free sending and receiving of signals are realized through the optical fiber sending module and the optical fiber receiving module, so that external interference can be effectively resisted, and the accuracy and the real-time performance of the signals are ensured.

Description

Technical Field

[0001] The invention relates to the field of water depth power amplifier signal transmission, and in particular to a CPLD-based analog signal digital remote transmission method and system. Background Art

[0002] With the continuous development of electronic technology, analog signals have certain limitations in transmission, processing and storage, which has led to the need to digitize analog signals.

[0003] Analog signals are easily affected by external interference during transmission, and the transmission distance of analog signals is limited. Due to the attenuation characteristics of analog signals, exceeding a certain distance will affect the reception and recognition of signals; analog signals are difficult to effectively encrypt during transmission.

[0004] At present, although analog signal digitization technology is relatively mature and communication methods are constantly being updated, the application of these technologies in the field of deep water power amplifiers still faces many challenges. Due to the particularity of the working environment, deep water power amplifiers are easily interfered by external factors when transmitting signals, resulting in signal distortion, making it difficult to monitor the output of deep water power amplifiers in real time in a timely and effective manner. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a CPLD-based analog signal digital remote transmission method and system, which is used to solve the problem that the existing communication equipment is easily interfered by external factors when the deep water power amplifier transmits signals, resulting in signal distortion, and it is difficult to timely and effectively monitor the output of the deep water power amplifier in real time.

[0006] The present invention provides a CPLD-based analog signal digital remote transmission method, comprising: S1: Start data transmission, the encoding and sending module and the decoding and receiving module perform synchronous operation; S2: The encoding and sending module sends the binary string according to a preset period, and the decoding and receiving module reads the binary string according to a preset period.

[0007] Preferably, step S1 specifically comprises: S11: The main control module sends a data transmission instruction to the encoding and sending module and the decoding and receiving module, and the encoding and sending module and the decoding and receiving module read the synchronization code; S12: If the encoding and sending module and the decoding and receiving module complete the reading of the synchronization code at the same time, the encoding and sending module and the decoding and receiving module complete the synchronization and enter step S2; otherwise, return to step S11.

[0008] Preferred: The synchronization code includes: a start segment, a middle segment and an end segment; The start segment consists of four clock cycles of low level; The middle segment consists of a high level of twelve clock cycles; The end segment consists of four clock cycles of low level.

[0009] Preferably, step S2 specifically comprises: S21: After the encoding and sending module and the decoding and receiving module are synchronized, the encoding and sending module transmits binary data to the decoding and receiving module starting from the highest U-th bit of the binary string; S22: the encoding and sending module sends the u-th binary data of the binary string to the decoding and receiving module through the optical fiber sending module within n2 consecutive clock cycles; S23: the decoding receiving module reads through the optical fiber receiving module at the n1th clock cycle, and if it is a high level, it determines that the uth binary data is 1, and if it is a low level, it determines that the uth binary data is 0; n1 is less than n2; S24: let u=u-1; S25: Repeat steps S22-S24 until the transmission of binary data from the Uth bit to the 0th bit of the binary string is completed.

[0010] A CPLD-based analog signal digital remote transmission system, used to implement the CPLD-based analog signal digital remote transmission method, comprising: Main control module, encoding and sending module and decoding and receiving module; The main control module is in communication connection with the encoding and sending module and the decoding and receiving module, and the encoding and sending module is in optical fiber connection with the decoding and receiving module.

[0011] Preferred: The encoding and sending module includes: a first CPLD module, a first power supply processing module, an analog signal voltage following and differential module, an A / D analog-to-digital conversion module, an optical fiber sending driving module and an optical fiber sending module; The first power supply processing module is connected with the first CPLD module, the analog signal voltage follower and differential module, the A / D analog-to-digital conversion module and the optical fiber transmission drive module; The analog signal voltage follower and differential module, the A / D analog-to-digital conversion module, the first CPLD module, the optical fiber transmission drive module and the optical fiber transmission module are connected in sequence.

[0012] Preferred: The decoding receiving module includes: a second CPLD module, a second power supply processing module, an analog signal conditioning module, a D / A digital-to-analog conversion module, a signal comparison module and an optical fiber receiving module; The second power processing module is connected with the second CPLD module, the analog signal conditioning module, the D / A digital-to-analog conversion module and the optical fiber receiving module; The optical fiber receiving module, the signal comparing module, the second CPLD module, the D / A digital-to-analog conversion module and the analog signal conditioning module are connected in sequence.

[0013] Preferred: The first CPLD module has the same structure as the second CPLD module, and the first power supply processing module has the same structure as the second power supply processing module; The CPLD module includes: CPLD interface circuit, active crystal oscillator, download circuit, circuit normal working indication module and indicator light; The power processing module is connected with the CPLD interface circuit, the active crystal oscillator and the circuit normal working indication module; The CPLD interface circuit is connected with the active crystal oscillator, the download circuit and the circuit normal working indication module, and the circuit normal working indication module is connected with the indicator light.

[0014] The present invention has the following beneficial effects: The encoding and decoding of binary strings by CPLD in the encoding and sending module and the decoding and receiving module improves the accuracy of data transmission. The optical fiber sending module and the optical fiber receiving module realize efficient and interference-free signal transmission and reception, which can effectively resist external interference and ensure the accuracy and real-time performance of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a flow chart of a method according to an embodiment of the present invention; Figure 2 An example decoding diagram for the encoding and sending module and the decoding and receiving module; Figure 3 It is the structural diagram of the encoding and sending module; Figure 4 It is the structural diagram of the decoding receiving module; The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0017] Reference Figure 1 The present invention provides a CPLD-based analog signal digital remote transmission method, which can realize the remote transmission, monitoring and control of the output signal of the water depth power amplifier, greatly improving the safety and efficiency of the measurement work.

[0018] include: S1: Start data transmission, the encoding and sending module and the decoding and receiving module perform synchronous operation; Furthermore, step S1 is specifically as follows: S11: The main control module sends a data transmission instruction to the encoding and sending module and the decoding and receiving module, and the encoding and sending module and the decoding and receiving module read the synchronization code; Further, the synchronization code includes: a start segment, a middle segment, and an end segment; The start segment consists of four clock cycles of low level; The middle segment consists of a high level of twelve clock cycles; The end segment consists of four clock cycles of low level.

[0019] Specifically, Figure 2 As shown in the "Sample Decoding Diagram", the CPLD will follow a specific pattern to perform data encoding, transmission or decoding and recovery operations. Data processing starts from the highest bit. Whether it is sending or receiving, it first goes through a synchronization code lasting twenty clock cycles as the start preparation for the operation. The synchronization code consists of three parts, namely blue, red, and blue from left to right in the figure; red represents digital signal 1, and blue represents digital signal 0.

[0020] (1) Start segment: First, the synchronization code starts with a digital signal 0 that lasts for four clock cycles. This digital signal start segment serves as the start mark of synchronization and helps the CPLD identify the beginning of the data stream.

[0021] (2) Middle segment: Next, there is a digital signal 1 that lasts for twelve clock cycles. This signal not only further confirms the progress of the synchronization process, but also enhances the stability and reliability of the synchronization signal through its longer duration.

[0022] (3) End segment: Finally, the synchronization code ends with a digital signal 0 that lasts for four clock cycles again. The digital signal 0 of the end segment echoes the start segment to form a complete synchronization code sequence, marking the completion of the synchronization process and preparing to receive or start processing subsequent data.

[0023] S12: If the encoding and sending module and the decoding and receiving module complete the reading of the synchronization code at the same time, the encoding and sending module and the decoding and receiving module complete the synchronization and enter step S2; otherwise, return to step S11.

[0024] S2: The encoding and sending module sends the binary string according to a preset period, and the decoding and receiving module reads the binary string according to a preset period.

[0025] Furthermore, step S2 is specifically as follows: S21: After the encoding and sending module and the decoding and receiving module are synchronized, the encoding and sending module transmits binary data to the decoding and receiving module starting from the highest U-th bit of the binary string; S22: the encoding and sending module sends the u-th binary data of the binary string to the decoding and receiving module through the optical fiber sending module within n2 consecutive clock cycles; S23: the decoding receiving module reads through the optical fiber receiving module at the n1th clock cycle, and if it is a high level, it determines that the uth binary data is 1, and if it is a low level, it determines that the uth binary data is 0; n1 is less than n2; S24: let u=u-1; S25: Repeat steps S22-S24 until the transmission of binary data from the Uth bit to the 0th bit of the binary string is completed.

[0026] Specifically, Figure 2 As shown in the "Example Decoding Diagram", after the synchronization code ends, the encoding or decoding of valid data begins. The binary number 10 1011 1010 0010 is used as an example. The value of n1 is 4, the value of n2 is 9, and the length of the binary string is 14.

[0027] After receiving the synchronization code signal, the CPLD is responsible for performing the encoding or decoding task of the valid data. In view of the characteristic requirements of the A / D analog-to-digital conversion module and the D / A digital-to-analog conversion module, the CPLD interface circuit needs to process 14-bit binary data during the data processing process, and then perform necessary conversion and processing. The encoding process follows a specific timing, that is, one bit of binary data is sent every nine clock cycles. Therefore, the total time required to complete the encoding of 14 bits of binary data is:

[0028] Among them, CLK is the clock cycle; The decoding process starts with the reception of the synchronization code, and then the CPLD interface circuit starts the timing mechanism. The first binary data bit is read four clock cycles after the synchronization code is received, and each subsequent binary data bit is read in the ninth clock cycle after the previous binary data bit is read. The total time taken for the decoding process of a frame of data, from receiving the synchronization code to completing the reading of all fourteen bits of data, is:

[0029] The above formula (1) and formula (2) are respectively the time taken by the CPLD interface circuit in encoding and decoding.

[0030] During encoding, the CPLD first outputs a high-level signal to Bit13 for nine consecutive clock cycles to represent digital signal 1 (represented by the first green portion from left to right in the figure); during decoding, the first bit of binary data is read in the fourth clock cycle after the end of the synchronization code. If it is a high level, the data bit is determined to be 1 (the first green portion from left to right in the figure indicates that Bit13 is 1).

[0031] For the next data bit (when Bit12 is 0), the CPLD outputs a low-level signal (indicating digital signal 0) for nine consecutive clock cycles during encoding; during decoding, the data is read in the thirteenth clock cycle after the end of the synchronization code, that is, in the ninth clock cycle after the first bit of binary data is read. If the signal is low, the data bit is determined to be 0 (the first black part from left to right in the diagram indicates that BIT12 is 0). When reading the next data, it is nine clock cycles away from reading the previous data. Following this pattern, the encoding and decoding of all remaining data bits are completed in sequence until the entire data sequence is processed.

[0032] According to the above description of encoding and decoding, the maximum frequency that can be sampled by the present invention can be calculated: Since the A / D analog-to-digital conversion module and the D / A digital-to-analog conversion module are parallel, the CPLD can process the data of one sampling point in two clock cycles. Assuming that N points are sampled in each cycle, the sampled signal frequency can be calculated according to the following formula:

[0033]

[0034]

[0035]

[0036] In formula (3), Tm represents a clock cycle, fm represents the main frequency of CPLD, TN represents the clock cycle required for sampling N points, and fN represents the frequency of the sampled signal for sampling N points in one cycle. According to the Nyquist sampling theorem, the sampling frequency must be greater than twice the sampled frequency, so the actual frequency of the sampled signal is as shown in formula (6).

[0037]

[0038] Assuming that the crystal oscillator used in this embodiment is 70 MHz and 50 points are sampled in each cycle, formula (8) is derived based on the above formula to calculate the highest undistorted sampling frequency of 700 KHz.

[0039]

[0040] The present invention provides a CPLD-based analog signal digital remote transmission system, which is used to implement the CPLD-based analog signal digital remote transmission method, comprising: Main control module, encoding and sending module and decoding and receiving module; The main control module is in communication connection with the encoding and sending module and the decoding and receiving module, and the encoding and sending module is in optical fiber connection with the decoding and receiving module.

[0041] Specifically, the signal is collected, differentially amplified and digitized by the encoding and transmitting module, sent by the optical fiber transmitting module on the component, and transmitted to the decoding and receiving module via the optical cable. The decoding and receiving module shapes, demodulates, amplifies, filters and converts the received signal to restore the original analog signal.

[0042] Furthermore, the encoding and sending module is as follows Figure 3 As shown: The encoding and sending module includes: a first CPLD module, a first power supply processing module, an analog signal voltage following and differential module, an A / D analog-to-digital conversion module, an optical fiber sending driving module and an optical fiber sending module; The first power supply processing module is connected with the first CPLD module, the analog signal voltage follower and differential module, the A / D analog-to-digital conversion module and the optical fiber transmission drive module; The analog signal voltage follower and differential module, the A / D analog-to-digital conversion module, the first CPLD module, the optical fiber transmission drive module and the optical fiber transmission module are connected in sequence.

[0043] Specifically, the encoding and sending module is seamlessly connected to the analog signal source to be captured through the wiring terminal. Subsequently, the analog signal voltage follower and differential module are used to effectively enhance the signal driving ability and reduce the risk of signal distortion for subsequent processing. Furthermore, the signal differential circuit is introduced to accurately convert the single-ended analog signal into a differential signal, significantly improving the signal's anti-interference ability during transmission and ensuring the stability and reliability of the signal quality.

[0044] After completing the above signal preprocessing, the analog signal is sent to the A / D analog-to-digital conversion module for high-precision quantization conversion, that is, the continuously changing analog quantity is accurately mapped into a discrete digital quantity. The digital signal generated by the A / D analog-to-digital conversion module is transmitted to the CPLD interface circuit 1 for complex logical operations and data processing, as well as necessary signal format adjustment to meet subsequent transmission requirements. After the CPLD interface circuit 1 completes the signal processing, it transmits the optimized signal to the optical fiber transmission drive module through its powerful data management capabilities. The optical fiber transmission drive module, as a module connecting the previous level and the subsequent transmission of optical signals, has the functions of reducing signal delay and distortion in the circuit, input protection, etc. Finally, the signal is sent to the receiving end and the analog signal recovery component at high speed and long distance through the optical fiber medium in the form of an optical signal via the optical fiber transmission module for subsequent decoding, restoration and further processing.

[0045] Furthermore, the decoding receiving module is as follows Figure 4 As shown: The decoding receiving module includes: a second CPLD module, a second power supply processing module, an analog signal conditioning module, a D / A digital-to-analog conversion module, a signal comparison module and an optical fiber receiving module; The second power processing module is connected with the second CPLD module, the analog signal conditioning module, the D / A digital-to-analog conversion module and the optical fiber receiving module; The optical fiber receiving module, the signal comparing module, the second CPLD module, the D / A digital-to-analog conversion module and the analog signal conditioning module are connected in sequence.

[0046] Specifically, the decoding and receiving module first uses the optical fiber receiving module to accurately capture the optical fiber signal sent by the analog signal conversion and transmission components. The received digital signal then enters the signal comparison module, which is responsible for fine-tuning the digital signal to ensure that the output signal level is strictly defined between high level (+5V) and low level (0V).

[0047] The digital signal after this processing is subjected to complex logic operations and data processing through the CPLD interface circuit 2 to achieve accurate analysis and adjustment of the signal content. Further, the processed digital signal is sent to the D / A digital-to-analog conversion module for conversion from digital to analog signals. However, the analog signal output by the initial conversion may have the problem of insufficient waveform regularity, so it is necessary to further optimize the processing with the help of an analog signal conditioning circuit. The conditioning circuit is intended to improve the quality of the analog signal, ensure that the final output analog signal waveform is smooth and stable, and its voltage range is accurately controlled between -12V and +12V to meet the requirements of signal output.

[0048] Further: The first CPLD module has the same structure as the second CPLD module, and the first power supply processing module has the same structure as the second power supply processing module; The CPLD module includes: CPLD interface circuit, active crystal oscillator, download circuit, circuit normal working indication module and indicator light; The power processing module is connected with the CPLD interface circuit, the active crystal oscillator and the circuit normal working indication module; The CPLD interface circuit is connected with the active crystal oscillator, the download circuit and the circuit normal working indication module, and the circuit normal working indication module is connected with the indicator light.

[0049] Specifically, the power processing module processes the power supply of the analog signal conversion and sending components based on the 12V input, including a 12V to +5V circuit, a +5V to +3.3V circuit, and a +5V to -5V circuit. According to the voltage conversion relationship, the output of the 12V to +5V circuit module is respectively connected to the +5V to +3.3V circuit and the +5V to -5V circuit; The active crystal oscillator is used to provide clock signals for CPLD interface circuit 1 and CPLD interface circuit 2. The download circuit is used to provide the CPLD with a written program for burning and simulation. The circuit normal operation indication module is used to indicate whether the circuit can work normally. Its status is controlled by CPLD interface circuit 1 and CPLD interface circuit 2. When the circuit fails or the transmission error occurs and cannot work normally, the circuit normal operation indication module will light up the fault indicator light to remind the user of the failure.

[0050] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0051] The serial numbers of the embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. In a unit claim that lists several means, several of these means may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order and these words may be interpreted as identifiers.

[0052] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A CPLD-based analog signal digital remote transmission method, characterized in that: include: S1: Start data transmission, the encoding and sending module and the decoding and receiving module perform synchronous operation; S2: The encoding and sending module sends the binary string according to a preset period, and the decoding and receiving module reads the binary string according to a preset period.

2. The CPLD-based analog signal digital remote transmission method according to claim 1, characterized in that: Step S1 is specifically as follows: S11: The main control module sends a data transmission instruction to the encoding and sending module and the decoding and receiving module, and the encoding and sending module and the decoding and receiving module read the synchronization code; S12: If the encoding and sending module and the decoding and receiving module complete the reading of the synchronization code at the same time, the encoding and sending module and the decoding and receiving module complete the synchronization and enter step S2; otherwise, return to step S11.

3. The CPLD-based analog signal digital remote transmission method according to claim 2, characterized in that: The synchronization code includes: a start segment, a middle segment and an end segment; The start segment consists of four clock cycles of low level; The middle segment consists of a high level of twelve clock cycles; The end segment consists of four clock cycles of low level.

4. The CPLD-based analog signal digital remote transmission method according to claim 1, characterized in that: Step S2 is specifically as follows: S21: After the encoding and sending module and the decoding and receiving module are synchronized, the encoding and sending module transmits binary data to the decoding and receiving module starting from the highest U-th bit of the binary string; S22: the encoding and sending module sends the u-th binary data of the binary string to the decoding and receiving module through the optical fiber sending module within n2 consecutive clock cycles; S23: the decoding receiving module reads through the optical fiber receiving module at the n1th clock cycle, and if it is a high level, it determines that the uth binary data is 1, and if it is a low level, it determines that the uth binary data is 0; n1 is less than n2; S24: let u=u-1; S25: Repeat steps S22-S24 until the transmission of binary data from the Uth bit to the 0th bit of the binary string is completed.

5. A CPLD-based analog signal digital remote transmission system, used to implement the CPLD-based analog signal digital remote transmission method as claimed in any one of claims 1 to 4, characterized in that: include: Main control module, encoding and sending module and decoding and receiving module; The main control module is in communication connection with the encoding and sending module and the decoding and receiving module, and the encoding and sending module is in optical fiber connection with the decoding and receiving module.

6. The CPLD-based analog signal digital remote transmission system according to claim 5, characterized in that: The encoding and sending module includes: a first CPLD module, a first power supply processing module, an analog signal voltage following and differential module, an A / D analog-to-digital conversion module, an optical fiber sending driving module and an optical fiber sending module; The first power supply processing module is connected with the first CPLD module, the analog signal voltage follower and differential module, the A / D analog-to-digital conversion module and the optical fiber transmission drive module; The analog signal voltage follower and differential module, the A / D analog-to-digital conversion module, the first CPLD module, the optical fiber transmission drive module and the optical fiber transmission module are connected in sequence.

7. The CPLD-based analog signal digital remote transmission system according to claim 5, characterized in that: The decoding receiving module includes: a second CPLD module, a second power supply processing module, an analog signal conditioning module, a D / A digital-to-analog conversion module, a signal comparison module and an optical fiber receiving module; The second power processing module is connected with the second CPLD module, the analog signal conditioning module, the D / A digital-to-analog conversion module and the optical fiber receiving module; The optical fiber receiving module, the signal comparing module, the second CPLD module, the D / A digital-to-analog conversion module and the analog signal conditioning module are connected in sequence.

8. The CPLD-based analog signal digital remote transmission system according to claim 6 or 7, characterized in that: The first CPLD module has the same structure as the second CPLD module, and the first power supply processing module has the same structure as the second power supply processing module; The CPLD module includes: CPLD interface circuit, active crystal oscillator, download circuit, circuit normal working indication module and indicator light; The power processing module is connected with the CPLD interface circuit, the active crystal oscillator and the circuit normal working indication module; The CPLD interface circuit is connected with the active crystal oscillator, the download circuit and the circuit normal working indication module, and the circuit normal working indication module is connected with the indicator light.

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