Capacitor for high-speed analog-to-digital converter and capacitor array layout

Abstract

The invention provides a capacitor for a high-speed analog-to-digital converter and a capacitor array layout, and relates to the technical field of power electronics, the capacitor comprises a first connecting layer and a second connecting layer, the first connecting layer comprises two first connecting strips and a first connecting ring, and the two first connecting strips are respectively arranged at two sides of the first connecting ring; the second connecting layer comprises two second connecting strips, a second connecting ring and a dividing strip, the dividing strip is fixed in the middle of the second connecting ring and divides the second connecting ring into two sub-connecting rings with the same size, and the two second connecting strips are arranged in the middle of the two sub-connecting rings respectively; the third connecting ring layer, the fourth connecting layer and the second connecting layer are the same in structure. The analog-to-digital converter has the advantages of high precision, low parasitic effect, good matching and symmetry and the like, wiring simplification and integration level improvement are facilitated, and the analog-to-digital converter can exert excellent performance in a high-speed and high-precision application scene by jointly acting on the analog-to-digital converter.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a capacitor and a capacitor array layout for a high-speed analog-to-digital converter. Background Art

[0002] In the field of high-speed analog-to-digital converters (ADCs), as the requirements for data processing speed and accuracy continue to increase, capacitive successive approximation register (SAR) ADCs have become an important component of modern electronic systems due to their low power consumption, high speed, and good linearity. However, with the refinement of semiconductor manufacturing processes, especially the continuous reduction of feature sizes, the mismatch problem of capacitor components has become increasingly prominent, becoming a key factor restricting the further improvement of SAR ADC performance. Capacitor mismatch not only increases the quantization noise of the ADC, but also causes a decrease in linearity, affecting the overall conversion accuracy and dynamic range.

[0003] It is often difficult to achieve the ideal mismatch level for capacitors using traditional standard processes, especially at small sizes, where the change in capacitance is extremely sensitive to process deviations. Therefore, it is necessary to develop a new type of customized unit capacitor structure, aiming to significantly reduce the mismatch rate by optimizing the capacitor shape, material, or using advanced manufacturing processes.

[0004] The layout of the capacitor array directly affects the signal integrity, parasitic effects, and matching between capacitors. In high-speed ADCs, an unreasonable layout may introduce large parasitic capacitance and inductance of the routing, resulting in increased signal delay, crosstalk, and noise. In addition, capacitors at the edge are often more susceptible to environmental factors, further exacerbating the mismatch problem.

[0005] Therefore, a capacitor and a capacitor array layout for a high-speed analog-to-digital converter is proposed. Summary of the invention

[0006] This specification provides a capacitor and capacitor array layout for a high-speed analog-to-digital converter, which has the advantages of high precision, low parasitic effects, good matching and symmetry, etc., which is conducive to simplifying wiring and improving integration, and works together with the analog-to-digital converter to enable it to perform excellent performance in high-speed, high-precision application scenarios.

[0007] This specification provides a capacitor for a high-speed analog-to-digital converter, including:

[0008] a first connection layer, a second connection layer, a third connection layer, and a fourth connection layer;

[0009] The first connection layer includes two first connection bars and a first connection ring, and the two first connection bars are respectively arranged on both sides of the first connection ring;

[0010] The second connection layer includes two second connection bars, a second connection ring and a separator bar, wherein the separator bar is fixed in the middle of the second connection ring to divide the second connection ring into two sub-connection rings of the same size, and the two second connection bars are respectively arranged in the middle of the two sub-connection rings;

[0011] The third connection layer, the fourth connection layer and the second connection layer have the same structure.

[0012] Optionally, the connection relationship of the capacitor upper plate connection layer includes: first through holes are symmetrically opened on both sides of the first connection strip; third through holes are symmetrically opened on both sides of the second connection ring, and a fourth through hole is opened in the middle of the separation strip; sixth through holes are symmetrically opened on both sides of the third connection layer, and a seventh through hole is opened in the middle of the third connection layer;

[0013] The first connecting bar is connected to the second connecting ring through the first through hole, the second connecting ring is connected to the connecting ring of the third connecting layer through the third through hole and the fourth through hole, and the connecting ring of the third connecting layer is connected to the connecting ring of the fourth connecting layer through the sixth through hole and the seventh through hole.

[0014] Optionally, the connection relationship of the capacitor lower plate connection layer includes: the first connection ring is symmetrically provided with a second through hole, the second connection bar is symmetrically provided with a fifth through hole, and the connection bar of the third connection layer is symmetrically provided with an eighth through hole;

[0015] The first connecting ring is connected to the second connecting bar through the second through hole, the second connecting bar is connected to the connecting bar of the third connecting layer through the fifth through hole, and the connecting bar of the third connecting layer is connected to the connecting bar of the fourth connecting layer through the eighth through hole.

[0016] Optionally, the connection relationship of the first connection layer when two capacitors are connected in parallel includes: a first capacitor and a second capacitor;

[0017] The upper plate of the first capacitor is naturally connected to the upper plate of the second capacitor through the first connecting bar of the first capacitor and the first connecting bar of the second capacitor, and the lower plate of the first capacitor is connected to the lower plate of the second capacitor through the splicing connecting bar.

[0018] Optionally, the connection relationship of the fourth connection layer when two capacitors are connected in parallel includes:

[0019] The upper electrode plate of the first capacitor and the upper electrode plate of the second capacitor are naturally connected through the connecting ring of the fourth connecting layer of the first capacitor and the connecting ring of the fourth connecting layer of the second capacitor, the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are connected to the first connecting layer through the eighth through hole, the fifth through hole, and the second through hole, and the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are then connected through a splicing connecting strip.

[0020] The present specification provides a capacitor array layout for a high-speed analog-to-digital converter, characterized in that it includes: the upper plates are connected, and the lower plates are connected to a switch; the charge of the upper plate is redistributed by switching the voltage of the switch of the lower plate; the capacitance values ​​of capacitors C64_P, C64_N, C32_P, C32_N, C16_P, C16_N, C8_P, C8_N, C4_P, C4_N, C2_P, C2_N, C1_P, and C1_N are 64C, 64C, 32C, 32C, 16C, 16C, 8C, 8C, 4C, 4C, 2C, 2C, 1C, and 1C, respectively; wherein C is a unit capacitance.

[0021] Optional, including:

[0022] Eight unit capacitors are grouped together to form a row;

[0023] Follow the principle of large capacitors surrounding small capacitors and being symmetrical from top to bottom, and intersperse C64_P, C32_P, C64_P, C16_P, C64_P, C32_P, C64_P, C8_P, C64_N, C32_N, C64_N, C16_N, C64_N, C32_N, C64_N, C4_P, C1_P, C2_P, C2_N, C1_N, C4_N, C64_N, C32_N, C64_N, C16_N, C64_N, C32_N, C64_N, C8_N, C64_P, C32_P, C64_P, C16_P, C64_P, C32_P and C64_P in sequence;

[0024] Dummy capacitors CD are added on the top, bottom and right to avoid the influence of edge positions on the capacitance, and a switch is placed on the left.

[0025] Optionally, also include:

[0026] When the number of capacitors is less than 8, dummy capacitors CD are used to fill the gap and left-align it.

[0027] In the present invention, the customized capacitor structure can produce small capacitors at the level of femtofarads (fF), which is crucial for high-precision analog-to-digital converters. The precise control of small capacitors helps to reduce quantization errors and improve conversion accuracy. During layout design, the lower plate is connected through a simple first connection layer, which reduces the complexity of routing, thereby reducing parasitic capacitance and parasitic inductance. These parasitic effects are common noise sources in high-speed circuits, and reducing them can significantly improve signal integrity and conversion speed. The capacitor array follows the layout principle of large capacitors surrounding small capacitors. This layout helps to reduce the capacitance value deviation caused by process changes and improve the matching between capacitors. Good matching is an important factor in ensuring the linearity and accuracy of the analog-to-digital converter. The upper and lower symmetrical layout is not only beautiful, but more importantly, it can balance the asymmetric effects in the circuit and reduce the errors caused thereby. This symmetry also helps to improve the stability and reliability of the circuit. When two customized capacitors are placed on the same side, the upper plate is naturally connected, and this design greatly simplifies the wiring process. In high-speed analog-to-digital converters, complex wiring often leads to signal delays and crosstalk, while simplified wiring helps to reduce these problems. Using dummy capacitors to surround the entire capacitor array can effectively reduce the impact of edge effects on capacitor performance. This design strategy helps improve the integral nonlinearity (INL) and differential nonlinearity (DNL) of the analog-to-digital converter, thereby improving the accuracy and reliability of the conversion results. Due to the small parasitic capacitance and parasitic inductance, simple wiring and good matching, this capacitor and capacitor array layout is very suitable for high-speed analog-to-digital converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a plan view of the first connection layer;

[0030] Figure 2 is a plan view of the second connection layer;

[0031] Figure 3 is a plan view of the third connection layer;

[0032] Figure 4 is a plan view of the fourth connection layer;

[0033] Figure 5 It is a side view of the connection of the upper plate connection layer of the capacitor;

[0034] Figure 6 It is a side view of the connection layer of the capacitor bottom plate;

[0035] Figure 7 A diagram showing the position relationship between the capacitor upper plate connection layer and the capacitor lower plate connection layer;

[0036] Figure 8 It is a schematic diagram of the first connection layer when two capacitors are connected in parallel;

[0037] Fig. 9 It is a schematic diagram of the fourth connection layer when two capacitors are connected in parallel;

[0038] Fig.10 is a schematic diagram of a seven-bit binary capacitor array;

[0039] Fig.11 This is the layout of the seven-bit binary capacitor array.

[0040] The accompanying drawings illustrate: 10, first connecting layer; 11, first connecting strip; 12, first connecting ring; 13, first through hole; 14, second through hole; 20, second connecting layer; 21, second connecting strip; 22, second connecting ring; 23, dividing strip; 24, third through hole; 25, fourth through hole; 26, fifth through hole; 30, third connecting layer; 31, sixth through hole; 32, seventh through hole; 33, eighth through hole; 40, fourth connecting layer; 5, splicing connecting strip. DETAILED DESCRIPTION

[0041] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0042] The following is combined with Figure 1-11 The exemplary embodiments of the present invention are described more fully. However, the exemplary embodiments can be implemented in various forms, and it should not be understood that the present invention is limited to the embodiments set forth herein. On the contrary, providing these exemplary embodiments can make the present invention more comprehensive and complete, and it is more convenient to fully convey the inventive concept to those skilled in the art. The same reference numerals in the figures represent the same or similar elements, components or parts, and thus their repeated description will be omitted.

[0043] Under the premise of being consistent with the technical concept of the present invention, the features, structures, characteristics or other details described in a specific embodiment do not exclude that they can be combined in one or more other embodiments in a suitable manner.

[0044] In the description of specific embodiments, the features, structures, characteristics or other details described in the present invention are for the purpose of enabling those skilled in the art to fully understand the embodiments. However, it does not exclude that those skilled in the art can practice the technical solutions of the present invention without one or more of specific features, structures, characteristics or other details.

[0045] The flowcharts shown in the accompanying drawings are only illustrative and do not necessarily include all the contents and operations / steps, nor do they necessarily have to be executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0046] The block diagrams shown in the accompanying drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0047] The term "and / or" or "及 / 或" includes all combinations of any one or more of the associated listed items.

[0048] A capacitor for a high-speed analog-to-digital converter provided in an embodiment of this specification includes: as Figure 1-Figure 4 shown, a first connection layer, a second connection layer, a third connection layer, and a fourth connection layer, all of which are made of metal. The overall shape formed by splicing the first connection layer, the second connection layer, the third connection layer, and the fourth connection layer is rectangular, which enhances the stability and rigidity of the overall structure and is crucial for reducing parasitic effects caused by vibration or external forces. The first connection layer includes two connection bars and an "O"-shaped connection ring. The two connection bars are respectively arranged on both sides of the connection ring. The connection bars and the connection ring provide a low-impedance path for signals or currents, which helps to reduce the attenuation and distortion of signals during transmission and improve signal integrity. The second connection layer includes two connection bars, a connection ring, and a partition bar. The partition bar is fixed in the middle of the connection ring, dividing the connection ring into two sub-connection rings of the same size, forming a "日"-shaped structure. The two connection bars are respectively arranged in the middle of the two sub-connection rings; the third connection layer and the fourth connection layer have the same structure as the second connection layer. Through the design of the "O"-shaped connection ring and the "日"-shaped connection ring, the electric field distribution can be made more uniform, which helps to reduce electric field concentration and edge effects, thereby reducing parasitic capacitance and parasitic inductance.

[0049] As Figure 5As shown, the connection relationship of the upper plate connection layer of the capacitor includes: the first through hole is symmetrically opened on both sides of the first connection strip; the third through hole is symmetrically opened on both sides of the second connection ring, and the fourth through hole is opened in the middle of the separation strip; the sixth through hole is symmetrically opened on both sides of the third connection layer, and the seventh through hole is opened in the middle of the third connection layer; the first connection strip is connected to the second connection ring through the first through hole, the second connection ring is connected to the connection ring of the third connection layer through the third through hole and the fourth through hole, and the connection ring of the third connection layer is connected to the connection ring of the fourth connection layer through the sixth through hole and the seventh through hole. Through the alignment connection between the through holes, the horizontal connection between the layers is realized, ensuring the smooth transmission of current or signals in the horizontal direction.

[0050] like Figure 6 As shown, the connection relationship of the capacitor lower plate connection layer includes: the first connection ring is symmetrically provided with a second through hole, the second connection bar is symmetrically provided with a fifth through hole, and the connection bar of the third connection layer is symmetrically provided with an eighth through hole; the first connection ring is connected to the second connection bar through the second through hole, the second connection bar is connected to the connection bar of the third connection layer through the fifth through hole, and the connection bar of the third connection layer is connected to the connection bar of the fourth connection layer through the eighth through hole. The stacked capacitor structure helps to reduce parasitic effects, improve signal integrity and reduce noise interference.

[0051] like Figure 8 As shown, the connection relationship of the first connection layer when two capacitors are connected in parallel includes: a first capacitor and a second capacitor; the upper plate of the first capacitor and the upper plate of the second capacitor are naturally connected through the first connecting strip of the first capacitor and the first connecting strip of the second capacitor, that is, the upper plates of the two capacitors (or the parts connected thereto in their first connecting layers) are directly in contact or connected through a conductive medium (such as solder, conductive glue, etc.), thereby forming a common potential point. The lower plate of the first capacitor is connected to the lower plate of the second capacitor through a spliced ​​connecting strip. In the circuit, two capacitors in parallel mean that their positive plates are connected together, and the negative plates are also connected together, so as to share the same voltage. This connection method can increase the total capacitance value because the total capacitance of the parallel capacitors is equal to the sum of the individual capacitance values. The above method ensures that the two capacitors can work in parallel, thereby increasing the total capacitance value and meeting the needs of the circuit.

[0052] like Figure 7 As shown, the capacitor upper plate connection layer and the capacitor lower plate connection layer form a small capacitor, which is stacked up and connected together through the through holes between the layers to form a large capacitor in parallel to increase the capacitance density. The position of the through holes in each layer is guaranteed to be symmetrical to improve matching.

[0053] like Fig. 9As shown, the connection relationship of the fourth connection layer when two capacitors are connected in parallel includes: the upper electrode plate of the first capacitor and the upper electrode plate of the second capacitor are naturally connected through the connecting ring of the fourth connection layer of the first capacitor and the connecting ring of the fourth connection layer of the second capacitor, the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are connected to the first connection layer through the eighth through hole, the fifth through hole, and the second through hole, and the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are then connected through the splicing connecting strip.

[0054] A capacitor array layout for a high-speed analog-to-digital converter, characterized in that it includes: Fig.10 As shown, the upper plates are connected and the lower plates are connected to a switch; the voltage is switched by the switch of the lower plate to complete the redistribution of the charge on the upper plate; the capacitances of capacitors C64_P, C64_N, C32_P, C32_N, C16_P, C16_N, C8_P, C8_N, C4_P, C4_N, C2_P, C2_N, C1_P, and C1_N are 64C, 64C, 32C, 32C, 16C, 16C, 8C, 8C, 4C, 4C, 2C, 2C, 1C, and 1C, respectively; wherein C is the unit capacitance, and the capacitances of the capacitors are arranged in descending order of powers of 2 (64C, 32C, 16C, 8C, 4C, 2C, and 1C), and precise charge distribution and voltage generation are achieved through simple switching operations.

[0055] like Fig.10 As shown, 8 unit capacitors are grouped into a row; when the number of capacitors is less than 8, they are filled with dummy capacitors CD and left-aligned; following the principle of large capacitors surrounding small capacitors and being symmetrical from top to bottom, C64_P, C32_P, C64_P, C16_P, C64_P, C32_P, C64_P, C8_P, C64_N, C32_N, C64_N, C16_N, C64_N, C32_N, C64_N, C4_P, C 1_P, C2_P, C2_N, C1_N, C4_N, C64_N, C32_N, C64_N, C16_N, C64_N, C32_N, C64_N, C8_N, C64_P, C32_P, C64_P, C16_P, C64_P, C32_P and C64_P; Dummy capacitors CD are added above, below and on the right. These dummy capacitors are not only used to make up, but also protect the actual capacitors from edge effects. The switches are placed on the left side of the layout, which means that the lower plate of each capacitor (or the plate that needs to be switched) will be connected to the corresponding switch on the left through a wire. This layout helps to simplify wiring and may improve signal integrity.

[0056] In the present invention, the customized capacitor structure can produce small capacitors at the level of femtofarads (fF), which is crucial for high-precision analog-to-digital converters. The precise control of small capacitors helps to reduce quantization errors and improve conversion accuracy. During layout design, the lower plate is connected through a simple first connection layer, which reduces the complexity of routing, thereby reducing parasitic capacitance and parasitic inductance. These parasitic effects are common noise sources in high-speed circuits, and reducing them can significantly improve signal integrity and conversion speed. The capacitor array follows the layout principle of large capacitors surrounding small capacitors. This layout helps to reduce the capacitance value deviation caused by process changes and improve the matching between capacitors. Good matching is an important factor in ensuring the linearity and accuracy of the analog-to-digital converter. The upper and lower symmetrical layout is not only beautiful, but more importantly, it can balance the asymmetric effects in the circuit and reduce the errors caused thereby. This symmetry also helps to improve the stability and reliability of the circuit. When two customized capacitors are placed on the same side, the upper plate is naturally connected, and this design greatly simplifies the wiring process. In high-speed analog-to-digital converters, complex wiring often leads to signal delays and crosstalk, while simplified wiring helps to reduce these problems. Using dummy capacitors to surround the entire capacitor array can effectively reduce the impact of edge effects on capacitor performance. This design strategy helps improve the integral nonlinearity (INL) and differential nonlinearity (DNL) of the analog-to-digital converter, thereby improving the accuracy and reliability of the conversion results. Due to the small parasitic capacitance and parasitic inductance, simple wiring and good matching, this capacitor and capacitor array layout is very suitable for high-speed analog-to-digital converters.

[0057] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the present invention is not inherently related to any specific computer, virtual device or electronic device, and various general devices can also implement the present invention. The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0058] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0059] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A capacitor for a high-speed analog-to-digital converter, characterized in that: include: A first connecting layer (10), a second connecting layer (20), a third connecting layer (30), and a fourth connecting layer (40); The first connection layer (10) comprises two first connection bars (11) and a first connection ring (12), wherein the two first connection bars (11) are respectively arranged on both sides of the first connection ring (12); The second connection layer (20) comprises two second connection strips (21), a second connection ring (22) and a separator strip (23); the separator strip (23) is fixed in the middle of the second connection ring (22) to divide the second connection ring (22) into two sub-connection rings of the same size; the two second connection strips (21) are respectively arranged in the middle of the two sub-connection rings; The third connection layer (30), the fourth connection layer (40) and the second connection layer (20) have the same structure.

2. The capacitor for a high-speed analog-to-digital converter according to claim 1, characterized in that: The connection relationship of the capacitor upper plate connection layer comprises: first through holes (13) are symmetrically provided on both sides of the first connection strip (11); third through holes (24) are symmetrically provided on both sides of the second connection ring (22), and a fourth through hole (25) is provided in the middle of the separation strip (23); sixth through holes (31) are symmetrically provided on both sides of the third connection layer (30), and a seventh through hole (32) is provided in the middle of the third connection layer (30); The first connecting strip (11) is connected to the second connecting ring (22) via the first through hole (13); the second connecting ring (22) is connected to the connecting ring of the third connecting layer (30) via the third through hole (24) and the fourth through hole (25); and the connecting ring of the third connecting layer (30) is connected to the connecting ring of the fourth connecting layer (40) via the sixth through hole (31) and the seventh through hole (32).

3. The capacitor for a high-speed analog-to-digital converter according to claim 2, characterized in that: The connection relationship of the capacitor lower plate connection layer comprises: the first connection ring (12) is symmetrically provided with a second through hole (14), the second connection bar (21) is symmetrically provided with a fifth through hole (26), and the connection bar of the third connection layer (30) is symmetrically provided with an eighth through hole (33); The first connecting ring (12) is connected to the second connecting bar (21) via the second through hole (14), the second connecting bar (21) is connected to the connecting bar of the third connecting layer (30) via the fifth through hole (26), and the connecting bar of the third connecting layer (30) is connected to the connecting bar of the fourth connecting layer (40) via the eighth through hole (33).

4. The capacitor for a high-speed analog-to-digital converter according to claim 3, characterized in that: The connection relationship of the first connection layer (10) when two capacitors are connected in parallel includes: a first capacitor and a second capacitor; The upper electrode plate of the first capacitor is naturally connected to the upper electrode plate of the second capacitor through the first connecting bar (11) of the first capacitor and the first connecting bar (11) of the second capacitor, and the lower electrode plate of the first capacitor is naturally connected to the lower electrode plate of the second capacitor through the splicing connecting bar (5).

5. The capacitor for a high-speed analog-to-digital converter according to claim 4, characterized in that: The connection relationship of the fourth connection layer (40) when two capacitors are connected in parallel includes: The upper electrode plate of the first capacitor and the upper electrode plate of the second capacitor are naturally connected through the connecting ring of the fourth connecting layer (40) of the first capacitor and the connecting ring of the fourth connecting layer (40) of the second capacitor; the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are connected to the first connecting layer (10) through the eighth through hole (33), the fifth through hole (26) and the second through hole (14); and the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are further connected through the splicing connecting strip (5).

6. A capacitor array layout for a high-speed analog-to-digital converter, characterized in that: include: The upper plates are connected, and the lower plates are connected to a switch; the voltage of the switch of the lower plate is switched to complete the redistribution of the charge of the upper plate; the capacitance values ​​of capacitors C64_P, C64_N, C32_P, C32_N, C16_P, C16_N, C8_P, C8_N, C4_P, C4_N, C2_P, C2_N, C1_P, and C1_N are 64C, 64C, 32C, 32C, 16C, 16C, 8C, 8C, 4C, 4C, 2C, 2C, 1C, and 1C, respectively; wherein C is the unit capacitance.

7. The capacitor array layout for a high-speed analog-to-digital converter according to claim 6, characterized in that: include: Eight unit capacitors are grouped together to form a row; Follow the principle of large capacitors surrounding small capacitors and being symmetrical from top to bottom, and intersperse C64_P, C32_P, C64_P, C16_P, C64_P, C32_P, C64_P, C8_P, C64_N, C32_N, C64_N, C16_N, C64_N, C32_N, C64_N, C4_P, C1_P, C2_P, C2_N, C1_N, C4_N, C64_N, C32_N, C64_N, C16_N, C64_N, C32_N, C64_N, C8_N, C64_P, C32_P, C64_P, C16_P, C64_P, C32_P and C64_P in sequence; Dummy capacitors CD are added on the top, bottom and right to avoid the influence of edge positions on the capacitance, and a switch is placed on the left.

8. The capacitor array layout for a high-speed analog-to-digital converter according to claim 7, characterized in that: Also includes: When the number of capacitors is less than 8, dummy capacitors CD are used to fill the gap and left-align it.

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