A frequency synthesis module of a frequency conversion module and a signal processing method of the frequency synthesis module

Abstract

To address the problem of narrow LO2 signal bandwidth in the prior art, the present invention provides a frequency synthesis module for a frequency conversion module and a signal processing method for the frequency synthesis module. The frequency synthesis module of the frequency conversion module includes: an adaptive reference AGC module, which is used to implement automatic gain control of the reference signal; a clock distribution module, whose input end is connected to the output end of the adaptive reference AGC module and is used to generate a clock signal; a universal local oscillator module, whose input end is connected to the output end of the clock distribution module and is used to generate an input signal for the frequency conversion module; and a power control module, whose output end is connected to the input end of the adaptive reference AGC module, the input end of the clock distribution module, and the input end of the universal local oscillator module and is used to provide voltage. The mixing technology of the present invention increases the upper limit of the LO2 signal frequency by 40.4 GHz. It can output four LO signals simultaneously, supporting four frequency conversion channels to operate simultaneously.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a frequency synthesis module of a frequency conversion module and a signal processing method of the frequency synthesis module. Background Art

[0002] One of the primary functions of a frequency synthesizer module is to generate stable and accurate signals at multiple frequencies. Within the frequency conversion module, it synthesizes the required local oscillator (LO) signals, including LO1 and LO2, based on system requirements. In communications systems, frequency synthesizers can generate multiple LO signals of varying frequencies to achieve frequency conversion processing for signals in different frequency bands.

[0003] In the prior art, the LO2 signal frequency generated by the frequency synthesizer module has a defect of a low upper limit, which is basically 40 GHz. Summary of the Invention

[0004] In order to solve the problem of narrow bandwidth of LO2 signal in the prior art, the present invention provides a frequency synthesis module of a frequency conversion module and a signal processing method of the frequency synthesis module.

[0005] The technical solution adopted in the present invention is:

[0006] A frequency synthesis module of a frequency conversion module, comprising:

[0007] An adaptive reference AGC module is used to implement automatic gain control of a reference signal.

[0008] A clock distribution module, wherein the input end of the clock distribution module is connected to the output end of the adaptive reference AGC module, and is used to generate a clock signal.

[0009] A universal local oscillator module, the input end of which is connected to the output end of the clock distribution module, is used to generate an input signal for the frequency conversion module.

[0010] A power control module, wherein the output end of the power control module is connected to the input end of the adaptive reference AGC module, the input end of the clock distribution module and the input end of the universal local oscillator module, and is used to provide voltage.

[0011] Furthermore, the adaptive reference AGC module includes:

[0012] Power divider A,

[0013] Attenuator A, wherein the input end of the attenuator A is connected to an output end of the power divider A.

[0014] Amplifier A, wherein the input end of the amplifier A is connected to the output end of the attenuator A.

[0015] An attenuator B has an input end connected to the output end of the amplifier A.

[0016] Amplifier B, the input end of the amplifier B is connected to the output end of the attenuator B. The output end of the amplifier B is the output end of the adaptive reference AGC module.

[0017] Detector A, the input end of the detector A is connected to the other output end of the power divider A.

[0018] An ADC chip, wherein the input end of the ADC chip is connected to the output end of the detector A.

[0019] FPGA, the FPGA is connected to the detector A and is used to receive the data collected by the ADC chip, thereby realizing automatic gain control of the reference signal.

[0020] Furthermore, the clock distribution module includes:

[0021] Attenuator C; the input end of the attenuator C is connected to the output end of the amplifier B.

[0022] Switch A, one input end of the switch A is connected to the output end of the attenuator C, and the other input end of the switch A is grounded.

[0023] A 10M internal reference signal source provides a 10MHz internal reference signal.

[0024] Switch B, one input end of the switch B is connected to the output end of the 10M internal reference signal source, and the other input end of the switch B is grounded.

[0025] Switch C, one input end of the switch C is connected to the output end of the switch A, and the other input end of the switch C is connected to the output end of the switch B.

[0026] A frequency divider A, wherein an input end of the frequency divider A is connected to an output end of the switch C.

[0027] A 100M reference source, wherein the input end of the 100M reference source is connected to the output end of the frequency divider A.

[0028] Amplifier C, wherein the input end of the amplifier C is connected to the output end of the 100M reference source.

[0029] A filter A, wherein the input end of the filter A is connected to the output end of the amplifier C.

[0030] A power divider B, wherein the input end of the power divider B is connected to the output end of the filter A.

[0031] A power divider C, wherein an input end of the power divider C is connected to an output end of the power divider B.

[0032] An attenuator D, wherein an input end of the attenuator D is connected to the other output end of the power divider B.

[0033] A power divider D, wherein an input end of the power divider D is connected to an output end of the power divider C.

[0034] An attenuator G, wherein an input end of the attenuator G is connected to an output end of the power divider D. The attenuator G outputs a 100 MHz clock signal.

[0035] An attenuator F has an input end connected to the other output end of the power divider D. The attenuator F outputs a 100 MHz clock signal.

[0036] A power divider E, wherein an input end of the power divider E is connected to another output end of the power divider C.

[0037] An attenuator E, wherein an input end of the attenuator E is connected to an output end of the power divider E.

[0038] A power divider F, wherein the input end of the attenuator F is connected to the other output end of the power divider E.

[0039] An attenuator H has an input end connected to an output end of the power divider F. The attenuator H outputs a 100 MHz clock signal.

[0040] A power divider G, wherein an input end of the power divider G is connected to another output end of the power divider F.

[0041] Furthermore, the universal local oscillator module, when used as a universal slow-frequency integrated local oscillator module, includes:

[0042] A frequency multiplier A, wherein the input end of the frequency multiplier A is connected to the output end of the attenuator D.

[0043] A comb spectrum generator A, wherein the input end of the comb spectrum generator A is connected to the output end of the frequency multiplier A.

[0044] A power divider I, wherein the input end of the power divider I is connected to the output end of the comb spectrum generator A.

[0045] Filter B, where an input end of the filter B is connected to an output end of the power divider I.

[0046] An amplifier D, wherein an input end of the amplifier D is connected to an output end of the filter B.

[0047] A filter C, wherein an input end of the filter C is connected to an output end of the amplifier D.

[0048] An amplifier E, wherein an input end of the amplifier E is connected to an output end of the filter C.

[0049] A power divider J, wherein the input end of the power divider J is connected to the output end of the amplifier E. The power divider J outputs two local oscillator signals.

[0050] An amplifier F, wherein an input end of the amplifier F is connected to the other output end of the power divider I.

[0051] A switching filter A, wherein an input end of the switching filter A is connected to an output end of the amplifier F.

[0052] An amplifier G, wherein an input end of the amplifier G is connected to an output end of the switching filter A.

[0053] A frequency multiplier B, wherein the input end of the frequency multiplier B is connected to the output end of the amplifier G.

[0054] A filter D, wherein the input end of the filter D is connected to the output end of the frequency multiplier B.

[0055] An amplifier H, wherein an input end of the amplifier H is connected to an output end of the filter D.

[0056] A frequency divider B, wherein an input end of the frequency divider B is connected to an output end of the attenuator E.

[0057] A frequency source A, wherein an input end of the frequency source A is connected to an output end of the frequency divider B.

[0058] A mixer A, one input end of the mixer A is connected to the output end of the frequency source A, and the other input end of the mixer A is connected to the output end of the amplifier H.

[0059] A switching filter B, wherein an input end of the switching filter B is connected to an output end of the mixer A.

[0060] An amplifier I, wherein an input end of the amplifier I is connected to an output end of the switching filter B.

[0061] A filter E, wherein an input end of the filter E is connected to an output end of the amplifier I.

[0062] An amplifier J, wherein an input end of the amplifier J is connected to an output end of the filter E.

[0063] A power divider K, wherein the input end of the power divider K is connected to the output end of the amplifier J. The power divider K outputs two local oscillator signals.

[0064] Furthermore, the universal local oscillator module can be used as a universal fast-frequency integrated local oscillator module, and when used as a universal fast-frequency integrated local oscillator module, it includes:

[0065] Frequency multiplier A1.

[0066] A comb spectrum generator A1, wherein the input end of the comb spectrum generator A1 is connected to the output end of the frequency multiplier A1.

[0067] A power divider I1 , wherein the input end of the power divider I1 is connected to the output end of the comb spectrum generator A1 .

[0068] Filter B1, the input end of the filter B1 is connected to an output end of the power divider I1.

[0069] An amplifier D1 , wherein an input end of the amplifier D1 is connected to an output end of the filter B1 .

[0070] The filter C1 has an input end connected to the output end of the amplifier D1.

[0071] An amplifier E1 , wherein an input end of the amplifier E1 is connected to an output end of the filter C1 .

[0072] A power divider J1, wherein the input end of the power divider J1 is connected to the output end of the amplifier E1. The power divider J1 outputs two local oscillator signals.

[0073] Amplifier F1, the input end of the amplifier F1 is connected to the other output end of the power divider I1.

[0074] A switching filter A1 , wherein an input end of the switching filter A1 is connected to an output end of the amplifier F1 .

[0075] An amplifier G1 , wherein an input end of the amplifier G1 is connected to an output end of the switching filter A1 .

[0076] A frequency multiplier B1 , wherein an input end of the frequency multiplier B1 is connected to an output end of the amplifier G1 .

[0077] The filter D1 has an input end connected to the output end of the frequency multiplier B1.

[0078] An amplifier H1 , wherein an input end of the amplifier H1 is connected to an output end of the filter D1 .

[0079] The frequency divider B1 has an input end connected to the output end of the attenuator E.

[0080] A comb spectrum generator A2, wherein the input end of the comb spectrum generator A2 is connected to the output end of the frequency divider B1.

[0081] A frequency source A1, wherein an input end of the frequency source A1 is connected to an output end of the power divider G.

[0082] DDS, the input end of the DDS is connected to the output end of the frequency source A1.

[0083] A mixer A2, one input end of the mixer A2 is connected to the output end of the comb spectrum generator A2, and the other input end of the mixer A2 is connected to the output end of the DDS.

[0084] A switching filter B2, wherein an input end of the switching filter B2 is connected to an output end of the mixer A2.

[0085] A mixer A1, one input end of the mixer A1 is connected to the output end of the amplifier H1, and the other input end of the mixer A1 is connected to the output end of the switching filter B2.

[0086] A switching filter B1 , wherein an input end of the switching filter B1 is connected to an output end of the mixer A1 .

[0087] Amplifier I1 , wherein an input end of the amplifier I1 is connected to an output end of the switching filter B1 .

[0088] The filter E1 has an input end connected to the output end of the amplifier I1.

[0089] Amplifier J1 , wherein the input end of the amplifier J1 is connected to the output end of the filter E1 .

[0090] The power divider K1 has an input end connected to the output end of the amplifier J1 and outputs two local oscillator signals.

[0091] Furthermore, the FPGA is connected to the detector A to receive the data collected by the ADC chip, thereby realizing the specific method of automatic gain control of the reference signal: the REF signal outside the frequency synthesis module enters the power divider A, the power divider A outputs 2 signals, one of which is detected by the detector A, and then the detected analog voltage is sampled by the ADC chip, and the sampled data is transmitted to the FPGA for data collection, thereby realizing automatic gain control of the reference signal. At the same time, the presence or absence of an external reference signal can be determined based on the data collected by the FPGA, and the automatic switching of the internal and external references can be realized based on the result of the determination of the presence or absence of the external reference signal. The FPGA can also transmit the current internal and external reference status back to the host computer in real time for reporting. The other signal path output by the power divider A enters the clock distribution module after amplification, attenuation, and amplification processing.

[0092] Furthermore, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the frequency source A1 is a 3.5 GHz point frequency source, and the 3.5 GHz point frequency source includes:

[0093] A point frequency source phase detector, wherein the input end of the point frequency source phase detector is connected to the output end of the power divider G. The input end of the point frequency source phase detector is the input end of the frequency source A1.

[0094] A point frequency source VCO, wherein an input end of the point frequency source VCO is connected to an output end of the point frequency source phase detector.

[0095] A point frequency source power divider, wherein the input end of the point frequency source power divider is connected to the output end of the point frequency source VCO.

[0096] A point frequency source amplifier A, wherein the input end of the point frequency source amplifier A is connected to an output end of the point frequency source power splitter, and the output end of the point frequency source amplifier A is connected to the input end of the DDS.

[0097] A point frequency source amplifier B, wherein the input end of the point frequency source amplifier B is connected to the other output end of the point frequency source power divider. The output end of the point frequency source amplifier B is connected to the input end of the point frequency source phase detector.

[0098] Furthermore, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the DDS is connected to the FPGA, the 3.5 GHz point frequency source provides a 3.5 GHz reference signal to the DDS, and the FPGA controls the DDS to cause the DDS to generate frequency hopping.

[0099] A signal processing method of a frequency synthesis module of a frequency conversion module is implemented based on the frequency synthesis module of the frequency conversion module described above, comprising the steps of:

[0100] Step S1: The power control module provides voltage to the adaptive reference AGC module, the clock distribution module and the universal local oscillator module.

[0101] Step S2: The reference signal REF outside the frequency synthesis module enters the adaptive reference AGC module, which is used to implement automatic gain control of the reference signal and generate an automatic gain signal REF-0.

[0102] Step S3: the automatic gain signal REF-0 enters the clock distribution module, the input end of the clock distribution module is connected to the output end of the adaptive reference AGC module, and is used to generate a clock signal.

[0103] Step S4: the clock signal generated by the adaptive reference AGC module enters the universal local oscillator module, and the universal local oscillator module generates input signals LO1 and LO2 of the frequency conversion module.

[0104] The beneficial effects of the present invention are:

[0105] The LO1 signal of the present invention directly performs frequency multiplication, filtering, amplification and power division on the reference signal before outputting the signal. The design is simple, avoids the introduction of other non-related signals, and ensures better output signal quality. The LO2 signal is mixed and filtered on the basis of the LO1 signal, reducing the introduction of other signals.

[0106] The frequency mixing technology of the present invention increases the upper limit of the LO2 signal frequency by 40.4 GHz, making the function more powerful.

[0107] The present invention can output 4 LO signals simultaneously and support 4 frequency conversion channels to work simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0109] Figure 1 This is the overall structure diagram of the frequency synthesis module.

[0110] Figure 2 The figure shows the structure of the universal local oscillator module as a universal fast local oscillator module.

[0111] Figure 3 This is the structural diagram of the 3.5GHz point frequency source. DETAILED DESCRIPTION

[0112] The following disclosure provides examples which are not intended to limit the present invention.

[0113] The embodiments of the invention are described in detail below with reference to the accompanying drawings.

[0114] A frequency synthesis module of a frequency conversion module, as shown in the attached Figure 1 As shown, including:

[0115] An adaptive reference AGC module is used to implement automatic gain control of a reference signal.

[0116] A clock distribution module, wherein an input end of the clock distribution module is connected to an output end of the adaptive reference AGC module, and is used to generate a clock signal.

[0117] A universal local oscillator module, the input end of which is connected to the output end of the clock distribution module, is used to generate an input signal for the frequency conversion module.

[0118] A power control module, wherein the output end of the power control module is connected to the input end of the adaptive reference AGC module, the input end of the clock distribution module and the input end of the universal local oscillator module, and is used to provide voltage.

[0119] This embodiment adds external devices and modules based on the complete structure of the reference processing module:

[0120] The reference signal source is used to provide a reference signal, referred to as REF. The host computer is used to send instructions to the frequency synthesis module of this embodiment.

[0121] The reference signal REF enters the adaptive reference AGC module, which generates the automatic gain signal REF-O. REF-O enters the clock distribution module, which provides a clock for the universal local oscillator module. The universal local oscillator module generates a 100 MHz signal and LO1 and LO2 signals that enter the frequency synthesizer module. The power control module provides voltage to the adaptive reference AGC module, clock distribution module, and universal local oscillator module.

[0122] Furthermore, the adaptive reference AGC module, as shown in the attached Figure 1 As shown, including:

[0123] A power divider A, wherein the input end of the power divider A is connected to the output end of the reference signal source, and the reference signal source provides a reference signal.

[0124] Attenuator A (attenuation of 0.5 dB in this embodiment), the input end of the attenuator A is connected to an output end of the power divider A.

[0125] Amplifier A, wherein the input end of the amplifier A is connected to the output end of the attenuator A.

[0126] Attenuator B (attenuation of 0.5 dB in this embodiment), the input end of attenuator B is connected to the output end of amplifier A.

[0127] Amplifier B, the input end of the amplifier B is connected to the output end of the attenuator B. The output end of the amplifier B is the output end of the adaptive reference AGC module.

[0128] Detector A, the input end of the detector A is connected to the other output end of the power divider A.

[0129] An ADC chip, wherein the input end of the ADC chip is connected to the output end of the detector A.

[0130] FPGA, the FPGA is connected to the detector A and is used to receive the data collected by the ADC chip, thereby realizing automatic gain control of the reference signal.

[0131] Furthermore, the clock distribution module, as shown in the attached Figure 1 As shown, including:

[0132] Attenuator C; the input end of the attenuator C is connected to the output end of the amplifier B.

[0133] Switch A, one input end of the switch A is connected to the output end of the attenuator C, and the other input end of the switch A is grounded.

[0134] A 10M internal reference signal source provides a 10MHz internal reference signal.

[0135] Switch B, one input end of the switch B is connected to the output end of the 10M internal reference signal source, and the other input end of the switch B is grounded.

[0136] Switch C, one input end of the switch C is connected to the output end of the switch A, and the other input end of the switch C is connected to the output end of the switch B.

[0137] A frequency divider A, wherein an input end of the frequency divider A is connected to an output end of the switch C.

[0138] A 100M reference source, wherein the input end of the 100M reference source is connected to the output end of the frequency divider A.

[0139] Amplifier C, wherein the input end of the amplifier C is connected to the output end of the 100M reference source.

[0140] A filter A, wherein the input end of the filter A is connected to the output end of the amplifier C.

[0141] A power divider B, wherein the input end of the power divider B is connected to the output end of the filter A.

[0142] A power divider C, wherein an input end of the power divider C is connected to an output end of the power divider B.

[0143] Attenuator D (5 dB attenuation in this embodiment), the input end of the attenuator D is connected to the other output end of the power divider B.

[0144] A power divider D, wherein an input end of the power divider D is connected to an output end of the power divider C.

[0145] Attenuator G (attenuation 2 dB in this embodiment), the input end of the attenuator G is connected to one output end of the power divider D. The attenuator G outputs a 100 MHz clock signal.

[0146] Attenuator F (attenuation 2 dB in this embodiment), the input end of the attenuator F is connected to the other output end of the power divider D. The attenuator F outputs a 100 MHz clock signal.

[0147] A power divider E, wherein an input end of the power divider E is connected to another output end of the power divider C.

[0148] Attenuator E (attenuation 0 dB in this embodiment), the input end of the attenuator E is connected to an output end of the power divider E.

[0149] A power divider F, wherein the input end of the attenuator F is connected to the other output end of the power divider E.

[0150] An attenuator H (attenuating 3 dB in this embodiment) has its input connected to an output of the power divider F. The attenuator H outputs a 100 MHz clock signal.

[0151] A power divider G, wherein an input end of the power divider G is connected to another output end of the power divider F.

[0152] As attached Figure 1 As shown in the figure, the signal processed by the adaptive reference AGC module is REF-O. After attenuation and amplification, and after being selected by the 10 MHz reference signal source via switch C (the switch is controlled by the FPGA), it provides a reference for the 100 MHz reference oscillator. The 100 MHz reference source generates a 100 MHz signal, which is amplified and passed through a multi-stage power divider to produce multiple output signals. 100M-O1 and 100M-O3 provide reference signals for the universal local oscillator module. 100M-1, 100M-2, and 100M-O2 are directly output as 100 MHz clocks. 100M-3 and 100M-4 are reserved ports for functional expansion.

[0153] Furthermore, the universal local oscillator module is used as a universal slow frequency integrated local oscillator module. Figure 1 As shown, including:

[0154] A frequency multiplier A, wherein the input end of the frequency multiplier A is connected to the output end of the attenuator D.

[0155] A comb spectrum generator A, wherein the input end of the comb spectrum generator A is connected to the output end of the frequency multiplier A.

[0156] A power divider I, wherein the input end of the power divider I is connected to the output end of the comb spectrum generator A.

[0157] Filter B, where an input end of the filter B is connected to an output end of the power divider I.

[0158] An amplifier D, wherein an input end of the amplifier D is connected to an output end of the filter B.

[0159] A filter C, wherein an input end of the filter C is connected to an output end of the amplifier D.

[0160] An amplifier E, wherein an input end of the amplifier E is connected to an output end of the filter C.

[0161] A power divider J, wherein the input end of the power divider J is connected to the output end of the amplifier E. The power divider J outputs two local oscillator signals.

[0162] An amplifier F, wherein an input end of the amplifier F is connected to the other output end of the power divider I.

[0163] A switching filter A, wherein an input end of the switching filter A is connected to an output end of the amplifier F.

[0164] An amplifier G, wherein an input end of the amplifier G is connected to an output end of the switching filter A.

[0165] A frequency multiplier B, wherein the input end of the frequency multiplier B is connected to the output end of the amplifier G.

[0166] A filter D, wherein the input end of the filter D is connected to the output end of the frequency multiplier B.

[0167] An amplifier H, wherein an input end of the amplifier H is connected to an output end of the filter D.

[0168] A frequency divider B, wherein an input end of the frequency divider B is connected to an output end of the attenuator E.

[0169] A frequency source A, wherein an input end of the frequency source A is connected to an output end of the frequency divider B.

[0170] A mixer A, one input end of the mixer A is connected to the output end of the frequency source A, and the other input end of the mixer A is connected to the output end of the amplifier H.

[0171] A switching filter B, wherein an input end of the switching filter B is connected to an output end of the mixer A.

[0172] An amplifier I, wherein an input end of the amplifier I is connected to an output end of the switching filter B.

[0173] A filter E, wherein an input end of the filter E is connected to an output end of the amplifier I.

[0174] An amplifier J, wherein an input end of the amplifier J is connected to an output end of the filter E.

[0175] A power divider K, wherein the input end of the power divider K is connected to the output end of the amplifier J. The power divider K outputs two local oscillator signals.

[0176] As attached Figure 1 As shown, the signal generated by the 100M-O1 signal after the frequency multiplier is used as the reference signal of the comb spectrum generator A (a 2G comb spectrum generator is selected in this embodiment). The 2G comb spectrum generator generates a series of frequency spectra, which are divided into two paths after two power splitters (power splitter I). One path passes through filter B to select the 26GHz signal, which is then filtered out by filter B to remove clutter and then split into two LO1 signals for use by the frequency conversion module.

[0177] The other path passes through the amplifier and then switches filter A to select the 14G / 16G / 18G / 20G signals. This signal is amplified by amplifier F and doubled by filter B. Filter D then selects the 28-40 GHz signal. The 28-40 GHz signal is amplified and used as the LO signal for mixer A.

[0178] After being divided by divider B, 100M-O3 serves as the reference signal for frequency source A (a 2594 GHz frequency source is used in this embodiment). The IF signal generated by the 2594 GHz frequency source is mixed with the 28-40 GHz LO signal to generate an RF signal. Different filters in switch filter A are used to select signals of 24.2-26.5 GHz, 26.5-30.5 GHz, 30.5-34.5 GHz, 34.5-38.5 GHz, and 38.5-40.4 GHz, respectively. After amplification, filtering, and power division, two LO2 signals are output for use by the frequency conversion module.

[0179] Furthermore, the universal local oscillator module can be used as a universal fast frequency integrated local oscillator module, as shown in the attached Figure 2 As shown in the figure, when used as a general fast-frequency integrated local oscillator module, it includes:

[0180] Frequency multiplier A1.

[0181] A comb spectrum generator A1, wherein the input end of the comb spectrum generator A1 is connected to the output end of the frequency multiplier A1.

[0182] A power divider I1 , wherein the input end of the power divider I1 is connected to the output end of the comb spectrum generator A1 .

[0183] Filter B1, the input end of the filter B1 is connected to an output end of the power divider I1.

[0184] An amplifier D1 , wherein an input end of the amplifier D1 is connected to an output end of the filter B1 .

[0185] The filter C1 has an input end connected to the output end of the amplifier D1.

[0186] An amplifier E1 , wherein an input end of the amplifier E1 is connected to an output end of the filter C1 .

[0187] A power divider J1, wherein the input end of the power divider J1 is connected to the output end of the amplifier E1. The power divider J1 outputs two local oscillator signals.

[0188] Amplifier F1, the input end of the amplifier F1 is connected to the other output end of the power divider I1.

[0189] A switching filter A1 , wherein an input end of the switching filter A1 is connected to an output end of the amplifier F1 .

[0190] An amplifier G1 , wherein an input end of the amplifier G1 is connected to an output end of the switching filter A1 .

[0191] A frequency multiplier B1 , wherein an input end of the frequency multiplier B1 is connected to an output end of the amplifier G1 .

[0192] The filter D1 has an input end connected to the output end of the frequency multiplier B1.

[0193] An amplifier H1 , wherein an input end of the amplifier H1 is connected to an output end of the filter D1 .

[0194] The frequency divider B1 has an input end connected to the output end of the attenuator E.

[0195] A comb spectrum generator A2, wherein the input end of the comb spectrum generator A2 is connected to the output end of the frequency divider B1.

[0196] A frequency source A1, wherein an input end of the frequency source A1 is connected to an output end of the power divider G.

[0197] DDS, the input end of the DDS is connected to the output end of the frequency source A1.

[0198] A mixer A2, one input end of the mixer A2 is connected to the output end of the comb spectrum generator A2, and the other input end of the mixer A2 is connected to the output end of the DDS.

[0199] A switching filter B2, wherein an input end of the switching filter B2 is connected to an output end of the mixer A2.

[0200] A mixer A1, one input end of the mixer A1 is connected to the output end of the amplifier H1, and the other input end of the mixer A1 is connected to the output end of the switching filter B2.

[0201] A switching filter B1 , wherein an input end of the switching filter B1 is connected to an output end of the mixer A1 .

[0202] Amplifier I1 , wherein an input end of the amplifier I1 is connected to an output end of the switching filter B1 .

[0203] The filter E1 has an input end connected to the output end of the amplifier I1.

[0204] Amplifier J1 , wherein the input end of the amplifier J1 is connected to the output end of the filter E1 .

[0205] The power divider K1 has an input end connected to the output end of the amplifier J1 and outputs two local oscillator signals.

[0206] As attached Figure 2 As shown, the signal generated by the 100M-O1 signal after the frequency multiplier is used as the reference signal of the comb spectrum generator A1 (a 2G comb spectrum generator is selected in this embodiment). The 2G comb spectrum generator generates a series of frequency spectra, which are divided into two paths after two power splitters (power splitter I1). One path passes through the filter B1 to select the 26G signal, which is then filtered out by the filter B1 to remove clutter and then split into two LO1 signals for use by the frequency conversion module.

[0207] The other path passes through the amplifier and then switches filter A1 to select the 14G / 16G / 18G / 20G signals. These signals are amplified by amplifier F1 and then doubled by filter B1. Filter D1 then selects the 28-40G signals. The amplified 28-40G signals serve as the LO signals for mixer A1.

[0208] After being divided by the frequency divider, the 100M-4 provides a reference signal for the frequency source (a 3.5GHz point frequency source is selected in this embodiment), generating a 3.5GHz signal. The 3.5GHz signal enters the DDS and provides a clock signal for the DDS. Under the control of the FPGA, the DDS generates a 250-750MHz baseband signal, which is mixed with the 4.25-7.75GHz LO signal to generate a 3.5-7.5GHz intermediate frequency signal, which is then selected by the switch filter and enters the next mixing.

[0209] The 4.25-7.75 GHz LO signal is generated by multiplying the 100M-O3 reference signal by five times to generate a 500 MHz signal, which is then divided by two by the frequency divider B1 to generate a 250 MHz signal, thereby driving the comb spectrum generator A2 to generate high-order harmonics of 4.25-7.75 GHz. These point-frequency local oscillator signals are then extracted through the switching filter B2 and provided to the baseband mixer for local oscillator drive.

[0210] After the next mixing cycle, mixer A1 generates an RF signal. Different filters in switch filter B1 are used to select 24.2-26.5 GHz, 26.5-30.5 GHz, 30.5-34.5 GHz, 34.5-38.5 GHz, and 38.5-40.4 GHz signals. After amplification, filtering, and power division, two LO2 signals are output for use by the frequency conversion module.

[0211] Furthermore, the FPGA is connected to the detector A to receive the data collected by the ADC chip, thereby realizing the specific method of automatic gain control of the reference signal: the REF signal outside the frequency synthesis module enters the power divider A, the power divider A outputs 2 signals, one of which is detected by the detector A, and then the detected analog voltage is sampled by the ADC chip, and the sampled data is transmitted to the FPGA for data collection, thereby realizing automatic gain control of the reference signal. At the same time, the presence or absence of an external reference signal can be determined based on the data collected by the FPGA, and the automatic switching of the internal and external references can be realized based on the result of the determination of the presence or absence of the external reference signal. The FPGA can also transmit the current internal and external reference status back to the host computer in real time for reporting. The other signal path output by the power divider A enters the clock distribution module after amplification, attenuation, and amplification processing.

[0212] Furthermore, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the frequency source A1 is a 3.5 GHz point frequency source. Figure 3 As shown, including:

[0213] A point frequency source phase detector, wherein the input end of the point frequency source phase detector is connected to the output end of the power divider G. The input end of the point frequency source phase detector is the input end of the frequency source A1.

[0214] A point frequency source VCO, wherein an input end of the point frequency source VCO is connected to an output end of the point frequency source phase detector.

[0215] A point frequency source power divider, wherein the input end of the point frequency source power divider is connected to the output end of the point frequency source VCO.

[0216] A point frequency source amplifier A, wherein the input end of the point frequency source amplifier A is connected to an output end of the point frequency source power splitter, and the output end of the point frequency source amplifier A is connected to the input end of the DDS.

[0217] A point frequency source amplifier B, wherein the input end of the point frequency source amplifier B is connected to the other output end of the point frequency source power divider. The output end of the point frequency source amplifier B is connected to the input end of the point frequency source phase detector.

[0218] Furthermore, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the DDS is connected to the FPGA, the 3.5 GHz point frequency source provides a 3.5 GHz reference signal to the DDS, and the FPGA controls the DDS to cause the DDS to generate frequency hopping.

[0219] A signal processing method of a frequency synthesis module of a frequency conversion module is implemented based on the frequency synthesis module of the frequency conversion module described above, comprising the steps of:

[0220] Step S1: The power control module provides voltage to the adaptive reference AGC module, the clock distribution module and the universal local oscillator module.

[0221] Step S2: The reference signal REF outside the frequency synthesis module enters the adaptive reference AGC module, which is used to implement automatic gain control of the reference signal and generate an automatic gain signal REF-0.

[0222] Step S3: the automatic gain signal REF-0 enters the clock distribution module, the input end of the clock distribution module is connected to the output end of the adaptive reference AGC module, and is used to generate a clock signal.

[0223] Step S4: the clock signal generated by the adaptive reference AGC module enters the universal local oscillator module, and the universal local oscillator module generates input signals LO1 and LO2 of the frequency conversion module.

Claims

1. A frequency synthesis module of a frequency conversion module, characterized in that: include: An adaptive reference AGC module, wherein the adaptive reference AGC module is used to implement automatic gain control of a reference signal; a clock distribution module, wherein an input end of the clock distribution module is connected to an output end of the adaptive reference AGC module, and is configured to generate a clock signal; a universal local oscillator module, the input end of which is connected to the output end of the clock distribution module, and is used to generate an input signal for the frequency conversion module; a power control module, wherein an output end of the power control module is connected to an input end of the adaptive reference AGC module, an input end of the clock distribution module, and an input end of the universal local oscillator module, for providing voltage; The universal local oscillator module is a universal fast-frequency integrated local oscillator module, which includes a frequency multiplier A1, a comb spectrum generator A1, a power divider I1, a filter B1, an amplifier D1, a filter C1, an amplifier E1 and a power divider J1 connected in sequence, and a frequency divider B1, a comb spectrum generator A2, a mixer A2, a switching filter B2, a mixer A1, a switching filter B1, an amplifier I1, a filter E1, an amplifier J1 and a power divider K1 connected in sequence; An amplifier F1, a switching filter A1, an amplifier G1, a frequency multiplier B1, a filter D1 and an amplifier H1 are sequentially arranged between the power divider I1 and the mixer A1; After the frequency source A1 is connected to the DDS, it is then connected to the mixer A2; The power divider J1 and the power divider K1 respectively output two local oscillator signals.

2. The frequency synthesizer module of the frequency conversion module according to claim 1, characterized in that: The adaptive reference AGC module includes: Power divider A, an attenuator A, wherein an input end of the attenuator A is connected to an output end of the power divider A; an amplifier A, wherein an input end of the amplifier A is connected to an output end of the attenuator A; an attenuator B, wherein an input end of the attenuator B is connected to an output end of the amplifier A; Amplifier B, the input end of the amplifier B is connected to the output end of the attenuator B; the output end of the amplifier B is the output end of the adaptive reference AGC module; Detector A, the input end of the detector A is connected to the other output end of the power divider A; An ADC chip, wherein the input end of the ADC chip is connected to the output end of the detector A; FPGA, the FPGA is connected to the detector A and is used to receive the data collected by the ADC chip, thereby realizing automatic gain control of the reference signal.

3. The frequency synthesizer module of the frequency conversion module according to claim 2, characterized in that: The clock distribution module includes: Attenuator C; the input end of the attenuator C is connected to the output end of the amplifier B; a switch A, wherein one input end of the switch A is connected to the output end of the attenuator C, and the other input end of the switch A is grounded; A 10 MHz internal reference signal source, wherein the 10 MHz internal reference signal source provides a 10 MHz internal reference signal; a switch B, wherein one input end of the switch B is connected to the output end of the 10M internal reference signal source, and the other input end of the switch B is grounded; a switch C, wherein one input terminal of the switch C is connected to the output terminal of the switch A, and the other input terminal of the switch C is connected to the output terminal of the switch B; A frequency divider A, wherein an input end of the frequency divider A is connected to an output end of the switch C; A 100M reference source, wherein an input end of the 100M reference source is connected to an output end of the frequency divider A; An amplifier C, wherein an input end of the amplifier C is connected to an output end of the 100M reference source; A filter A, wherein an input end of the filter A is connected to an output end of the amplifier C; A power divider B, wherein the input end of the power divider B is connected to the output end of the filter A; A power divider C, wherein an input end of the power divider C is connected to an output end of the power divider B; an attenuator D, wherein an input end of the attenuator D is connected to the other output end of the power divider B; a power divider D, wherein an input end of the power divider D is connected to an output end of the power divider C; an attenuator G, wherein an input end of the attenuator G is connected to an output end of the power divider D; the attenuator G outputs a 100 MHz clock signal; an attenuator F, wherein an input end of the attenuator F is connected to the other output end of the power divider D; the attenuator F outputs a 100 MHz clock signal externally; a power divider E, wherein an input end of the power divider E is connected to another output end of the power divider C; an attenuator E, wherein an input end of the attenuator E is connected to an output end of the power divider E; a power divider F, wherein the input end of the attenuator F is connected to the other output end of the power divider E; an attenuator H, wherein an input end of the attenuator H is connected to an output end of the power divider F; the attenuator H outputs a 100 MHz clock signal; A power divider G, wherein an input end of the power divider G is connected to another output end of the power divider F.

4. The frequency synthesizer module of the frequency conversion module according to claim 3, characterized in that: The universal local oscillator module, when used as a universal slow-frequency integrated local oscillator module, includes: a frequency multiplier A, wherein an input end of the frequency multiplier A is connected to an output end of the attenuator D; A comb spectrum generator A, wherein the input end of the comb spectrum generator A is connected to the output end of the frequency multiplier A; A power divider I, wherein an input end of the power divider I is connected to an output end of the comb spectrum generator A; a filter B, wherein an input end of the filter B is connected to an output end of the power divider I; an amplifier D, wherein an input end of the amplifier D is connected to an output end of the filter B; a filter C, wherein an input end of the filter C is connected to an output end of the amplifier D; an amplifier E, wherein an input end of the amplifier E is connected to an output end of the filter C; A power divider J, wherein the input end of the power divider J is connected to the output end of the amplifier E; the power divider J outputs two local oscillator signals externally; an amplifier F, wherein an input end of the amplifier F is connected to the other output end of the power divider I; a switching filter A, wherein an input end of the switching filter A is connected to an output end of the amplifier F; an amplifier G, wherein an input end of the amplifier G is connected to an output end of the switching filter A; a frequency multiplier B, wherein an input end of the frequency multiplier B is connected to an output end of the amplifier G; a filter D, wherein an input end of the filter D is connected to an output end of the frequency multiplier B; an amplifier H, wherein an input end of the amplifier H is connected to an output end of the filter D; A frequency divider B, wherein an input end of the frequency divider B is connected to an output end of the attenuator E; A frequency source A, wherein an input end of the frequency source A is connected to an output end of the frequency divider B; A mixer A, one input end of the mixer A is connected to the output end of the frequency source A, and the other input end of the mixer A is connected to the output end of the amplifier H; a switching filter B, wherein an input end of the switching filter B is connected to an output end of the mixer A; an amplifier I, wherein an input end of the amplifier I is connected to an output end of the switching filter B; a filter E, wherein an input end of the filter E is connected to an output end of the amplifier I; an amplifier J, wherein an input end of the amplifier J is connected to an output end of the filter E; A power divider K, wherein the input end of the power divider K is connected to the output end of the amplifier J; the power divider K outputs two local oscillator signals to the outside.

5. The frequency synthesizer module of the frequency conversion module according to claim 2, characterized in that: The FPGA is connected to the detector A, and the FPGA is connected to the detector A to receive data collected by the ADC chip, thereby realizing the specific method of automatic gain control of the reference signal: the REF signal outside the frequency synthesis module enters the power divider A, the power divider A outputs two signals, one of which is detected by the detector A, and then the detected analog voltage is sampled by the ADC chip, and the sampled data is transmitted to the FPGA for data collection, thereby realizing automatic gain control of the reference signal. At the same time, the presence or absence of an external reference signal can be judged based on the data collected by the FPGA, and automatic switching of internal and external references can be realized based on the result of the judgment of the presence or absence of the external reference signal; the FPGA can also transmit the current internal and external reference status back to the host computer in real time for reporting; the other signal path output by the power divider A enters the clock distribution module after amplification, attenuation, and amplification processing.

6. The frequency synthesizer module of the frequency conversion module according to claim 2, characterized in that: When the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the frequency source A1 is a 3.5 GHz point frequency source, and the 3.5 GHz point frequency source includes: Point frequency source phase detector; the input end of the point frequency source phase detector is connected to the output end of the power divider G; the input end of the point frequency source phase detector is the input end of the frequency source A1; Point frequency source VCO; the input end of the point frequency source VCO is connected to the output end of the point frequency source phase detector; A point frequency source power divider; the input end of the point frequency source power divider is connected to the output end of the point frequency source VCO; Point frequency source amplifier A; the input end of the point frequency source amplifier A is connected to an output end of the point frequency source power splitter; the output end of the point frequency source amplifier A is connected to the input end of the DDS; Point frequency source amplifier B; the input end of the point frequency source amplifier B is connected to the other output end of the point frequency source power divider; the output end of the point frequency source amplifier B is connected to the input end of the point frequency source phase detector.

7. The frequency synthesizer module of the frequency conversion module according to claim 6, characterized in that: When the universal local oscillator module is used as a universal fast-frequency integrated local oscillator module, the DDS is connected to the FPGA; the 3.5 GHz point frequency source provides a 3.5 GHz reference signal for the DDS, and the FPGA controls the DDS to cause the DDS to generate a frequency jump.

8. A signal processing method of a frequency synthesizer module of a frequency conversion module, implemented based on the frequency synthesizer module of a frequency conversion module according to any one of claims 1 to 7, characterized in that: Including steps: Step S1: The power control module provides voltage to the adaptive reference AGC module, the clock distribution module and the universal local oscillator module; Step S2: The reference signal REF outside the frequency synthesis module enters the adaptive reference AGC module, which is used to implement automatic gain control of the reference signal and generate an automatic gain signal REF-0; Step S3: the automatic gain signal REF-0 enters a clock distribution module, the input end of the clock distribution module is connected to the output end of the adaptive reference AGC module, and is used to generate a clock signal; Step S4: the clock signal generated by the adaptive reference AGC module enters the universal local oscillator module, and the universal local oscillator module generates input signals LO1 and LO2 of the frequency conversion module.

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