Combined data center and rack throttling

Abstract

The present technology generally relates to a power throttling mechanism controlled by a payload receiving power provided by a rack or other such power source. The power level provided by the rack may be maintained for a predetermined period of time. The power throttling mechanism may include determining a predetermined time period and a throttling offset for the payload. The payload may perform power throttling by adjusting a voltage reference based on a throttling offset, after which the payload may maintain power usage for at least a predetermined period of time. According to some examples, power capping may occur substantially simultaneously in addition to throttling the power of the payload. The power capping mechanism may transmit notifications to a controller, such as a baseboard management controller, to cap the power consumption of the data center.

Description

Background Art

[0001] The power output of a rack in a server system is relatively consistent, typically with small fluctuations based on the payload of the rack. For example, at a typical payload, the power output of a rack can be as high as 10kW as the amount of power drawn by the payload increases. The amount of power continuously provided by the rack may be limited to 10kw, but the rack power components and power distribution can support higher power for short periods of time. The typical power consumption of a server is generally less than the maximum possible power consumption of the server. It is expensive to build and supply a data center to maximize the power output of each server. In addition, maximizing the power capacity of each server can cause the server to exceed the power limit. This can cause the server, rack, and / or other such components of the data center to overload or short-circuit, which can cause component damage, data loss, or fire. Summary of the invention

[0002] The present technology generally relates to a power throttling mechanism controlled by a payload receiving power provided by a rack or other such power source. The power level provided by the rack can be maintained for a predetermined time period. The power throttling mechanism can include the payload determining a predetermined time period and a throttling offset. The payload can perform power throttling by adjusting a voltage reference based on the throttling offset, after which the payload can maintain power usage for at least a predetermined time period. By throttling the power consumption of the payload for at least a predetermined time period, the power available to the payload is maintained for at least a predetermined time period, so that the payload has enough time to back up data before shutting down. According to some examples, in addition to throttling the power of the payload, power capping can occur substantially simultaneously. The power capping mechanism can transmit a notification to a controller such as a baseboard management controller to cap the power consumption of the data center.

[0003] One aspect of the present disclosure relates to a method that includes detecting, by one or more processors of a first payload, an input voltage, determining, by the one or more processors, a reduction in the input voltage based on the detected input voltage, determining, by the one or more processors, at least one throttling offset based on the reduction in the input voltage, and adjusting, by the one or more processors, a voltage reference based on the determined throttling offset.

[0004] The method may further include latching, by the one or more processors, the power throttling for a latching period. The latching period may be based on a power supply of a rack providing an input voltage to the first payload and correspond to a predetermined time period.

[0005] Adjusting the voltage reference, the method may further include reducing, by the one or more processors, power consumption of the first payload.

[0006] The at least one throttle offset may be determined by a sequencer.The method may further include selecting, by one or more processors, one of the at least one throttle offset.

[0007] The at least one throttle offset may be determined by a voltage divider.

[0008] The reduction in input voltage may correspond to a throttling signal.The method may further include transmitting, by the one or more processors, the throttling signal to a software control loop.

[0009] The voltage reference may be monitored by a pulse width modulator ("PWM") controller.

[0010] The method may further include throttling, by the one or more processors, power consumption of the first payload based on the voltage reference.

[0011] Another aspect of the present disclosure relates to a system comprising one or more processors. The one or more processors may be configured to detect an input voltage provided to a payload, determine a reduction in the input voltage based on the input voltage, determine a throttling offset based on the reduction in the input voltage, and adjust a voltage reference based on the determined throttling offset.

[0012] Yet another aspect of the present disclosure relates to one or more non-transitory computer-readable storage media encoding instructions that, when executed by one or more processors of a payload, cause the one or more processors to perform operations including detecting an input voltage, determining a reduction in the input voltage, determining at least one throttling offset based on the reduction in the input voltage, and adjusting a voltage reference based on the determined throttling offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of a power throttling system according to aspects of the present disclosure.

[0014] Figure 2 is a graphical representation of power oversubscription in accordance with aspects of the present disclosure.

[0015] Figure 3 is a graphical representation of the output voltage of a power source according to aspects of the present disclosure.

[0016] Figure 4A is a circuit diagram of a portion of a power throttling system according to aspects of the present disclosure.

[0017] Figure 4B is a circuit diagram of a sequencer according to aspects of the present disclosure.

[0018] Figure 5A is a perspective view of a rack according to aspects of the present disclosure.

[0019] Figure 5B According to various aspects of the present disclosure Figure 4A Another perspective view of the rack.

[0020] Figure 6 is a schematic diagram of an example power architecture in accordance with aspects of the present disclosure.

[0021] Figure 7 is a block diagram of an example system in accordance with aspects of the present disclosure.

[0022] Figure 8 is a flow chart of an example method of throttling power consumption with delays according to aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The present technology generally relates to a power throttling mechanism controlled by a payload receiving power provided by a rack or other such power source. The power level provided by the rack can be maintained for a predetermined time period. The power throttling mechanism can include the payload determining the predetermined time period and a throttling offset. The payload can perform power throttling by adjusting a voltage reference based on the throttling offset, after which the payload can maintain power usage for at least the predetermined time period. By throttling the power consumption of the payload for at least the predetermined time period, the power available to the payload is maintained for at least the predetermined time period, so that the payload has sufficient time to back up data before shutting down.

[0024] The system may include a rack and one or more payloads in communication with the rack. The rack may include a rectifier configured to output a voltage to the payload. The output voltage of the rectifier may be an input voltage to the payload. The payload may be, for example, one or more trays within the rack. The payload may include a digital controller, a power supply, a sequencer, one or more processors, and other such computing components.

[0025] The payload may detect the voltage being received from the rectifier of the rack. The rectifier may generate a throttling signal when the power consumption of the payload exceeds a threshold power amount within a predetermined time period. The threshold power amount may be a percentage of the total available power or a predetermined value. The throttling signal may be a reduction in the output voltage from the rectifier.

[0026] In the case where the throttling signal is a reduction in the output voltage from the rectifier, the payload can detect the reduction in the input voltage. The payload can determine that the reduction in the input voltage is a throttling signal. In some examples, after detecting the throttling signal, the sequencer can latch the throttling signal for a predetermined time period so that the power used by the payload is reduced. Latching the throttling signal can make the throttling signal valid for a predetermined time period. The predetermined time period can be, for example, a latching period. The latching period can be maintained until the predetermined time period ends or until another control signal allows the latched throttling signal to change.

[0027] The cause of the throttling signal may be unknown. In some examples, the throttling signal may be caused by the rectifier exceeding a threshold capacity. In another example, the throttling signal may be caused by switching to battery power. In order to maximize the amount of time that the payload can continue to consume power, the throttling signal may be latched for a predetermined time period. The predetermined time period may be based on the battery capacity. In some examples, the predetermined time period may be selected so that the battery capacity is not exceeded.

[0028] In some examples, a throttling signal can be detected by a comparator in the payload and transmitted to a sequencer in the payload. Transmitting the throttling signal to the sequencer provides flexibility to adjust the latch period, such as a predetermined time period, without having to include additional components in the tray. In some examples, by transmitting the throttling signal to the sequencer, a delay can be added before throttling power consumption. For example, the sequencer can delay throttling the power consumption of the payload by a threshold time period. Delaying throttling the power consumption of the payload by the threshold time period can allow a rectifier to rebuild power, normalize the power consumption itself, etc. before throttling the power consumption.

[0029] The latch period along with the throttling offset may be transmitted to a digital controller of the payload. According to some examples, the throttling offset may be determined using an offset function. The throttling offset may be used to add a preset voltage to a voltage sensing input of a pulse width modulator ("PWM") controller. The PWM controller may adjust the output PWM to throttle the power consumption of the payload. For example, the throttling offset may cause the PWM controller to determine that the payload is consuming more power than the payload actually consumes.

[0030] As an example, if the processor of the payload is configured with a target power of 500 W and the actual power consumption is 450 W, the processor may increase or adjust the PWM controller up to increase the power consumption of the payload. In some examples, if the actual power consumption is 550 W and the target power is 500 W, the processor may decrease or adjust the PWM controller down to reduce the power consumption of the payload. In some examples, the increase or decrease of the PWM controller may be determined based on a throttling offset.

[0031] According to some examples, the throttling signal may be transmitted to a software control loop. The software control loop may be, for example, a baseboard management controller ("BMC"). The BMC may monitor the power consumption and / or power throttling of the payload. According to some examples, the BMC may communicate with both the payload and the rack such that the BMC may respond to data center level software signals as well as signals from the payload.

[0032] According to some examples, in addition to throttling power to the payload, the system can be configured to cap the power. The power capping mechanism can be managed by the data center software, while the power throttling of the payload can be managed by the hardware within the rack. Power capping can occur substantially simultaneously with the power throttling of the payload. Power capping can occur when the power consumption of the data center approaches the circuit breaker limit. When the power consumption approaches the circuit breaker limit, the power capping mechanism can transmit a notification to the BMC to cap the power consumption of the data center. The BMC can transmit a command to the PWM controller of the payload to reduce the power supplied to the payload. Reducing the power supplied to the payload can reduce the overall power consumption of the data center.

[0033] By adjusting the reference voltage input to the PWM controller, the payload can respond to a throttle signal in milliseconds, rather than seconds when the reference voltage is adjusted in the payload's software. Using hardware components within the payload to create a control loop allows the control loop to be a fast control loop, such as being able to respond to a throttle signal in milliseconds.

[0034] Adjusting the voltage reference based on the throttling offset can enable the payload's digital controller to reduce power consumption, thereby extending the amount of time the payload can continue to operate when a power event occurs. In some examples, by adjusting the voltage reference, the payload can continue to operate for at least a predetermined latch period. This can allow recovery from power events, such as a power outage. In some examples, this can allow the payload to back up any data or functionality before shutting down.

[0035] In some examples, by throttling the power supplied to the payload, the data center may be able to oversubscribe power and, therefore, reduce infrastructure costs associated with operating the data center. For example, when the power consumption of the data center approaches a circuit breaker limit, the data center software may transmit a request to throttle power. The request may be received by the BMC. According to some examples, since the BMC may communicate with both the data center and the payload, the BMC may determine a power cap value and communicate the power cap value to the payload's PWM controller.

[0036] Figure 11 is a schematic diagram of a power throttling system 100. The power throttling system 100 may include a power path 102, a throttling path 114, and a control and monitoring path 116. The system 100 may include a payload 140. The system 100 may be part of a data center, a rack within a data center, etc. According to one example, the system 100 may be a rack within a data center, and the payload 140 may be a server within the rack.

[0037] The power path 102 may include a power system of a data center and / or a rack within a data center. For example, the power path 102 may include a power distributor 106, one or more rectifiers 108, and one or more batteries 104. According to some examples, the power path 102 may include power system features of a payload 140. For example, within the power path 102, the payload 140 may include a power source 110 and one or more application specific integrated circuits (“ASICs”) 112.

[0038] The throttle path 114 may include a multiplier 131, a comparator 132, a sequencer 134, an offset function 136, and a controller 130. The multiplier 131 may be an analog multiplier configured to determine power based on a voltage and a current of the system, for example, by multiplying the voltage by the current. The multiplier 131, the comparator 132, the sequencer 134, the offset function 136, and the controller 130 may be part of a payload 140. The payload 140 may include a Figure 1 Computers other than and / or in lieu of those shown in Figure 1 other such computers as those shown in .

[0039] The control and monitoring path 116 may include power monitoring software 118 and management software 120. The power monitoring software 118 may be, for example, data center power monitoring software. The management software 120 may be, for example, machine management software. According to some examples, the power consumption of the system 100 may be monitored. For example, a data center may oversubscribe power to reduce infrastructure costs. In order to safely and efficiently oversubscribe power, the payload may be actively reduced if the circuit breaker limit is approached. The control and monitoring path 116 may further include a baseboard management controller ("BMC") 122. The BMC 122 may include a server 124, power capping software 128, and a monitor 126. In some examples, the server 124 may be a Redfile server. According to some examples, the monitor 126 may be a general purpose input / output ("GPIO") monitor. The BMC 122 may be part of the payload 140. According to some examples, the BMC 122 may be a software control loop. The BMC 122 may monitor the power consumption and / or power throttling of the payload 140. According to some examples, BMC 122 can communicate with both payload 140 and rack so that BMC 122 can respond to data center level software signals as well as signals from payload 140. In some examples, the signal can be a throttling signal.

[0040] refer to Figure 2 , when the power payload 248 of the data center approaches the circuit breaker limit 242, the payload 248 can be reduced. For example, the payload 248 can exceed the power capping threshold 240 and approach the circuit breaker limit 242. If the data center payload 248 is not reduced, the payload 248 will surge 254, 256 to the subscription limit 244. When the payload 248 is between the circuit breaker limit 242 and the subscription limit 244, the data center power is oversubscribed.

[0041] Return to reference Figure 1 In order to reduce the power payload of the data center, the power monitoring software 118 can transmit a request to the management software 120 to throttle power. In some examples, the power monitoring software 118 and / or the management software 120 can be software within the system 100. In some examples, the request to throttle power can be a software application programming interface (“API”). In some examples, throttling power can be a reduction in power consumption of the payload 140 compared to destructively suspending operations.

[0042] The BMC 122 may receive a power throttling request from the management software 120. In some examples, the BMC 122 may be software within the payload 140. According to some examples, the management software 120 may transmit a request to the server 124. The request may be a software API. In some examples, the management software 120 may transmit a power limit to the server 124. Based on the power limit, the server 124 may transmit a power capping command to the power capping software 128. The power capping software 128 may transmit a voltage command to the controller 130. In some examples, the voltage command may be a digital signal transmitted from the power capping software 128 to the controller 130. Based on the voltage command transmitted by the power capping software 128, the controller 130 may adjust the power consumption of the payload 140. For example, the power consumption of the payload 140 may be reduced. In some examples, reducing the power consumption of the payload 140 may reduce the power consumption of the data center.

[0043] According to some examples, by throttling the power supplied to the payload, the data center may be able to oversubscribe power. Oversubscription of power may reduce infrastructure costs associated with operating the data center.

[0044] The power capping mechanism can be managed by data center software, while power throttling of payload 140 can be managed by hardware within the rack. Power capping can occur substantially simultaneously with power throttling of payload 140.

[0045] According to some examples, racks within a data center may oversubscribe power at the same time as the data center oversubscribes power and / or in addition to the data center oversubscribing power. According to some examples, rack power oversubscription may be more local and time sensitive than data center power oversubscription. In some examples, power throttling for a rack must occur in less than about 15 ms.

[0046] like Figure 3 As shown in the figure, the DC bus of the rack, such as the rectifier 108 of the rack, can be configured to output up to at least 55V. The output voltage of the rectifier 108 can decrease as the payload power consumption increases. For example, when the rectifier power is turned on, when the payload is at 95% capacity, the rectifier can output a 52V voltage. When the payload capacity increases and / or when there is a power event, the DC bus voltage can drop below 52V. The power event can include, for example, a power outage. In an example where there is a power event, the battery power supply can provide an output voltage of approximately 51V or less.

[0047] Return to reference Figure 1, the reduction in the output voltage of the rectifier 108 can be a throttling signal. The throttling signal can be detected by the comparator 132 and transmitted to the sequencer 134. The throttling signal detected by the comparator 132 can be an analog signal. In some examples, the comparator 132 can be hardware within the payload 140. The throttling signal transmitted from the comparator 132 to the sequencer 134 can be a digital signal. The sequencer 134 can be hardware within the payload 140. Transmitting the throttling signal to the sequencer 134 provides flexibility in adjusting the latching period without having to include additional components in the tray. The latching period can be a predetermined time period based on the capacity of the battery 104, for example. In some examples, the predetermined time period can be selected so that the capacity of the battery 104 is not exceeded. The latching period can maximize the amount of time that the payload 140 can continue to consume power.

[0048] In some examples, a delay may be added before throttling power consumption by transmitting a throttling signal to sequencer 134. For example, sequencer 134 may delay throttling power consumption of payload 140 by a threshold period of time. Delaying throttling power consumption of payload 140 by the threshold period of time may allow rectifier 108 to rebuild power, normalize power consumption itself, etc. before throttling power consumption.

[0049] According to some examples, a throttling signal may be transmitted from the sequencer 134 to the BMC 122. For example, the throttling signal may be transmitted to the monitor 126 for monitoring. The throttling signal transmitted to the monitor 126 may be a digital signal. The monitor 126 may monitor the power consumption and / or power throttling of the payload 140.

[0050] The latch period may be transmitted to the controller 130 along with the throttling offset. In some examples, the throttling offset may be an analog signal. The controller 130 may be hardware within the payload 140. In some examples, the controller may be a digital controller, a pulse width modulator (“PWM”) controller, etc. The throttling offset may be determined by an offset function 136. In some examples, the offset function 136 may be used to add a preset voltage to a voltage sensing input of the controller 130. The controller 130 may adjust the output to throttle the power consumption of the payload 140. For example, if the controller 130 is a PWM controller, the PWM controller may adjust the output PWM to throttle the power consumption of the payload 140. Throttling the power consumption of the payload 140 may reduce the power consumption of the payload 140, which in some examples may extend the amount of time that the payload 140 may continue to operate when a power event occurs. According to some examples, adjusting the voltage reference may allow the payload 140 to continue to operate at least during the latch period. This may allow recovery from power events such as a power outage, allow the payload 140 to back up any data or functionality prior to shutdown, etc.

[0051] In some examples, the throttle offset may cause the controller 130 to determine that the payload 140 is consuming more power than the payload 140 itself. As an example, if the processor of the payload 140 is configured with a target power of 525W, and the actual power consumption is 485W, the processor of the payload 140 may increase or adjust the controller 130 up to increase the power consumption of the payload 140. In some examples, if the actual power consumption is 595W and the target power is 550W, the processor of the payload 140 may decrease or adjust the controller 130 down to reduce the power consumption of the payload 140. In some examples, the increase or decrease of the controller 130 may be determined based on the throttle offset.

[0052] By increasing or decreasing the reference voltage input to the controller 130, the payload 140 can respond to the throttling signal detected by the comparator 132 with a response time of milliseconds, rather than responding with a response time of seconds when the reference voltage is adjusted in the software of the payload 140. The software of the payload 140 may be, for example, the BMC 122. The power supply 110, the comparator 132, the sequencer 134, the offset function 136, the controller 130, and the AS IC 112 may be hardware components within the payload 140. Using hardware components within the payload 140 to create a control loop allows the control loop within the payload 140 to be a fast control loop, for example, capable of responding to a throttling signal with a response time of milliseconds.

[0053] Figure 4A An example circuit diagram of a portion of a payload is shown. As shown, circuit 400A may include hot swap controller 470, comparator 432, sequencer 434, BMC 422, controller 430, offset function 436, analog multiplier 472, and AS ICs 474-477. Multiplier 472 may be similar to multiplier 131, comparator 432 may be similar to comparator 132, sequencer 434 may be similar to sequencer 134, BMC 422 may be similar to BMC 122, controller 430 may be similar to controller 130, and offset function 436 may be similar to offset function 136.

[0054] Comparator 432 can detect a decrease in input voltage. In some examples, the decrease in input voltage can be a throttling signal. Comparator 432 can be a high-precision comparator. The high-precision comparator can be configured to detect a voltage change of approximately 4%, and in some examples, the resistor divider accuracy can be taken into account.

[0055] BMC 422 can be configured to periodically sample the status of rack-level power throttling for logging and warning. Sampling can be performed at a frequency that allows Figure 1 The system 100 detects and classifies slow performing racks to determine that rack-level power capping is occurring at the racks.

[0056] Sequencer 434 may be configured to transmit a throttle signal. The throttle signal may be a digital signal. In some examples, sequencer 434 may be configured to invert the polarity of the signal, apply one or more filters, add a delay, etc. According to some examples, sequencer 434 may be a filter configured to remove short glitches. Offset function 436 may be configured to determine a throttle offset. The throttle offset may be used to add a preset voltage to the output of multiplier 472. Adding a preset voltage to the output of multiplier 472 may cause Figure 1 The system 100 responds as if the voltage reference of the controller 430 is adjusted. Figure 4A As shown, the offset function 436 can be a separate component from the multiplier 472. In some examples, such as Figure 4B In the circuit 400A shown in the circuit diagram, the multiplier 472 may include an offset function.

[0057] like Figure 4B As shown, the sequencer can output to the Z input. The throttling offset can be determined based on the resistor-divided sequencer output to the Z input. According to some examples, the throttling amount can be a predetermined amount based on the resistor divider. Adjusting the throttling amount can include reprogramming a voltage regulator between the sequencer and the Z input. According to some examples, the voltage regulator can be a low dropout regulator.

[0058] Return to reference Figure 4A , the throttling offset may be transmitted to the controller 430. The throttling offset may be used to add a preset voltage to a voltage sensing input of the controller 430. The controller 430 may be a PWM controller. The controller 430 may adjust the output, such as PWM, to throttle the power consumption of the payload. The adjusted output may be transmitted to the ASIC 474-477.

[0059] Figure 5A and Figure 5B An example of a server system 500 is shown. Figure 5A A server system 500 is depicted that may include a data center rack 510 having a bottom 501, a top 503, side walls 506, a plurality of shelves 514a-514q for accommodating payloads, a rack monitoring unit ("RMU") 511 for monitoring the status of rack features, a plurality of payloads 550-552, and a power system 525 including a plurality of rectifiers 524 and backup batteries 509 (including battery cells 513).

[0060] In one example, payload 550 may be a dedicated storage device, for example, including any type of memory capable of storing information that can be accessed by a processor, such as a hard drive, a memory card, a ROM, a RAM, a DVD, a CD-ROM, or a solid-state memory. In another example, payload 551 may be a pre-programmed payload that draws power from the main bus to test the operation of system 500. According to some examples, one or more payloads 550-552 may be a tray. Additionally or alternatively, payloads 550-552 may be any device that generates a load. In some examples, payloads 550-552 may be any device that consumes power.

[0061] Figure 5B is an example of a rack 510 without shelves 514a-514q. Figure 5B 5, it can be seen that the rack 510 includes a main bus 534. The main bus 534 can be connected to each shelf 514a-514q of the rack 510 to provide power and data to the payload.

[0062] Figure 6 An example system 600 is shown in which the features described above and herein may be implemented. Although multiple components are shown, such components are merely non-limiting examples and other components may be included in addition or alternatively. The accompanying drawings should not be considered to limit the scope of the present disclosure or the usefulness of the features described herein. In this example, the system 600 may include a rack 610 and a payload 630.

[0063] The rack 610 may include a rack monitoring unit 611, a power system 625, and a main bus 634. The rack monitoring unit may include one or more processors 640, memory 642, instructions 644, and data 646.

[0064] Processor 640 may include any type of conventional processor, such as a commercially available microprocessor. Alternatively, one or more processors may be an application specific integrated circuit ("ASIC") or other hardware based processor. Although Figure 6 The processor, memory, and other elements of the rack 610 are functionally shown as being located within the same box, but it will be understood by those of ordinary skill in the art that the processor, computing device, or memory may actually include multiple processors, computing devices, or memories that may or may not be stored within the same physical housing. Similarly, the memory may be a hard drive or other storage medium located in a housing different from the housing of the rack 610. Therefore, references to a processor or computing device will be understood to include references to a collection of processors or computing devices or memories that may or may not operate in parallel.

[0065] The memory 642 can store information that can be accessed by the processor, including instructions 644 that can be executed by the processor 640. The memory 642 can be a type of memory that operates to store information that can be accessed by the processor 640, including non-transitory computer readable media, or other media that stores data that can be read by electronic devices, such as hard drives, memory cards, read-only memories ("ROM"), random access memories ("RAM"), optical disks, and other write-to and read-only memories. The subject matter disclosed herein can include different combinations of the foregoing, whereby different portions of the instructions 644 and data 646 are stored on different types of media.

[0066] The memory 642 can be retrieved, stored or modified by the processor 640 according to the instructions 644. For example, although the present disclosure is not limited to a specific data structure, the data 646 can be stored in a computer register, in a relational database as a table with multiple different fields and records, in an XML document, or in a flat file. The data 646 can also be formatted in a computer readable format such as, but not limited to, binary values, ASCII or Unicode. As a further example only, the data 646 can be stored as a bitmap, which includes pixels stored in a compressed or uncompressed format or various image formats (e.g., JPEG), vector-based formats (e.g., SVG) or computer instructions for drawing graphics. In addition, the data 646 can include information sufficient to identify the relevant information, such as a number, descriptive text, proprietary code, pointer, reference to data stored in other memories (including other network locations) or information used by a function to calculate the relevant data.

[0067] Instructions 644 may be any set of instructions, such as machine code, to be executed directly by processor 640, or any set of instructions, such as scripts, to be executed indirectly. In this regard, the terms "instructions," "applications," "steps," and "programs" may be used interchangeably herein. Instructions may be stored in an object code format to be processed directly by a processor, or in any other computing device language, including scripts or independent source code module collections that are interpreted on demand or compiled in advance. The functions, methods, and routines of instructions will be explained in more detail below.

[0068] The processor 640 may include a power consumption monitor that monitors the power consumption of one or more payloads 630. The power consumption monitor may detect whether the power consumption of the payload 630 exceeds a threshold power consumption. When the power consumption monitor detects that the power consumption of the payload exceeds the threshold within a predetermined time period, the processor 640, in conjunction with the power system 625, may send a throttling signal to the payload 630 via the main bus 634. The throttling signal may be, for example, a reduction in voltage. For example, the processor 640 may execute an instruction 644 to reduce the output voltage of the power system 625. The reduced output voltage may be transmitted to the payload 630 via the main bus 634. According to some examples, the reduced output voltage within a predetermined time period may be a throttling signal to the payload. According to some examples, the throttling signal may be detected by the comparator 666 and transmitted to the sequencer 664 of the payload 630.

[0069] The power system 625 may include one or more rectifiers 624 and a backup battery 609. The rectifier 624 may be connected to the main bus 634 and supply voltage and thus power the payload 630. The backup battery 609 may include one or more battery cells, such as the battery cell 513, as shown in FIG. Figure 5A The backup battery 609 can provide power in the event of an electrical event such as a power outage.

[0070] Figure 7 625. The AC power source 740 can be connected to the rectifier 624. In this example, the rectifier 624 can be an AC to DC rectifier 724, such as Figure 7 The rectifier 724 can be connected to the main bus 634 and can provide power to a payload such as Figure 5A The payloads 550-552 are shown as being powered. The payload 742 may be connected in parallel to a plurality of uninterruptible power supply units (UPS) 746. The UPS 746 may correspond to Figure 5A Battery units 513 are shown arranged on shelves 514a-514c. According to some examples, UPS 746 can constitute a backup battery power supply 509,609.

[0071] return Figure 6 , the main bus 634 can provide power and data from the rack 610 to the payload 630. Additionally or alternatively, the main bus 634 can provide data from the payload 630 to the rack 610.

[0072] The payload 630 may include one or more processors 650, memory 652, instructions 654, and data 656 that are substantially similar to the processors, memories, instructions, and data described herein with respect to the chassis 610. The payload 630 may further include a power supply 660, a controller 662, a sequencer 664, a comparator 666, and an offset function 668.

[0073] The processor 650 may include an input voltage monitor that monitors the input voltage of the power system 625 from the rack 610. The input voltage monitor may monitor the input voltage to detect a reduction in voltage. A reduction in voltage for a threshold time period may be a throttling signal. For example, if the rack monitoring unit 611 detects that the power consumption of the payload 630 has exceeded a threshold power consumption for a threshold time period, the output voltage of the power system 625 may be reduced. In an example where the default output voltage of the power system 625 is 54.5V when there is no payload from the payload 630 and the default output voltage of the power system is 53.5V when there is a full payload from the payload 630, the output voltage of the power system 625 may be reduced to 52 volts. The processor 650 of the payload 630 may detect that the input voltage has dropped to 52V, which is within a tolerance range. The processor 650 of the payload may determine that the reduction in input voltage is a throttling signal.

[0074] The comparator 666 can detect the throttling signal and transmit the throttling signal to the sequencer 664 in the payload 630. In some examples, by transmitting the throttling signal to the sequencer, a delay can be added before throttling the power consumption. For example, the sequencer can delay throttling the power consumption of the payload by a threshold period of time. Delaying throttling the power consumption of the payload by the threshold period of time can allow the rectifier to rebuild power, normalize the power consumption itself, etc. before throttling the power consumption.

[0075] According to some examples, the sequencer 664 can be configured to add a delay before throttling the power consumption of the payload 630. For example, the sequencer 664 can delay throttling the power consumption by a threshold period of time to allow the rectifier 624 to rebuild power, normalize the power consumption, etc. before the payload 630 throttles the power consumption.

[0076] In some examples, the sequencer 664 can latch the throttle signal. Latching the throttle signal can make the throttle signal valid for a predetermined time period, such as a latching period. The latching period can be maintained until the predetermined time period ends or until another control signal allows the latched throttle signal to change.

[0077] The throttle offset may be determined by the offset function 668. The throttle offset may be used to add a preset voltage to the voltage sense input of the controller 662.

[0078] The controller 662 may be configured to receive a throttle offset and a latch period. In some examples, the controller may be a PWM controller. The controller 662 may adjust an output, such as a PWM, to throttle the power consumption of the payload. The controller 662 may adjust the output based on the throttle offset and the latch period. For example, the throttle offset may cause the controller 662 to determine that the payload 630 is consuming more power than the actual power of the payload 630.

[0079] Figure 8 An example method of delaying throttling power consumption is shown. The following operations do not have to be performed in the exact order described below. Instead, the various operations may be processed in a different order or simultaneously, and operations may be added or omitted.

[0080] In block 810, an input voltage may be detected by a first payload. The first payload may be in communication with a chassis configured to output a voltage to the first payload.

[0081] In block 820, a reduction in input voltage may be determined by one or more processors of the first payload. The reduction in input voltage may be determined based on the detected input voltage. According to some examples, the reduction in input voltage may correspond to a throttling signal. The throttling signal may be transmitted to a software control loop.

[0082] According to some examples, the power throttling can be latched within a latching period. The latching period can be based on the power supply of the rack. In some examples, the latching period can correspond to a predetermined time period.

[0083] In block 830, at least one throttling offset may be determined based on the reduction in input voltage. The at least one throttling offset may be determined by a sequencer. In this example, one of the at least one throttling offset is selected. According to some examples, the throttling offset may be determined by a voltage divider.

[0084] In block 840, a voltage reference may be adjusted based on a throttling offset. Adjusting the reference voltage may include, for example, reducing power consumption of the first payload. According to some examples, the voltage reference may be monitored by a controller. The controller may be a PWM controller. In some examples, power consumption may be throttled based on the reference voltage.

[0085] Adjusting the reference voltage input to the controller may allow the payload to respond to a throttle signal in milliseconds, rather than seconds when the reference voltage is adjusted in the payload's software. Using pre-existing hardware components within the payload may create a control loop without adding additional components. The control loop created by the hardware components within the payload may provide a fast control loop, such as a control loop capable of responding to a throttle signal with a response time in milliseconds.

[0086] In some examples, by adjusting the voltage reference based on the throttling offset, the power consumption of the payload can be reduced, thereby extending the amount of time the payload can continue to operate on the backup battery instead of the rectifier. This can allow the payload to continue to operate without interruption until power is restored. In some examples, this can allow the payload to back up data or functions before shutting down after the backup battery is exhausted.

[0087] Unless otherwise stated, the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. Since these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the previous description of the embodiments should be made in an illustrative manner rather than in a manner that limits the subject matter defined by the claims. In addition, the examples described herein and the provision of clauses expressed as "such as", "including", etc. should not be interpreted as limiting the subject matter of the claims to specific examples; on the contrary, these examples are intended to illustrate only one of many possible embodiments. In addition, the same reference numerals in different figures may identify the same or similar elements.

Claims

1. A method for delaying throttling of power consumption, characterized in that: include: detecting, by one or more processors of the first payload, an input voltage; determining, by the one or more processors, a reduction in input voltage based on the detected input voltage; determining, by the one or more processors, at least one throttling offset based on the reduction in input voltage; as well as A voltage reference is adjusted, by the one or more processors, based on the determined throttling offset.

2. The method according to claim 1, characterized in that Further including: The power throttling is latched by the one or more processors during a latch period.

3. The method according to claim 2, characterized in that The latch period is based on a power supply of a rack that provides the input voltage to the first payload and corresponds to a predetermined time period.

4. The method according to claim 1, characterized in that While adjusting the voltage reference, the method further includes reducing, by the one or more processors, power consumption of the first payload.

5. The method according to claim 1, characterized in that The at least one throttle offset is determined by a sequencer.

6. The method according to claim 1, characterized in that Further including: A throttle offset of the at least one throttle offset is selected by the one or more processors.

7. The method according to claim 1, characterized in that The at least one throttling offset is determined by a voltage divider.

8. The method according to claim 1, characterized in that The reduction in input voltage corresponds to a throttling signal.

9. The method according to claim 8, characterized in that Further including: The throttling signal is transmitted by the one or more processors to a software control loop.

10. The method according to claim 1, characterized in that The voltage reference is monitored by a pulse width modulator PWM controller.

11. The method according to claim 1, characterized in that Further including: Power consumption of the first payload is throttled by the one or more processors based on the voltage reference.

12. A system for delaying throttling of power consumption, characterized in that include: One or more processors configured to: detecting the input voltage provided to the payload; determining a reduction in input voltage based on the input voltage; determining a throttling offset based on said reduction in input voltage; as well as A voltage reference is adjusted based on the determined throttling offset.

13. The system of claim 12, wherein: Further included is a sequencer including one or more processors and configured to latch the power throttling during a latch period.

14. The system of claim 13, wherein: The latch period is based on a power supply and corresponds to a predetermined time period, and The one or more processors are further configured to determine the latch period based on the power supply.

15. The system of claim 14, wherein: The power throttling is latched during the latching period to reduce the power used by the effective load.

16. The system of claim 12, wherein: When adjusting the voltage reference, the one or more processors are further configured to reduce the power consumption of the payload.

17. The system of claim 12, wherein: Further comprising a software control loop, wherein the one or more processors are further configured to transmit the throttle offset to the software control loop.

18. The system of claim 12, wherein: Further included is a controller including a power management bus.

19. One or more non-transitory computer-readable storage media, characterized in that: The one or more non-transitory computer-readable storage media encode instructions that, when executed by one or more processors of the payload, cause the one or more processors to perform operations comprising: Detect input voltage; Determine the reduction in input voltage; determining at least one throttling offset based on the reduction in input voltage; and A voltage reference is adjusted based on the determined throttling offset.

20. The one or more non-transitory computer-readable storage media of claim 19, wherein: Further comprising latching the power throttling during the latching period.

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