High-reliability MBUS host end device and working method thereof

Abstract

The invention belongs to the field of communication, and provides a high-reliability MBUS host end device and a working method thereof, and the high-reliability MBUS host end device comprises a host end receiving circuit and a host end overload protection circuit; the host end receiving circuit is formed by connecting a first receiving branch and a second receiving branch, the input end of the first receiving branch is connected to an MBUS-signal end, and the input end of the first receiving branch is further connected with a first operational amplifier. The output end of the first operational amplifier is connected with the second operational amplifier of the second receiving branch and the operational comparator respectively; the second receiving branch comprises a second operational amplifier and an operational comparator which are connected in sequence; the output end of the second operational amplifier is connected to the operational comparator through two parallel branches, the first parallel branch is formed by connecting a backward diode and a resistor in series, and the second parallel branch is formed by connecting a forward diode and a resistor in series. A pair of diodes are connected in parallel to a bypass, so that the voltage difference between the voltage after capacitance integration and the original voltage value is effectively limited all the time.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to a highly reliable MBUS host-end device and a working method thereof. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] MBUS is a master-slave communication technology for data exchange between intelligent instruments and collectors. It has the characteristics of strong anti-interference ability, long communication distance, flexible power supply mode, etc., and is widely used in data collection of various intelligent instruments. Existing MBUS host circuits usually have the disadvantages of complex and redundant circuits, fragile and slow overload response, incomplete protection functions, poor communication rate compatibility, and low meter reading success rate, which makes project equipment selection, installation and maintenance very complicated. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a highly reliable MBUS host-side device and a working method thereof. The present invention provides a host-side MBUS circuit with a simple and reliable structure, complete and flexible functions, sensitive and comprehensive protection, and good compatibility with slaves. The overload detection and protection action circuit adopts a structure directly connected with a precision operational amplifier and a relay, which has accurate judgment, rapid response, and reliable cutoff, thereby ensuring that the equipment is not damaged; there is no capacitor charging and discharging timing circuit in the MBUS transceiver circuit, and it has good compatibility with various communication rates; the single-chip microcomputer control circuit has control over the above circuits through an ingenious structure, making the equipment function flexible and efficient.

[0005] According to some embodiments, a first solution of the present invention provides a highly reliable MBUS host-side device, which adopts the following technical solution:

[0006] A highly reliable MBUS host-end device, comprising a host-end receiving circuit and a host-end overload protection circuit;

[0007] The host-side receiving circuit is composed of a first receiving branch and a second receiving branch, the input end of the first receiving branch is connected to the MBUS-signal end, the input end of the first receiving branch is also connected to the first operational amplifier, and the output end of the first operational amplifier is respectively connected to the second operational amplifier and the operational comparator of the second receiving branch; the second receiving branch includes a second operational amplifier and an operational comparator connected in sequence; the output end of the second operational amplifier is connected to the operational comparator through two parallel branches, the first parallel branch is a reverse diode connected in series with a resistor, and the second parallel branch is a forward diode connected in series with a resistor;

[0008] The input end of the overload protection circuit is also connected to the MBUS-signal end, and the MBUS-signal end is connected to the +IN / B pin of the hysteresis comparator through an input resistor, and the input resistor is also connected in parallel with a recovery circuit; the positive voltage is connected to the -IN / B pin of the hysteresis comparator through the positive resistor for comparison with the input level of the MBUS-signal end; the output end of the overload protection circuit is connected to the microprocessor to alarm for overload of the MBUS-signal end.

[0009] Furthermore, the input end of the first receiving branch is connected to the ground through two low-impedance resistors, and the two low-impedance branches are also connected in parallel with a first tantalum capacitor; one end of the first tantalum capacitor is grounded, and the other end of the first tantalum capacitor is connected to a second resistor, the second resistor is connected in parallel with the first resistor, and the first resistor is connected to the OUT / A pin of the first operational amplifier; the second resistor is also connected to the -IN / A pin of the first operational amplifier; the output end INPUT1 of the first operational amplifier is also connected between the first resistor and the OUT / A pin of the first operational amplifier.

[0010] Furthermore, the OUT / A pin of the first operational amplifier is also grounded via a first capacitor;

[0011] The +IN / A pin of the first operational amplifier is connected to a +1.5V voltage through a fourth resistor, the +VS pin of the first operational amplifier is connected to a +24V voltage, and the -VS pin of the first operational amplifier is grounded.

[0012] Further, the output terminal of the first operational amplifier is connected to the +IN / A pin of the second operational amplifier through a fifth resistor, and the OUT / A pin of the second operational amplifier outputs SIGNAL1 to the parallel branch;

[0013] A +VS pin of the second operational amplifier is connected to a +24V voltage, and a -VS pin of the second operational amplifier is grounded.

[0014] Furthermore, the output end of the first operational amplifier is connected to the 1IN+ pin of the operational comparator, and the two parallel branches are connected in parallel to the 1IN- pin of the operational comparator; the two parallel branches are connected in parallel and grounded through a tenth resistor, and the tenth resistor is also connected in parallel with a second tantalum capacitor, one end of the second tantalum capacitor is grounded, and the other end of the second tantalum capacitor is connected to the 1IN- pin of the operational comparator.

[0015] Furthermore, the 1OUT pin of the operational comparator is connected to a +3.3V voltage through a seventh resistor, and the 1OUT pin of the operational comparator is also grounded through a second capacitor.

[0016] Furthermore, the OUT / B pin of the hysteresis comparator is connected to the transistor of the operational amplifier branch through an output resistor; the +IN / B pin of the hysteresis comparator is also connected between the OUT / B pin of the hysteresis comparator and the output resistor through a signal resistor.

[0017] Furthermore, the collector of the transistor in the operational amplifier branch is connected to the microprocessor; the base of the transistor is connected to the output resistor; and the emitter of the transistor is grounded.

[0018] According to some embodiments, a second solution of the present invention provides a working method of a highly reliable MBUS host-end device, which adopts the following technical solution:

[0019] A working method of a highly reliable MBUS host-end device, comprising:

[0020] The MBUS-signal terminal is connected to the input terminal of the first receiving branch, and the first receiving branch amplifies the voltage signal of the MBUS-signal terminal to obtain a first input signal that is finally used for comparison;

[0021] The first input signal is also connected to the input end of the second operational amplifier in the second receiving branch, and the second operational amplifier generates a follow-up signal with the same potential as the input signal, and the follow-up signal passes through two parallel branches to form a second input signal that is finally compared; the first input signal and the second input signal are input to the operational comparator, and the output level is determined after the judgment of the operational comparator;

[0022] The MBUS-signal terminal is connected to the input terminal of the overload protection circuit. The overload protection circuit determines whether the voltage signal of the MBUS-signal terminal is higher than the threshold through the hysteresis comparator. When it is higher than the threshold, a signal higher than the threshold is sent to the microprocessor for alarm.

[0023] Furthermore, the first input signal and the second input signal are input to the operational comparator, and the output level is determined after the judgment of the operational comparator, specifically:

[0024] When the MBUS bus is in a silent state, the level of the MBUS-signal terminal remains stable, the first input signal formed after passing through the first receiving branch also remains stable, and the second input signal formed after passing through the first receiving branch undergoes a charging process, and the level rises. As the silent state time becomes longer, the level of the second input signal also tends to be stable, and due to the voltage drop of the diode in the parallel branch, the second input signal is slightly smaller than the first input signal, and the output of the operational comparator is a high level at this time;

[0025] When the MBUS bus signal switches from "0" to "1", the voltage of the MBUS-signal terminal increases, and the first input signal formed after passing through the first receiving branch decreases, and its level is lower than the second input signal. At this time, the output of the operational comparator is low level;

[0026] When the MBUS bus signal switches from "1" to "0", the voltage of the MBUS-signal terminal decreases, and the first input signal formed after passing through the first receiving branch increases, and its level is higher than the second input signal. At this time, the output of the operational comparator is high.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] In the present invention, the receiving circuit effectively limits the voltage difference between the voltage after capacitor integration and the original voltage value by connecting a pair of diodes in parallel in the bypass; the host-side overload protection circuit can realize automatic detection, circuit breaking and recovery of slave overload. The circuit structure in the present invention is simple, reliable, stable and efficient. The overload detection and protection action circuit adopts a structure directly connected with a precision operational amplifier and a relay, which has accurate judgment, rapid response and reliable cutting, ensuring that the equipment is not damaged; there is no capacitor charging and discharging timing circuit in the MBUS transceiver circuit, and it has good compatibility with various communication rates; the single-chip microcomputer control circuit has control over the above circuits through a clever structure, making the equipment function flexible and efficient.

[0029] The receiving circuit of the present invention adopts a structure of a pair of reverse diodes plus a resistor in parallel, one of which is responsible for charging the capacitor and the other for discharging. Since the diode itself has a voltage drop, no matter how long the charging and discharging time is, the voltage on the capacitor will always lag behind the output voltage of the current receiving amplifier circuit because it cannot be fully charged or emptied, so the selection of the resistance and capacitance values ​​becomes simple. The whole circuit has no capacitor charging and discharging timing circuit, has strong adaptability to different baud rates, and has high reliability and stability.

[0030] The overload judgment circuit of the present invention is composed of a hysteresis comparator, which directly controls the overload power-off relay through a diode amplifier circuit, has a fast response speed and reliable protection; after the overload fault is eliminated, it can be directly controlled by a single-chip microcomputer to realize automatic resetting of the overload judgment circuit; at the same time, the single-chip microcomputer also has the function of forcing the judgment circuit to enter an overload state and then forcing power off. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0032] Figure 1 is a schematic diagram of a first receiving circuit of a host-side receiving circuit in an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of a second receiving circuit of a host-side receiving circuit in an embodiment of the present invention;

[0034] Figure 3 is a diagram showing the relationship between a first received signal and a second received signal in an embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of a host-side overload protection circuit in an embodiment of the present invention;

[0036] Figure 5 Schematic diagram of a microprocessor control circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0038] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0040] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0041] Embodiment 1

[0042] This embodiment provides a highly reliable MBUS host-end device, a highly reliable MBUS host-end device including a host-end receiving circuit and a host-end overload protection circuit;

[0043] The host-side receiving circuit is composed of a first receiving branch and a second receiving branch, the input end of the first receiving branch is connected to the MBUS-signal end, the input end of the first receiving branch is also connected to the first operational amplifier U1, and the output end of the first operational amplifier U1 is respectively connected to the second operational amplifier U2 and the operational comparator U3 of the second receiving branch; the second receiving branch includes the second operational amplifier U2 and the operational comparator U3 connected in sequence; the output end of the second operational amplifier U2 is connected to the operational comparator U3 through two parallel branches, the first parallel branch is a reverse diode D1 connected in series with a resistor R8, and the second parallel branch is a forward diode D2 connected in series with a resistor R9;

[0044] The input end of the overload protection circuit is also connected to the MBUS-signal end, and the MBUS-signal end is connected to the +IN / B pin of the hysteresis comparator U4 through the input resistor R16, and the input resistor R16 is also connected in parallel with the recovery circuit OLD RST; the positive voltage +3.3V is connected to the -IN / B pin of the hysteresis comparator U4 through the positive resistor R14 to generate a reference level for comparison with the input level of the MBUS-signal end; the output end of the overload protection circuit is connected to the microprocessor U5 to alarm for overload of the MBUS-signal end.

[0045] It should be noted here that the reason for setting the recovery circuit OLD RST is that, first, during the power-on process of the whole machine, the input terminals +IN / B and -IN / B of U4 are prone to instability, which may cause the overload signal to be triggered by mistake. Therefore, during the power-on stage, the microprocessor U5 forces the +IN / B signal to be pulled low, and then released after the working state is stable. Second, when the MBUS- signal is reset, that is, when the current is zero, the voltage generated on the +IN / B pin of U4 minus the -IN / B pin voltage is less than the reset threshold voltage of U4, and the overload signal is not automatically reset. If the hysteresis comparator is to be reset, the microprocessor U5 needs to force the +IN / B signal to be pulled low.

[0046] like Figure 1 As shown, the input end of the first receiving branch is connected to the ground through two low-impedance resistors R3 and R6, and the two low-impedance branches are also connected in parallel with a first tantalum capacitor CT1; one end of the first tantalum capacitor CT1 is grounded, and the other end of the first tantalum capacitor CT1 is connected to a second resistor R2, and the second resistor R2 is connected in parallel with a first resistor R1, and the first resistor R1 is connected to the OUT / A pin of the first operational amplifier U1; the second resistor R2 is also connected to the -IN / A pin of the first operational amplifier U1; the output end INPUT1 of the first operational amplifier U1 is also connected between the first resistor R1 and the OUT / A pin of the first operational amplifier U1.

[0047] The OUT / A pin of the first operational amplifier U1 is also grounded via a first capacitor C1;

[0048] The +IN / A pin of the first operational amplifier U1 is connected to a +1.5V voltage through a fourth resistor R4 , the +VS pin of the first operational amplifier U1 is connected to a +24V voltage, and the -VS pin of the first operational amplifier U1 is grounded.

[0049] like Figure 2 As shown, the output terminal INPUT1 of the first operational amplifier U1 is connected to the +IN / A pin of the second operational amplifier U2 through the fifth resistor R5, and the OUT / A pin of the second operational amplifier U2 outputs SIGNAL1 to the parallel branch;

[0050] A +VS pin of the second operational amplifier U2 is connected to a +24V voltage, and a -VS pin of the second operational amplifier U2 is grounded.

[0051] The output terminal INPUT1 of the first operational amplifier U1 is connected to the 1IN+ pin of the operational comparator U3, and the two parallel branches are connected in parallel to the 1IN- pin of the operational comparator U3; the two parallel branches are connected in parallel and grounded through the tenth resistor R10, and the tenth resistor R10 is also connected in parallel with a second tantalum capacitor CT2, one end of the second tantalum capacitor CT2 is grounded, and the other end of the second tantalum capacitor CT2 is connected to the 1IN- pin of the operational comparator U3.

[0052] It should be noted that the value of the second tantalum capacitor CT2 is generally selected to be 2.2uF to 22uF.

[0053] The 1OUT pin of the operational comparator U3 is connected to a +3.3V voltage through a seventh resistor R7, and the 1OUT pin of the operational comparator U3 is also grounded through a second capacitor C2.

[0054] U3 is a 2-channel comparator. Only one channel is used in this schematic. The principle is to compare the levels of 1IN+ and 1IN-. If the level of 1IN+ is higher than that of 1IN-, a high level is output on the 1OUT pin, otherwise a low level is output.

[0055] The input end of the second receiving branch is also the output end of the first receiving branch, that is, the OUT / A pin of the first operational amplifier U1. The input end of the second receiving circuit is connected to the +INA pin of the second operational amplifier U2. The -IN / A pin of the second operational amplifier U2 is connected to the OUT / A pin of the second operational amplifier U2 to form a follower, so that the level of the OUT / A pin follows the level change of the +IN / A pin without affecting the +IN / A level. The OUT / A pin of the second operational amplifier U2 is connected to the diode and resistor circuit structure of the two parallel branches.

[0056] 1IN+ of the second operational amplifier U2 is connected to the output end INPUT1 of the first receiving branch, and 1IN- of the operational comparator U3 is connected to the output ends of the two parallel branches.

[0057] like Figure 4 , Figure 5 As shown, the OUT / B pin of the hysteresis comparator U4 is connected to the transistor Q1 of the operational amplifier branch through the output resistor R12; the +IN / B pin of the hysteresis comparator U4 is also connected between the OUT / B pin of the hysteresis comparator U4 and the output resistor R12 through the signal resistor R13.

[0058] The collector 3 output of the transistor Q1 in the operational amplifier branch is connected to the microprocessor; the base 1 of the transistor Q1 is connected to the output resistor R12; the emitter 2 of the transistor Q1 is grounded; and the grounding resistor R15 is connected to the positive resistor R14.

[0059] The overload protection circuit includes U4, R12, R13, R15, and R16. The difference between the hysteresis comparator U4 and the ordinary comparator is that when the ordinary comparator compares the two levels of the positive and negative inputs, when the magnitude relationship of the input levels changes, the output terminal will change immediately, which will cause the output level to jump high and low when the input levels are similar, and be in an unstable state. The characteristic of the hysteresis comparator is that the threshold design of the input level difference is added. When the difference of the input level exceeds the threshold, the output will change, avoiding the situation of unstable output.

[0060] After MBUS- is powered on, all the current will flow through the low impedance path R3-R6 to generate an input voltage signal; after the voltage signal is reversely amplified by the U1 operational amplifier (the multiple is determined by R1 and R2), the first receiving signal INPUT1 is generated; U2 acts as a follower, and its output is completely consistent with INPUT1 and will not interfere with the INPUT1 level; the output of the follower adopts a structure of a pair of reverse diodes plus resistors in parallel, one path is responsible for charging the capacitor and the other path is responsible for discharging, generating an INPUT2 signal; since the diode itself has a voltage drop, no matter how long the charging and discharging time is, the voltage on the capacitor cannot be fully charged or discharged, so the INPUT2 signal voltage value always lags behind the INPUT1 signal voltage value, and the selection of resistor and capacitor values ​​becomes simple; the entire circuit has no capacitor charging and discharging timing circuit, and is highly adaptable to different baud rates, and its reliability and stability are significantly improved.

[0061] The resistor parameters of the hysteresis comparator composed of the operational amplifier U4 should be selected to ensure that: when the current of the MBUS- signal is too large, the voltage generated on the +IN / B pin of U4 minus the voltage on the -IN / B pin is greater than the action threshold voltage of U4; when the MBUS- signal is reset, that is, the current is zero, the voltage generated on the +IN / B pin of U4 minus the voltage on the -IN / B pin is less than the reset threshold voltage of U4, ensuring that after the MBUS- signal is reset, this overload signal is not automatically reset. If you want to reset the hysteresis comparator, pull the level of the 5th pin of the microprocessor connected to U4 to GND.

[0062] Embodiment 2

[0063] This embodiment provides a working method of a highly reliable MBUS host device, including:

[0064] The MBUS-signal terminal is connected to the input terminal of the first receiving branch, and the first receiving branch amplifies the voltage signal of the MBUS-signal terminal to obtain a first input signal that is finally used for comparison;

[0065] The first input signal is also connected to the input end of the second operational amplifier in the second receiving branch, and the second operational amplifier generates a follow-up signal with the same potential as the input signal, and the follow-up signal passes through two parallel branches to form a second input signal that is finally compared; the first input signal and the second input signal are input to the operational comparator, and the output level is determined after the judgment of the operational comparator;

[0066] The MBUS-signal terminal is connected to the input terminal of the overload protection circuit. The overload protection circuit determines whether the voltage signal of the MBUS-signal terminal is higher than the threshold through the hysteresis comparator. When it is higher than the threshold, a signal higher than the threshold is sent to the microprocessor for alarm.

[0067] like Figure 3As shown, the first input signal and the second input signal are input to the operational comparator, and the output level is determined after the judgment of the operational comparator, which is specifically:

[0068] When the MBUS bus is in a silent state, the level of the MBUS-signal terminal remains stable, the first input signal formed after passing through the first receiving branch also remains stable, and the second input signal formed after passing through the first receiving branch undergoes a charging process, and the level rises. As the silent state time becomes longer, the level of the second input signal also tends to be stable, and due to the voltage drop of the diode in the parallel branch, the second input signal is slightly smaller than the first input signal, and the output of the operational comparator is a high level at this time;

[0069] When the MBUS bus signal switches from "0" to "1", the voltage of the MBUS-signal terminal increases, and the first input signal formed after passing through the first receiving branch decreases, and its level is lower than the second input signal. At this time, the output of the operational comparator is low level;

[0070] When the MBUS bus signal switches from "1" to "0", the voltage of the MBUS-signal terminal decreases, and the first input signal formed after passing through the first receiving branch increases, and its level is higher than the second input signal. At this time, the output of the operational comparator is high.

[0071] It should be noted that the characteristic of the MBUS receiving signal is that the data bit is represented by changing the current on the MBUS bus, and the way of changing is to increase the current bus current rather than generating a fixed current value. The MBUS bus maintains a stable bus current in a silent state. When a receiving signal is generated, if the data bit "1" is generated, the MBUS bus current is raised; if the data bit "0" is generated, the bus current returns to normal. This signal is connected to the receiving circuit in Example 1, and different voltages will be generated at the MBUS-end.

[0072] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A highly reliable MBUS host device, characterized in that: It includes a host-side receiving circuit and a host-side overload protection circuit; The host-side receiving circuit is composed of a first receiving branch and a second receiving branch, the input end of the first receiving branch is connected to the MBUS-signal end, the input end of the first receiving branch is also connected to the first operational amplifier, and the output end of the first operational amplifier is respectively connected to the second operational amplifier and the operational comparator of the second receiving branch; the second receiving branch includes a second operational amplifier and an operational comparator connected in sequence; the output end of the second operational amplifier is connected to the operational comparator through two parallel branches, the first parallel branch is a reverse diode connected in series with a resistor, and the second parallel branch is a forward diode connected in series with a resistor; The input end of the overload protection circuit is also connected to the MBUS-signal end, and the MBUS-signal end is connected to the +IN / B pin of the hysteresis comparator through an input resistor, and the input resistor is also connected in parallel with a recovery circuit; the positive voltage is connected to the -IN / B pin of the hysteresis comparator through the positive resistor for comparison with the input level of the MBUS-signal end; the output end of the overload protection circuit is connected to the microprocessor to alarm for overload of the MBUS-signal end.

2. A highly reliable MBUS host-end device as claimed in claim 1, characterized in that: The input end of the first receiving branch is connected to the ground through two low-impedance resistors, and the two low-impedance branches are also connected in parallel with a first tantalum capacitor; one end of the first tantalum capacitor is grounded, and the other end of the first tantalum capacitor is connected to a second resistor, the second resistor is connected in parallel with the first resistor, and the first resistor is connected to the OUT / A pin of the first operational amplifier; the second resistor is also connected to the -IN / A pin of the first operational amplifier; the output end INPUT1 of the first operational amplifier is also connected between the first resistor and the OUT / A pin of the first operational amplifier.

3. A highly reliable MBUS host-end device as claimed in claim 2, characterized in that: The OUT / A pin of the first operational amplifier is also connected to ground via a first capacitor; The +IN / A pin of the first operational amplifier is connected to a +1.5V voltage through a fourth resistor, the +VS pin of the first operational amplifier is connected to a +24V voltage, and the -VS pin of the first operational amplifier is grounded.

4. A highly reliable MBUS host-end device as claimed in claim 1, characterized in that: The output end of the first operational amplifier is connected to the +IN / A pin of the second operational amplifier through a fifth resistor, and the OUT / A pin of the second operational amplifier outputs SIGNAL1 to the parallel branch; A +VS pin of the second operational amplifier is connected to a +24V voltage, and a -VS pin of the second operational amplifier is grounded.

5. A highly reliable MBUS host-end device as claimed in claim 1, characterized in that: The output end of the first operational amplifier is connected to the 1IN+ pin of the operational comparator, and the two parallel branches are connected in parallel to the 1IN- pin of the operational comparator; the two parallel branches are connected in parallel and grounded through a tenth resistor, and the tenth resistor is also connected in parallel with a second tantalum capacitor, one end of the second tantalum capacitor is grounded, and the other end of the second tantalum capacitor is connected to the 1IN- pin of the operational comparator.

6. A highly reliable MBUS host-end device as claimed in claim 5, characterized in that: The 1OUT pin of the operational comparator is connected to a +3.3V voltage through a seventh resistor, and the 1OUT pin of the operational comparator is also grounded through a second capacitor.

7. A highly reliable MBUS host-end device as claimed in claim 1, characterized in that: The OUT / B pin of the hysteresis comparator is connected to the transistor of the operational amplifier branch through an output resistor; the +IN / B pin of the hysteresis comparator is also connected between the OUT / B pin of the hysteresis comparator and the output resistor through a signal resistor.

8. A highly reliable MBUS host-end device as claimed in claim 7, characterized in that: The collector of the triode in the operational amplifier branch is connected to the microprocessor; the base of the triode is connected to the output resistor; and the emitter of the triode is grounded.

9. A working method of a highly reliable MBUS host device, characterized in that: The MBUS-signal terminal is connected to the input terminal of the first receiving branch, and the first receiving branch amplifies the voltage signal of the MBUS-signal terminal to obtain a first input signal that is finally used for comparison; The first input signal is also connected to the input end of the second operational amplifier in the second receiving branch, and the second operational amplifier generates a follow-up signal with the same potential as the input signal, and the follow-up signal passes through two parallel branches to form a second input signal that is finally compared; the first input signal and the second input signal are input to the operational comparator, and the output level is determined after the judgment of the operational comparator; The MBUS-signal terminal is connected to the input terminal of the overload protection circuit. The overload protection circuit determines whether the voltage signal of the MBUS-signal terminal is higher than the threshold through the hysteresis comparator. When it is higher than the threshold, a signal higher than the threshold is sent to the microprocessor for alarm.

10. A working method of a highly reliable MBUS host device as claimed in claim 9, characterized in that: The first input signal and the second input signal are input to the operational comparator, and the output level is determined by the operational comparator, specifically: When the MBUS bus is in a silent state, the level of the MBUS-signal terminal remains stable, the first input signal formed after passing through the first receiving branch also remains stable, and the second input signal formed after passing through the first receiving branch undergoes a charging process, and the level rises. As the silent state time becomes longer, the level of the second input signal also tends to be stable, and due to the voltage drop of the diode in the parallel branch, the second input signal is slightly smaller than the first input signal, and the output of the operational comparator is a high level at this time; When the MBUS bus signal switches from "0" to "1", the voltage of the MBUS-signal terminal increases, and the first input signal formed after passing through the first receiving branch decreases, and its level is lower than the second input signal. At this time, the output of the operational comparator is low level; When the MBUS bus signal switches from "1" to "0", the voltage at the MBUS-signal terminal decreases, and the first input signal formed after passing through the first receiving branch increases, and its level is higher than the second input signal. At this time, the output of the operational comparator is high.

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