Port fault detection method, device and equipment of FC bus type network and medium

Abstract

The invention relates to the technical field of high-speed serial data transmission, and provides a port fault detection method, device and equipment for an FC (Fiber Channel) bus type network and a medium. Detecting a to-be-detected node port of the FC bus type network through a port detection circuit to obtain a first comparison value and a second comparison value; performing XOR processing on the first comparison value and the second comparison value based on a port detection circuit to obtain a first comprehensive result; and determining the fault type of the to-be-tested node port based on the first comprehensive result. According to the method, the unique comprehensive result is obtained through the XOR processing, so that the detection efficiency is improved, and the detection complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed serial data transmission, and in particular to a port fault detection method, device, equipment and medium for an FC bus network. Background Art

[0002] High-speed (Fiber Channel, FC) bus network is to connect all nodes on a bus, which is easy to implement, low cost, flexible wiring, and good scalability. For FC bus network, if the node port has open link, short circuit or grounding, it will directly affect the signal transmission.

[0003] In the relevant detection method, the test result is directly given by the analog circuit. However, when the line is medium or short, the echo signal of the far-end open circuit will overlap with the excitation signal, thereby changing the level of the test signal, making the output level the same as the level of other ports and indistinguishable. Therefore, in order to further distinguish them, a secondary judgment is required, which makes the detection operation complicated and inefficient. Summary of the invention

[0004] The present invention provides a port fault detection method, device, equipment and medium for an FC bus network, which are used to solve the defect in the prior art that the echo signal of a far-end open circuit overlaps with an excitation signal and requires a secondary judgment, and obtain a unique comprehensive result through XOR processing, thereby improving the detection efficiency and reducing the detection complexity.

[0005] The present invention provides a port fault detection method for an FC bus network, comprising: In the case where the FC bus network generates a periodic pulse signal; the port detection circuit detects the node port to be tested of the FC bus network to obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times; Performing an XOR process on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; Based on the first comprehensive result, a fault type of the port of the node to be tested is determined.

[0006] According to a port fault detection method for an FC bus network provided by the present invention, the fault type of the node port to be tested is determined based on the first comprehensive result, including: when the first comprehensive result is a first preset result, the node port to be tested of the FC bus network is detected by a pulse counter to obtain a pulse value measured by the pulse counter; the first preset result is used to characterize the output result of the port detection circuit detection; when the pulse value is a preset pulse value, determining that the fault type of the node port to be tested is normal; when the pulse value is not the preset pulse value, determining that the fault type of the node port to be tested is a remote open circuit.

[0007] According to a port fault detection method for an FC bus network provided by the present invention, the method of determining the fault type of the node port to be tested based on the first comprehensive result includes: when the first comprehensive result is a second preset result, determining the fault type of the node port to be tested as a far-end open circuit; the second preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is a third preset result, determining the fault type of the node port to be tested as a near-end open circuit; the third preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is a fourth preset result, determining the fault type of the node port to be tested as a far-end short circuit; the fourth preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is a fifth preset result, determining the fault type of the node port to be tested as a near-end short circuit; the fifth preset result is used to characterize the output result of the port detection circuit detection, the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result are all different output results, and different output results correspond to different fault types.

[0008] According to a port fault detection method of an FC bus network provided by the present invention, the node port to be tested includes at least two node ports to be tested, the near-end short circuit includes near-end short circuit and hanging and near-end short circuit to ground; the determination of the fault type of the node port to be tested as near-end short circuit includes: controlling the output circuit of the FC bus network to be single-tube effective, detecting the closed node port to be tested through the port detection circuit, and obtaining a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the node port to be tested is at a third level, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the node port to be tested is at a third level, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the node port to be tested is at a third level, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested and the first reference levels when the node port to be tested is at a third level, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested and the first reference levels when the node port to be tested is at a third level, and the third ... The fourth comparison value is used to characterize the comparison result between the closed node port to be tested and each of the first reference levels when the port is at a fourth level, and the third level and the fourth level are levels at different times; based on the port detection circuit, the third comparison value and the fourth comparison value are XOR-processed to obtain a second comprehensive result; when the second comprehensive result is the first preset result, it is determined that the fault type of the node port to be tested is a near-end short circuit and is suspended; when the second comprehensive result is the fifth preset result, it is determined that the fault type of the node port to be tested is a near-end short circuit to ground.

[0009] According to a port fault detection method for an FC bus network provided by the present invention, the node port to be tested includes at least two node ports to be tested, the remote short circuit includes: remote short circuit and hanging, remote short circuit to one end of the termination, remote short circuit to both ends of the termination and remote short circuit to ground; the determination that the fault type of the node port to be tested is a remote short circuit includes: controlling the output circuit of the FC bus network to be single-tube effective, detecting the closed node port to be tested by the port detection circuit, and obtaining a fifth comparison value and a sixth comparison value; the fifth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a fifth level, and the sixth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a sixth level, and the fifth level and the sixth level are levels at different times; performing XOR processing on the fifth comparison value and the sixth comparison value based on the port detection circuit to obtain a third comprehensive result; When the third comprehensive result is the first preset result, it is determined that the fault type of the node port to be tested is far-end short connection and hanging; when the third comprehensive result is the sixth preset result, it is determined that the fault type of the node port to be tested is far-end short connection to one end of the termination; the sixth preset result is used to characterize the output result of the port detection circuit; when the third comprehensive result is the seventh preset result, it is determined that the fault type of the node port to be tested is far-end short connection to both ends of the termination; the seventh preset result is used to characterize the output result of the port detection circuit, and the sixth preset result and the seventh preset result are both output results different from the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types; when the third comprehensive result is the fifth preset result, it is determined that the fault type of the node port to be tested is far-end short connection to ground.

[0010] According to a port fault detection method for an FC bus network provided by the present invention, the port detection circuit is obtained by connecting at least one comparator in parallel, the positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminal of each comparator is connected to an XOR processing unit; each numerical value in the first comparison value corresponds to the comparator one-to-one, and each numerical value in the second comparison value corresponds to the comparator one-to-one; performing XOR processing on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result includes: performing XOR processing on each numerical value in the first comparison value corresponding to the same comparator and each numerical value in the second comparison value to obtain the first comprehensive result.

[0011] According to a port fault detection method for an FC bus network provided by the present invention, the pulse counter comprises: at least one inverter and at least one trigger, the inverters are connected in series in sequence, the inverters in the last position in series are respectively connected to the triggers, the pulse counter detects the node port to be tested of the FC bus network to obtain the pulse value measured by the pulse counter, including: inputting an input signal to the inverter in the first position in series through the pulse counter, adjusting the edge of the input signal and the level waveform of the input signal to obtain a target signal; the input signal is obtained based on the periodic pulse signal; and the pulses of the target signal are counted based on the trigger to obtain the pulse value.

[0012] The present invention also provides a port fault detection device for an FC bus network, comprising: An acquisition module is used for, when the FC bus network generates a periodic pulse signal, detecting the node port to be tested of the FC bus network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times; a processing module, configured to perform an XOR process on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; A determination module is used to determine the fault type of the port of the node to be tested based on the first comprehensive result.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the port fault detection method for the FC bus network described above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the port fault detection method of the FC bus network as described in any one of the above is implemented.

[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the port fault detection method for the FC bus network described above is implemented.

[0016] The present invention provides a port fault detection method, device, equipment and medium for an FC bus network. When the FC bus network generates a periodic pulse signal, the port detection circuit is used to detect the node port to be tested of the FC bus network, and a comparison result (i.e., a first comparison value) between the node port to be tested and at least one first reference level of the node port to be tested when the node port to be tested is at a first level and a comparison result (i.e., a second comparison value) between the node port to be tested and the first reference level when the node port to be tested is at a second level is obtained, wherein the first level and the second level are levels at different times; the port detection circuit performs an XOR process on the first comparison value and the second comparison value to obtain a unique first comprehensive result, and thus the unique first comprehensive result is used to determine the fault type of the node port to be tested. In this way, the unique first comprehensive result can be used to directly determine the fault type of the node port to be tested, without the need for secondary judgment, thereby improving the efficiency of fault detection and reducing the judgment complexity of fault detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 This is one of the flow charts of the port fault detection method of the FC bus network provided by the present invention.

[0019] Figure 2 It is a schematic diagram of the periodic pulse signal (Vi) provided by the present invention.

[0020] Figure 3 Schematic diagram of the excitation signal (Vi_d) provided by the present invention.

[0021] Figure 4 It is a schematic diagram of a test signal (Vin) provided by the present invention.

[0022] Figure 5 It is a structural schematic diagram of the FC long-line bus network provided by the present invention.

[0023] Figure 6 It is a structural schematic diagram of the port detection circuit provided by the present invention.

[0024] FIG. 7A is a schematic diagram of a test waveform in a normal state provided by the present invention.

[0025] Figure 7B It is a schematic diagram of a test waveform of a near-end open circuit provided by the present invention.

[0026] Figure 7C This is one of the schematic diagrams of the test waveform of the far-end open circuit provided by the present invention.

[0027] Fig.7D This is one of the schematic diagrams of the test waveform of the far-end short circuit provided by the present invention.

[0028] Fig. 7E It is a schematic diagram of the test waveform of the near-end short circuit provided by the present invention.

[0029] Fig. 8A This is the second schematic diagram of the test waveform of the far-end open circuit provided by the present invention.

[0030] Figure 8B This is the second schematic diagram of the test waveform of the far-end short circuit provided by the present invention.

[0031] Fig. 9 The present invention provides a schematic diagram of a serial interface transceiver output circuit.

[0032] Fig.10 It is a structural schematic diagram of the pulse counter provided by the present invention.

[0033] Fig.11 It is a schematic diagram of the reset signal (Reset) provided by the present invention.

[0034] Fig. 12A This is the second flow chart of the port fault detection method of the FC bus network provided by the present invention.

[0035] Fig. 12B This is the third flow chart of the port fault detection method for the FC bus network provided by the present invention.

[0036] Fig.13 It is a structural schematic diagram of a port fault detection device for an FC bus network provided by the present invention.

[0037] Fig.14 It is a structural schematic diagram of the electronic device provided by the present invention.

[0038] Reference numerals: 210: high-speed node; 220: first directional coupler; 230: second directional coupler; 1001: first inverter; 1002: second inverter; 1003: first D flip-flop; 1004: second D flip-flop; 1005: third inverter. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] At present, the node ports of FC bus networks need to be tested. Traditional methods mainly include the following: one is manual detection, that is, when an error occurs during the communication process, an additional tester is used to perform open and short circuit detection, which is not only cumbersome but also inefficient; the other is online automatic detection: However, there are incomplete test items, such as the inability to distinguish between short-circuit suspension, short-circuit termination and short-circuit grounding, resulting in the need for manual secondary analysis of the test results.

[0041] With the development of technology, a method for detecting near and far ports of long-line high-speed bus-type nodes has been proposed, which uses analog circuits to directly give test results. However, this method has the following shortcomings during testing: one is that when the line is a medium or short line, the echo signal of the far-end open circuit will overlap with the excitation signal, thereby changing the level of the test signal, making the output level the same as the level of other ports. Therefore, in order to further distinguish, a secondary judgment is required; the other is that when the line is a long line, the echo signal of the far-end open circuit does not overlap with the excitation signal. In order to distinguish it from the normal situation of the port, pulse number statistics are required at this time. The traditional method is to use analog-to-digital converter (ADC) sampling and then make judgments in the digital domain. The ADC circuit is added additionally, and the sampling period must be less than the pulse width of the excitation signal, otherwise the echo signal is easily missed. The power consumption of the ADC is positively correlated with the sampling frequency, so the power consumption of the circuit is increased.

[0042] Based on the above problems, the present invention provides a port fault detection method for an FC bus network. The fault type of the port of the node to be tested can be directly determined by using a unique first comprehensive result without the need for secondary judgment, thereby improving the efficiency of fault detection and reducing the complexity of fault detection judgment.

[0043] Combine the following Figure 1-Figure 1 2 describes the port fault detection method of the FC bus type network of the present invention. The execution subject of the method can be an electronic device, or it can be a port fault detection method of the FC bus type network set in the electronic device. The port fault detection of the FC bus type network can be implemented by software, hardware or a combination of the two.

[0044] Figure 1 FIG. 1 is one of the flow charts of the port fault detection method of the FC bus network provided by the present invention, such as Figure 1 As shown, the method includes the following: Step 101: When the FC bus network generates a periodic pulse signal, a port detection circuit is used to detect a node port to be detected in the FC bus network to obtain a first comparison value and a second comparison value. Among them, the first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times.

[0045] Here, the number of the port detection circuits may be two, and the number of the node ports to be tested may also be two, such as a P port and an n port, wherein one port detection circuit detects the P port, and the other port detection circuit detects the n port.

[0046] For example, Figure 2 is a schematic diagram of the periodic pulse signal (Vi) provided by the present invention, such as Figure 2 As shown, T0 is the period of the periodic pulse signal (Vi); T0-T1 is the pulse width; T1 is the duration of the low level of the pulse. Here, in order to ensure that the delay time Td of the return signal of the periodic pulse signal does not overlap with the next periodic signal T0, T0 can be much larger than T1, for example, T0 is 10 times T1.

[0047] It should be noted that the excitation signal is obtained after the periodic pulse signal is delayed.

[0048] For example, Figure 3 is a schematic diagram of the excitation signal (Vi_d) provided by the present invention, such as Figure 3 As shown, the excitation signal (Vi_d) is obtained by delaying the periodic pulse signal (Vi) by Td0 (Td0>T1), where T1 is the pulse width of the excitation signal.

[0049] It should be noted that the first level and the second level may be the same or different.

[0050] It should be noted that if the first level or the second level is greater than the first reference level, the comparison result is 1; if the first level or the second level is less than the first reference level, the comparison result is 0. A comparison value includes multiple comparison results, and the number of comparison results is the same as the number of first reference levels. For example, the comparison value is 01110, indicating that there are 5 reference levels.

[0051] Here, the first reference level can be a preset appropriate level. For example, the first reference level ref1 is Vref - 0.25×V0, the second reference level ref2 is Vref + v3, the third reference level ref3 is Vref + v2, the fourth reference level ref4 is Vref + v1, and the fifth reference level ref5 is Vref + 1.5×V0. Here, 0 < v3 < V03 < v2 < V02 < v1 < V01 < V0, and from ref1 to ref5, their corresponding values increase gradually.

[0052] It should be noted that the port detection circuit detects the port of the node to be tested, essentially by detecting the level of the test signal on the port of the node to be tested. The first level can be the high level of the test signal, and the second level can be the low level of the test signal. Among them, the test signal can be obtained after the serial interface transceiver processes the excitation signal.

[0053] Exemplarily, Figure 4 is a schematic diagram of a test signal (Vin) provided by the present invention. As Figure 4 shown, the low level of the test signal (Vin) is Vref (reference level), the high level is Vref + V0, V0 is the auxiliary voltage, T1 is the pulse width of the test signal, and Td is the delay of the test signal.

[0054] The first level and the second level can be adjacent levels. For example, the first level is the high level at the first moment, and the second level is the low level at the second moment.

[0055] Here, the exclusive - OR operation is a logical operation, where the result is 0 for the same values and 1 for different values.

[0056] Figure 5 is a schematic structural diagram of the FC long - line bus - type network provided by the present invention. As Figure 5 shown, the high - speed node 210 is connected to the first directional coupler 220 and the second directional coupler 230 through differential cables Lp / Ln, and finally accesses the differential bus - type network (corresponding to bus p and bus n in the figure). Among them, the high - speed node 210 uses time - division multiplexing, that is, the working type of the transceiver of the bus - type network (also known as the high - speed serial transceiver) is the time - division multiplexing type. For the differential ports p / n, the reception is always connected, and the transmission is selected to be connected or disconnected according to the instruction through switches T11 / T12. For the high - speed serial transceiver, Figure 5Ports 7 and 8 are receiving ports, both with high input impedance, C11 / C12 isolates input bias, and uses R11 / R12 for input matching. Ports 5 and 6 are transmitting ports, both with open-drain outputs, using R11 / R12 for output matching, R11 and R12 are connected through VDD to provide power for ports 5 and 6. C13 / C14 is connected to port p / n through a DC blocking capacitor. Port p / n is connected to port 3 (coupling port) of directional coupler D1 / D2 through differential cables Lp / Ln. C15 / C16 is connected to the signal end of R11 / R12 through a DC blocking capacitor. So far, C13 / C14 and C15 / C16 isolate DC for test point vp / vn, and the DC of vp / vn is provided by Vref through bias resistors R15 / R16. C17 / C18 is connected to the signal 1 port of pulse counter 1 / pulse counter 2 through a DC blocking capacitor, and the other end is connected to the test point vp / vn. The DC of the signal 1 port of pulse counter 1 / pulse counter 2 is provided by Vbias through bias resistors R17 / R18 to ensure that the signal is within the amplitude input range of the pulse counter. The signal 2 port of pulse counter 1 / pulse counter 2 is the recovery port (reset), the signal 3 port of pulse counter 1 is the first clock pulse input port (Operation Pulse. OPP1), and the signal 4 port of pulse counter 1 is the second clock pulse input port (Operation Pulse. OPP2), the signal port 3 of the pulse counter 2 is the first enable port (onn1), the signal port 4 of the pulse counter 2 is the second enable port (onn2), Tx_rp indicates that the port 1 of the digital controller sends a certain parameter, protocol or port to the port 1 of the high-speed serial transceiver, Tx_rn indicates that the port 2 of the digital controller sends a certain device, network, protocol or function to the port 2 of the high-speed serial transceiver, Rx_rp indicates that the port 3 of the digital controller receives a certain parameter, protocol or port sent by the port 3 of the high-speed serial transceiver, and Tx_rn indicates that the port 4 of the digital controller receives a certain device, network, protocol or function sent by the port 4 of the high-speed serial transceiver. TX_P and TX_N indicate that the high-speed serial transceiver sends signals to port detection circuit 1 and port detection circuit 2 through port 5 and port 6 respectively, RX_P and RX_N indicate that the high-speed serial transceiver receives signals sent by port detection circuit 1 and port detection circuit 2 through port 7 and port 8 respectively, op1-op5 in port detection circuit 1 represent 5 clock pulse input ports, on1-on5 in port detection circuit 2 represent 5 enable ports, port p is the first node port to be tested, and port n is the first node port to be tested.

[0057] Step 102: Perform an XOR process on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result.

[0058] It should be noted that the first comparison value and the second comparison value are obtained by a plurality of comparators in the port detection circuit, and the number of the comparators corresponds to the number of the first reference levels one by one.

[0059] Exemplarily, the port detection circuit is obtained by connecting at least one comparator in parallel, the positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminal of each comparator is connected to an XOR processing unit; each numerical value in the first comparison value corresponds one-to-one to the comparator, and each numerical value in the second comparison value corresponds one-to-one to the comparator; the first comparison value and the second comparison value are XOR-processed based on the port detection circuit to obtain a first comprehensive result, including: each numerical value in the first comparison value corresponding to the same comparator is XOR-processed with each numerical value in the second comparison value to obtain the first comprehensive result.

[0060] It should be noted that the first numerical value and the second digital value obtained by each comparator need to be XORed one by one. For example, if the first comparison value is 01110 and the second comparison value is 11100, the first comprehensive result after XORing is 10010.

[0061] For example, Figure 6 is a schematic diagram of the structure of the port detection circuit provided by the present invention, such as Figure 6 As shown, the port detection circuit includes five comparators, the negative ends of the five comparators are connected to the level ref1 / ref2 / ref3 / ref4 / ref5 respectively, port 1 is the signal input end connected to the positive end of the comparator, that is, the signal input end, the outputs of comparators 1 / 2 / 3 / 4 / 5 are output ports 2 / 3 / 4 / 5 / 6 respectively, and the output ends of comparators 1, 2, 3, 4 and 5 (corresponding to ports 2, 3, 4, 5 and 6 in the figure) are used to output the comparison results. It should be noted that Vref can also flow into the detection circuit through R15. Among them, the first comparison value or the second comparison value of the detection circuit can be composed of the five-bit potential value (i.e., numerical value) outputted by ports 2, 3, 4, 5 and 6 respectively. Each comparator is connected to a delay unit, each delay unit is connected to an XOR unit, and the delay unit is used for each XOR unit to XOR the first comparison result and the second comparison result of the corresponding comparator to obtain the first comprehensive result.

[0062] further, Figure 5Two port detection circuits are shown, namely port detection circuit 1 and port detection circuit 2. Port 1 of port detection circuit 1 is connected to the common point of C13 and C15, and port 1 of port detection circuit 2 is connected to the common point of C14 and C16.

[0063] In one embodiment, the matching circuit load resistance corresponding to the FC bus network can be Figure 5 R11, R12, R13, and R14 are all equal, that is, R11=R12=R13=R14=R.

[0064] In another embodiment, let V0=R×I, where I is the current value of the tail current source M1. Taking the first reference level of ref1-ref5 as an example, ref1 is Vref-0.25×V0, ref2 is Vref+v3, ref3= is Vref+v2, ref4 is Vref+v1, ref5 is Vref+1.5×V0, and Table 1 is obtained through the port detection circuit. Table 1 is the first comprehensive result of the port detection of the node to be tested: Table 1

[0065] In Table 1, the highest level of the port signal is the first level, the first level is Vref+V0, Vref+V0 is compared with ref1-ref5 to obtain a first comparison value of 01111, the lowest level of the port signal is the second level, the second level is Vref, Vref is compared with ref1-ref5 to obtain a second comparison value of 00001, 01111 and 00001 are XORed to obtain a first comprehensive result of 01110; the first level is Vref+2×V0, Vref+2×V0 is compared with ref1-ref5 to obtain a first comparison value of 11111, the second level is Vref, Vref is compared with ref1-ref5 to obtain a second comparison value of 00001, 11111 and 00001 are XORed to obtain a first comprehensive result of 11110. Similarly, other first comprehensive results are obtained by XORing the first comparison value and the second comparison value.

[0066] For example, Fig. 7A is a schematic diagram of the test waveform of the normal state provided by the present invention, such as Fig. 7A As shown, T0 is the period of the normal state level signal, Vref is the lowest level, Vref+V0 is the highest level, and there is one waveform in one period.

[0067] Figure 7B Schematic diagram of the test waveform of the near-end open circuit provided by the present invention, such as Figure 7B As shown, Vref is the lowest level and Vref+2V0 is the highest level.

[0068] Figure 7C is one of the schematic diagrams of the test waveform of the far-end open circuit provided by the present invention, such as Figure 7C As shown, Vref is the lowest level, Vref+V0 is the highest level, and there are two waveforms in one cycle.

[0069] Fig.7D is one of the schematic diagrams of the test waveform of the far-end short circuit provided by the present invention, such as Fig.7D As shown, Vref+V0 is the highest level, Vref is the middle level, and Vref-V0 is the lowest level.

[0070] Fig. 7E is a schematic diagram of the test waveform of the near-end short circuit provided by the present invention, such as Fig. 7E As shown, the level of the near-end short-circuit waveform is always Vref.

[0071] In the embodiment of the present invention, an XOR operation is performed on adjacent levels to obtain a unique comprehensive result, which can directly distinguish various situations of the port without secondary judgment.

[0072] Step 103: Determine the fault type of the port of the node to be tested based on the first comprehensive result.

[0073] It should be noted that the first comprehensive result needs to be combined with a mapping relationship to determine the fault type of the port of the node to be tested. The mapping relationship table is a preset correspondence between the first comprehensive result and the fault type.

[0074] Exemplary. The above Table 1 may be a mapping relationship, wherein if the first comprehensive result is 01110, the port of the node to be tested is normal or the far end is open; if the first comprehensive result is 11110, the near end of the port of the node to be tested is open; if the first comprehensive result is 00000, the near end of the port of the node to be tested is short-circuited; if the first comprehensive result is 00001, the far end of the port of the node to be tested is short-circuited.

[0075] It should be noted that the far end is the coupling port corresponding to the node port to be tested, and the near end is the node port to be tested. Therefore, a near-end open circuit means that the node port to be tested is open, a near-end short circuit means that the node port to be tested is short-circuited, and a far-end open circuit means that the coupling port corresponding to the node port to be tested is open, and a far-end short circuit means that the coupling port corresponding to the node port to be tested is short-circuited.

[0076] Table 2 is a corresponding relationship table of the first comprehensive result and the fault type of the short-line bus network in FC. If the first comprehensive result is 10000, the remote end of the port of the node to be tested is open.

[0077] Table 2

[0078] For example, Fig. 8A This is a second schematic diagram of the test waveform of the remote open circuit provided by the present invention, such as Fig. 8A As shown, Vref+2×V0 is the highest level, Vref+V0 is the middle level, Vref is the lowest level, and the time relationship is T2+T3=T1, 0= <T2<=T1,0=<T3<=T1; Figure 8B This is a second schematic diagram of the test waveform of the far-end short circuit provided by the present invention, such as Figure 8B As shown, Vref+V0 is the highest level, Vref is the middle level, and Vref-V1 is the lowest level. The time relationship is T4+T5=T1, 0= <T4<=T1,0=<T5<=T1。

[0079] Further, the fault type of the node port to be tested is determined based on the first comprehensive result, including: when the first comprehensive result is a first preset result, detecting the node port to be tested of the FC bus network by a pulse counter to obtain a pulse value measured by the pulse counter; the first preset result is used to characterize the output result of the port detection circuit detection; when the pulse value is a preset pulse value, determining that the fault type of the node port to be tested is normal; when the pulse value is not the preset pulse value, determining that the fault type of the node port to be tested is a remote open circuit.

[0080] Here, the first preset result can be understood as a preset result set in a preset mapping relationship.

[0081] According to Table 1 above, when the first comprehensive result is 01110, the port of the node to be tested may be normal or remotely open. Therefore, the pulse value is required for judgment. When the pulse value is 01, the port of the node to be tested is normal, otherwise the port of the node to be tested is remotely open.

[0082] Furthermore, the pulse counter includes: at least one inverter and at least one trigger, the inverters are connected in series in sequence, the inverter in the last position in series is connected to each of the triggers respectively, and the pulse counter detects the node port to be tested of the FC bus network to obtain the pulse value measured by the pulse counter, including: inputting the input signal to the inverter in the first position in series through the pulse counter, adjusting the edge of the input signal and the level waveform of the input signal to obtain the target signal; the input signal is obtained based on the periodic pulse signal; and the pulse value is obtained by counting the pulses of the target signal based on the trigger.

[0083] Here, the input signal may be a test signal, and the test signal may be a signal obtained after the serial interface transceiver outputs it.

[0084] For example, Fig. 9 Schematic diagram of a serial interface transceiver output circuit provided by the present invention, such as Fig. 9 As shown, M1 is the tail current tube, vb is the bias voltage, which ensures that M1 works in the saturation region, M2 and M3 are differential input tubes of the same size, vin and vip are input signals, M4 and M5 are output tubes of the same size, vc1 and vc2 are control voltages, vc1 ensures that M4 works in the saturation region, and GND represents grounding.

[0085] For example, Fig.10 Schematic diagram of the structure of the pulse counter provided by the present invention, such as Fig.10 As shown, the pulse counter includes a first inverter 1001, a second inverter 1002, a first D flip-flop 1003 and a second D flip-flop 1004. The pulse input signal Vin is shaped by the first inverter 1001 and the second inverter 1002 to realize edge and level waveform shaping. The first D flip-flop 1003 and the second D flip-flop 1004 are used to count pulses, wherein: Fig.10 Q1 in the figure represents the output of the first D flip-flop 1003, Q2 represents the output of the second D flip-flop 1004, the D port in the first D flip-flop 1003 and the second D flip-flop 1004 represents the data input port, the C port represents the clock input port, -Q represents the complement output port of the Q1 port and the Q2 port, and the R port generally represents the reset input port. In addition, Fig.10 The 2nd port of the pulse counter in is the periodic pulse signal Vi, and the reset signal Reset generated after passing through the third inverter 1005 is a high-level reset. Since Td0>T1, the counter is fully reset before the signal pulse comes. Since T0 is 10 times T1, it is ensured that the echo pulse is fully counted before being reset. In the T0 period, Vin is a pulse input signal, and the output of the pulse counter 3 / 4 port is 01. When Vin is two pulses, the output of the pulse counter 3 / 4 port is 10.

[0086] For example, Fig.11 is a schematic diagram of the reset signal (Reset) provided by the present invention, such as Fig.11 As shown, T1 is the pulse width.

[0087] In the embodiment of the present invention, a pulse counter is added to work only at the signal edge of the test signal, which greatly reduces the working time of the signal edge and saves power consumption. When the echo signal and the excitation signal do not overlap, the state of the port of the node to be tested can be successfully judged at one time. At the same time, the pulse technology is introduced so that the detection of the port of the node to be tested is carried out in the analog domain, without introducing ADC conversion and requiring secondary judgment in the digital domain. Therefore, it is fast, direct, simple and effective.

[0088] In another embodiment, the determining of the fault type of the node port to be tested based on the first comprehensive result includes: when the first comprehensive result is the second preset result, determining that the fault type of the node port to be tested is a far-end open circuit; the second preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is the third preset result, determining that the fault type of the node port to be tested is a near-end open circuit; the third preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is the fourth preset result, determining that the fault type of the node port to be tested is a far-end short circuit; the fourth preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is the fifth preset result, determining that the fault type of the node port to be tested is a near-end short circuit; the fifth preset result is used to characterize the output result of the port detection circuit detection, the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result are all different output results, and different output results correspond to different fault types.

[0089] In the embodiment of the present invention, the port status is intelligently and automatically determined according to the first comprehensive result, and a complete process of port detection of a high-speed bus-type node is provided.

[0090] It should be noted that when there are at least two node ports to be tested in the FC bus network, multiple node port short fault types to be tested may occur. The following is a further classification of multiple node port short fault types to be tested.

[0091] In one embodiment, the node port to be tested includes at least two node ports to be tested, and the proximal end short circuit includes proximal ends being shorted to each other and suspended and proximal ends being shorted to ground; and determining that the fault type of the node port to be tested is a proximal end short circuit includes: The output circuit of the FC bus network is controlled to be single-tube effective, and the closed node port to be tested is detected by the port detection circuit to obtain a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a third level, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a fourth level, and the third level and the fourth level are levels at different times; Performing an XOR process on the third comparison value and the fourth comparison value based on the port detection circuit to obtain a second comprehensive result; When the second comprehensive result is the first preset result, determining that the fault type of the node port to be tested is near-end short and hanging; When the second comprehensive result is the fifth preset result, it is determined that the fault type of the port of the node to be tested is a near-end short to ground.

[0092] In another embodiment, the node port to be tested includes at least two node ports to be tested, and the remote short circuit includes: the remote ends are shorted to each other and suspended, the remote ends are shorted to one end of the terminal, the remote ends are shorted to both ends of the terminal, and the remote ends are shorted to the ground; The step of determining that the fault type of the port of the node to be tested is a remote short circuit includes: The output circuit of the FC bus network is controlled to be single-tube effective, and the closed node port to be tested is detected by the port detection circuit to obtain a fifth comparison value and a sixth comparison value; the fifth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a fifth level, and the sixth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a sixth level, and the fifth level and the sixth level are levels at different times; Performing an XOR process on the fifth comparison value and the sixth comparison value based on the port detection circuit to obtain a third comprehensive result; When the third comprehensive result is the first preset result, determining that the fault type of the node port to be tested is a far-end short circuit and hanging; In the case where the third comprehensive result is the sixth preset result, determining that the fault type of the port of the node to be tested is a far-end short to a termination end; the sixth preset result is used to characterize the output result of the port detection circuit; In the case where the third comprehensive result is the seventh preset result, it is determined that the fault type of the port of the node to be tested is a far-end short to both ends of the termination; the seventh preset result is used to characterize the output result of the port detection circuit, the sixth preset result and the seventh preset result are both output results different from the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types; When the third comprehensive result is the fifth preset result, it is determined that the fault type of the port of the node to be tested is a far-end short to ground.

[0093] In one embodiment, when it is determined that multiple ports of the nodes to be tested are short-circuited, the output circuit of the chip (ie, the serial interface transceiver) selects a single tube to be effective, such as selecting Figure 5 The output of the middle p channel (port 5) is valid.

[0094] When it is determined that multiple ports of the tested nodes are short-circuited, Fig. 9 In the middle, switch T1 is turned on and switch T2 is turned off. At this time, vc2 = GND and M5 is turned off. Fig. 9 It can be seen that the current of M1 only enters and exits from port 5. The AC equivalent circuit is as follows Figure 7A-7B As shown, the terminating resistor is the input impedance R of the directional coupler port 3. It can be seen that the number of parallel loads R is different in different situations, so the high level and low level are also different. According to the comparison reference values ​​of ref1 / ref2 / ref3 / ref4 / ref5 in the first item, we detect the high level, and the second and third comprehensive results are shown in Table 3: Table 3

[0095] In Table 3, the closed port can be Figure 5 The port N in the shutdown end signal may be the third level or the fifth level, the shutdown end signal may be the fourth level or the sixth level, the comprehensive result may be the second comprehensive result or the third comprehensive result, and the port state is the fault type, wherein Table 3 may be a mapping relationship between the second comprehensive result and the fault type, and a mapping relationship between the third comprehensive result and the fault type.

[0096] In the embodiment of the present invention, when a differential short circuit occurs, it is possible to further distinguish details such as the far end or the near end, whether the short circuit point is grounded or suspended, and accurately locate the fault.

[0097] In the embodiment of the present invention, when the FC bus network generates a periodic pulse signal, the port detection circuit is used to detect the node port to be tested of the FC bus network, and the comparison result (i.e., the first comparison value) between the node port to be tested and at least one first reference level of the node port to be tested when the node port to be tested is at a first level and the comparison result (the second comparison value) between the node port to be tested and the first reference level when the node port to be tested is at a second level are obtained, and the first level and the second level are levels at different times; the first comparison value and the second comparison value are XOR-processed by the port detection circuit to obtain a unique first comprehensive result, so as to determine the fault type of the node port to be tested by using the unique first comprehensive result. In this way, the fault type of the node port to be tested can be directly determined by using the unique first comprehensive result, without the need for secondary judgment, thereby improving the efficiency of fault detection and reducing the judgment complexity of fault detection.

[0098] The following is an application scenario of the port fault detection method of the FC bus network provided by the present invention, wherein the port P of the node to be tested and the port N of the node to be tested are included, the detection circuit 1 detects the port P of the node to be tested, the detection circuit 2 detects the port N of the node to be tested, and the detection circuit 1 and the detection circuit 2 are Figure 6 The detection circuit and the pulse counter are shown in FIG8 .

[0099] Fig. 12A FIG. 2 is a flow chart of a method for detecting port failures in a FC bus network provided by the present invention. Fig. 12A As shown, including: Step 1201: The chip sends a periodic pulse signal with a period of T0.

[0100] Step 1202, determine whether the detection circuit 1 outputs 10000, if so, execute step 1203; determine whether the detection circuit 1 outputs 01110, if so, execute step 1204; determine whether the detection circuit 1 outputs 11110, if so, execute step 1206; determine whether the detection circuit 1 outputs 00001, if so, execute step 1207; determine whether the detection circuit 2 outputs 00001, if so, execute step 1209.

[0101] Step 1203: Determine whether the P port is remotely open.

[0102] Step 1204, determine whether pulse counter 1 outputs 01, if so, execute step 1205; otherwise, execute step 1203.

[0103] Step 1205: Determine whether the P port is normal.

[0104] Step 1206: Determine whether the near end of the P port is open.

[0105] Step 1207 , determine that the P port is far short-circuited, and execute step 1208 .

[0106] Step 1208, determine whether the detection circuit 2 outputs 00001, if so, execute step 1211; otherwise, execute step 1212.

[0107] Step 1209, determine that the N port is far short-circuited, and execute step 1210; Step 1210, determine whether the detection circuit 1 outputs 00001, if so, execute step 1211; otherwise, execute step 1213.

[0108] Step 1211, the chip sends a pulse differential signal with a period of T0, the output circuit of the chip selects single tube to be valid, and executes step 1214.

[0109] Here, for example, the output of port 5 is valid, at which time detection circuit 1 tests the output terminal, and detection circuit 2 tests the shutdown terminal.

[0110] Step 1212: Determine whether the far end of the P port is short-circuited to ground.

[0111] Step 1213: Determine whether the far end of the N port is short-circuited to ground.

[0112] Step 1214, determine whether the detection circuit 2 outputs 01110, if yes, execute step 1215; determine whether the detection circuit 2 outputs 00110, if yes, execute step 1216; determine whether the detection circuit 2 outputs 00010, if yes, execute step 1217; determine whether the detection circuit 2 outputs 00000, if yes, execute step 1218; Step 1215: Determine that the far end is short and suspended.

[0113] Step 1216: Determine whether the far end is shorted to a termination end.

[0114] Step 1217: Determine whether the far-end short circuit is terminated at both ends.

[0115] Step 1218: Determine whether the far end is shorted to ground.

[0116] Fig. 12B FIG. 3 is a flow chart of a method for detecting port failures in a FC bus network provided by the present invention. Fig. 12B As shown, including: Step 1219, determine whether detection circuit 1 outputs 00000, if so, execute step 1220; determine whether detection circuit 2 outputs 00000, if so, execute step 1227; determine whether detection circuit 2 outputs 11110, if so, execute step 1230; determine whether detection circuit 2 outputs 01110, if so, execute step 1231; determine whether the output is 10000, if so, execute step 1233.

[0117] It should be noted that the judgment in step 1219 is performed after the pulse differential signal is sent in step 1201.

[0118] Step 1220 , determine that the P terminal is short-circuited near the end, and execute step 1221 .

[0119] Step 1221, determine whether the detection circuit 2 outputs 00000, if so, execute step 1222; otherwise, execute step 1223.

[0120] Step 1222, the chip sends a pulse differential signal with a period of T0, the output circuit of the chip selects single tube to be valid, and executes step 1224.

[0121] Step 1223: Determine that the near end of the P port is short-circuited to ground.

[0122] Step 1224, determine whether the detection circuit 2 outputs 01110, if so, execute step 1225; determine whether the detection circuit 2 outputs 00000, if so, execute step 1226; Step 1225: Determine that the near ends are short and suspended.

[0123] Step 1226: Determine whether the near-end short circuit is to ground.

[0124] Step 1227 , determine that the N port near-end is short-circuited, and execute step 1228 .

[0125] Step 1228, determine whether the detection circuit 1 outputs 00000, if so, execute step 1222; otherwise, execute step 1229.

[0126] Step 1229: Determine whether the near end of the N port is short-circuited to ground.

[0127] Step 1230: Determine whether the near end of the N port is open.

[0128] Step 1231, determine whether pulse counter 2 outputs 01, if so, execute step 1232; otherwise, execute step 1233.

[0129] Step 1232: Determine whether the N port is normal.

[0130] Step 1233: Determine whether the far end of the N port is open.

[0131] The port fault detection device for a FC bus type network provided by the present invention is described below. The port fault detection device for a FC bus type network described below and the port fault detection method for a FC bus type network described above can be referred to each other.

[0132] Fig.13 FIG. 1 is a schematic diagram of the structure of a port fault detection device for an FC bus network provided by the present invention. Fig.13 As shown, the port fault detection device 1300 of the FC bus network includes: The acquisition module 1301 is used for, when the FC bus network generates a periodic pulse signal, detecting the node port to be tested of the FC bus network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times; A processing module 1302 is used to perform an XOR process on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; The determination module 1303 is used to determine the fault type of the port of the node to be tested based on the first comprehensive result.

[0133] In some embodiments, the determination module 1303 is specifically used to: when the first comprehensive result is a first preset result, detect the node port to be tested of the FC bus network through a pulse counter to obtain the pulse value measured by the pulse counter; the first preset result is used to characterize the output result of the port detection circuit detection; when the pulse value is a preset pulse value, determine that the fault type of the node port to be tested is normal; when the pulse value is not the preset pulse value, determine that the fault type of the node port to be tested is a remote open circuit.

[0134] In some embodiments, the determination module 1303 is further specifically used to: when the first comprehensive result is the second preset result, determine that the fault type of the node port to be tested is a far-end open circuit; the second preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is the third preset result, determine that the fault type of the node port to be tested is a near-end open circuit; the third preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is the fourth preset result, determine that the fault type of the node port to be tested is a far-end short circuit; the fourth preset result is used to characterize the output result of the port detection circuit detection; when the first comprehensive result is the fifth preset result, determine that the fault type of the node port to be tested is a near-end short circuit; the fifth preset result is used to characterize the output result of the port detection circuit detection, and the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result are all different output results, and different output results correspond to different fault types.

[0135] In some embodiments, the node port to be tested includes at least two node ports to be tested, and the near-end short circuit includes near-end short circuit and hanging and near-end short circuit to ground; the determination module 1303 is also specifically used to: determine that the fault type of the node port to be tested is a near-end short circuit, including: controlling the output circuit of the FC bus network to be single-tube effective, detecting the closed node port to be tested through the port detection circuit, and obtaining a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed node port to be tested when it is at a third level and each of the first reference levels, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested when it is at a fourth level and each of the first reference levels, and the third level and the fourth level are levels at different times; based on the port detection circuit, the third comparison value and the fourth comparison value are XOR-processed to obtain a second comprehensive result; when the second comprehensive result is the first preset result, determine that the fault type of the node port to be tested is near-end short circuit and hanging; when the second comprehensive result is the fifth preset result, determine that the fault type of the node port to be tested is near-end short circuit to ground.

[0136] In some embodiments, the node port to be tested includes at least two node ports to be tested, and the remote short circuit includes: remote short circuit and hanging, remote short circuit to one end of the termination, remote short circuit to both ends of the termination and remote short circuit to ground; the determination module 1303 is also specifically used to: determine that the fault type of the node port to be tested is a remote short circuit, including: controlling the output circuit of the FC bus network to be single-tube effective, detecting the closed node port to be tested through the port detection circuit, and obtaining a fifth comparison value and a sixth comparison value; the fifth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when it is at a fifth level, and the sixth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when it is at a sixth level, and the fifth level and the sixth level are levels at different times; based on the port detection circuit, the fifth comparison value and the sixth comparison value are XORed to obtain a third comprehensive result; in the When the third comprehensive result is the first preset result, it is determined that the fault type of the node port to be tested is far-end short connection and hanging; when the third comprehensive result is the sixth preset result, it is determined that the fault type of the node port to be tested is far-end short connection to one end of the termination; the sixth preset result is used to characterize the output result of the port detection circuit; when the third comprehensive result is the seventh preset result, it is determined that the fault type of the node port to be tested is far-end short connection to both ends of the termination; the seventh preset result is used to characterize the output result of the port detection circuit, and the sixth preset result and the seventh preset result are both output results different from the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types; when the third comprehensive result is the fifth preset result, it is determined that the fault type of the node port to be tested is far-end short connection to ground.

[0137] In some embodiments, the port detection circuit is obtained by connecting at least one comparator in parallel, the positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminal of each comparator is connected to an XOR processing unit; each numerical value in the first comparison value corresponds one-to-one to the comparator, and each numerical value in the second comparison value corresponds one-to-one to the comparator; the processing module 1302 is used to: perform XOR processing on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result, including: performing XOR processing on each numerical value in the first comparison value corresponding to the same comparator with each numerical value in the second comparison value to obtain a first comprehensive result.

[0138] In some embodiments, the pulse counter includes: at least one inverter and at least one trigger, the inverters are connected in series in sequence, and the inverter in the last position in series is respectively connected to each of the triggers, and the determination module 1303 is also specifically used for: detecting the node port to be tested of the FC bus network through the pulse counter to obtain the pulse value measured by the pulse counter, including: inputting the input signal to the inverter connected in series at the first position through the pulse counter, adjusting the edge of the input signal and the level waveform of the input signal to obtain the target signal; the input signal is obtained based on the periodic pulse signal; and counting the pulses of the target signal based on the trigger to obtain the pulse value.

[0139] Fig.14 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Fig.14 As shown, the electronic device may include: a processor (processor) 1410 , a communication interface (Communications Interface) 1420 , a memory (memory) 1430 and a communication bus 1440 , wherein the processor 1410 , the communication interface 1420 , and the memory 1430 communicate with each other through the communication bus 1440 . The processor 1410 can call the logic instructions in the memory 1430 to execute the port fault detection method of the FC bus type network, the method comprising: when the FC bus type network generates a periodic pulse signal; detecting the node port to be tested of the FC bus type network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different moments; performing XOR processing on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; and determining the fault type of the node port to be tested based on the first comprehensive result.

[0140] In addition, the logic instructions in the above-mentioned memory 1430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk.

[0141] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the port fault detection method of the FC bus type network provided by the above methods. The method includes: when the FC bus type network generates a periodic pulse signal; detecting the node port to be tested of the FC bus type network through a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different times; based on the port detection circuit, the first comparison value and the second comparison value are XORed to obtain a first comprehensive result; based on the first comprehensive result, determine the fault type of the node port to be tested.

[0142] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the port fault detection method of the FC bus type network provided by the above-mentioned methods, the method comprising: when the FC bus type network generates a periodic pulse signal; detecting the node port to be tested of the FC bus type network by a port detection circuit to obtain a first comparison value and a second comparison value; the first comparison value is used to characterize the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to characterize the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; the first level and the second level are levels at different moments; performing XOR processing on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; and determining the fault type of the node port to be tested based on the first comprehensive result.

[0143] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0144] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting port failure in an FC bus network, characterized in that: include: In the case where the FC bus type network generates a periodic pulse signal; Detecting the node port to be tested of the FC bus network by a port detection circuit to obtain a first comparison value and a second comparison value; The first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; The first level and the second level are levels at different moments; Performing an XOR process on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; Based on the first comprehensive result, a fault type of the port of the node to be tested is determined.

2. The method for detecting port failure of FC bus network according to claim 1, characterized in that: The determining, based on the first comprehensive result, the fault type of the port of the node to be tested includes: In the case where the first comprehensive result is the first preset result, the node port to be tested of the FC bus network is detected by a pulse counter to obtain the pulse value measured by the pulse counter; the first preset result is used to characterize the output result of the port detection circuit detection; When the pulse value is a preset pulse value, determining that the fault type of the node port to be tested is normal; When the pulse value is not the preset pulse value, it is determined that the fault type of the port of the node to be tested is a remote open circuit.

3. The method for detecting port failure of FC bus network according to claim 2, characterized in that: The determining, based on the first comprehensive result, the fault type of the port of the node to be tested includes: In the case where the first comprehensive result is the second preset result, determining that the fault type of the port of the node to be tested is a remote open circuit; the second preset result is used to characterize the output result of the port detection circuit detection; In the case where the first comprehensive result is a third preset result, determining that the fault type of the port of the node to be tested is a near-end open circuit; the third preset result is used to characterize the output result of the port detection circuit detection; In the case where the first comprehensive result is a fourth preset result, determining that the fault type of the port of the node to be tested is a far-end short circuit; the fourth preset result is used to characterize the output result of the port detection circuit detection; When the first comprehensive result is the fifth preset result, the fault type of the port of the node to be tested is determined to be a near-end short circuit; the fifth preset result is used to characterize the output result of the port detection circuit detection, and the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result are all different output results, and different output results correspond to different fault types.

4. The method for detecting port failure of FC bus network according to claim 3, characterized in that: The node port to be tested includes at least two node ports to be tested, and the proximal end short circuit includes proximal ends being shorted to each other and suspended in the air and proximal ends being shorted to the ground; The determining that the fault type of the port of the node to be tested is a near-end short circuit includes: The output circuit of the FC bus network is controlled to be single-tube effective, and the closed node port to be tested is detected by the port detection circuit to obtain a third comparison value and a fourth comparison value; the third comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a third level, and the fourth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a fourth level, and the third level and the fourth level are levels at different times; Performing an XOR process on the third comparison value and the fourth comparison value based on the port detection circuit to obtain a second comprehensive result; When the second comprehensive result is the first preset result, determining that the fault type of the node port to be tested is near-end short and hanging; When the second comprehensive result is the fifth preset result, it is determined that the fault type of the port of the node to be tested is a near-end short to ground.

5. The method for detecting port failure of FC bus network according to claim 3, characterized in that: The node port to be tested includes at least two node ports to be tested, and the remote short circuit includes: the remote ends are shorted to each other and suspended, the remote ends are shorted to one end of the terminal, the remote ends are shorted to both ends of the terminal, and the remote ends are shorted to the ground; The step of determining that the fault type of the port of the node to be tested is a remote short circuit includes: The output circuit of the FC bus network is controlled to be single-tube effective, and the closed node port to be tested is detected by the port detection circuit to obtain a fifth comparison value and a sixth comparison value; the fifth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a fifth level, and the sixth comparison value is used to represent the comparison result between the closed node port to be tested and each of the first reference levels when the closed node port to be tested is at a sixth level, and the fifth level and the sixth level are levels at different times; Performing an XOR process on the fifth comparison value and the sixth comparison value based on the port detection circuit to obtain a third comprehensive result; When the third comprehensive result is the first preset result, determining that the fault type of the node port to be tested is a far-end short circuit and hanging; In the case where the third comprehensive result is the sixth preset result, determining that the fault type of the port of the node to be tested is a far-end short to a termination end; the sixth preset result is used to characterize the output result of the port detection circuit; In the case where the third comprehensive result is the seventh preset result, it is determined that the fault type of the port of the node to be tested is a far-end short to both ends of the termination; the seventh preset result is used to characterize the output result of the port detection circuit, the sixth preset result and the seventh preset result are both output results different from the first preset result, the second preset result, the third preset result, the fourth preset result and the fifth preset result, and the sixth preset result and the seventh preset result correspond to different fault types; When the third comprehensive result is the fifth preset result, it is determined that the fault type of the port of the node to be tested is a far-end short to ground.

6. The method for detecting port failure of an FC bus network according to any one of claims 1 to 5, characterized in that: The port detection circuit is obtained by connecting at least one comparator in parallel, wherein the positive input terminal of the comparator receives the first level or the second level, the negative input terminal of the comparator receives the corresponding first reference level, and the output terminal of each comparator is connected to an exclusive OR processing unit; each value in the first comparison value corresponds to the comparator one by one, and each value in the second comparison value corresponds to the comparator one by one; The performing XOR processing on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result includes: Performing an XOR process on each value in the first comparison value and each value in the second comparison value corresponding to the same comparator to obtain a first comprehensive result.

7. The method for detecting port failure of FC bus network according to claim 2, characterized in that: The pulse counter comprises: at least one inverter and at least one trigger, wherein the inverters are connected in series in sequence, and the last inverter in series is connected to each of the triggers respectively. The step of detecting the node port to be tested of the FC bus network by using a pulse counter to obtain the pulse value measured by the pulse counter comprises: The input signal is input to the inverter connected in series at the first position through the pulse counter, and the edge of the input signal and the level waveform of the input signal are adjusted to obtain the target signal; the input signal is obtained based on the periodic pulse signal; The target signal is pulse counted based on the trigger to obtain the pulse value.

8. A port fault detection device for an FC bus network, characterized in that: include: An acquisition module is used when the FC bus network generates a periodic pulse signal; Detecting the node port to be tested of the FC bus network by a port detection circuit to obtain a first comparison value and a second comparison value; The first comparison value is used to represent the comparison result between the node port to be tested when it is at a first level and at least one first reference level of the node port to be tested, and the second comparison value is used to represent the comparison result between the node port to be tested when it is at a second level and each of the first reference levels; The first level and the second level are levels at different moments; a processing module, configured to perform an XOR process on the first comparison value and the second comparison value based on the port detection circuit to obtain a first comprehensive result; A determination module is used to determine the fault type of the port of the node to be tested based on the first comprehensive result.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the port failure detection method for the FC bus type network according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the port failure detection method for an FC bus network according to any one of claims 1 to 7 is implemented.

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