Ethernet PHY chip Link time test method and network device

Abstract

The invention discloses an Ethernet PHY chip Link time test method and network equipment. The Ethernet PHY chip Link time test method comprises the following steps that an operating system issues a test start command to a micro-control unit; the micro-control unit receiving the test start command issues a reset command to the Ethernet PHY chip to trigger Link down, and transmits a message that the issuing of the reset command is completed to an operating system, and the operating system records time T1 after receiving the message; the micro-control unit uninterruptedly reads the state of the Ethernet PHY chip, when the Link up state is detected, the micro-control unit stops reading and transmits a message that the Ethernet PHY chip has been Link up to the operating system, and the operating system records time T2 after receiving the message; and obtaining the Link up time of the PHY chip according to the time T1 and the time T2 recorded by the operating system. The test method is simple, the influence of system delay of network equipment is small, the test precision is high, measurement is completed without depending on a high-precision instrument, and the test cost is low.

Description

Technical Field

[0001] The present invention relates to the field of network technology, and in particular to a method for testing the Link time of an Ethernet PHY chip and a network device. Background Art

[0002] With the development of Ethernet technology in various fields of social life, Ethernet is gradually penetrating into data communication, industrial control and automotive fields. Different fields have different standards and requirements for Ethernet. Among them, the Link up time of Ethernet PHY chip is an important indicator of Ethernet technology. Especially in industrial Ethernet and automotive Ethernet, the Link up time of the chip needs to reach the millisecond level, which puts higher requirements on the accuracy of the Link up time test of Ethernet PHY chip.

[0003] Commonly used test methods include directly measuring Ethernet PHY link signals and reading Ethernet PHY chip status using software:

[0004] (1) The method of measuring Ethernet PHY link signals mainly uses instruments such as oscilloscopes to detect the signal changes before and after the Ethernet PHY chip is linked down and linked up to calculate the time. This method is suitable for testing in the chip development stage and testing a single chip. It has high accuracy, but is not suitable for multiple stress tests. In addition, it requires the support of high-precision instruments such as oscilloscopes, and the testing cost is high.

[0005] (2) The software reading method mainly sends a reset command to the microcontroller unit (MCU) through the upper operating system (OS), and the MCU sends a command to the Ethernet PHY chip, which triggers link down and up. During this process, the operating system continuously sends instructions to the MCU to read the link status of the Ethernet PHY chip. When the operating system obtains the link up status of the chip, it can calculate the time from the link up state to the reset issuance, which is used as the link up time. Refer to the following Figure 1, is an existing technical solution. All read and write instructions are sent by the operating system, and then the microcontroller unit sends commands to the Ethernet PHY chip. T1' and T2' are the actual link up time. T1 and T2 are the time when the operating system sends the reset instruction and receives the link up. It can be seen that due to the transmission delay between the operating system and the microcontroller unit, the obtained link up time = T2-T1> T2'-T1'. If the delay of the operating system reading and writing the microcontroller unit reaches the millisecond level, it will definitely affect the test results. This software method has high requirements for the read and write speed of the operating system and the consistency of the system delay. If the upper-level operating system reads and writes the serial port instruction time reaches the millisecond level or the system freezes during the reading and writing process, it will definitely affect the test accuracy. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a test method and network device for Ethernet PHY chip Link time, which has little impact on system delay, high test accuracy, does not rely on high-precision instruments to complete the measurement, and has low test cost.

[0007] The present invention is achieved through the following technical solutions:

[0008] A method for testing the Link time of an Ethernet PHY chip comprises the following steps:

[0009] The operating system sends a test start command to the microcontroller unit;

[0010] The microcontroller unit that receives the test start command sends a reset command to the Ethernet PHY chip to trigger Link down, and at the same time transmits a message that the reset command has been sent to the operating system. After the operating system receives the message, it records the time as T1;

[0011] The microcontroller unit continuously reads the status of the Ethernet PHY chip. When the Link up status is detected, it stops reading and simultaneously transmits the message that the Ethernet PHY chip has been Linked up to the operating system. After the operating system receives the message, it records the time as T2.

[0012] The Link up time of the PHY chip is obtained according to the times T1 and T2 recorded by the operating system.

[0013] Furthermore, the method further comprises: writing a reset instruction and a Link status acquisition instruction into the micro control unit.

[0014] Furthermore, the Link up time of the PHY chip=T2-T1.

[0015] Furthermore, T1 includes the extended time T0 of the process of the micro control unit transmitting to the operating system.

[0016] Furthermore, T2 includes the extended time T0 of the process of the micro control unit transmitting to the operating system.

[0017] A network device for executing the above Ethernet PHY chip Link time testing method, comprising:

[0018] Ethernet PHY chip;

[0019] Operating system, used to issue a test start command;

[0020] The microcontroller unit has a reset instruction written inside, which is used to send the reset instruction to the Ethernet PHY chip to trigger Link down, and at the same time transmit the message that the reset command has been sent to the operating system; it also has a Link status acquisition instruction written inside, which is used to continuously read the Ethernet PHY chip status. When the Link up status is detected, it stops reading and simultaneously transmits the message that the Ethernet PHY chip has been Link up to the operating system.

[0021] Compared with the prior art, the advantages of the present invention are:

[0022] 1. Based on the software reading method, the present invention writes both the reset instruction and the link status acquisition instruction into the chip control unit, and the upper operating system only issues a test start command. After the test starts, the chip control unit issues a reset instruction, reads the Ethernet chip link status, and obtains two time points and passes them upward to the operating system. This effectively avoids the influence of the operating system's read and write instruction speed and reduces link delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A test framework diagram of a method of using software reading in the prior art;

[0024] Figure 2 This is a flow chart of a method for testing the Link time of an Ethernet PHY chip according to an embodiment of the present invention;

[0025] Figure 3 This is a test framework diagram of the software reading method adopted in the present invention. DETAILED DESCRIPTION

[0026] The following is a further non-restrictive detailed description of the technical solution of the invention in conjunction with the preferred embodiments and the accompanying drawings. In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and cannot be understood as limitations on the present invention.

[0027] In the prior art, in the fields of smart cars and industrial control, the International Organization for Standardization has put forward stricter requirements on the link up time of PHY. The existing solutions need to occupy more CPU resources, and the measured time is not accurate enough. This requires a more accurate test solution to test the link up time of the PHY chip.

[0028] In order to solve the above problem, a method for testing the Link time of an Ethernet PHY chip according to an embodiment of the present invention effectively avoids the influence of the read and write instruction speed of the operating system and reduces the link delay. Figure 2 This is a schematic diagram of the steps of a method for testing the Link time of an Ethernet PHY chip provided in an embodiment of this invention. This specification provides method operation steps as described in the embodiment or flowchart, but may include more or fewer operation steps based on conventional or non-creative labor. The order of steps listed in the embodiment is only one way of executing the order of many steps and does not represent the only order of execution. When the actual system or device product is executed, it can be executed in the order of the method shown in the embodiment or the accompanying drawings or in parallel.

[0029] Specific as Figure 1 As shown, the method may include the following steps:

[0030] S1: Write the reset command and the Link status acquisition command into the microcontroller unit.

[0031] S2: The operating system sends a test start command to the microcontroller unit.

[0032] The operating system can be a computer, a host computer, etc.

[0033] S3: The microcontroller unit that receives the test start command sends a reset command to the Ethernet PHY chip to trigger Linkdown, and at the same time transmits a message that the reset command has been sent to the operating system. After the operating system receives the message, it records the time as T1.

[0034] T1 includes the extended time T0 of the microcontroller unit transferring the information to the operating system.

[0035] S4: The microcontroller unit continuously reads the status of the Ethernet PHY chip. When the Link up status is detected, it stops reading and simultaneously transmits a message that the Ethernet PHY chip has been Linked up to the operating system. After the operating system receives the message, it records the time as T2.

[0036] T2 includes the extended time T0 of the micro control unit transferring the process to the operating system.

[0037] S5: Obtain the Link up time of the PHY chip according to the times T1 and T2 recorded by the operating system.

[0038] Specifically, the Link up time of the PHY chip = T2 - T1. In the process of subtracting T2 from T1, the influence caused by the extended time T0 is eliminated.

[0039] After the test starts, the chip control unit sends a reset command, reads the Ethernet chip link status, and obtains two time points and passes them upward to the operating system. This effectively avoids the impact of the operating system's read and write instruction speed and reduces link delay.

[0040] as follows Figure 3The figure shows a flowchart of the above method. The English explanations in the figure are: OS: operating system; MCU: microcontroller unit; PHY: Ethernet PHY chip; LP: link partner. The present invention encapsulates the reset instruction of the Ethernet PHY chip and the instruction to obtain the link status into the program of the microcontroller unit MCU. After the microcontroller receives the Test start instruction from the MCU to the upper operating system OS, the microcontroller MCU sends a reset instruction to the Ethernet PHY chip to trigger Link down, and at the same time sends a message to the operating system OS that the reset command has been sent. After receiving the message, the operating system OS records the time T1. After the sending is completed, the microcontroller MCU continuously reads the status of the Ethernet PHY chip. When Link up is detected, it stops reading and simultaneously sends a message to the operating system OS that the Ethernet PHY chip has been Link up. After receiving the message, the operating system OS records the time T2, and then the Link up time = T2-T1 can be obtained. The entire read and write operation is completed by the hardware MCU, and the link delay is at the nanosecond level, which is much smaller than the millisecond level of the read and write operation of the operating system OS. At the same time, the delay transmitted to the operating system OS is also offset by the difference between T1 and T2, and the Link up time = T2'-T1' = T2-T1, and the test result is close to the test result of the measured Ethernet link signal.

[0041] Based on the software reading method, the present invention writes both the reset instruction and the link status acquisition instruction into the chip control unit, and the upper layer operating system only issues a test start command. After the test starts, the chip control unit issues a reset instruction, reads the Ethernet chip link status, and obtains two time points by the chip control unit and passes them upward to the operating system. This effectively avoids the influence of the operating system's read and write instruction speed, while reducing link delay.

[0042] The present invention uses a software system to complete the test, the test method is simple, is less affected by the system delay of the network device, has high test accuracy, is close to the hardware test result, is convenient for large-scale stress testing, does not rely on high-precision instruments to complete the measurement, and has low test cost.

[0043] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for testing the Link time of an Ethernet PHY chip, characterized in that: The following steps are involved: The operating system sends a test start command to the microcontroller unit; The microcontroller unit that receives the test start command sends a reset command to the Ethernet PHY chip to trigger Link down, and at the same time transmits a message that the reset command has been sent to the operating system. After the operating system receives the message, it records the time as T1; The microcontroller unit continuously reads the status of the Ethernet PHY chip. When the Link up status is detected, it stops reading and simultaneously transmits the message that the Ethernet PHY chip has been Linked up to the operating system. After the operating system receives the message, it records the time as T2. The Link up time of the PHY chip is obtained according to the times T1 and T2 recorded by the operating system.

2. The method for testing the Link time of an Ethernet PHY chip according to claim 1, characterized in that: The method further comprises: writing a reset instruction and a Link status acquisition instruction into the micro control unit.

3. The method for testing the Ethernet PHY chip Link time according to claim 1, characterized in that: The Link up time of the PHY chip = T2 - T1.

4. The method for testing the Ethernet PHY chip Link time according to claim 1, characterized in that: The T1 includes the extended time T0 of the microcontroller unit transmitting the process to the operating system.

5. The method for testing the Link time of an Ethernet PHY chip according to claim 1, characterized in that: The T2 includes the extended time T0 of the micro control unit transmitting the process to the operating system.

6. A network device for executing the Ethernet PHY chip Link time test method according to any one of claims 1 to 5, characterized in that: include: Ethernet PHY chip; Operating system, used to issue a test start command; A microcontroller unit has a reset command written inside it, which is used to send the reset command to the Ethernet PHY chip to trigger Linkdown, and at the same time transmit the message that the reset command has been sent to the operating system; It also has a Link status acquisition instruction written inside, which is used to continuously read the Ethernet PHY chip status. When the Link up status is detected, the reading is stopped and the message that the Ethernet PHY chip has been Linked up is transmitted to the operating system at the same time.

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