Virtual channel distribution method for deadlock-free routing in storage and calculation integrated intelligent calculation architecture

Abstract

The invention discloses a virtual channel distribution method for a deadlock-free route in a storage and calculation integrated intelligent calculation architecture, which is based on a scheme of avoiding deadlock through virtual channel isolation in a Crossbar separated router in the intelligent calculation architecture, solves the problem of virtual channel number distribution, and improves the distribution efficiency of the number of virtual channels on the premise of reducing the number of the virtual channels as much as possible. A communication flow distributed in a network on chip is used as an object for modeling, the concept of communication conflicts is introduced, a communication conflict graph with the communication flow as a vertex and the communication conflicts as edges is formed, and therefore the virtual channel number distribution problem is abstracted into the vertex coloring problem of the communication conflict graph; therefore, the deadlock-free design of the network-on-chip is realized under the condition that the number of the virtual channels is minimum. According to the invention, any on-chip network communication system with fixed communication flow distribution based on the Crossbar separated router can be expanded and used.

Description

Technical Field

[0001] The present invention relates to storage-computing integrated intelligent computing, and in particular to a method for allocating virtual channels for deadlock-free routing in a storage-computing integrated intelligent computing architecture. Background Art

[0002] In recent years, artificial intelligence has developed rapidly. Artificial intelligence algorithms represented by neural networks are computationally and memory-intensive tasks. Most of the hardware resources in traditional CPUs (processors) are used for general control rather than computing, so they cannot provide sufficient computing power for the deployment of artificial intelligence algorithms. GPGPUs (general-purpose graphics processors) provide more computing resources at the expense of general control performance, providing an ideal deployment platform for artificial intelligence algorithms. However, GPGPUs still belong to the von Neumann architecture, and their computing and storage are separated. Therefore, in GPGPUs, data transfer between neural network layers must pass through memory. As the computing speed of GPGPUs increases, the time required to perform a calculation becomes smaller and smaller, which makes the proportion of data exchange time between computing units and memory continue to increase, even exceeding the computing time, forming a memory constraint. Memory constraints mean that memory access has become a bottleneck for computing. At this time, it is difficult to expand computing power simply by expanding the scale of computing units.

[0003] In order to eliminate memory constraints, it is necessary to reduce or avoid data movement between computing units and memory. However, in the von Neumann architecture where computing and storage are separated, memory cannot be bypassed by data. Therefore, it is necessary to go beyond the scope of the von Neumann architecture and explore a computing architecture that integrates storage and computing, that is, a storage-computing integrated architecture. In the storage-computing integrated architecture, the memory is given the function of computing, so the data generated by the memory can be calculated on the spot, thereby greatly reducing or even avoiding data movement during computing and eliminating memory constraints.

[0004] The current storage-computing integrated systems are mainly divided into three categories according to the type of in-memory computing devices they are based on: SRAM (static random access memory) storage-computing integrated, DRAM (dynamic random access memory) storage-computing integrated, and NVM (Non-Volatile Memory) storage-computing integrated. Due to the low storage density of SRAM, SRAM storage-computing integrated is difficult to achieve large capacity and is insufficient to support the deployment of large-scale artificial intelligence algorithms. DRAM has an extremely complex and closed hardware model and protocol stack, so only memory manufacturers have the conditions to conduct DRAM storage-computing integrated research. NVM, such as ReRAM, MRAM, PCM, and NOR-FLASH, not only has high storage density, but also has a simple and unified hardware model and strong universality. In addition, NVM also has the advantage of low power consumption. Therefore, how to design an NVM storage-computing integrated intelligent computing architecture to achieve an energy-efficient artificial intelligence algorithm deployment platform has become an open and valuable research topic.

[0005] In the NVM storage-computing integrated intelligent computing architecture (hereinafter referred to as the storage-computing integrated intelligent computing architecture), multiple computing units (Tiles) are usually combined into a computing array, and a special interconnection structure is provided in the computing array for communication between multiple computing units. When executing algorithm tasks, each Tile is responsible for performing a part of the matrix multiplication operation. Multiple Tiles can perform calculations in parallel and rely on the interconnection network to send input data and transmit calculation results, ultimately realizing the forward reasoning process of the neural network.

[0006] In the storage-computing integrated intelligent computing architecture, an on-chip network is usually used to undertake the interconnection and communication tasks of multiple computing units (Tiles). In order to improve the transmission speed of the on-chip network and reduce hardware power consumption, the communication network between tiles is generally based on the Crossbar separated router. Deadlock is a fatal problem of on-chip network communication. Virtual channel isolation is a proven effective solution to avoid deadlock. At present, there is a complete router micro-architecture solution that supports virtual channels, but the specific allocation number of router virtual channels still needs to be customized according to the situation.

[0007] The number of virtual channels determines the scale of the router. In a Crossbar separation router, the number of virtual channels corresponds to the number of Crossbars, and then corresponds to the number of cache FIFOs and the size of the punch, which affects the circuit scale and power consumption of the router. Therefore, minimizing the number of virtual channels is conducive to low-power and low-scale circuit design. At the same time, in order to avoid possible deadlock problems inside the router, sufficient virtual channels are required to isolate different communication flows. This gives rise to the core technical problem that the present invention needs to solve: how to reduce the number of virtual channels of the router as much as possible while ensuring that the on-chip network is free of deadlock. Summary of the invention

[0008] The purpose of the present invention is to propose a virtual channel allocation method for deadlock-free routing in a storage-computing integrated intelligent computing architecture.

[0009] The technical solution to achieve the purpose of the present invention is: A method for allocating virtual channels for deadlock-free routing in a storage-computing integrated intelligent computing architecture, comprising: Step 1: Introduce the concept of communication flow, number all routing links of the on-chip network, abstract a single communication flow into a set of router link numbers, and introduce the concepts of communication conflict and communication conflict graph. Take the communication flow as the vertex of the communication conflict graph, and construct the communication conflict graph by analyzing the communication conflict. Step 2: Color the vertices of the communication conflict graph. Different colors represent different virtual channels. Adjacent vertices represent communication conflicts between the two vertices, and the colors are different. On this basis, the minimum coloring number of the graph coloring problem is solved to obtain the minimum number of virtual channels.

[0010] Furthermore, in step 1, the concept of communication flow is introduced, all routing links of the on-chip network are numbered, and a single communication flow is abstracted into a set of router link numbers. At the same time, the concepts of communication conflict and communication conflict graph are introduced, and the communication flow is used as the vertex of the communication conflict graph. By analyzing the communication conflict, the communication conflict graph is constructed: The data transmission channel between routers is a routing link, and the communication flow is a set of routing links. If there is an intersection of links between two communication flows, there is a communication conflict between the two communication flows. The communication flow is taken as the vertex of the communication conflict graph. If there is a communication conflict between the communication flows represented by two vertices, an edge is connected between the two vertices. After traversing all vertices in sequence, the communication conflict graph is formed.

[0011] Furthermore, the communication flows are fixedly distributed in the on-chip network and do not change dynamically.

[0012] Furthermore, a single communication flow will not cause network deadlock.

[0013] Compared with the prior art, the present invention has the following significant advantages: the invention explores the essence of the on-chip network virtual channel communication isolation problem, abstracts it into a complete graph model, uses the graph coloring problem to find the optimal solution, solves the problem of allocating the number of virtual channels, and adopts the minimum number of virtual channels while ensuring that the virtual channel isolation is deadlock-free, thereby realizing the low-power consumption and low-scale circuit design of the router. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a flow chart for constructing a communication conflict graph.

[0015] Figure 2It is the coloring result of the corresponding communication conflict graph under the simple communication flow distribution case. A total of 6 virtual channels need to be deployed, among which the communication flow represented by vertex a and the communication flow represented by vertex g share the same virtual channel. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0017] In order to deploy convolutional neural networks into a storage-computing integrated intelligent computing architecture, the present invention introduces the concepts of communication flow and communication conflict, and constructs an abstract model for analyzing virtual channel allocation, so as to find the optimal virtual channel number allocation scheme by solving the graph coloring problem.

[0018] The path tree of a single computing unit Tile in the on-chip network is called a communication flow; the current convolution layer will receive data from the previous convolution layer to generate a cast communication flow (one-to-many communication), and may also receive data fusion from the residual block to generate a gather communication flow (one-to-one communication). Both communication flows are completed by the on-chip network based on the Crossbar separation router. When different communication flows pass through the same link of the router, link contention may occur there to generate routing dependencies, and there are data dependencies between communication flows. If multiple dependencies at different locations in the on-chip network are first connected to form a ring, it will cause a deadlock problem. For this reason, all communication flows are isolated through virtual channels to break all possible dependencies.

[0019] Before building the model, the concept of communication conflict is introduced. The data transmission channel between routers is called a routing link. The communication flow can be regarded as a set of routing links. If there is an intersection of links between two communication flows, it is said that there is a communication conflict between the two communication flows. Two extreme cases are considered below. On the one hand, for N communication flows, only N virtual channels need to be set up, and each communication flow occupies one virtual channel. However, two communication flows with no communication conflict can occupy the same virtual channel for deadlock-free transmission, so fewer virtual channels can be used. On the other hand, for a single link, if the maximum communication conflict is M, setting M virtual channels can isolate all communication flows on a single link. However, due to the coupling between multiple communication flows, such allocation still cannot isolate all communication flows. Since it is impossible to obtain the optimal solution from an intuitive perspective, it is essentially abstracted as a graph coloring problem for solution.

[0020] The communication flows are taken as the vertices of the communication conflict graph. If there is a communication conflict between the communication flows represented by two vertices, an edge is connected between the two vertices, and all vertices are traversed in sequence. Next, the vertices of the communication conflict graph are colored. The colors of two adjacent vertices are different. The number of different colors used in the final coloring is the number of virtual channels required. Different colors represent different virtual channels. Adjacent vertices represent a communication conflict between the two. This can completely satisfy the complete isolation between the communication flows. On this basis, the minimum coloring number of the graph coloring problem is obtained through the optimization algorithm, which is the minimum number of virtual channels.

[0021] In fact, for all scenarios where stream computing tasks are implemented on a network on chip, the method of the present invention can be used to determine the number of router virtual channels as long as the following two conditions are met: The communication flow is fixedly distributed in the on-chip network and does not change dynamically.

[0022] A single communication stream will not cause network deadlock.

[0023] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0024] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for allocating virtual channels for deadlock-free routing in a storage-computing integrated intelligent computing architecture, characterized in that: include: Step 1: Introduce the concept of communication flow, number all routing links of the on-chip network, abstract a single communication flow into a set of router link numbers, and introduce the concepts of communication conflict and communication conflict graph. Take the communication flow as the vertex of the communication conflict graph, and construct the communication conflict graph by analyzing the communication conflict. Step 2: Color the vertices of the communication conflict graph. Different colors represent different virtual channels. Adjacent vertices represent communication conflicts between the two vertices, and the colors are different. On this basis, the minimum coloring number of the graph coloring problem is solved to obtain the minimum number of virtual channels.

2. The method for allocating virtual channels for deadlock-free routing in a storage-computing integrated intelligent computing architecture according to claim 1, characterized in that: Step 1: Introduce the concept of communication flow, number all routing links of the on-chip network, abstract a single communication flow into a set of router link numbers, and introduce the concepts of communication conflict and communication conflict graph. Take the communication flow as the vertex of the communication conflict graph, and construct the communication conflict graph by analyzing the communication conflict: The data transmission channel between routers is a routing link, and the communication flow is a set of routing links. If there is an intersection of links between two communication flows, there is a communication conflict between the two communication flows. The communication flows are taken as vertices of the communication conflict graph. If there is a communication conflict between the communication flows represented by two vertices, an edge is connected between the two vertices. The communication conflict graph is constructed by traversing all vertices in sequence.

3. The method for allocating virtual channels for deadlock-free routing in a storage-computing integrated intelligent computing architecture according to claim 1, characterized in that: The communication flow is fixedly distributed in the on-chip network and does not change dynamically.

4. The method for allocating virtual channels for deadlock-free routing in a storage-computing integrated intelligent computing architecture according to claim 1, characterized in that: A single communication stream will not cause network deadlock.

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