Video encoding and decoding method and device and medium

Abstract

A method of decoding an encoded video bitstream using at least one processor, comprising: obtaining a video coding layer (VCL) network abstraction layer (NAL) unit; determining whether the VCL NAL unit is a first VCL NAL unit of a picture unit (PU) containing the VCL NAL unit; based on determining that the VCL NAL unit is the first VCL NAL unit of the PU, determining whether the VCL NAL unit is the first VCL NAL unit of an access unit (AU) including the PU; and based on determining that the VCL NAL unit is the first VCL NAL unit of the AU, decoding the AU according to the VCL NAL unit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 63 / 005,640 filed in the U.S. Patent and Trademark Office on April 6, 2020 and U.S. Application No. 17 / 096,168 filed in the U.S. Patent and Trademark Office on November 12, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present application relates to the technical field of video encoding and decoding, and in particular to signaling picture headers in an encoded video stream. Background Art

[0003] ITU-T VCEG (Q6 / 16) and ISO / IEC MPEG (JTC 1 / SC 29 / WG 11) published the H.265 / HEVC (High Efficiency Video Coding) standard in 2013 (version 1), 2014 (version 2), 2015 (version 3), and 2016 (version 4). In 2015, the two standards organizations jointly formed JVET (Joint Video Exploration Team) to explore the potential of developing the next video coding standard beyond HEVC. In October 2017, the two standards organizations issued a joint call for proposals (CfP) on video compression with capabilities beyond HEVC. By February 15, 2018, 22 CfP responses for standard dynamic range (SDR), 12 CfP responses for high dynamic range (HDR), and 12 CfP responses for 360 video categories were submitted. In April 2018, all received CfP responses were evaluated at the 122MPEG / 10th JVET meeting. As a result of this meeting, JVET formally launched the standardization process for the next generation of video coding beyond HEVC. The new standard was named Versatile Video Coding (VVC), and JVET was renamed the Joint Video Experts Group.

[0004] However, in the latest VVC specification draft, it is unclear how to identify the first video coding layer VCL network abstraction layer NAL unit of a picture unit PU or access unit AU. Summary of the invention

[0005] In an embodiment, a method for decoding an encoded video bitstream using at least one processor is provided, the method comprising: obtaining a video coding layer (VCL) network abstraction layer (NAL) unit; determining whether the VCL NAL unit is the first VCL NAL unit of a picture unit (PU) containing the VCL NAL unit; determining whether the VCL NAL unit is the first VCL NAL unit of an access unit (AU) containing the PU based on determining that the VCL NAL unit is the first VCL NAL unit of the PU; and decoding the AU according to the VCL NAL unit based on determining that the VCL NAL unit is the first VCL NAL unit of the AU.

[0006] In an embodiment, a device for decoding a coded video bitstream is provided, the device comprising: at least one memory configured to store program code; and at least one processor configured to read the program code and operate as indicated by the program code, the program code comprising: a first obtaining code configured to cause at least one processor to obtain a video coding layer (VCL) network abstraction layer (NAL) unit; a first determining code configured to cause at least one processor to determine whether the VCL NAL unit is the first VCL NAL unit of a picture unit (PU) containing the VCL NAL unit; a second determining code configured to cause at least one processor to determine whether the VCL NAL unit is the first VCL NAL unit of an access unit (AU) containing the PU based on determining that the VCL NAL unit is the first VCL NAL unit of the PU; and a decoding code configured to cause at least one processor to decode the AU according to the VCL NAL unit based on determining that the VCL NAL unit is the first VCL NAL unit of the AU.

[0007] In an embodiment, a non-transitory computer-readable medium storing instructions is provided, wherein the instructions include one or more instructions, which, when executed by one or more processors of an apparatus for decoding a coded video bitstream, cause the one or more processors to perform the following operations: obtain a video coding layer (VCL) network abstraction layer (NAL) unit; determine whether the VCL NAL unit is the first VCL NAL unit of a picture unit (PU) containing the VCL NAL unit; determine whether the VCL NAL unit is the first VCL NAL unit of an access unit (AU) containing the PU based on determining that the VCL NAL unit is the first VCL NAL unit of the PU; and decode the AU according to the VCL NAL unit based on determining that the VCL NAL unit is the first VCL NAL unit of the AU. It can be seen that in the present application, when decoding an encoded video bitstream, a VCL NAL unit is obtained; it is determined whether the VCL NAL unit is the first VCL NAL unit of a PU containing the VCL NAL unit; based on determining that the VCL NAL unit is the first VCL NAL unit of the PU, it is determined whether the VCL NAL unit is the first VCL NAL unit of an AU containing the PU; and based on determining that the VCL NAL unit is the first VCL NAL unit of the AU, the AU is decoded according to the VCL NAL unit. Therefore, the present application provides a method for identifying the first VCL NAL unit of a PU or AU to decode an encoded video bitstream. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, properties, and various advantages of the disclosed subject matter will become more apparent from the following detailed description and the accompanying drawings, in which:

[0009] Figure 1 is a schematic diagram of a simplified block diagram of a communication system according to an embodiment;

[0010] Figure 2 is a schematic diagram of a simplified block diagram of a communication system according to another embodiment;

[0011] Figure 3 is a schematic diagram of a simplified block diagram of a decoder according to another embodiment;

[0012] Figure 4 is a schematic diagram of a simplified block diagram of an encoder according to another embodiment;

[0013] Figure 5 is a schematic diagram of an example of a syntax table according to another embodiment;

[0014] FIG. 6A to FIG. 6C is a flow chart of an example process for decoding an encoded video bitstream according to another embodiment;

[0015] Figure 7 is a schematic diagram of a computer system according to another embodiment. DETAILED DESCRIPTION

[0016] Figure 1 A simplified block diagram of a communication system 100 according to an embodiment of the present disclosure is shown. The system 100 may include at least two terminals (110 to 120) interconnected via a network 150. For unidirectional transmission of data, a first terminal 110 may encode video data at a local location for transmission to another terminal 120 via the network 150. The second terminal 120 may receive the encoded video data of another terminal from the network 150, decode the encoded data, and display the recovered video data. Unidirectional data transmission may be common in media service applications and the like.

[0017] Figure 1 A second pair of terminals (130, 140) is shown, which are provided to support bidirectional transmission of encoded video that may occur, for example, during a video conference. For bidirectional transmission of data, each terminal (130, 140) can encode video data captured at a local location for transmission to the other terminal via network 150. Each terminal (130, 140) can also receive encoded video data transmitted by the other terminal, can decode the encoded data, and can display the recovered video data on a local display device.

[0018] exist Figure 1 In the embodiment of the present disclosure, the terminal (110 to 140) can be shown as a server, a personal computer and a smart phone, but the principle of the present disclosure may not be limited thereto. The embodiments of the present disclosure are applicable to notebook computers, tablet computers, media players and / or special video conferencing equipment. Network 150 represents any number of networks that transmit encoded video data between terminals (110 to 140), including, for example, wired and / or wireless communication networks. Communication network 150 can exchange data in circuit switching and / or packet switching channels. Representative networks include telecommunication networks, local area networks, wide area networks and / or the Internet. For the purpose of this discussion, unless otherwise described below, the architecture and topology of network 150 may be insignificant for the operation of the present disclosure.

[0019] As examples of applications of the disclosed subject matter, Figure 2Arrangements of video encoders and decoders in a streaming environment are shown.The disclosed subject matter may be equally applicable to other video-enabled applications including, for example, video conferencing, digital TV, storage of compressed video on digital media including CDs, DVDs, memory sticks, etc., etc.

[0020] The streaming system may include a capture subsystem 213, which may include a video source 201, such as a digital video camera, that creates, for example, an uncompressed video sample stream 202. This sample stream 202, depicted as a thick line to emphasize the high amount of data compared to the encoded video bitstream, may be processed by an encoder 203 coupled to the camera 201. The encoder 203 may include hardware, software, or a combination thereof to implement or implement aspects of the disclosed subject matter as described in more detail below. The encoded video bitstream 204, depicted as a thin line to emphasize the lower amount of data compared to the sample stream, may be stored on a streaming server 205 for future use. One or more streaming clients (206, 208) may access the streaming server 205 to retrieve a copy (207, 209) of the encoded video bitstream 204. The client 206 may include a video decoder 210 that decodes an incoming copy 207 of an encoded video bitstream and creates an outgoing video sample stream 211 that may be presented on a display 212 or other presentation device (not depicted). In some streaming systems, the video bitstreams (204, 207, 209) may be encoded according to certain video encoding / compression standards. Examples of these standards include ITU-T Recommendation H.265. Under development is a video coding standard informally referred to as Versatile Video Coding or VVC. The disclosed subject matter may be used in the context of VVC.

[0021] Figure 3 2 may be a functional block diagram of a video decoder 210 according to an embodiment of the present disclosure.

[0022] The receiver 310 may receive one or more codec video sequences to be decoded by the decoder 210; in the same or another embodiment, one coded video sequence is received at a time, wherein the decoding of each coded video sequence is independent of the other coded video sequences. The coded video sequence may be received from a channel 312, which may be a hardware / software link to a storage device storing the coded video data. The receiver 310 may receive the coded video data and other data that may be forwarded to its corresponding use entity (not depicted), such as coded audio data and / or auxiliary data streams. The receiver 310 may separate the coded video sequence from the other data. To combat network jitter, a buffer memory 315 may be coupled between the receiver 310 and an entropy decoder / parser 320 (hereinafter referred to as a "parser"). When the receiver 310 receives data from a storage / forwarding device with sufficient bandwidth and controllability or from an isochronous network, the buffer 315 may not be needed, or the buffer 315 may be very small. In order to use a packet network such as the Internet as much as possible, a buffer 315 may be needed, which may be relatively large and may advantageously have an adaptive size.

[0023] The video decoder 210 may include a parser 320 that reconstructs symbols 321 from the entropy-coded video sequence. The categories of these symbols include information for managing the operation of the decoder 210 and potential information for controlling a presentation device that is not part of the decoder but may be coupled to the decoder, such as the display 212, e.g. Figure 3As shown. The control information of the presentation device may be in the form of a supplementary enhancement information (SEI message) or a video usability information (VUI) parameter set fragment (not depicted). The parser 320 may parse / entropy decode the received coded video sequence. The coding of the coded video sequence may be performed according to a video coding technique or standard, and may follow principles known to those skilled in the art, including variable length coding, Huffman coding, arithmetic coding with or without context sensitivity, etc. The parser 320 may extract a subgroup parameter set of at least one subgroup of the subgroups of pixels in the video decoder from the coded video sequence based on at least one parameter corresponding to the group. The subgroup may include: a group of pictures (Group of Pictures, GOP), a picture, a sub-picture, a tile, a slice, a brick, a macroblock, a coding tree unit (Coding Tree Unit, CTU), a coding unit (Coding Unit, CU), a block, a transform unit (Transform Unit, TU), a prediction unit (Prediction Unit, PU), etc. A tile may indicate a rectangular area of ​​a CU / CTU within a particular tile column and row in a picture. A block may indicate a rectangular area of ​​a CU / CTU row within a particular tile. A slice may indicate one or more blocks of a picture that are contained in a NAL unit. A sub-picture may indicate a rectangular area of ​​one or more slices in a picture. The entropy decoder / parser may also extract information from the encoded video sequence, such as transform coefficients, quantizer parameter values, motion vectors, etc.

[0024] Parser 320 may perform entropy decoding / parsing operations on the video sequence received from buffer 315 to create symbols 321 .

[0025] The reconstruction of the symbol 321 may involve a number of different units depending on the type of the coded video picture or portion thereof, e.g., inter- and intra-pictures, inter- and intra-blocks, and other factors. Which units are involved and how this is done may be controlled by sub-group control information parsed from the coded video sequence by the parser 320. For clarity, such sub-group control information flow between the parser 320 and the following multiple units is not depicted.

[0026] In addition to the functional blocks already mentioned, decoder 210 can be conceptually subdivided into a plurality of functional units as described below. In actual implementation operations under commercial constraints, many of these units interact closely with each other and can be at least partially integrated with each other. However, for the purpose of describing the disclosed subject matter, it is appropriate to conceptually subdivide into the following functional units.

[0027] The first unit is a sealer / inverse transform unit 351. The sealer / inverse transform unit 351 receives the quantized transform coefficients as symbols 321 from the parser 320, as well as control information including which transform to use, block size, quantization factor, quantization scaling matrix, etc. The sealer / inverse transform unit 351 may output a block including sample values, which may be input into an aggregator 355.

[0028] In some cases, the output samples of the sealer / inverse transform 351 may belong to an intra-coded block; that is, a block that does not use predictive information from a previously reconstructed picture but can use predictive information from a previously reconstructed portion of the current picture. Such predictive information may be provided by an intra-picture prediction unit 352. In some cases, the intra-picture prediction unit 352 uses surrounding already reconstructed information obtained from the current partially reconstructed picture 358 to generate a block of the same size and shape as the block being reconstructed. In some cases, the aggregator 355 adds the prediction information already generated by the intra-prediction unit 352 to the output sample information provided by the sealer / inverse transform unit 351 on a per-sample basis.

[0029] In other cases, the output samples of the sealer / inverse transform unit 351 may belong to an inter-frame coded and possibly motion compensated block. In this case, the motion compensated prediction unit 353 may access the reference picture memory 357 to obtain samples for prediction. After the obtained samples are motion compensated according to the symbols 321 belonging to the block, these samples may be added to the output of the sealer / inverse transform unit by the aggregator 355, in this case referred to as residual samples or residual signals, to generate output sample information. The address within the reference picture memory from which the motion compensation unit extracts the predicted samples may be controlled by a motion vector, which can be used for the motion compensation unit in the form of a symbol 321, which may have, for example, an X component, a Y component, and a reference picture component. Motion compensation may also include interpolation of sample values ​​extracted from the reference picture memory when using sub-sample accurate motion vectors, motion vector prediction mechanisms, etc.

[0030] The output samples of aggregator 355 may be subjected to various loop filtering techniques in loop filter unit 356. The video compression techniques may include in-loop filter techniques controlled by parameters included in the coded video bitstream and available to loop filter unit 356 as symbols 321 from parser 320, but the video compression techniques may also be responsive to meta-information obtained during decoding of a previous (in decoding order) portion of a coded picture or coded video sequence, and to previously reconstructed and loop filtered sample values.

[0031] The output of the loop filter unit 356 may be a sample stream that may be output to the rendering device 212 and stored in a reference picture memory for future inter-picture prediction.

[0032] Once fully reconstructed, certain coded pictures may be used as reference pictures for future prediction. Once a coded picture is fully reconstructed and the coded picture is identified as a reference picture (e.g., by parser 320), current reference picture 358 may become part of reference picture buffer 357, and new current picture memory may be reallocated before starting reconstruction of a subsequent coded picture.

[0033] The video decoder 210 may perform decoding operations according to a predetermined video compression technique that may be recorded in a standard such as ITU-T H.265 Recommendation. In the sense that the encoded video sequence follows the syntax of the video compression technique or standard as specified in the video compression technology document or standard and specifically in the profile document therein, the encoded video sequence may conform to the syntax specified by the video compression technology or standard used. For compliance, the complexity of the encoded video sequence is also required to be within the range defined by the hierarchy of the video compression technology or standard. In some cases, the hierarchy limits the maximum picture size, the maximum frame rate, the maximum reconstructed sample rate measured in units of, for example, megasamples per second, the maximum reference picture size, etc. In some cases, the limits set by the hierarchy may be further defined by the metadata of the HRD buffer management signaled in the encoded video sequence, the Hypothetical Reference Decoder, the HRD specification, and the HRD buffer management signaled in the encoded video sequence.

[0034] In an embodiment, the receiver 310 may receive additional (redundant) data along with the encoded video. The additional data may be included as part of the encoded video sequence. The video decoder 210 may use the additional data to properly decode the data and / or more accurately reconstruct the original video data. The additional data may be in the form of, for example, time, space or SNR enhancement layers, redundant slices, redundant pictures, forward error correction codes, etc.

[0035] Figure 4 203 according to an embodiment of the present disclosure.

[0036] Encoder 203 may receive video samples from video source 201 (which is not part of the encoder), which may capture video images to be encoded by encoder 203 .

[0037] The video source 201 can provide a source video sequence to be encoded by the video encoder 203 in the form of a digital video sample stream, and the digital video sample stream can have any suitable bit depth (e.g., 8 bits, 10 bits, 12 bits ...), any color space (e.g., BT.601Y CrCB, RGB ...) and any suitable sampling structure (e.g., Y CrCb 4:2:0, YCrCb4:4:4). In a media service system, the video source 201 can be a storage device that stores previously prepared videos. In a video conferencing system, the video source 203 can be a camera that captures local image information as a video sequence. The video data can be provided as multiple separate pictures that are given motion when viewed in sequence. The picture itself can be organized as a spatial pixel array, wherein each pixel can include one or more samples depending on the sampling structure, color space, etc. used. The relationship between pixels and samples can be easily understood by those skilled in the art. The following focuses on describing samples.

[0038] According to an embodiment, the encoder 203 can encode and compress the pictures of the source video sequence into an encoded video sequence 443 in real time or under any other time constraints required by the application. It is a function of the controller 450 to implement the appropriate encoding speed. The controller controls other functional units described below and is functionally coupled to these units. The coupling is not depicted for simplicity. The parameters set by the controller may include rate control related parameters (picture skipping, quantizer, lambda value of rate distortion optimization technology...), picture size, group of pictures (group of pictures, GOP) layout, maximum motion vector search range, etc. Those skilled in the art can easily identify other functions of the controller 450, because these functions may belong to the video encoder 203 optimized for a specific system design.

[0039] Some video encoders operate in a manner that is readily recognizable to those skilled in the art as a "coding loop". As an overly simplified description, the coding loop may include an encoding portion of an encoder 430 (hereinafter referred to as a "source encoder"), which is responsible for creating symbols based on the input picture to be encoded and the reference picture, and a (local) decoder 433 embedded in the encoder 203, which reconstructs the symbols to create sample data that will also be created by the (remote) decoder (because in the video compression techniques considered in the disclosed subject matter, any compression between the symbols and the encoded video bitstream is lossless). This reconstructed sample stream is input to a reference picture memory 434. Since the decoding of the symbol stream produces bit-accurate results independent of the decoder location (local or remote), the reference picture buffer contents are also bit-accurate between the local encoder and the remote encoder. In other words, the reference picture samples "seen" by the prediction portion of the encoder are exactly the same sample values ​​that the decoder will "see" when using prediction during decoding. The basic principles of this reference picture synchronization (and the drift that results when synchronization cannot be maintained, for example due to channel errors) are well known to those skilled in the art.

[0040] The operation of the "local" decoder 433 may be identical to the operation of the "remote" decoder 210, as described above in conjunction with Figure 3 The "remote" decoder 210 is described in detail. However, reference is also briefly made to Figure 4 , when symbols are available and encoding / decoding of the symbols into an encoded video sequence by the entropy encoder 445 and the parser 320 can be lossless, the entropy decoding portion of the decoder 210 including the channel 312, the receiver 310, the buffer 315 and the parser 320 may not be fully implemented in the local decoder 433.

[0041] At this point, it can be observed that any decoder technology other than parsing / entropy decoding present in the decoder must also be present in the corresponding encoder in substantially the same functional form. For this reason, the disclosed subject matter focuses on the decoder operation. Since the encoder technology is mutually inverse to the decoder technology that has been fully described, the description of the encoder technology can be simplified. A more detailed description is only required and provided in certain places hereinafter.

[0042] As part of its operation, source encoder 430 may perform motion compensated predictive encoding, which predictively encodes an input frame with reference to one or more previously encoded frames from a video sequence that are designated as “reference frames.” In this manner, encoding engine 432 encodes the differences between pixel blocks of an input frame and pixel blocks of a reference frame that may be selected as a prediction reference for the input frame.

[0043] The local video decoder 433 can decode the encoded video data of the frame that can be designated as the reference frame based on the symbol created by the source encoder 430. The operation of the encoding engine 432 can advantageously be a lossy process. Figure 4 The reconstructed video sequence may typically be a copy of the source video sequence with some errors when the source video sequence is decoded at a remote location (not shown). The local video decoder 433 replicates the decoding process that may be performed by the video decoder on the reference frame and may cause the reconstructed reference frame to be stored in the reference picture cache 434. In this way, the encoder 203 may locally store a copy of the reconstructed reference frame that has common content (absent transmission errors) with the reconstructed reference frame that will be obtained by the remote video decoder.

[0044] The predictor 435 may perform a prediction search on the encoding engine 432. That is, for a new frame to be encoded, the predictor 435 may search the reference picture memory 434 for sample data (as a candidate reference pixel block) or certain metadata, such as reference picture motion vectors, block shapes, etc., that may be used as a suitable prediction reference for the new picture. The predictor 435 may operate on a pixel block by pixel block basis to find a suitable prediction reference. In some cases, as determined by the search results obtained by the predictor 435, the input picture may have prediction references extracted from multiple reference pictures stored in the reference picture memory 434.

[0045] The controller 450 may manage encoding operations of the video encoder 430 , including, for example, setting parameters and subgroup parameters for encoding video data.

[0046] The outputs of all the above-mentioned functional units may be subjected to entropy coding in the entropy encoder 445. The entropy encoder converts the symbols generated by the various functional units into a coded video sequence by losslessly compressing the symbols according to techniques well known to those skilled in the art (e.g., Huffman coding, variable length coding, arithmetic coding, etc.).

[0047] Transmitter 440 may buffer the encoded video sequence created by entropy encoder 445 in preparation for transmission via communication channel 460, which may be a hardware / software link to a storage device where the encoded video data will be stored. Transmitter 440 may combine the encoded video data from video encoder 430 with other data to be transmitted, such as encoded audio data and / or auxiliary data streams (source not shown).

[0048] The controller 450 may manage the operation of the encoder 203. During encoding, the controller 450 may assign a certain coded picture type to each coded picture, which may affect the coding techniques that may be applied to the corresponding picture. For example, a picture may generally be assigned one of the following frame types:

[0049] An intra picture (I picture) may be a picture that can be encoded and decoded without using any other frame in the sequence as a prediction source. Some video codecs allow different types of intra pictures, including, for example, independent decoder refresh pictures. Those skilled in the art are aware of these variations of I pictures and their corresponding applications and features.

[0050] A predictive picture (P picture) may be a picture that may be encoded and decoded using intra prediction or inter prediction, which uses at most one motion vector and a reference index to predict sample values ​​for each block.

[0051] Bi-directional predictive pictures (B pictures), which can be pictures that can be encoded and decoded using intra-frame prediction or inter-frame prediction, which uses up to two motion vectors and reference indices to predict the sample values ​​of each block. Similarly, multi-predictive pictures can use more than two reference pictures and associated metadata for reconstruction of a single block.

[0052] The source picture may typically be spatially subdivided into a plurality of blocks of samples (e.g., blocks of 4×4, 8×8, 4×8, or 16×16 samples, respectively) and coded block by block. Blocks may be predictively coded with reference to other (already coded) blocks as determined according to the coding allocation applied to the corresponding picture of the block. For example, blocks of an I picture may be non-predictively coded, or blocks of an I picture may be predictively coded (spatial prediction or intra-prediction) with reference to already coded blocks of the same picture. Pixel blocks of a P picture may be non-predictively coded via spatial prediction or via temporal prediction with reference to one previously coded reference picture. Blocks of a B picture may be non-predictively coded via spatial prediction or via temporal prediction with reference to one or two previously coded reference pictures.

[0053] The video encoder 203 may perform encoding operations according to a predetermined video encoding technique or standard, such as ITU-T H.265 Recommendation. In its operation, the video encoder 203 may perform various compression operations, including predictive encoding operations that exploit temporal and spatial redundancy in the input video sequence. Thus, the encoded video data may conform to the syntax specified by the video encoding technique or standard used.

[0054] In an embodiment, the transmitter 440 may transmit the additional data along with the encoded video. The video encoder 430 may include such data as part of the encoded video sequence. The additional data may include temporal / spatial / SNR enhancement layers, other forms of redundant data such as redundant pictures and slices, Supplementary Enhancement Information (SEI) messages, Visual Usability Information (VUI) parameter set fragments, etc.

[0055] Embodiments may involve modifications to the syntax and semantics associated with the picture header. At least one embodiment may involve signaling all_pic_coding_info_present_in_ph_flag in the PPS as a gating flag to save some bits to specify whether picture level coding tool information is present in the PH or SH. At least one embodiment may involve correcting the identification of the first VCL NAL unit of a PU or AU. At least one embodiment may involve modifying the semantics of gdr_or_irap_pic_flag to handle the case where mixed_nalu_types_flag is equal to 1.

[0056] In an embodiment, a picture parameter set (PPS) may refer to a syntax structure containing syntax elements that apply to zero or more complete coded pictures as determined by syntax elements found in each slice header.

[0057] In an embodiment, a picture header (PH) may refer to a syntax structure containing syntax elements applicable to all slices of a coded picture.

[0058] In an embodiment, a slice header (SH) may refer to a portion of a coded slice that contains data elements belonging to all tiles or coding tree unit (CTU) rows within tiles represented in the slice.

[0059] Implementations may relate to a video coding layer (Video Coding Layer, VCL).

[0060] In an embodiment, a network abstraction layer (NAL) unit may refer to a syntactic structure that contains an indication of the type of data to follow and the following bytes: the bytes contain the data in the form of a raw byte sequence payload (RBSP), which is interspersed with emulation prevention bytes when necessary.

[0061] In an embodiment, a VCL NAL unit may refer to a collective term for a subset of coded slice NAL units and NAL units having a reserved value of nal_unit_type, both of which are classified as VCL NAL units in this specification.

[0062] In an embodiment, a picture unit (PU) may refer to a set of NAL units that are associated with each other according to a specified classification rule, are consecutive in decoding order, and contain exactly one coded picture.

[0063] In an embodiment, an access unit (AU) may refer to a set of PUs that belong to different layers and contain coded pictures associated with the same time and output from a decoded picture buffer (DPB).

[0064] Embodiments may involve sample adaptive offset (SAO).

[0065] In an embodiment, an adaptive loop filter (ALF) may refer to a filtering process applied as part of the decoding process and controlled by parameters conveyed in an adaptation parameter set (APS).

[0066] Implementations may involve a quantization parameter (QP).

[0067] Embodiments may involve intra random access points (IRAPs).

[0068] Implementations may involve gradual decoding refresh (GDR).

[0069] In an embodiment, a GDR picture may refer to a picture in which each VCL NAL unit has nal_unit_type equal to GDR_NUT.

[0070] In the latest version of the VVC draft (JVET-Q2001-vE), six flags can be used in the PPS syntax structure to indicate whether picture-level coding information is present in the picture header or slice header. For example, rpl_info_in_ph_flag, dbf_info_in_ph_flag, sao_info_in_ph_flag, etc. In most cases, these values ​​can have the same value, that is, 0 or 1. It seems unlikely that each xxx_info_in_ph flag has a different value.

[0071] Therefore, in an embodiment, the gating flag all_pic_coding_info_present_in_ph_flag may indicate those flags are present in the PPS to save bits in the PPS. If the value of all_pic_coding_info_present_in_ph_flag is equal to 1, those xxx_info_in_ph flags are not signaled and the values ​​of those flags may be inferred to be equal to 1, because signaling picture-level coding information in a picture header may occur more frequently than signaling information for slice-level control in a slice header. Figure 5 An example of a syntax table consistent with an implementation example is shown in FIG.

[0072] In an embodiment, all_pic_coding_info_present_in_ph_flag equal to 1 may specify that rpl_info_in_ph_flag, dbf_info_in_ph_flag, sao_info_in_ph_flag, alf_info_in_ph_flag, wp_info_in_ph_flag, and qp_delta_info_in_ph_flag are not present in the PPS. all_pic_coding_info_present_in_ph_flag equal to 0 may specify that rpl_info_in_ph_flag, dbf_info_in_ph_flag, sao_info_in_ph_flag, alf_info_in_ph_flag, wp_info_in_ph_flag, and qp_delta_info_in_ph_flag are present in the PPS.

[0073] In an embodiment, rpl_info_in_ph_flag equal to 1 may specify that the reference picture list information is present in the PH syntax structure and is not present in the slice header of the reference PPS that does not contain the PH syntax structure. rpl_info_in_ph_flag equal to 0 may specify that the reference picture list information is not present in the PH syntax structure and may be present in the slice header of the reference PPS that does not contain the PH syntax structure. In the case where the reference picture list information is not present in the slice header of the reference PPS that does not contain the PH syntax structure, it can be inferred that the value of rpl_info_in_ph_flag is equal to 1.

[0074] In an embodiment, dbf_info_in_ph_flag equal to 1 may specify that the deblocking filter information is present in the PH syntax structure and is not present in the slice header of the reference PPS that does not contain the PH syntax structure. dbf_info_in_ph_flag equal to 0 may specify that the deblocking filter information is not present in the PH syntax structure and may be present in the slice header of the reference PPS that does not contain the PH syntax structure. In the case where the deblocking filter information is not present in the PH syntax structure, it can be inferred that the value of dbf_info_in_ph_flag is equal to 0. In the case where the deblocking filter information is not present in the slice header of the reference PPS that does not contain the PH syntax structure, it can be inferred that the value of dbf_info_in_ph_flag is equal to 1.

[0075] sao_info_in_ph_flag equal to 1 may specify that the SAO filter information is present in the PH syntax structure and is not present in the slice header of the reference PPS that does not contain the PH syntax structure. sao_info_in_ph_flag equal to 0 may specify that the SAO filter information is not present in the PH syntax structure and may be present in the slice header of the reference PPS that does not contain the PH syntax structure. In the case where the SAO filter information is not present in the slice header of the reference PPS that does not contain the PH syntax structure, it may be inferred that the value of sao_info_in_ph_flag is equal to 1.

[0076] alf_info_in_ph_flag equal to 1 may specify that the ALF information is present in the PH syntax structure and is not present in the slice header of the reference PPS that does not contain the PH syntax structure. alf_info_in_ph_flag equal to 0 may specify that the ALF information is not present in the PH syntax structure and may be present in the slice header of the reference PPS that does not contain the PH syntax structure. In the case where the ALF information is not present in the slice header of the reference PPS that does not contain the PH syntax structure, the value of alf_info_in_ph_flag equal to 1 may be inferred.

[0077] wp_info_in_ph_flag equal to 1 may specify that the weighted prediction information may be present in the PH syntax structure and may not be present in the slice header of the reference PPS that does not contain the PH syntax structure. wp_info_in_ph_flag equal to 0 may specify that the weighted prediction information may not be present in the PH syntax structure and may be present in the slice header of the reference PPS that does not contain the PH syntax structure. In the absence of wp_info_in_ph_flag, the value of 0 may be inferred. In the absence of weighted prediction information in the slice header of the reference PPS that does not contain the PH syntax structure, the value of 1 may be inferred.

[0078] qp_delta_info_in_ph_flag equal to 1 may specify that QP delta information is present in the PH syntax structure and not present in the slice header of the reference PPS that does not contain the PH syntax structure. qp_delta_info_in_ph_flag equal to 0 may specify that QP delta information is not present in the PH syntax structure and may be present in the slice header of the reference PPS that does not contain the PH syntax structure. In the case where QP delta information is not present in the slice header of the reference PPS that does not contain the PH syntax structure, the value of qp_delta_info_in_ph_flag equal to 1 may be inferred.

[0079] In the latest VVC specification draft, it is unclear how to identify the first VCL NAL unit of a PU or AU. Implementations may involve the following modifications to the description of the order of NAL units.

[0080] In an embodiment, a VCL NAL unit is the first VCL NAL unit of an AU and thus the PU containing the VCL NAL unit is the first PU of the AU if the VCL NAL unit is the first VCL NAL unit following a PH NAL unit or has picture_header_in_slice_header_flag equal to 1 and one or more of the following conditions are true: – The value of nuh_layer_id of a VCL NAL unit is less than the nuh_layer_id of the previous picture in decoding order. – The value of ph_pic_order_cnt_lsb of a VCL NAL unit is different from the ph_pic_order_cnt_lsb of the previous picture in decoding order. – The derived PicOrderCntVal for the VCL NAL unit is different from the PicOrderCntVal of the previous picture in decoding order.

[0081] In an embodiment, the flag gdr_or_irap_pic_flag in the picture header indicates whether the current picture is an IRAP picture or a GDR picture. When the value of gdr_or_irap_pic_flag is equal to 1, the flag no_output_of_prior_pics_flag may also be present in the picture header. When merging the bitstreams of sub-pictures, the value of no_output_of_prior_pics_flag of the IRAP sub-picture needs to be maintained for sub-picture extraction. To solve this problem, an embodiment may involve the following modification of the semantics of gdr_or_irap_pic_flag:

[0082] In an embodiment, gdr_or_irap_pic_flag equal to 1 may specify that the current picture is a GDR or IRAP picture or a picture with VCL NAL units equal to IDR_W_RADL, IDR_N_LP, or CRA_NUT and mixed_nalu_types_in_pic_flag equal to 1. gdr_or_irap_pic_flag equal to 0 may specify that the current picture may or may not be a GDR or IRAP picture

[0083] In an embodiment, gdr_or_irap_pic_flag equal to 1 may specify that the current picture is a GDR or IRAP picture or a picture containing an IRAP sub-picture with mixed_nalu_types_in_pic_flag equal to 1. gdr_or_irap_pic_flag equal to 0 may specify that the current picture may or may not be a GDR or IRAP picture.

[0084] In an embodiment, gdr_or_irap_pic_flag equal to 1 may specify that the current picture is a GDR or IRAP picture. gdr_or_irap_pic_flag equal to 0 may specify that the current picture may or may not be a GDR or IRAP picture.

[0085] When mixed_nalu_types_in_pic_flag is equal to 1, it may be a requirement for bitstream conformance that the value of gdr_or_irap_pic_flag shall be equal to 0.

[0086] FIG. 6A to FIG. 6C600A, 600B, and 600C are flow diagrams of example processes for decoding an encoded video bitstream. In some implementations, FIG. 6A to FIG. 6C One or more processing blocks of may be performed by decoder 210. In some implementations, FIG. 6A to FIG. 6C One or more processing blocks of may be performed by another device or a group of devices, such as encoder 203, separate from or including decoder 210.

[0087] In an embodiment, Fig. 6A One or more blocks shown in may correspond to Figure 6B and Figure 6C One or more blocks can be combined with Figure 6B and Figure 6C One or more blocks are executed together.

[0088] like Fig. 6A As shown, process 600A may include obtaining a video coding layer (VCL) network abstraction layer (NAL) unit (block 611).

[0089] like Fig. 6A As further shown in FIG. 6 , process 600A may include determining that the VCL NAL unit is a first VCL NAL unit of a picture unit (PU) that contains the VCL NAL unit (block 612 ).

[0090] like Fig. 6A As further shown in FIG. 6 , process 600A may include determining that the VCL NAL unit is the first VCL NAL unit of an access unit (AU) including the PU based on determining that the VCL NAL unit is the first VCL NAL unit of the PU (block 613 ).

[0091] like Fig. 6A As further shown in FIG. 6 , process 600A may include decoding the AU from the VCL NAL unit based on determining that the VCL NAL unit is the first VCL NAL unit of the AU (block 614).

[0092] In an embodiment, Figure 6B One or more blocks shown in may correspond to Fig. 6A and Figure 6C One or more blocks can be combined with Fig. 6A and Figure 6C One or more blocks are executed together.

[0093] like Figure 6BAs shown, process 600B may include obtaining a VCL NAL unit (block 621).

[0094] like Figure 6B As further shown in FIG. 6 , process 600B may include determining whether the VCL NAL unit is the first VCL NAL unit following a picture header NAL unit (block 622 ).

[0095] like Figure 6B As further shown in FIG. 6 , process 600B may include proceeding to block 623 based on determining that the VCL NAL unit is the first VCL NAL unit following a picture header NAL unit (yes at block 622 ).

[0096] like Figure 6B As further shown in FIG. 6 , process 600B may include proceeding to block 624 based on determining that the VCL NAL unit is not the first VCL NAL unit following a picture header NAL unit (NO at block 622 ). In an embodiment, process 600B may instead proceed to block 625 .

[0097] like Figure 6B As further shown in FIG. 6 , process 600B may include determining whether a flag in the VCL NAL unit is set to indicate that the picture header is included in a slice header included in the VCL NAL unit (block 624). In an embodiment, the flag may correspond to picture_header_in_slice_header_flag.

[0098] like Figure 6B As further shown in , process 600B may include proceeding to block 623 based on determining that a flag in the VCL NAL unit is set to indicate that the picture header is included in a slice header included in the VCL NAL unit (yes at block 624).

[0099] like Figure 6B As further shown in , process 600B may include proceeding to block 625 based on determining that a flag in the VCL NAL unit is not set to indicate that a picture header is included in a slice header included in the VCL NAL unit (No at block 624).

[0100] like Figure 6B As further shown in FIG. 6 , process 600B may include determining that the VCL NAL unit is the first VCL NAL unit of a PU that includes the VCL NAL unit (block 623 ).

[0101] like Figure 6BAs further shown in FIG. 6 , process 600B may include determining that the VCL NAL unit is not the first VCL NAL unit of the PU that contains the VCL NAL unit (block 625 ).

[0102] In an embodiment, Figure 6C One or more blocks shown in may correspond to Fig. 6A and Figure 6B One or more blocks can be combined with Fig. 6A and Figure 6B One or more blocks are executed together.

[0103] like Figure 6C As shown in , process 600C may include determining that the VCL NAL unit is the first VCL NAL unit of the PU (block 631).

[0104] like Figure 6C As further shown in FIG. 6 , process 600C may include determining whether a layer identifier of the VCL NAL unit is less than a layer identifier of a previous picture (block 632 ).

[0105] like Figure 6C As further shown in , process 600C may include proceeding to block 633 based on determining that the layer identifier of the VCL NAL unit is less than the layer identifier of the previous picture (yes at block 632).

[0106] like Figure 6C As further shown in , process 600C may include proceeding to block 634 based on determining that the layer identifier of the VCL NAL unit is not less than the layer identifier of the previous picture (no at block 632). In an embodiment, process 600C may instead proceed to block 635.

[0107] like Figure 6C As further shown in FIG. 6 , process 600C may include determining whether the picture order count of the VCL NAL unit is different from the picture order count of the previous picture (block 634). In an embodiment, this may be determined based on the least significant bit (LSB) of the picture order count.

[0108] like Figure 6C As further shown in , process 600C may include proceeding to block 633 based on determining that the picture order count of the VCL NAL unit is different from the picture order count of the previous picture (yes at block 634).

[0109] like Figure 6C As further shown in , process 600C may include proceeding to block 635 based on determining that the picture order count of the VCL NAL unit is not different from the picture order count of the previous picture (NO at block 634).

[0110] like Figure 6C As further shown in FIG. 6 , process 600C may include determining that the VCL NAL unit is the first VCL NAL unit of the AU that contains the VCL NAL unit (block 633 ).

[0111] like Figure 6C As further shown in FIG. 6 , process 600C may include determining that the VCL NAL unit is not the first VCL NAL unit of the AU that contains the VCL NAL unit (block 635 ).

[0112] In an embodiment, based on a flag indicating that all picture coding information is present in a picture header, a plurality of flags corresponding to picture coding information may not be signaled. In an embodiment, the flag may correspond to all_pic_coding_info_present_in_ph_flag.

[0113] although FIG. 6A to FIG. 6C Example blocks of processes 600A to 600C are shown, but in some implementations, FIG. 6A to FIG. 6C The processes 600A to 600C may include additional blocks, fewer blocks, different blocks, or differently arranged blocks compared to those depicted in. Additionally or alternatively, two or more of the blocks of the processes 600A to 600C may be performed in parallel.

[0114] In addition, the proposed method can be implemented by a processing circuit system (eg, one or more processors or one or more integrated circuits). In one example, one or more processors execute a program stored in a non-transitory computer-readable medium to perform one or more of the proposed methods.

[0115] The above techniques can be implemented as computer software using computer-readable instructions and physically stored in one or more computer-readable media. Figure 7 A computer system 700 suitable for implementing certain embodiments of the disclosed subject matter is shown.

[0116] Computer software may be encoded using any suitable machine code or computer language, which may be subjected to mechanisms such as assembly, compilation, and linking to create code comprising instructions that may be directly executed by a computer central processing unit (CPU), a graphics processing unit (GPU), or the like, or executed by a computer central processing unit (CPU), a graphics processing unit (GPU) through interpretation, microcode execution, or the like.

[0117] The instructions may be executed on various types of computers or components thereof, including, for example, personal computers, tablet computers, servers, smart phones, gaming devices, IoT devices, etc.

[0118] Figure 7 The components for computer system 700 shown in the example are exemplary in nature and are not intended to suggest any limitation on the scope of use or functionality of computer software implementing embodiments of the present disclosure. Nor should the configuration of components be interpreted as having any dependency or requirement related to any one or combination of components shown in the exemplary embodiment of computing system 700.

[0119] Computer system 700 may include certain human-machine interface input devices. Such human-machine interface input devices may be responsive to input by one or more human users through, for example, tactile input (e.g., keystrokes, swipes, data glove movements), audio input (e.g., voice, clapping), visual input (e.g., gestures), olfactory input (not depicted). Human-machine interface devices may also be used to capture certain media that are not necessarily directly related to conscious human input, such as audio (e.g., voice, music, ambient sounds), images (e.g., scanned images, photographic images obtained from a still image camera), and video (e.g., two-dimensional video, three-dimensional video including stereoscopic video).

[0120] Input human interface devices may include one or more of the following (only one of each is depicted): keyboard 701, mouse 702, touch pad 703, touch screen 710 and associated graphics adapter 750, data gloves, joystick 705, microphone 706, scanner 707, camera 708.

[0121] The computer system 700 may also include certain human-computer interface output devices. Such human-computer interface output devices may stimulate one or more human user senses through, for example, tactile output, sound, light, and smell / taste. Such human-computer interface output devices may include: tactile output devices (e.g., tactile feedback through touch screen 710, data gloves, or joystick 705, but there may also be tactile feedback devices that are not used as input devices), audio output devices (e.g., speakers 709, headphones (not depicted)), visual output devices such as screen 710, screen 710 includes cathode ray tube (CRT) screen, liquid crystal display (LCD) screen, plasma screen, organic light-emitting diode (OLED) screen, each screen has or does not have touch screen input capability, each screen has or does not have tactile feedback capability - some of which can output two-dimensional visual output or more than three-dimensional output in a manner such as stereographic output; virtual reality glasses (not depicted); holographic display and cigarette can (not depicted)) and printer (not depicted).

[0122] The computer system 700 may also include human-accessible storage devices and their associated media, such as optical media including CD / DVD ROM / RW 720 with CD / DVD or similar media 721, a thumb drive 722, a removable hard drive or solid state drive 723, traditional magnetic media such as tapes and floppy disks (not depicted), dedicated ROM / ASIC / PLD based devices such as security dongles (not depicted), etc.

[0123] Those skilled in the art should also understand that the term "computer-readable media" used in connection with the presently disclosed subject matter does not include transmission media, carrier waves, or other transient signals.

[0124] The computer system 700 may also include an interface to one or more communication networks 755. The network may be, for example, wireless, wired, optical. The network may also be local, wide, metropolitan, vehicle-mounted and industrial, real-time, delay-tolerant, etc. Examples of networks include: local area networks, such as Ethernet, wireless local area networks; cellular networks, including global systems for mobile communication (GSM), third generation (3G), fourth generation (4G), fifth generation (5G), long-term evolution (LTE), etc.; television wired or wireless wide area digital networks, including cable television, satellite television and terrestrial broadcast television; vehicle-mounted and industrial networks, including CAN bus (CANBus), etc. Some networks typically require an external network interface adapter 754 attached to some universal data port or peripheral bus 749 (such as, for example, a universal serial bus (USB) port of the computer system 700); other networks are typically integrated into the core of the computer system 700 by attaching to a system bus as described below (e.g., an Ethernet interface into a PC computer system or a cellular network interface into a smart phone computer system). As an example, a network 755 can be connected to the peripheral bus 749 using a network interface 754. The computer system 700 can use any of these networks to communicate with other entities. Such communication can be one-way receive only (e.g., broadcast television), one-way send only (e.g., CANbus to certain CANbus devices), or two-way, such as to other computer systems using local or wide area digital networks. Certain protocols and protocol stacks can be used on each of those networks and network interfaces 754 as described above.

[0125] The above-mentioned human-machine interface device, human-accessible storage device, and network interface may be attached to the core 740 of the computer system 700 .

[0126] The core 740 may include one or more central processing units (CPUs) 741, graphics processing units (GPUs) 742, dedicated programmable processing units in the form of field programmable gate arrays (FPGAs) 743, hardware accelerators 744 for certain tasks, etc. These devices, along with read-only memory (ROM) 745, random-access memory (RAM) 746, internal mass storage devices 747 such as internal non-user accessible hard drives, solid-state drives (SSDs), etc., may be connected via a system bus 748. In some computer systems, the system bus 748 may be accessed in the form of one or more physical plugs to enable expansion by additional CPUs, GPUs, etc. Peripheral devices may be attached to the core's system bus 748 directly or via a peripheral bus 749. The architecture of the peripheral bus includes peripheral component interconnect (PCI), USB, etc.

[0127] The CPU 741, GPU 742, FPGA 743, and accelerator 744 may execute certain instructions, which in combination may constitute the above-mentioned computer code. The computer code may be stored in ROM 745 or RAM 746. Transient data may also be stored in RAM 746, while permanent data may be stored in, for example, an internal mass storage device 747. Fast storage and retrieval of any of the storage devices may be achieved by using a cache memory, which may be closely associated with one or more of the CPU 741, GPU 742, mass storage device 747, ROM 745, RAM 746, etc.

[0128] The computer readable medium may have computer code thereon for performing various computer-implemented operations. The medium and computer code may be those specially designed and constructed for the purposes of the present disclosure, or the medium and computer code may be of a type well known and available to those skilled in the art of computer software.

[0129] As an example and not limitation, a computer system 700 having an architecture, and in particular a core 740, can provide functionality due to a processor (including a CPU, GPU, FPGA, accelerator, etc.) executing software contained in one or more tangible computer-readable media. Such a computer-readable medium can be a medium associated with a user-accessible mass storage device as described above and certain storage devices of the core 740 having non-transitory properties, such as a core internal mass storage device 747 or a ROM 745. Software implementing various embodiments of the present disclosure can be stored in such a device and executed by the core 740. Depending on specific needs, the computer-readable medium may include one or more memory devices or chips. The software can enable the core 740 and in particular the processor therein (including a CPU, GPU, FPGA, etc.) to perform a specific process or a specific part of a specific process described herein, including defining a data structure stored in the RAM 746 and modifying such a data structure according to a process defined by the software. Additionally or alternatively, a computer system may provide functionality due to logic contained in circuits (e.g., accelerator 744) that are hardwired or otherwise included, which logic may be used in place of software or in conjunction with software to perform a particular process or a particular portion of a particular process described herein. Where appropriate, references to software may encompass logic, and vice versa. Where appropriate, references to computer-readable media may encompass circuits (e.g., integrated circuits (ICs)) storing software for execution, circuits containing logic for execution, or both. The present disclosure encompasses any suitable combination of hardware and software.

[0130] Although the present disclosure has described several exemplary embodiments, there are changes, permutations, and various substitute equivalents that fall within the scope of the present disclosure. It will therefore be appreciated that those skilled in the art will be able to conceive of many systems and methods that, although not explicitly shown or described herein, implement the principles of the present disclosure and are therefore within the spirit and scope of the present disclosure.

Claims

1. A video encoding method, characterized in that: The method comprises: Determine whether a video coding layer VCL network abstraction layer NAL unit is the first VCL NAL unit of a picture unit PU containing the VCL NAL unit; Based on determining that the VCL NAL unit is the first VCL NAL unit of the PU, determining whether the VCL NAL unit is the first VCL NAL unit of an access unit AU including the PU; and Based on determining that the VCL NAL unit is the first VCL NAL unit of the AU, encoding the AU according to the VCL NAL unit; wherein, based on a value of all_pic_coding_info_present_in_ph_flag indicating that all picture coding information is present in a picture header, determining that a plurality of flags corresponding to the picture coding information are not signaled in a picture parameter set corresponding to the picture header, and The plurality of flags include at least one of rpl_info_in_ph_flag and wp_info_in_ph_flag.

2. The method according to claim 1, characterized in that The method further comprises: Based on determining that the VCL NAL unit is the first VCL NAL unit of the AU, determining that one or more of the following conditions are true: (1) the first value of nuh_layer_id of the VCL NAL unit is less than or equal to the second value of nuh_layer_id of the previous picture in decoding order; (2) a first value of the ph_pic_order_cnt_lsb of the VCL NAL unit is different from a second value of the ph_pic_order_cnt_lsb of a previous picture in decoding order; and (3) a first value of PicOrderCntVal derived for the VCL NAL unit is different from a second value of PicOrderCntVal of a previous picture in decoding order; and Based on determining that the one or more conditions are true, encoding the AU according to the VCL NAL unit.

3. The method according to claim 1, characterized in that: Determining that the VCL NAL unit is the first VCL NAL unit of the PU is based on at least one of the following: determining that the VCL NAL unit is the first VCL NAL unit following a picture header NAL unit, and It is determined that a flag in the VCL NAL unit is set to indicate that a picture header is included in a slice header included in the VCL NAL unit.

4. The method according to claim 1, characterized in that The VCL NAL unit is determined to be the first VCL NAL unit of the AU based on: It is determined that the VCL NAL unit is the first VCL NAL unit of the PU and that a layer identifier of the VCL NAL unit is less than another layer identifier.

5. The method according to claim 1, characterized in that: The VCL NAL unit is determined to be the first VCL NAL unit of the AU based on: It is determined that the VCL NAL unit is the first VCL NAL unit of the PU and that a picture order count of the VCL NAL unit is different from another picture order count.

6. The method according to claim 1, characterized in that The VCL NAL unit is determined to be the first VCL NAL unit of the AU based on: It is determined that the VCL NAL unit is the first VCL NAL unit of the PU and that a least significant bit of a picture order count of the VCL NAL unit is different from a least significant bit of another picture order count.

7. The method according to claim 1, characterized in that The plurality of flags include rpl_info_in_ph_flag and wp_info_in_ph_flag.

8. A method for decoding a coded video bit stream, characterized in that: The method comprises: Get the video coding layer VCL network abstraction layer NAL unit; Based on determining that the VCL NAL unit is the first VCL NAL unit of the picture unit PU of the VCL NAL unit, determining whether the VCL NAL unit is the first VCL NAL unit of the access unit AU including the PU; and Based on determining that the VCL NAL unit is the first VCL NAL unit of the AU, decoding the AU according to the VCL NAL unit; wherein, based on a value of all_pic_coding_info_present_in_ph_flag indicating that all picture coding information is present in a picture header, determining that a plurality of flags corresponding to the picture coding information are not signaled in a picture parameter set corresponding to the picture header, and The plurality of flags include at least one of rpl_info_in_ph_flag and wp_info_in_ph_flag.

9. The method according to claim 8, characterized in that The method further comprises: Based on determining that the VCL NAL unit is the first VCL NAL unit of the AU, determining that one or more of the following conditions are true: (1) the first value of nuh_layer_id of the VCL NAL unit is less than or equal to the second value of nuh_layer_id of the previous picture in decoding order; (2) a first value of the ph_pic_order_cnt_lsb of the VCL NAL unit is different from a second value of the ph_pic_order_cnt_lsb of a previous picture in decoding order; and (3) a first value of PicOrderCntVal derived for the VCL NAL unit is different from a second value of PicOrderCntVal of a previous picture in decoding order; and Based on determining that the one or more conditions are true, the AU is decoded according to the VCL NAL unit.

10. The method according to claim 8, characterized in that Determining that the VCL NAL unit is the first VCL NAL unit of the PU is based on at least one of the following: determining that the VCL NAL unit is the first VCL NAL unit following a picture header NAL unit, and It is determined that a flag in the VCL NAL unit is set to indicate that a picture header is included in a slice header included in the VCL NAL unit.

11. The method according to claim 8, characterized in that The VCL NAL unit is determined to be the first VCL NAL unit of the AU based on: It is determined that the VCL NAL unit is the first VCL NAL unit of the PU and that a layer identifier of the VCL NAL unit is less than another layer identifier.

12. The method according to claim 8, characterized in that The VCL NAL unit is determined to be the first VCL NAL unit of the AU based on: It is determined that the VCL NAL unit is the first VCL NAL unit of the PU and that a picture order count of the VCL NAL unit is different from another picture order count.

13. The method according to claim 8, characterized in that The VCL NAL unit is determined to be the first VCL NAL unit of the AU based on: It is determined that the VCL NAL unit is the first VCL NAL unit of the PU and that a least significant bit of a picture order count of the VCL NAL unit is different from a least significant bit of another picture order count.

14. The method according to claim 8, characterized in that The plurality of flags include rpl_info_in_ph_flag and wp_info_in_ph_flag.

15. An apparatus for encoding a coded video bit stream, characterized in that: The device comprises: at least one memory configured to store program code; and At least one processor is configured to read the program code and execute the method according to any one of claims 1-7.

16. An apparatus for decoding a coded video bit stream, characterized in that: The device comprises: at least one memory configured to store program code; and At least one processor is configured to read the program code and execute the method according to any one of claims 8-14.

17. A method for processing a video code stream, characterized in that: The video code stream is generated according to the encoding method described in any one of claims 1-7, or is decoded based on the decoding method described in any one of claims 8-14.

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