Vertical gate all-around (GAA) memory cells and methods of forming same

Abstract

The invention discloses a vertical gate all-around (GAA) memory cell and a method of forming the same. Various embodiments of the present disclosure relate to vertical gate all-around (GAA) memory cells. The intermediate conductor overlies the lower conductor and decreases in width toward the lower conductor to reach a point spaced apart from the lower conductor. An insulator structure is between the lower conductor and the intermediate conductor. A semiconductor channel overlies the intermediate conductor, and a gate electrode laterally surrounds the semiconductor channel on sidewalls of the semiconductor channel. A gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlies the semiconductor channel. The lower and intermediate conductors and the insulator structure correspond to the resistor, while the intermediate conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to the transistor at the top of the resistor.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly to a vertical gate all around (GAA) memory cell and a method of forming the same. Background Art

[0002] Internet of Things (IoT) devices and the like increasingly use physical unclonable function (PUF) devices to generate unique digital fingerprints. PUF devices generate unique values ​​based on randomness in the electrical characteristics of the PUF device that is inherently generated by manufacturing differences. Static random access memory (SRAM) storage cells are typically used for PUF devices. Summary of the invention

[0003] According to a first aspect of the present disclosure, a memory cell is provided, comprising: a lower conductor; an intermediate conductor overlying the lower conductor and decreasing in width toward the lower conductor to reach a point spaced apart above the lower conductor; an insulator structure between the lower conductor and the intermediate conductor; a semiconductor channel overlying the intermediate conductor; a gate electrode laterally surrounding the semiconductor channel on a sidewall of the semiconductor channel; a gate dielectric layer separating the gate electrode from the semiconductor channel; and an upper conductor at the top of the semiconductor channel.

[0004] According to a second aspect of the present disclosure, an integrated chip is provided, comprising: a first memory unit, comprising a first resistor and a first transistor on top of the first resistor, wherein the first resistor comprises a first conductor and shares a second conductor with the first transistor, and wherein the second conductor overlies the first conductor and has a first tip extending toward the first conductor; and a second memory unit, comprising a second resistor and a second transistor on top of the second resistor, wherein the second resistor comprises a third conductor and shares a fourth conductor with the second transistor, and wherein the fourth conductor overlies the third conductor and has a second tip extending toward the third conductor; wherein the first tip and the second tip have different heights.

[0005] According to a third aspect of the present disclosure, a method for forming a memory cell is provided, comprising: patterning a first dielectric layer to form a groove, the groove exposing a lower conductor; depositing an insulator layer, the insulator layer filling the groove, wherein a seam is formed and sealed in the groove during the deposition of the insulator layer; etching back the insulator layer to remove the insulator layer from above the top surface of the first dielectric layer and open the seam; forming an intermediate conductor after the etching back, the intermediate conductor filling the unfilled portion of the groove and conforming thereto; forming a semiconductor channel on top of the intermediate conductor; forming a gate electrode surrounding the semiconductor channel; and forming an upper conductor on top of the semiconductor channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood from the following specific implementations. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the sizes of various features may be arbitrarily increased or reduced.

[0007] Figure 1 Cross-sectional views of some embodiments of vertical gate all around (GAA) memory cells used as physically unclonable function (PUF) devices are shown.

[0008] Figure 2A and Figure 2B Shows Figure 1 Top layout diagram of some embodiments of vertical GAA memory cells.

[0009] Figure 3 Shows Figure 1 Circuit diagram of some embodiments of a vertical GAA memory cell.

[0010] Figure 4 Shows Figure 1 Cross-sectional view of some embodiments of an integrated chip with a vertical GAA memory cell on the front side of a logic device.

[0011] Figure 5 Shown include Figure 4 Circuit diagram of some embodiments of a memory array having multiple vertical GAA memory cells in FIG.

[0012] FIG. 6A to FIG. 6C Shows the change of vertical GAA memory cell and interconnect structure Figure 4 Cross-sectional views of some alternative embodiments of integrated chips.

[0013] Figure 7 Shown include Figure 6CCircuit diagram of some embodiments of a memory array having multiple vertical GAA memory cells in FIG.

[0014] Fig. 8A and Figure 8B Shows the change of vertical GAA memory cell and interconnect structure Figure 6C Cross-sectional views of some alternative embodiments of integrated chips.

[0015] Fig. 9 Shows Figure 1 Cross-sectional view of some embodiments of an integrated chip with a vertical GAA memory cell on the back side of a logic device.

[0016] FIG. 10A to FIG. 10C Shows the change of vertical GAA memory cell and interconnect structure Fig. 9 Cross-sectional views of some alternative embodiments of integrated chips.

[0017] Fig.11A and Fig. 11B Shows the change of vertical GAA memory cell and interconnect structure Fig. 10C Cross-sectional views of some alternative embodiments of integrated chips.

[0018] Figures 12 to 37 A series of cross-sectional views of some embodiments of methods for forming a pair of vertical GAA memory cells for use as a PUF device are shown.

[0019] Fig.38 Shows Figures 12 to 37 A block diagram of some embodiments of the method.

[0020] Figure 39 to Figure 42 Shows Figures 12 to 37 A series of cross-sectional views of some first alternative embodiments of the method.

[0021] Figures 43 to 48 Shows Figures 12 to 37 A series of cross-sectional views of some second alternative embodiments of the method.

[0022] Figures 49 to 51 A series of cross-sectional views of some embodiments of a method for forming an integrated chip with a pair of vertical GAA memory cells on the front side of a logic device are shown.

[0023] Figure 52 to Figure 64 A series of cross-sectional views of some embodiments of a method for forming an integrated chip with a pair of vertical GAA memory cells on the backside of a logic device are shown. DETAILED DESCRIPTION

[0024] The present disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0026] Static random access memory (SRAM) cells may have random differences in electrical characteristics, which are inherently caused by manufacturing variations. These random differences can be used to generate a physical unclonable function (PUF) value (e.g., "0" or "1") for each SRAM cell. For example, an SRAM cell may have a preferred state (e.g., logical "0" or logical "1") when powered on and before initialization. This preferred state may vary randomly from SRAM cell to SRAM cell due to inherent manufacturing variations, and therefore can be used as a PUF value for the SRAM cell.

[0027] The challenge of using SRAM cells as PUF devices is that SRAM cells have low stability. The electrical characteristics that generate the PUF value may change in response to environmental conditions (such as temperature, etc.). For example, the preferred state of the SRAM cell may change in response to environmental conditions. Therefore, the unique digital fingerprint generated from the PUF value of the SRAM cell may change with environmental conditions, which may cause problems because the unique digital fingerprint is expected to be constant regardless of the environmental conditions.

[0028] Various embodiments of the present disclosure relate to a vertical gate all around (GAA) memory cell used as a PUF device. In contrast to an SRAM cell, the electrical characteristics of a vertical GAA memory cell have high stability. For example, the electrical characteristics may be less affected by environmental conditions (e.g., temperature, etc.). Therefore, compared with a PUF value generated by an SRAM cell, a PUF value generated by a vertical GAA memory cell has high stability.

[0029] It has been recognized that high stability results from vertical GAA memory cells having a small number of functional elements. For example, a vertical GAA memory cell may have only two functional elements (e.g., a resistor and a transistor), whereas an SRAM cell may have six or more functional elements (e.g., six transistors). A small number of functional elements may also result in a small size and therefore a high memory density.

[0030] In some embodiments, a vertical GAA memory cell includes a resistor and a GAA transistor overlying the resistor and electrically coupled in series therewith. The resistor is formed by a pair of conductors stacked vertically and separated from each other by an insulator structure. The pair of conductors includes a first conductor and a second conductor. The second conductor overlies the first conductor and decreases in width vertically toward the first conductor to reach a point spaced above the first conductor. The resistance of the resistor varies depending on the spacing between the point and the first conductor.

[0031] It has been recognized that the spacing between the point and the first conductor has a randomness inherently generated by manufacturing variations. Therefore, the resistance of the resistor has a randomness inherently generated by manufacturing variations. This randomness can be used to generate a PUF value and thus a unique digital fingerprint. In addition, because the vertical GAA memory has high stability, the PUF value and the unique digital fingerprint can remain constant regardless of environmental conditions, etc.

[0032] refer to Figure 1 , a cross-sectional view 100 of some embodiments of a vertical GAA memory cell 102 used as a PUF device is provided. The vertical GAA memory cell 102 includes a resistor 104 and a GAA transistor 106. As will be seen below, the vertical GAA memory cell 102 can be viewed as a single transistor single resistor (1T1R) memory cell, a resistive random access memory (RRAM) memory cell, or the like.

[0033] The resistor 104 is formed by a first conductor 108 and a second conductor 110, which are stacked vertically and separated from each other by an insulator structure 112. The first conductor 108 is below the second conductor 110 and the insulator structure 112, and also has a flat or substantially flat surface facing the second conductor 110 and the insulator structure 112. The second conductor 110 extends into the insulator structure 112 toward the first conductor 108. In addition, the width W of the second conductor 110 is sc It decreases vertically toward the first conductor 108 to reach a point spaced above the first conductor 108 .

[0034] The resistance of resistor 104 varies, depending on the spacing between the point and the first conductor 108. It has been recognized that the spacing between the point and the first conductor has a randomness inherently generated by manufacturing variations. Therefore, the resistance of resistor 104 has a randomness inherently generated by manufacturing variations. This randomness can be used to generate a PUF value, and therefore a unique digital fingerprint. In addition, it has been recognized that the resistance has a high stability. For example, the resistance is not or is substantially not affected by environmental conditions. Therefore, the PUF value and the unique digital fingerprint can have a high stability.

[0035] The high stability of the PUF value and the unique digital fingerprint can be produced, for example, by the PUF value generated from a small number of functional elements. For example, a PUF value can be generated from only two functional elements (resistor 104; and GAA transistor 106). In contrast, an SRAM cell that generates a PUF value from six or more transistors can generate a PUF value with low stability. A small number of functional elements can also lead to a small size and therefore a high memory density.

[0036] GAA transistor 106 overlies resistor 104 and is electrically coupled in series therewith. In addition, GAA transistor 106 and resistor 104 share a second conductor 110. While second conductor 110 serves as the top electrode of resistor 104, second conductor 110 serves as the lower source / drain of GAA transistor 106. 源极 / 漏极可 The term "source" or "drain" may be used to refer to a source or a drain, either individually or collectively, depending on the context.

[0037] The semiconductor channel 114 overlies the second conductor 110, and the third conductor 116 overlies the semiconductor channel 114. The semiconductor channel 114 has a columnar profile extending from the second conductor 110 to the third conductor 116. The third conductor 116 is on the top surface of the semiconductor channel 114 and also on the sidewalls of the semiconductor channel 114. In an alternative embodiment, the third conductor 116 is located at the top surface of the semiconductor channel 114. In addition, the third conductor 116 serves as an upper source / drain of the GAA transistor 106. In some embodiments, the second conductor 110 serves as a drain of the GAA transistor 106, and the third conductor 116 serves as a source of the GAA transistor 106, or vice versa.

[0038] The gate electrode 118 laterally surrounds the semiconductor channel 114 on the sidewalls of the semiconductor channel 114 and has a pair of segments, at least in the cross-sectional view 100, with the semiconductor channel 114 laterally sandwiched between the pair of segments. In addition, the gate electrode 118 is vertically located between the second conductor 110 and the third conductor 116, and is laterally separated from the semiconductor channel 114 by the gate dielectric layer 120.

[0039] The dielectric structure surrounds the vertical GAA memory cell 102. In addition, the dielectric structure includes a plurality of interconnect dielectric layers 126, a first etch stop layer 128a, and a second etch stop layer 128b. The plurality of interconnect dielectric layers 126 are alternately and vertically stacked with the first etch stop layer 128a and the second etch stop layer 128b. The first etch stop layer 128a is below the gate electrode 118 and the gate dielectric layer 120, while the second etch stop layer 128b overlies the gate electrode 118 and the gate dielectric layer 120. In addition, the second etch stop layer 128b is below the third conductor 116 to separate the third conductor 116 from the gate electrode 118 and the gate dielectric layer 120.

[0040] During use of the vertical GAA memory cell 102, the gate electrode 118 can be selectively biased to change the conductivity of the semiconductor channel 114 and change the electrical coupling between the second conductor 110 and the third conductor 116. For example, under a first bias condition, the gate-source voltage can be greater than a threshold. In this way, the semiconductor channel 114 can have a high conductivity and can electrically couple the second conductor 110 and the third conductor 116 together. Under a second bias condition, the gate-source voltage can be less than a threshold. In this way, the semiconductor channel 114 can have a low conductivity and can electrically isolate the second conductor 110 and the third conductor 116 from each other.

[0041] When the semiconductor channel 114 is in the on state (e.g., due to the first bias condition described above), the resistance of the resistor 104 can be used to generate a PUF value. For example, a low voltage can be applied across the resistor 104 from the first conductor 108 to the third conductor 116, and the resulting current can be compared to a reference current to determine the PUF value. A resulting current that is less than the reference current can produce a PUF value of "0", and a resulting current that is greater than the reference current can produce a PUF value of "1", or vice versa. The low voltage can be, for example, low so that it does not cause dielectric breakdown of the insulator structure 112.

[0042] Although the foregoing discussion assumes that the vertical GAA memory cell 102 is used as a PUF device, the vertical GAA memory cell 102 is not limited to being used as a PUF device. In an alternative embodiment, the vertical GAA memory cell 102 can be used as a one-time programmable (OTP) memory cell, where the resistor 104 is an antifuse.

[0043] For example, when the vertical GAA memory cell 102 is initially formed, the vertical GAA memory cell 102 may be in a high resistance state (HRS). The HRS is subject to intrinsic randomness, which may be used to generate a PUF value as described above. In addition, the vertical GAA memory cell 102 may be irreversibly changed to a low resistance state (LRS) by applying a high voltage to the resistor 104. For example, the high voltage may burn off a portion of the insulator structure 112 that separates the tip from the first conductor 108, resulting in low conductivity from the tip to the first conductor 108. The HRS may, for example, represent a logical "0", and the LRS may, for example, represent a logical "1", or vice versa.

[0044] For example, when the semiconductor channel 114 is in a conductive state, the logic state may be determined from the resistance of the vertical GAA memory cell 102. For example, a low voltage may be applied across the resistor 104 from the first conductor 108 to the third conductor 116, and the resulting current may be compared to a reference current to determine the state of the vertical GAA memory cell 102. The low voltage may, for example, be low so that it does not cause any dielectric breakdown of the insulator structure 112.

[0045] In some embodiments, the vertical GAA memory cell 102 is one of many memory cells in multiple rows and columns. In some such embodiments, the first conductor 108 is electrically coupled to the bit line BL, the third conductor 116 is electrically coupled to the source line SL through the first via 124a, and the gate electrode 118 is electrically coupled to the word line WL through the second via 124b. The source line SL or the bit line BL can be grounded during use of the vertical GAA memory cell 102, for example.

[0046] In some embodiments, the width W of the second conductor 110 is sc The width of the second conductor 110 decreases continuously from the top surface of the second conductor 110 to the point of the second conductor 110. In some embodiments, the maximum width of the second conductor 110 is at the top surface of the second conductor 110, and / or the point of the second conductor 110 is at the bottommost height of the second conductor 110. In some embodiments, the top surface of the second conductor 110 is flush with the top surface of the isolation structure 112. In some embodiments, the maximum width of the second conductor is substantially the same as the maximum width of the insulator structure 112. In some embodiments, the width W of the second conductor 110 is greater than or equal to the maximum width of the insulator structure 112. sc Having a maximum width of about 130 to 150 nanometers, or some other suitable value.

[0047] In some embodiments, the first conductor 108 is or includes a conductive material selected from the electrode material group. In some embodiments, the second conductor 110 is or includes a conductive material selected from the electrode material group. In some embodiments, the third conductor 116 is or includes a conductive material selected from the electrode material group. In some embodiments, the gate electrode 118 is or includes a conductive material selected from the electrode material group. The electrode material group can, for example, be substantially composed of or include the following: titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), molybdenum nitride (e.g., MoN), tungsten nitride (e.g., WN), aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination of the foregoing. In some embodiments, but not all embodiments, the first conductor 108, the second conductor 110, the third conductor 116, and the gate electrode 118 are the same material (e.g., titanium nitride or some other suitable material).

[0048] In some embodiments, the insulator structure 112 is or includes hafnium oxide (e.g., HHfO2), tantalum oxide (e.g., Ta2O5), titanium oxide (e.g., TiO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), or any combination of the foregoing. In addition, in some embodiments, the insulator structure 112 is or includes silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), silicon carbonitride (e.g., SiCN), silicon carbon oxynitride (e.g., SiCON), or any combination of the foregoing.

[0049] In some embodiments, the semiconductor channel 114 is or includes amorphous silicon, indium gallium zinc oxide (IGZO), copper oxide (e.g., Cu2O), nickel oxide (e.g., NiO), tin oxide (e.g., SnO), some other suitable semiconductor material, or any combination of the foregoing. In addition, in some embodiments, the semiconductor channel 114 is doped with n-type doping or p-type doping. For example, the semiconductor channel 114 can be or include n-type amorphous silicon, p-type amorphous silicon, n-type IGZO, p-type copper oxide, p-type nickel oxide, or p-type tin oxide.

[0050] In some embodiments, the first conductor 108, the second conductor 110, and the third conductor 116 may also be regarded as a first electrode, a second electrode, and a third electrode, respectively. In addition, in some embodiments, the first conductor 108, the second conductor 110, and the third conductor 116 may also be regarded as a lower conductor or a lower electrode, a middle conductor or a middle electrode, and an upper conductor or an upper electrode, respectively.

[0051] refer to Figure 2A and Figure 2B , provides Figure 1 Top layout diagrams 200A, 200B of some embodiments of a vertical GAA memory cell 102 are shown. Figure 2A is along Figure 1 The resistor 104 in FIG. Figure 2B is along Figure 1 The first conductor 108 is intercepted by the line BB' at the GAA transistor 106 in FIG. Figure 2A and Figure 2B Shown in dashed lines to provide a common reference point.

[0052] Focus on Figure 2A , first conductor 108, second conductor 110, and insulator structure 112 have a square top geometry. In alternative embodiments, first conductor 108, second conductor 110, and insulator structure 112 have a circular top geometry, a triangular top geometry, or some other suitable top geometry. Second conductor 110 is smaller (e.g., in length and width) than insulator structure 112, and insulator structure 112 is smaller (e.g., in length and width) than first conductor 108.

[0053] Focus on Figure 2B, the gate electrode 118 and the gate dielectric layer 120 extend continuously in a closed path around the respective semiconductor channel 114, and the gate dielectric layer 120 separates the gate electrode 118 from the semiconductor channel 114. In other words, the gate electrode is "all" around the semiconductor channel 114. In alternative embodiments, the gate electrode 108 has one, two, or more breaks around the semiconductor channel 114. In addition, the semiconductor channel 114 has a square top geometry. In alternative embodiments, the semiconductor channel 114 has a circular top geometry, a triangular top geometry, or some other suitable top geometry.

[0054] refer to Figure 3 , provides Figure 1 300 of some embodiments of a vertical GAA memory cell 102. The resistor 104 and the GAA transistor 106 are electrically coupled in series such that a first (e.g., lower) source / drain of the GAA transistor 106 is electrically coupled to a first (e.g., upper) terminal of the resistor 104. In some embodiments, a second (e.g., lower) terminal of the resistor 104 is electrically coupled to a bit line BL. Furthermore, in some embodiments, a second (e.g., upper) source / drain of the GAA transistor 106 is electrically coupled to a source line SL, and a gate of the GAA transistor 106 is electrically coupled to a word line WL.

[0055] refer to Figure 4 , a cross-sectional view 400 of some embodiments of an integrated chip with a pair of vertical GAA memory cells 102 on the front side FS of a first logic device 402a is provided. Each vertical GAA memory cell 102 is as shown in FIG. Figure 1 In addition, each vertical GAA memory cell 102 may be additionally or alternatively configured as Figure 2A , Figure 2B and Figure 3 Any of or as shown in any of the subsequent figures.

[0056] The first logic device 402a overlies the semiconductor substrate 404 and is adjacent to the second logic device 402b. The front side FS of the first logic device 402a corresponds to the upper side of the first logic device 402a, which faces the interconnect structure 406. The front side FS is opposite to the back side BS of the first logic device 402a. The back side BS of the first logic device 402a corresponds to the lower side of the first logic device 402a. In some embodiments, the semiconductor substrate 404 is or includes silicon, germanium, gallium, zinc, indium, oxygen, some other suitable material, or any combination of the foregoing.

[0057] The first logic device 402a and the second logic device 402b are separated from each other by an isolation structure 408. The isolation structure 408 may be, for example, or include a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) isolation structure, some other suitable isolation structure, or any combination of the foregoing. In addition, the first logic device 402a and the second logic device 402b may be, for example, a planar field effect transistor (planar FET), a fin field effect transistor (FinFET), a gate all around (GAA) field effect transistor (GAAFET), some other suitable type of logic device and / or transistor, or any combination of the foregoing.

[0058] The first logic device 402a and the second logic device 402b include respective gate electrodes 410, respective gate dielectric layers 412, and respective source / drain region pairs 414. The source / drain region pairs 414 are inserted into the top of the semiconductor substrate 404. The gate electrodes 410 are respectively overlaid on the gate dielectric layers 412 and are respectively between the source / drain region pairs 414. In some embodiments, the first logic device 402a and the second logic device 402b further include respective wells 416. The wells 416 correspond to the doped regions of the semiconductor substrate 404 and are respectively below the source / drain region pairs 414 and the gate electrodes 410.

[0059] In some embodiments, gate electrode 410 is or includes polysilicon, silicon, titanium, tantalum, aluminum, tungsten, nitrogen, zinc, indium, gallium, germanium, carbon, some other suitable material, or any combination of the foregoing. In some embodiments, gate dielectric layer 412 is or includes silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO), lanthanum, silicon oxynitride (e.g., SiON), silicon oxynitride carbon (e.g., SiCON), zinc, zirconium, some other suitable material, or any combination of the foregoing. In some embodiments, source / drain region pair 414 is or includes silicon, germanium, carbon, phosphorus, boron, some other suitable material, or any combination of the foregoing.

[0060] The interconnect structure 406 overlies the first logic device 402a and the second logic device 402b and is electrically coupled to the first logic device 402a and the second logic device 402b at the front side FS of the first logic device 402a. The interconnect structure 406 includes a plurality of wires 418 and a plurality of vias 124. The plurality of wires 418 are grouped into a plurality of wire layers, and the plurality of vias 124 are grouped into a plurality of via layers stacked alternately with the plurality of wire layers. The wire layers are labeled M1, M2, etc. to M6 from the bottom of the interconnect structure 406 to the top of the interconnect structure 406. The via layers are labeled V0, V1, etc. to V5 from the bottom of the interconnect structure 406 to the top of the interconnect structure 406.

[0061] The dielectric structure surrounds the interconnect structure 406 and includes a plurality of interconnect dielectric layers 126, a first etch stop layer 128a, and a second etch stop layer 128b. The plurality of interconnect dielectric layers 126 are alternately and vertically stacked with the first etch stop layer 128a and the second etch stop layer 128b. In some embodiments, the first etch stop layer 128a and the second etch stop layer 128b are or include silicon nitride, silicon carbide, some other suitable dielectric, or any combination of the foregoing. In some embodiments, the plurality of interconnect dielectric layers 126 are or include undoped silicate glass (USG), borosilicate glass (BSG), silicon oxide, some other suitable dielectric, or any combination of the foregoing.

[0062] The pair of vertical GAA memory cells 102 are located vertically between the wire layer M3 and the wire layer M4 in the interconnect structure 406. In an alternative embodiment, the pair of vertical GAA memory cells 102 are located between different wire levels. In addition, in an alternative embodiment, the interconnect structure 406 includes more or fewer wire layers and / or more or fewer via layers. Therefore, the pair of vertical GAA memory cells 102 can be more generally referred to as being located vertically between the wire layer M3 and the wire layer M4. x and conductor layer M x+1 Where x is an integer representing the number of conductor layers, such as 3 or some other suitable number.

[0063] As described above, each vertical GAA memory cell 102 is Figure 1 As shown, and for example, it may additionally or alternatively be as Figure 2A , Figure 2B and Figure 3 Thus, the vertical GAA memory cell 102 includes a respective first conductor 108 , a respective second conductor 110 , a respective third conductor 116 , a respective semiconductor channel 114 , a respective gate electrode 118 , and a respective gate dielectric layer 120 .

[0064] The first conductor 108 is shared with the interconnect structure 406 and corresponds to the wire at the wire layer M3. In some embodiments, the first conductor 108 is electrically coupled to or otherwise corresponds to the common bit line BL, which is located at Figure 4 The first conductors 108 extend continuously between the vertical GAA memory cells 102 outside the cross-sectional view 400. In other embodiments, the first conductors 108 are electrically coupled to or correspond to respective bit lines BL.

[0065] The second conductors 110 overlie the first conductors 108, respectively, and have respective tips extending toward the first conductors 108. In addition, the tips are separated from the first conductors 108 by different distances due to randomness inherently generated by manufacturing variations. Therefore, the vertical GAA memory cell 102 has different resistances as described above. In some embodiments, the second conductors 110 have respective different heights and / or cross-sectional areas due to randomness inherently generated by manufacturing variations.

[0066] The third conductors 116 respectively overlie the semiconductor channels 114, and the gate electrodes 118 respectively surround the semiconductor channels 114 laterally. In addition, the vias at the via layer V3 extend from the third conductors 116 and the gate electrodes 118 to the wires at the wire layer M4. In some embodiments, the wires to which the gate electrodes 118 at the wire layer M4 are electrically coupled correspond to the word lines WL. In addition, in some embodiments, the third conductors 116 are electrically coupled to the common wires at the wire layer M5, and the common wires correspond to the source lines SL.

[0067] refer to Figure 5 , provides multiple Figure 4 500 of some embodiments of a memory array of vertical GAA memory cells 102 in FIG. More specifically, a plurality of vertical GAA memory cells 102 are grouped into non-overlapping pairs along a row, and each pair of vertical GAA memory cells is as follows: Figure 4 In addition, each of the plurality of vertical GAA memory cells 102 may additionally or alternatively be as follows: Figure 1 , Figure 2A ,, Figure 2B and Figure 3 Any of or as shown in any of the subsequent figures.

[0068] The memory array has M rows and N columns, where M and N are integers. In addition, the memory array has M bit lines corresponding one-to-one with the M rows, M source lines corresponding one-to-one with the M rows, and N word lines corresponding one-to-one with the N columns. However, other correspondences (e.g., one-to-two) are acceptable in alternative embodiments, as will be seen below. The bit lines are labeled BL1, BL2, etc. until BL M , where the subscripts correspond to the row numbers. The source lines are labeled SL1, SL2, and so on until SL M , where the subscripts correspond to the line numbers. The word lines are labeled WL1, WL2, and so on up to WL N , where the subscripts correspond to the column numbers.

[0069] The source line of any given row is electrically coupled to the source / drain of each GAA transistor 106 in the given row, and the bit line of any given row is electrically coupled to the terminal of each resistor 104 in the given row. The word line of any given column is electrically coupled to the gate electrode of each GAA transistor 106 in the given column.

[0070] As described above, the GAA transistor is selectively turned on, depending on how the corresponding gate electrode is biased. When the GAA transistor of the vertical GAA memory cell is in a conducting state, the vertical GAA memory cell can be considered to be selected. When the GAA transistor of the vertical GAA memory cell is in a non-conducting state, the vertical GAA memory cell can be considered to be unselected. Therefore, because the word line allows the bias conditions at the gate electrode of the GAA transistor to be controlled, the word line of a given column allows the vertical GAA memory cells in the column to be selected for read and / or write operations. In this way, the GAA transistor 106 of the vertical GAA memory cell 102 can also be referred to as a selection transistor, an access transistor, etc.

[0071] The vertical GAA memory cells 102 can be used as PUF devices and / or OTP memory cells. For example, the vertical GAA memory cells in the first row of the memory array can be used as PUF devices, while the vertical GAA memory cells in the remaining rows of the memory array can be used as OTP memory cells. As another example, all vertical GAA memory cells 102 can be used as PUF devices or as OTP memory cells. Due to the small number of functional elements (e.g., resistors and transistors) per memory cell and because of the vertical stacking of these functional elements, the memory density can be high.

[0072] The vertical GAA memory cells used as PUF devices can have respective PUF values ​​which are connected in series to generate a unique digital fingerprint. The PUF device is in a HRS with inherent randomness. The PUF value of the PUF device can be determined by selecting the PUF device using the corresponding word line and then applying a low voltage on the resistor of the PUF device using the corresponding source line and bit line. The resulting current is then compared with a reference current to determine the PUF value. The low voltage can, for example, be low so that it does not cause dielectric breakdown of the resistor.

[0073] The vertical GAA memory cell used as an OTP memory cell can have respective logic values, which are used to store data. The OTP memory cell is in HRS when formed and can be irreversibly changed to LRS. The OTP memory cell can be irreversibly changed to LRS by selecting the OTP memory cell using the corresponding word line. Then a high voltage is applied to the resistor of the OTP memory cell using the corresponding bit line and source line to irreversibly break down the dielectric of the resistor. The state of the OTP memory cell (e.g., LRS or HRS) can be determined by selecting the OTP memory cell using the corresponding word line and then applying a low voltage to the resistor of the OTP memory cell using the corresponding source line and bit line. Then, the generated current is compared with the reference current to determine whether the OTP memory cell is in HRS or in LRS. The low voltage is low compared to the high voltage and does not cause dielectric breakdown of the resistor.

[0074] refer to FIG. 6A to FIG. 6C , providing a change in the pair of vertical GAA memory cells 102 and the interconnect structure 406 Figure 4 Cross-sectional views 600A to 600C of some alternative embodiments of integrated chips.

[0075] exist Fig. 6A , the vias at the via layer V3 extend from the gate electrode 118 to the wires at the wire layer M4. In addition, the vias at the via layer V4 extend from the third conductor 116 to the wires at the wire layer M5. Therefore, the vias at the gate electrode 118 are in a different via layer from the vias at the third conductor 116.

[0076] exist Figure 6B In the embodiment, the second conductors 110 are integrated with the semiconductor channels 114, respectively. In other words, each second conductor and its corresponding semiconductor channel are formed by a common semiconductor structure. In some embodiments, the second conductors 110 have a doping concentration of p-type or n-type dopant increased relative to the semiconductor channels 114.

[0077] exist Figure 6C In FIG. 1 , the pair of vertical GAA memory cells 102 share a common word line WL, a common gate electrode 118 , and a common gate dielectric layer 120 .

[0078] refer to Figure 7 , provides multiple Figure 6C 700 of some embodiments of a memory array of vertical GAA memory cells 102 in FIG. More specifically, a plurality of vertical GAA memory cells 102 are grouped into non-overlapping pairs along a row, and each pair of vertical GAA memory cells is as follows: Figure 6C shown.

[0079] refer to Fig. 8A and Figure 8B , providing a change in the pair of vertical GAA memory cells 102 and the interconnect structure 406 Figure 6C Cross-sectional views 800A, 800B of some alternative embodiments of an integrated chip.

[0080] exist Fig. 8A , the vias at the via layer V3 extend from the gate electrode 118 to the wires at the wire layer M4. In addition, the vias at the via layer V4 extend from the third conductor 116 to the wires at the wire layer M5. Therefore, the vias at the gate electrode 118 are in a different via layer from the vias at the third conductor 116.

[0081] exist Figure 8B In the embodiment, the second conductors 110 are integrated with the semiconductor channels 114, respectively. In other words, each second conductor and its corresponding semiconductor channel are formed by a common semiconductor structure. In some embodiments, the second conductors 110 have a doping concentration of p-type or n-type dopant increased relative to the semiconductor channels 114.

[0082] refer to Fig. 9 , a cross-sectional view 900 of some embodiments of an integrated chip with a pair of vertical GAA memory cells 102 on the back side BS of a first logic device 902a is provided. Each vertical GAA memory cell 102 is as shown Figure 1 In addition, each vertical GAA memory cell 102 may be additionally or alternatively configured as Figure 2A , Figure 2B and Figure 3 Any of or as shown in any of the subsequent figures.

[0083] The first logic device 902a overlies the carrier substrate 904 and is adjacent to the second logic device 902b. The front side FS of the first logic device 902a corresponds to the lower side of the first logic device 902a and faces the first interconnect structure 906. In addition, the front side FS is opposite to the back side BS of the first logic device 902a. The back side BS corresponds to the upper side of the first logic device 902a and faces the second interconnect structure 406. In addition, the back side BS is surrounded by an isolation structure 907.

[0084] In some embodiments, the carrier substrate 904 is a semiconductor substrate and / or some other suitable type of carrier substrate. In addition, in some embodiments, the semiconductor substrate 904 is or includes silicon, germanium, gallium, zinc, indium, oxygen, some other suitable material, or any combination of the foregoing. In some embodiments, the isolation structure 907 is or includes an STI structure and / or some other suitable isolation structure.

[0085] The first logic device 902a and the second logic device 902b are GAA FETs. However, the first logic device 902a and the second logic device 902b may alternatively be, for example, planar FETs, FinFETs, some other suitable type of logic device and / or transistor, or any combination of the foregoing. The first logic device 902a and the second logic device 902b include respective multiple semiconductor channels 908, respective protection layers 910, respective gate electrodes 912, respective gate dielectric layers 914, and corresponding source / drain regions 916.

[0086] The semiconductor channels 908 of a given one of the first logic device 902a and the second logic device 902b are stacked vertically and covered by a corresponding one of the protection layers 910. In addition, the semiconductor channels 908 of a given one of the first logic device 902a and the second logic device 902b are laterally sandwiched between two source / drain regions 916 and are vertically separated from each other by a corresponding one of the gate electrodes 912. As shown, the first logic device 902a and the second logic device 902b share a source / drain region 916, but this may not be the case in alternative embodiments. The gate electrodes 912 are separated from the semiconductor channels 908 by gate dielectric layers 914, respectively.

[0087] In some embodiments, the first logic device 902a and the second logic device 902b further include respective first spacer structures 918, respective second spacer structures 920, and respective third spacer structures 922. The first spacer structures 918 are on the sidewalls of the gate electrode 912, separating the corresponding semiconductor channels 908 from each other. The second spacer structures 920 and the third spacer structures 922 are below the semiconductor channels 908. In addition, the second spacer structure 920 is on the sidewalls of the gate electrode 912, and the third spacer structure 922 is on the sidewalls of the second spacer structure 920.

[0088] In some embodiments, the gate electrode 912 is or includes polysilicon, silicon, titanium, tantalum, aluminum, tungsten, nitrogen, zinc, indium, gallium, germanium, carbon, some other suitable material, or any combination of the foregoing. In some embodiments, the gate dielectric layer 914 is or includes silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO), lanthanum, silicon oxynitride (e.g., SiON), silicon oxynitride carbon (e.g., SiCON), zinc, zirconium, some other suitable material, or any combination of the foregoing. In some embodiments, the source / drain region pair 916 is or includes silicon, germanium, carbon, phosphorus, boron, some other suitable material, or any combination of the foregoing.

[0089] The first interconnect structure 906 is below the first logic device 902a and the second logic device 902b and is electrically coupled to the first logic device 902a and the second logic device 902b on the front side of the first logic device 902a. The first interconnect structure 906 includes a plurality of conductive features, including a plurality of first-layer contacts 924, a plurality of second-layer contacts 926, conductive lines 928, and vias 930. The second-layer contacts 926 are below and spaced apart from the gate electrode 912, and the first-layer contacts 924 extend from the second-layer contacts 926 to the gate electrode 912. The conductive lines 928 are spaced apart below the second-layer contacts 926, and the vias 930 extend from the conductive lines 928 to a corresponding one of the second-layer contacts 926.

[0090] In some embodiments, the wire 928 can also be considered as a redistribution layer (RDL). Although only one wire and one via are shown, more wires and / or more vias are acceptable. In addition, although only one via layer and one wire layer are shown, more via layers and / or more wire layers are acceptable. In such an embodiment, the wire layer and the via layer are alternately stacked away from the second layer contact 926.

[0091] The heat sink conductor 932 overlies the carrier substrate 904 and is bonded to the wire 928 at a bonding interface 934 to facilitate heat dissipation. In an alternative embodiment, the heat sink conductor 932 is omitted. The bonding interface 934 includes a conductor-to-conductor component (e.g., at the heat sink conductor 932) and a dielectric-to-dielectric component (e.g., at a dielectric layer discussed below).

[0092] The dielectric structure surrounds the first interconnect structure 906, the front sides of the first logic device 902a and the second logic device 902b, and the heat sink conductor 932. The dielectric structure includes an interlayer dielectric (ILD) layer 936, a plurality of interconnect dielectric layers 938, a plurality of etch stop layers 940, and a bonding dielectric layer 942 stacked vertically on the carrier substrate 904. In some embodiments, the etch stop layer 940 is or includes silicon nitride, silicon carbide, some other suitable dielectric, or any combination of the foregoing. In some embodiments, the ILD layer 936, the plurality of interconnect dielectric layers 938, and the bonding dielectric layer 942 are each or include a dielectric from the following group, the group consisting essentially of or including the following: USG, BSG, silicon oxide, some other suitable dielectric, or any combination of the foregoing.

[0093] The second interconnect structure 406 overlies the first logic device 902a and the second logic device 902b and is electrically coupled to the first logic device 902a and the second logic device 902b at the back side BS of the first logic device 902a. In some embodiments, the second interconnect structure 406 is electrically coupled to the first logic device 902a and the second logic device 902b through a source / drain region 916 shared by the first logic device 902a and the second logic device 902b. In addition to the corresponding portion of the second interconnect structure 406 as described below, the second interconnect structure 406 is also as described with respect to Figure 4 The corresponding part described.

[0094] The second interconnect structure 406 includes a plurality of wires 418 and a plurality of vias 124, which are grouped into a plurality of wire layers and a plurality of via layers, respectively. The wire layers are labeled M0, M1, etc. from the bottom of the second interconnect structure 406 to the top of the second interconnect structure 406 until M5. The via layers are labeled V0, V1, etc. from the bottom of the second interconnect structure 406 to the top of the second interconnect structure 406 until V4. In addition, the second interconnect structure 406 includes a contact plug 944, which extends from the wire layer M0 to the first logic device 902a and the second logic device 902b. For example, the contact plug 944 can extend to a source / drain region 916 shared by the first logic device 902a and the second logic device 902b. In some embodiments, the contact plug 944 can be regarded as a backside power rail, etc. In some embodiments, the contact plug 944 is or includes tungsten, tungsten nitride, ruthenium, iridium, molybdenum, molybdenum nitride, copper, aluminum, silicon, or any combination of the foregoing items.

[0095] The dielectric structure surrounds the second interconnect structure 406 and includes a plurality of interconnect dielectric layers 126, a first etch stop layer 128a, and a second etch stop layer 128b. In addition, the plurality of interconnect dielectric layers 126 and the first etch stop layer 128a and the second etch stop layer 128b are alternately and vertically stacked.

[0096] The pair of vertical GAA memory cells 102 are vertically located between the conductive line layer M2 and the conductive line layer M3 in the second interconnect structure 406. In alternative embodiments, the pair of vertical GAA memory cells 102 are located between different conductive line layers, and / or the second interconnect structure 406 includes more or fewer conductive line layers and / or more or fewer via layers. As described above, each vertical GAA memory cell 102 is vertically located between the conductive line layer M2 and the conductive line layer M3. Figure 1 As shown, and for example, it may additionally or alternatively be as Figure 2A , Figure 2B and Figure 3Thus, the vertical GAA memory cell 102 includes a respective first conductor 108 , a respective second conductor 110 , a respective third conductor 116 , a respective semiconductor channel 114 , a respective gate electrode 118 , and a respective gate dielectric layer 120 .

[0097] refer to FIG. 10A to FIG. 10C , providing a change in the pair of vertical GAA memory cells 102 and the interconnect structure 406 Fig. 9 Cross-sectional views 1000A to 1000C of some alternative embodiments of an integrated chip.

[0098] exist Fig. 10A , the vias at the via layer V2 extend from the gate electrode 118 to the wires at the wire layer M3. In addition, the vias at the via layer V3 extend from the third conductor 116 to the wires at the wire layer M4. Therefore, the vias at the gate electrode 118 are at a different via layer from the vias at the third conductor 116.

[0099] exist Fig. 10B In the embodiment, the second conductors 110 are integrated with the semiconductor channels 114, respectively. In other words, each second conductor and its corresponding semiconductor channel are formed by a common semiconductor structure. In some embodiments, the second conductors 110 have a doping concentration of p-type or n-type dopant increased relative to the semiconductor channels 114.

[0100] exist Fig. 10C In the embodiment, the pair of vertical GAA memory cells 102 share a common word line WL, a common gate electrode 118 and a common gate dielectric layer 120. The vertical GAA memory cell 102 may be, for example, Figure 7 A portion of a memory array is shown.

[0101] refer to Fig.11A and Fig. 11B , providing a change in the pair of vertical GAA memory cells 102 and the interconnect structure 406 Fig. 10C Cross-sectional views 1100A, 1100B of some alternative embodiments of an integrated chip.

[0102] exist Fig.11A , the vias at the via layer V2 extend from the gate electrode 118 to the wires at the wire layer M3. In addition, the vias at the via layer V3 extend from the third conductor 116 to the wires at the wire layer M4. Therefore, the vias at the gate electrode 118 are at a different via layer from the vias at the third conductor 116.

[0103] exist Fig. 11BIn the embodiment, the second conductors 110 are integrated with the semiconductor channels 114, respectively. In other words, each second conductor and its corresponding semiconductor channel are formed by a common semiconductor structure. In some embodiments, the second conductors 110 have a doping concentration of p-type or n-type dopant increased relative to the semiconductor channels 114.

[0104] refer to Figures 12 to 37 , a series of cross-sectional views 1200 to 3700 of some embodiments of a method for forming a pair of vertical GAA memory cells used as a PUF device are provided. The pair of vertical GAA memory cells may be, for example, Figure 1 , Figure 4 and Fig. 9 In addition, the pair of vertical GAA memory cells may have, for example, Figure 2A and / or Figure 2B The top layout in .

[0105] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a pair of first conductors 108 covered by the first interconnect dielectric layer 126a is provided or otherwise formed. The pair of first conductors 108 correspond to the wires 418 of the interconnect structure and are formed in the wire layer M x , where x is an integer representing the number of conductor layers.

[0106] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , the first interconnect dielectric layer 126 a is patterned to form a pair of trenches 1302 that overlie the first conductor 108 and expose the first conductor 108, respectively. In some embodiments, the width W of each trench 1302 is tr The thickness of the nanostructured carbon fiber is about 130 to 150 nanometers or some other suitable value. The patterning can be performed, for example, by a photolithography / etching process or some other suitable process.

[0107] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14 , the insulator layer 1121 is deposited to cover the first interconnect dielectric layer 126a and line the trench 1302. The deposition may be performed, for example, by physical vapor deposition (PVD), high growth rate chemical vapor deposition (CVD), or some other suitable deposition method.

[0108] During the deposition of the insulator layer 1121, the material of the insulator layer 1121 is deposited faster at the top corners of the first interconnect dielectric layer 126a in the trench 1302. As a result, the trench 1302 is closed before being fully formed, and a pair of seams 1402 are formed in the trenches 1302, respectively. Due to the inherent randomness in the deposition of the insulator layer 1121, the seams 1402 may have different depths, cross-sectional areas, heights, etc. As will be seen below, this randomness allows the generation of PUF values.

[0109] In some embodiments, the insulator layer 1121 is a high-k dielectric material and / or is or includes hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, or any combination of the foregoing. In some embodiments, the insulator layer 1121 is or includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxynitride carbon, or any combination of the foregoing.

[0110] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 15, the insulator layer 1121 is etched back. This removes the insulator layer 1121 from the top of the first interconnect dielectric layer 126a and forms a pair of insulator structures 112 in the trenches 1302, respectively. The insulator structures 112 only partially fill the trenches 1302 due to the seams 1402. In addition, the unfilled portions of the trenches 1302 have respective profiles that decrease in width toward the first conductor 108 and reach a point that points toward the first conductor 108.

[0111] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , the conductive layer 1101 is deposited to cover the first interconnect dielectric layer 126a and fill the remaining portion of the trench 1302 above the insulator structure 112. The conductive layer 1101 can be deposited, for example, by atomic layer deposition (ALD) or some other suitable deposition process. In some embodiments, the conductive layer 1101 is or includes titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination of the foregoing.

[0112] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , planarization is performed in the conductive layer 1101. The planarization may be performed, for example, by chemical mechanical polishing (CMP) or some other suitable planarization process.

[0113] The planarization removes the conductive layer 1101 from the top of the first interconnect dielectric layer 126a and forms a pair of second conductors 110. The second conductors 110 are respectively overlying the first conductors 108 and are separated from the first conductors 108 by the insulator structure 112. In addition, the width of the second conductors 110 decreases from the top of the first interconnect dielectric layer 126a toward the first conductor 108 to reach a point.

[0114] The first conductor 108, the insulator structure 112 and the second conductor 110 together form a pair of resistors 104. Fig.14 ) dimensions, the second conductor 110 has inherent randomness in height, cross-sectional area, spacing from the first conductor 108, etc. This inherent randomness results in inherent randomness in the resistance of the resistor 104, which can be used to generate a PUF value and thus a unique digital fingerprint.

[0115] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , a first etch stop layer 128a is deposited on top of the first interconnect dielectric layer 126a and the resistor 104. The first etch stop layer 128a is a dielectric material different from the first interconnect dielectric layer 126a. In some embodiments, the first etch stop layer 128a is or includes silicon nitride, silicon carbide, silicon oxynitride, some other suitable material, or any combination of the foregoing.

[0116] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , the first etch stop layer 128a is patterned to form a pair of openings 1902 overlying the second conductor 110 and respectively exposing the second conductor 110. The patterning may be performed, for example, by a photolithography / etching process or some other suitable process.

[0117] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , a semiconductor layer 2002 is deposited on top of the first etch stop layer 128a and fills the opening 1902 at the top of the resistor 104. In some embodiments, the top surface of the semiconductor layer 2002 is further flattened by planarization or the like. For example, the planarization can be performed by CMP and / or some other suitable planarization process.

[0118] In some embodiments, semiconductor layer 2002 is or includes amorphous silicon, indium gallium zinc oxide, copper oxide, nickel oxide, tin oxide, some other suitable semiconductor material, or any combination of the foregoing. In addition, in some embodiments, semiconductor layer 2002 is doped with n-type doping or p-type doping. For example, semiconductor layer 2002 can be or include n-type amorphous silicon, p-type amorphous silicon, n-type indium gallium zinc oxide, p-type copper oxide, p-type nickel oxide, or p-type tin oxide. However, other suitable materials are also acceptable.

[0119] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 1 , the semiconductor layer 2002 is patterned to form a pair of semiconductor channels 114 on the resistor 104, respectively. In some embodiments, the patterning enables the semiconductor channels 114 to have a shape similar to the opening 1902 (see FIG. 1 ). Fig.19 ) have the same or similar widths. The patterning can be performed, for example, by a photolithography / etching process or some other suitable process. To the extent that the patterning is performed by a photolithography / etching process, the first etch stop layer 128a can be used, for example, as an etch stop during etching of the semiconductor layer 2002.

[0120] like Fig. 22As shown in the cross-sectional view 2200 of FIG. 2 , the dielectric layer 1201 and the conductive layer 1181 are deposited to overlie the first etch stop layer 128a and the semiconductor channel 114, and further line the sidewalls of the semiconductor channel 114. The dielectric layer 1201 can be deposited, for example, by ALD and / or some other suitable deposition process. The conductive layer 1181 is deposited on the dielectric layer 1201, and can be deposited, for example, by ALD and / or some other suitable deposition process.

[0121] In some embodiments, the conductive layer 1181 is or includes titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination of the foregoing. In some embodiments, the dielectric layer 1201 is or includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxynitride carbon, or any combination of the foregoing.

[0122] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 23, the conductive layer 1181 and the dielectric layer 1201 are patterned to form a pair of gate stacks for each of the semiconductor channels 114. Alternatively, the patterning forms a single continuous gate stack common to the semiconductor channels 114, such as Figure 6C , Fig. 8A , Figure 8B , Fig. 10C , Fig.11A ,or Fig. 11B Each gate stack includes a gate electrode 118 formed of a conductive layer 118l, and each gate stack also includes a gate dielectric layer 120 formed of a dielectric layer 120l. The gate stack is on the sidewall of the semiconductor channel 114, and in some embodiments, when viewed from above, completely surrounds the corresponding semiconductor channel. For example, see Figure 2B The patterning may be performed, for example, by a photolithography / etching process or some other suitable process.

[0123] like Fig.24 As shown in the cross-sectional view 2400 , the second interconnect dielectric layer 126 b is deposited to cover the gate electrode 118 and the first etch stop layer 128 b , and also along the sidewalls of the gate electrode 118 .

[0124] like Fig.25 As shown in the cross-sectional view 2500 of , planarization is performed in the second interconnect dielectric layer 126b. The planarization flattens the top surface of the second interconnect dielectric layer 126b and recesses the top surface until it is flush with the top surface of the gate electrode 118. For example, the planarization can be performed by CMP and / or some other suitable planarization process.

[0125] like Fig.26As shown in the cross-sectional view 2600 of FIG. 26 , an etch back is performed to recess the top surface of the second interconnect dielectric layer 126 b relative to the top surface of each of the gate electrodes 118. The etch back exposes the upper sidewall portion of the gate electrode 118, while leaving the lower sidewall portion covered by the second interconnect dielectric layer 126 b. The etch back can be performed, for example, using an etchant having a high etching rate for the second interconnect dielectric layer 126 b relative to the gate electrode 118, so that the gate electrode 118 is minimally etched.

[0126] like Fig. 27 As shown in the cross-sectional view 2700 of FIG. 27 , another back etch is performed to recess the respective top surfaces of the gate electrodes 118 and the respective top surfaces of the gate dielectric layer 120 relative to the respective surfaces of the semiconductor channel 114. In some embodiments, the respective top surfaces of the gate electrodes 118 and the respective top surfaces of the gate dielectric layer 120 are etched back until they are flush or substantially flush with the top surface of the second interconnect dielectric layer 126b. The back etch can be performed, for example, using an etchant having a high etching rate for the gate electrodes 118 and the gate dielectric layer 120 relative to the semiconductor channel 114 and the second interconnect dielectric layer 126b, so that the semiconductor channel 114 and the second interconnect dielectric layer 126b are minimally etched.

[0127] like Fig.28 As shown in the cross-sectional view 2800 of , the second etch stop layer 128b is deposited to overlie the second interconnect dielectric layer 126b and the semiconductor channel 114, and also to line the sidewalls of the semiconductor channel 114. The second etch stop layer 128b is a dielectric material, and is a different dielectric material type from the second interconnect dielectric layer 126b. In some embodiments, the second interconnect dielectric layer 126b is or includes silicon nitride, silicon carbide, silicon oxynitride, some other suitable material, or any combination of the foregoing.

[0128] like Fig.29 As shown in the cross-sectional view 2900 of FIG. 29 , the second etch stop layer 128 b is patterned to remove the second etch stop layer 128 b from the top of the semiconductor channel 114. In addition, the patterning partially removes the second etch stop layer 128 b from the sidewalls of the semiconductor channel 114. In some embodiments, after patterning, the second etch stop layer 128 b has a substantially uniform height throughout. The patterning can be performed, for example, by a photolithography / etching process or some other suitable process.

[0129] like Fig.30As shown in the cross-sectional view 3000 of FIG. 1 , the conductive layer 1161 is deposited to overlie the second etch stop layer 128b and the semiconductor channel 114, and also to line the sidewalls of the semiconductor channel 114. The conductive layer 1161 may be deposited, for example, by ALD and / or some other suitable deposition process. In some embodiments, the conductive layer 1161 is or includes titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination of the foregoing.

[0130] like Fig.31 As shown in the cross-sectional view 3100 of FIG. 3100 , the conductive layer 1161 is patterned to form a pair of third conductors 116 on the semiconductor channel 114, respectively. The patterning can be performed, for example, by a photolithography / etching process or some other suitable process. Insofar as the patterning is performed by a photolithography / etching process, the second etch stop layer 128b can be used as an etch stop during etching of the conductive layer 1161, for example.

[0131] The second conductor 110, the semiconductor channel 114, the third conductor 116, the gate electrode 118 and the gate dielectric layer 120 jointly form a pair of GAA transistors 106 on the resistor 104. In addition, the resistor 104 and the GAA transistor 106 form a pair of vertical GAA memory cells 102. The vertical GAA memory cell 102 can be used as a PUF device and / or an OTP memory cell, for example.

[0132] The resistance of the vertical GAA memory cell 102 may have inherent randomness due to manufacturing variations. This is shown by the different distances from the points of the second conductor 110 to the first conductor 108 below, respectively. The larger the distance, the more dielectric material separates the first conductor from the second conductor, and thus the greater the resistance. The smaller the distance, the less dielectric material separates the first conductor from the second conductor, and thus the smaller the resistance. Therefore, when the vertical GAA memory cell is used as a PUF device, the resistance can be used to generate a PUF value.

[0133] In some embodiments, the PUF value of the vertical GAA memory cell is generated by applying a low voltage across a resistor of the vertical GAA memory cell and comparing the resulting current to a reference current. A resulting current less than the reference current may generate a PUF value of "0", and a resulting current greater than the reference current may generate a PUF value of "1", or vice versa. The low voltage may be, for example, low so that it does not cause dielectric breakdown of the insulator structure.

[0134] It is known that the resistance of the vertical GAA memory cell 102 has a high stability. For example, the resistance is not or is substantially not affected by environmental conditions. Therefore, the PUF value can have a high stability. The high stability of the PUF value can be generated, for example, by a PUF value generated from a small number of functional elements. For example, a PUF value can be generated from only two functional elements (a resistor; and a GAA transistor). In contrast, an SRAM cell that generates a PUF value from six or more transistors can generate a PUF value with low stability.

[0135] When the vertical GAA memory cell 102 is formed as above, the vertical GAA memory cell 102 is in HRS. However, the vertical GAA memory cell can be irreversibly changed to LRS by applying a high voltage to the resistor of the vertical GAA memory cell. The high voltage burns off the portion of the insulator structure that separates the tip of the second conductor from the first conductor, resulting in low conductivity from the tip to the first conductor. HRS and LRS can be used to represent data when the vertical GAA memory cell is used as an OTP memory cell. HRS can represent a logical "0", for example, and LRS can represent a logical "1", for example, or vice versa.

[0136] like Fig.32 As shown in the cross-sectional view 3200, the third interconnect dielectric layer 126c is deposited to cover the third conductor 116 and the second etch stop layer 128b.

[0137] like Fig.33 As shown in the cross-sectional view 3300 of FIG. 3300 , planarization is performed in the third interconnect dielectric layer 126 c to flatten the top surface of the third interconnect dielectric layer 126 c. For example, the planarization can be performed by CMP and / or some other suitable planarization process.

[0138] like Fig.34 As shown in the cross-sectional view 3400, the through hole 124 of the interconnect structure and the additional conductive line 418 of the interconnect structure are formed in the second interconnect dielectric layer 126b and the third interconnect dielectric layer 126c and the second etch stop layer 128b. The additional conductive line 418 forms a conductive line layer 418 on top of the third interconnect dielectric layer 126c. x+1 The through hole 124 is in the conductor layer M x and conductor layer M x+1 Through hole layer V y , and extend from the additional wire 418 to the gate electrode 118 and the third conductor 116, respectively. x is an integer representing the number of wire layers, and y is an integer representing the number of via layers.

[0139] For forming the through hole layer V y and conductor layer M x+1The process may include, for example, patterning the second interconnect dielectric layer 126b and the third interconnect dielectric layer 126c and the second etch stop layer 128b to form a dielectric layer having the same dielectric layer as the via layer V. y and conductor layer M x+1 Thereafter, a conductive layer may be deposited to fill the opening, and planarization may be performed to make the top surface of the conductive layer flush with the top surface of the third interconnect dielectric layer 126c. However, other suitable methods are also acceptable.

[0140] like Fig.35 As shown in the cross-sectional view 3500, additional dielectric material is deposited to make the third interconnect dielectric layer 126c on the conductor layer M x+1 Furthermore, in some embodiments, planarization is performed to flatten the top surface of the third interconnect dielectric layer 126 c. For example, the planarization may be performed by CMP and / or some other suitable planarization process.

[0141] like Fig.36 As shown in the cross-sectional view 3600 of FIG. 36A , an additional through hole 124 of the interconnect structure and an additional conductive line 418 of the interconnect structure are formed in the third interconnect dielectric layer 126 c. The additional conductive line 418 forms a conductive line layer 414 on top of the third interconnect dielectric layer 126 c. x+2 The additional through hole 124 is provided in the conductor layer M x+1 and conductor layer M x+2 Through hole layer V y+1 , to interconnect these wire layers. x is an integer representing the number of wire layers, and y is an integer representing the number of via layers. y+1 and conductor layer M x+2 The process can be used to form the via layer V y and conductor layer M x+1 However, other suitable methods are also acceptable.

[0142] like Fig.37 As shown in the cross-sectional view 3700, repeat about Fig.35 and Fig.36 Repeating these actions further extends the third interconnect dielectric layer 126c and forms additional vias 124 and additional conductive lines 418, which are grouped into via layers V and V, respectively. y+2 and conductor layer M x+3 It is worth noting that the through hole layer V y+2 The through hole at Fig.37 In an alternative embodiment, the cross-sectional view 3700 is not repeated or is repeated two or more times. Fig.35 and Fig.36 Describe the action.

[0143] Although reference is made to a method describing Figures 12 to 37 , but it should be understood that the structures shown in these figures are not limited to this method, but can exist independently of this method. Figures 12 to 37 Although described as a series of actions, it should be understood that the order of these actions may be changed in other embodiments. Figures 12 to 37 A particular set of actions are shown and described, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0144] refer to Fig.38 , provides Figures 12 to 37 Block diagram 3800 of some embodiments of the method.

[0145] At 3802, a first interconnect dielectric layer is patterned to form a trench exposing a first conductor, wherein the first conductor corresponds to a conductive line of a partially formed interconnect structure. Fig.12 and Fig.13 .

[0146] At 3804, an insulator layer is deposited overlying the first interconnect dielectric layer and lining the trench, wherein a seam is formed in the trench during deposition. Fig.14 .

[0147] At 3806, the insulator layer is etched back to remove the insulator layer from the top of the first interconnect dielectric layer and open the seam. Fig.15 .

[0148] At 3808, a second conductor is formed to fill the unfilled portion of the trench above the insulator layer, wherein the width of the second conductor decreases toward the first conductor to form a tip. Fig.16 and Fig.17 .

[0149] At 3810, a first stop layer is formed on top of the second conductor and the first interconnect dielectric layer. Fig.18 .

[0150] At 3812, a semiconductor channel is formed extending through the first etch stop layer to the second conductor. Figures 19 to 21 .

[0151] At 3814, a gate stack is formed on the top of the semiconductor channel and on the sidewalls of the semiconductor channel. Fig. 22 and Fig.23 .

[0152] At 3816, a second interconnect dielectric layer is formed to cover a lower sidewall portion of the gate stack, leaving an upper sidewall portion of the gate stack exposed. Figure 24 to Figure 26 .

[0153] At 3818, an upper portion of the gate stack including an upper sidewall portion is removed. Fig. 27 .

[0154] At 3820, a second etch stop layer is formed overlying the gate stack and the second interconnect dielectric layer and having a top surface that is recessed relative to a top surface of the semiconductor channel. Fig.28 and Fig.29 .

[0155] At 3822, a third conductor is formed on top of the semiconductor channel. Fig.30 and Fig.31 .

[0156] At 3824, the interconnect structure is completed over the third conductor. See, for example Figure 32 to Figure 37 .

[0157] Although Fig.38 The block diagram 3800 is shown and described herein as a series of actions or events, but it should be understood that the order shown in such actions or events is not interpreted in a restrictive sense. For example, some actions may occur in a different order or simultaneously with other actions or events other than those shown and / or described herein. In addition, not all shown actions may need to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0158] refer to Figure 39 to Figure 42 , provides Figures 12 to 37 A series of cross-sectional views 3900 to 4200 of some first alternative embodiments of the method of. For example, such embodiments can be used to form Fig. 6A , Fig. 8A , Fig. 10A or Fig.11A An interconnect structure in or some other suitable interconnect structure.

[0159] like Fig.39 As shown in the cross-sectional view 3900, the Figures 12 to 34 Except for the through hole layer V y There is no through hole extending to the third conductor 116 and the conductor layer M x+1 Except for the wires that are not electrically coupled to the third conductor 116 through the through hole, these actions are as described with respect to Figures 12 to 34 was performed as described.

[0160] like Fig.40 As shown in the cross-sectional view 4000, the execution of Fig.35 The described actions enable the third interconnect dielectric layer 126c to be formed at the via layer V y and conductor layer M x+1 Extends above.

[0161] like Fig.41 As shown in the cross-sectional view 4100, the Fig.36 Describes the actions to form a via layer V y+1 and conductor layer M x+2 . In addition to the through hole layer V y+1 is formed to include a conductor layer M x+2 The third conductor 116 is extended outside the through hole. Fig.36 was performed as described.

[0162] like Fig.42 As shown in the cross-sectional view 4200, the execution of Fig.37 Describes the actions to form a via layer V y+2 and conductor layer M x+3 .

[0163] Although reference is made to a method describing Figure 39 to Figure 42 , but it should be understood that the structures shown in these figures are not limited to this method, but can exist independently of this method. Figure 39 to Figure 42 Although described as a series of actions, it should be understood that the order of these actions may be changed in other embodiments. Figure 39 to Figure 42 A particular set of actions are shown and described, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0164] refer to Figures 43 to 48 , provides Figures 12 to 37 A series of cross-sectional views 4300 to 4200 of some second alternative embodiments of the method of. For example, such embodiments can be used to form Figure 8B or Fig. 10B The vertical GAA memory cell in FIG.

[0165] like Fig.43 As shown in the cross-sectional view 4300, the execution of Figures 12 to 16 Except that the sacrificial layer 4302l is used instead of the conductive layer 110l, these actions are the same as those described above. Figures 12 to 16 The sacrificial layer 43021 may be, for example, polysilicon and / or some other suitable sacrificial material.

[0166] like Fig.44As shown in the cross-sectional view 4400 of FIG. 4401 , planarization is performed in the sacrificial layer 43021. The planarization can be performed, for example, by CMP or some other suitable planarization process. The planarization removes the sacrificial layer 43021 from the top of the first interconnect dielectric layer 126a and forms a pair of sacrificial structures 4302. The sacrificial structures 4302 are respectively overlying the first conductor 108 and are separated from the first conductor 108 by the insulator structure 112. In addition, the width of the sacrificial structure 4302 decreases from the top of the first interconnect dielectric layer 126a toward the first conductor 108 to reach a point.

[0167] like Fig.45 As shown in the cross-sectional view 4500, the Fig.18 and Fig.19 The described actions are performed to form the first etch stop layer 128a having the opening 1902. Furthermore, thereafter, the sacrificial structure 4302 is removed to partially clear the trench 1302 at the opening 1902. This removal may be performed, for example, by an etching process and / or by some other suitable removal process.

[0168] like Fig.46 As shown in the cross-sectional view 4600 of FIG. 46A , the semiconductor layer 2002 is deposited on top of the first etch stop layer 128 a and also fills the opening 1902 and the remaining portion of the trench 1302 on top of the insulator structure 112. In some embodiments, the top surface of the semiconductor layer 2002 is further flattened by planarization. The planarization may be performed, for example, by CMP and / or some other suitable planarization process.

[0169] like Fig.47 As shown in the cross-sectional view 4700 of FIG. 47A , the semiconductor layer 2002 is patterned to form a pair of semiconductor channels 114 and a pair of second conductors 110. The patterning can be performed, for example, by a photolithography / etching process or some other suitable process. Insofar as the patterning is performed by a photolithography / etching process, the first etch stop layer 128 a can be used as an etch stop during etching of the semiconductor layer 2002, for example.

[0170] The pair of second conductors 110 and Fig.44 The semiconductor layer 2002 fills the groove 1302 and forms a pair of resistors 104 with the insulator structure 112 and the first conductor 108. The semiconductor channels 114 cover the second conductor 110 and Fig.44 The patterning corresponds to the portion of the semiconductor layer 2002 outside the trench 1302 in the semiconductor layer 2002. In some embodiments, the patterning causes the semiconductor channel 114 to have a shape corresponding to the opening 1902 (see Fig.43 ) have the same or similar widths.

[0171] like Fig.48As illustrated in the cross-sectional view 4800, the implementation of Figure 22 to Figure 37 The described actions complete the vertical GAA memory cell 102 and further complete the interconnect structure (eg, formed by conductive lines 418 and vias 124).

[0172] Although reference is made to a method describing Figures 43 to 48 , but it should be understood that the structures shown in these figures are not limited to this method, but can exist independently of this method. Figures 43 to 48 Although described as a series of actions, it should be understood that the order of these actions may be changed in other embodiments. Figures 43 to 48 A particular set of actions are shown and described, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0173] refer to Figures 49 to 51 , a series of cross-sectional views 4900 to 5100 of some embodiments of a method for forming an integrated chip with a pair of vertical GAA memory cells on the front side of a logic device are provided. The integrated chip and Figure 4 corresponds to, but can alternatively be, for example, FIG. 6A to FIG. 6C , Fig. 8A and Figure 8B Any one of them corresponds to .

[0174] like Fig.49 As shown in the cross-sectional view 4900 of FIG. 49 , a first logic device 402a and a second logic device 402b are formed on a semiconductor substrate 404. The first logic device 402a and the second logic device 402b are separated from each other by an isolation structure 408. The first logic device 402a and the second logic device 402b may be, for example, planar FETs, FinFETs, GAA FETs, some other suitable types of logic devices and / or transistors, or any combination of the foregoing.

[0175] In some embodiments, the first logic device 402a and the second logic device 402b include respective gate electrodes 410, respective gate dielectric layers 412, and respective source / drain region pairs 414. The source / drain region pairs 414 are inserted into the top of the semiconductor substrate 404. The gate electrodes 410 are respectively overlying the gate dielectric layers 412 and are respectively between the source / drain region pairs 414. In some embodiments, the first logic device 402a and the second logic device 402b further include respective wells 416, which are respectively below the gate electrodes 410 and in the semiconductor substrate 404.

[0176] like Fig.50As shown in the cross-sectional view 5000 of FIG. 50 , the interconnect structure 406 is partially formed to overlie the first logic device 402 a and the second logic device 402 b on a front side FS of the first logic device 402 a , the front side FS being opposite to a back side BS of the first logic device 402 a .

[0177] The interconnect structure 406 includes a plurality of wires 418 and a plurality of vias 124 in a first interconnect dielectric layer 126a. The plurality of wires 418 are grouped into a plurality of wire layers, and the plurality of vias 124 are grouped into a plurality of via layers stacked alternately with the plurality of wire layers. The wire layers are labeled M1, M2, and M3 from the bottom of the interconnect structure 406 to the top of the interconnect structure 406. In addition, two wires in the wire layer M3 correspond to a pair of first conductors 108 of a vertical GAA memory cell formed thereafter. The via layers are labeled V0, V1, and V2 from the bottom of the interconnect structure 406 to the top of the interconnect structure 406.

[0178] like Fig.51 As shown in the cross-sectional view 5100, the Figures 12 to 37 This forms a pair of vertical GAA memory cells 102 and completes the interconnect structure 406. The completed interconnect structure 406 also includes additional via layers V3, V4, and V5 and additional wire layers M4, M5, and M6. In an alternative embodiment, the steps of Figure 39 to Figure 42 The actions described, or alternatively, performing the Figures 43 to 48 The action described.

[0179] Although reference is made to a method describing Figures 49 to 51 , but it should be understood that the structures shown in these figures are not limited to this method, but can exist independently of this method. Figures 49 to 51 Although described as a series of actions, it should be understood that the order of these actions may be changed in other embodiments. Figures 49 to 51 A particular set of actions are shown and described, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0180] refer to Figure 52 to Figure 64 , a series of cross-sectional views 5200 to 6400 of some embodiments of a method for forming an integrated chip with a pair of vertical GAA memory cells on the back side of a logic device are provided. The integrated chip and Fig. 9 corresponds to, but can, for example, be replaced with FIG. 10A to FIG. 10C , Fig.11A and Fig. 11B Any one of them corresponds to .

[0181] like Fig.52As shown in the cross-sectional view 5200 of FIG. 5200 , the first logic device 902 a and the second logic device 902 b are formed adjacent to each other on a semiconductor substrate 5202. The semiconductor substrate 5202 may be or include, for example, silicon and / or some other suitable semiconductor material. The first logic device 902 a and the second logic device 902 b are GAA FETs, but may alternatively be, for example, planar FETs, FinFETs, some other suitable types of logic devices and / or transistors, or any combination of the foregoing.

[0182] The first logic device 902a and the second logic device 902b include respective multiple semiconductor channels 908, respective protection layers 910, respective gate electrodes 912, respective gate dielectric layers 914, and corresponding source / drain regions 916. The semiconductor channels 908 of a given one of the first logic device 902a and the second logic device 902b are vertically stacked on a corresponding one of the protection layers 910. In addition, the semiconductor channels 908 of a given one of the first logic device 902a and the second logic device 902b are laterally sandwiched between two source / drain regions 916 and vertically separated from each other by a corresponding one of the gate electrodes 912. The gate electrodes 912 are separated from the semiconductor channels 908 by the gate dielectric layers 914, respectively.

[0183] The first logic device 902a and the second logic device 902b further include respective first spacer structures 918, respective second spacer structures 920, and respective third spacer structures 922. The first spacer structures 918 are on the sidewalls of the gate electrode 912, separating the corresponding semiconductor channels 908 from each other. The second spacer structures 920 are on the sidewalls of the gate electrode 912, overlying the semiconductor channels 908, and the third spacer structures 922 are on the sidewalls of the second spacer structures 920, overlying the semiconductor channels 908.

[0184] The isolation structure 907 surrounds the bottom of the first logic device 902a and the second logic device 902b below the source / drain region 916. In addition, the ILD layer 936 surrounds the top of the first logic device 902a and the second logic device 902b above the source / drain region 916.

[0185] like Fig.53 As shown in the cross-sectional view 5300 of FIG. 53, the first interconnect structure 906 is formed to cover the first logic device 902a and the second logic device 902b on the front side FS of the first logic device 902a, and the front side FS is opposite to the back side BS of the first logic device 902a. In addition, the first interconnect structure 906 is formed in the dielectric structure. The dielectric structure includes a plurality of interconnect dielectric layers 938 and a plurality of etch stop layers 940 that are alternately and vertically stacked.

[0186] The first interconnect structure 906 includes a plurality of conductive features, including a plurality of first-layer contacts 924, a plurality of second-layer contacts 926, a conductive line 928, and a via 930. The second-layer contact 926 overlies the gate electrode 912 and is spaced apart therefrom, and the first-layer contact 924 extends from the second-layer contact 926 to the gate electrode 912. The conductive line 928 is spaced apart above the second-layer contact 926, and the via 930 extends from the conductive line 928 to a corresponding one of the second-layer contacts 926. In some embodiments, the conductive line 928 may also be considered as an RDL. In addition, although only one via layer and one conductive line layer are shown, more via layers and / or more conductive line layers are acceptable.

[0187] like Fig.54 As shown in the cross-sectional view 5400 of , a heat sink conductor 932 and a bonding dielectric layer 942 are formed on the carrier substrate 904. The heat sink conductor 932 is inserted into the bonding dielectric layer 942 so that the top surface of the heat sink conductor 902 is flush with the top surface of the bonding dielectric layer 942.

[0188] like Fig.55 As shown in the cross-sectional view 5500, Fig.53 The structure is flipped vertically and bonded to the Fig.54 The bonding interface 934 includes a dielectric-to-dielectric interface between a bonding dielectric layer 942 and an interconnect dielectric layer 938. The bonding interface 934 also includes a conductor-to-conductor interface between a heat sink conductor 932 and a wire 928.

[0189] like Fig.56 As shown in the cross-sectional view 5600 of FIG. 56A , the semiconductor substrate 5202 is thinned from the back side BS of the first logic device 902 a. The thinning may be performed, for example, by CMP and / or some other suitable planarization.

[0190] like Fig.57 As shown in the cross-sectional view 5700 of FIG. 57 , the semiconductor substrate 5202 is removed to expose the isolation structure 907 and the protection layer 910. The removal may be performed, for example, by etching and / or some other suitable removal process.

[0191] like Fig.58 As shown in the cross-sectional view 5800 , a first interconnect dielectric layer 126 a is deposited on top of the isolation structure 907 and the protection layer 910 .

[0192] like Fig.59As shown in the cross-sectional view 5900 of FIG. 59 , the contact plug 944 is formed to be inserted into the first interconnect dielectric layer 126 a. The process for forming the contact plug 944 may, for example, include patterning the first interconnect dielectric layer 126 a to form an opening exposing the source / drain region common to the first logic device 902 a and the second logic device 902 b. A conductive layer may be deposited to fill the opening and cover the first interconnect dielectric layer 126 a, and thereafter planarization may be performed in the conductive layer to remove the conductive layer from the top of the first interconnect dielectric layer. However, other suitable methods are also acceptable.

[0193] like Fig.60 As shown in the cross-sectional view 6000 of FIG. 60, additional dielectric material is deposited on top of the contact plug 944 so that the first interconnect dielectric layer 126a extends over the contact plug 944. In addition, the wire 418 is formed to be inserted into the first interconnect dielectric layer 126a, cover the contact plug 944 and extend from the contact plug 944. The contact plug 944 and the wire 418 partially form the second interconnect structure 406, and the wire 418 corresponds to the wire layer 240 of the second interconnect structure 406. The wire 418 can be formed, for example, by patterning the first interconnect dielectric layer 126a to form an opening overlying the contact plug and then filling the opening with a conductive material.

[0194] like Fig.61 As shown in the cross-sectional view 6100 of , additional dielectric material is deposited on top of the wire layer M0. In addition, additional wires 418 and vias 124 are formed to be inserted into the first interconnect dielectric layer 126a and overlie the wire layer M0 to extend the second interconnect structure 406. Additional wires 418 form a wire layer M1 above the wire layer M0, and vias 124 form a via layer V0 extending between the wire layer M0 and the wire layer M1. Additional wires 418 and vias 124 can be formed, for example, by patterning the first interconnect dielectric layer 126a to form an opening overlying the wire layer M0 and then filling the opening with a conductive material.

[0195] like Fig.62 As shown in the cross-sectional view 6200, repeat about Fig.61 The actions described extend the second interconnect structure 406 with additional conductive lines 418 and additional vias 124. The additional conductive lines 418 form a conductive line layer M2, and the additional vias 124 form a via layer V1 between conductive line layers M1 and M2.

[0196] like Fig.63 As shown in the cross-sectional view 6300, additional dielectric material is deposited on top of the conductive line layer M2 to extend the first interconnect dielectric layer 126a.

[0197] like Fig.64 As shown in the cross-sectional view 6400, the execution of Figures 12 to 37 This forms a pair of vertical GAA memory cells 102 and completes the second interconnect structure 406. The completed second interconnect structure 406 also includes additional via layers V2, V3, and V4 and additional wire layers M3, M4, and M5. In an alternative embodiment, the steps of Figure 39 to Figure 42 The actions described, or alternatively, performing the Figures 43 to 48 The action described.

[0198] Although reference is made to a method describing Figure 52 to Figure 64 , but it should be understood that the structures shown in these figures are not limited to this method, but can exist independently of this method. Figure 52 to Figure 64 Although described as a series of actions, it should be understood that the order of these actions may be changed in other embodiments. Figure 52 to Figure 64 A particular set of actions are shown and described, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0199] In some embodiments, the present disclosure relates to a memory cell, comprising: a lower conductor; an intermediate conductor, overlying the lower conductor and decreasing in width toward the lower conductor to reach a point spaced apart above the lower conductor; an insulator structure, between the lower conductor and the intermediate conductor; a semiconductor channel, overlying the intermediate conductor; a gate electrode, laterally surrounding the semiconductor channel on the sidewalls of the semiconductor channel; a gate dielectric layer, separating the gate electrode from the semiconductor channel; and an upper conductor, on top of the semiconductor channel. In some embodiments, the intermediate conductor and the semiconductor channel correspond to different regions of a common semiconductor layer. In some embodiments, the intermediate conductor has a different material composition than the semiconductor channel. In some embodiments, the intermediate conductor has the same material type as the gate electrode and / or the upper conductor. In some embodiments, the insulator structure extends along the sidewalls of the intermediate conductor and is in direct contact with the lower conductor and the intermediate conductor. In some embodiments, the upper conductor wraps around the top of the semiconductor channel from the sidewalls of the semiconductor channel to the top surface of the semiconductor channel. In some embodiments, the memory cell further comprises an etch stop layer on the sidewalls of the semiconductor channel, wherein the etch stop layer separates the upper conductor from the gate dielectric layer and also separates the upper conductor from the gate electrode.

[0200] In some embodiments, the present disclosure relates to an integrated chip, comprising: a first memory unit, comprising a first resistor and a first transistor on top of the first resistor, wherein the first resistor comprises a first conductor and shares a second conductor with the first transistor, and wherein the second conductor overlies the first conductor and has a first tip extending toward the first conductor; and a second memory unit, comprising a second resistor and a second transistor on top of the second resistor, wherein the second resistor comprises a third conductor and shares a fourth conductor with the second transistor, and wherein the fourth conductor overlies the third conductor and has a second tip extending toward the third conductor; wherein the first tip and the second tip have different heights. In some embodiments, the first transistor and the second transistor comprise gate electrodes that are each continuously connected. In some embodiments, the integrated chip further comprises: a first wire and a second wire, the first wire and the second wire being flush with each other and overlying the first transistor; and a first through hole and a second through hole, extending from the first wire and the second wire to the gate electrode of the first transistor and the source / drain of the first transistor, respectively. In some embodiments, the integrated chip further includes: a first wire and a second wire, overlying the first transistor, wherein the top surface of the first wire is recessed relative to the bottom surface of the second wire; and a first conductive via and a second conductive via, extending from the first wire and the second wire to the gate electrode of the first transistor and the source / drain of the first transistor, respectively. In some embodiments, the integrated chip further includes: a gate all around (GAA) transistor having a front side and a back side opposite to the front side; a first interconnect structure, on the front side of the GAA transistor, wherein the first interconnect structure includes a conductive feature extending to the gate electrode of the GAA transistor; and a second interconnect structure, on the back side of the GAA transistor, wherein the second interconnect structure surrounds and is electrically coupled to the first memory cell and the second memory cell. In some embodiments, the integrated chip further includes: an interconnect structure, overlying the semiconductor substrate and including a plurality of wires and a plurality of conductive vias stacked alternately, wherein the first conductor and the third conductor correspond to two of the plurality of wires.

[0201] In some embodiments, the present disclosure provides a method for forming a memory cell, comprising: patterning a first dielectric layer to form a trench exposing a lower conductor; depositing an insulator layer filling the trench, wherein a seam is formed and sealed in the trench during the deposition of the insulator layer; etching back the insulator layer to remove the insulator layer from above the top surface of the first dielectric layer and open the seam; forming an intermediate conductor after etching back, the intermediate conductor filling the unfilled portion of the trench and conforming thereto; forming a semiconductor channel on top of the intermediate conductor; forming a gate electrode surrounding the semiconductor channel; and forming an upper conductor on top of the semiconductor channel. In some embodiments, the width of the unfilled portion of the trench decreases toward the lower conductor to reach a point spaced apart above the lower conductor. In some embodiments, forming the intermediate conductor comprises: depositing a conductive layer filling the unfilled portion of the trench; performing planarization on the conductive layer to remove the conductive layer from the top of the first dielectric layer, wherein a portion of the conductive layer in the trench corresponds to the intermediate conductor. In some embodiments, forming a semiconductor channel includes: depositing a semiconductor layer over an intermediate conductor; and patterning the semiconductor layer into a columnar structure at the top of the intermediate conductor, wherein the columnar structure corresponds to the semiconductor channel. In some embodiments, forming the intermediate conductor includes: depositing a sacrificial layer that fills an unfilled portion of the trench; performing planarization in the sacrificial layer to remove the sacrificial layer from the top of the first dielectric layer; depositing an etch stop layer that overlies the first dielectric layer and the sacrificial layer; patterning the etch stop layer to form an opening that exposes the sacrificial layer; and replacing the sacrificial layer with a semiconductor material corresponding to the intermediate conductor. In some embodiments, forming a gate electrode includes: depositing a conductive layer that overlies the semiconductor channel and lines the sidewalls of the semiconductor channel; and etching back the conductive layer so that the top surface of the conductive layer is recessed relative to the top surface of the semiconductor channel, wherein the portion of the conductive layer that remains on the sidewalls of the semiconductor channel corresponds to the gate electrode. In some embodiments, the method further includes depositing an etch stop layer overlying a top surface of the gate electrode, wherein forming an upper conductor includes: depositing a conductive layer overlying the semiconductor channel and the etch stop layer and also on a sidewall of the semiconductor channel; and patterning the conductive layer into an upper conductor.

[0202] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0203] Example

[0204] Example 1. A memory cell comprising: a lower conductor; an intermediate conductor overlying the lower conductor and decreasing in width toward the lower conductor to reach a point spaced apart above the lower conductor; an insulator structure between the lower conductor and the intermediate conductor; a semiconductor channel overlying the intermediate conductor; a gate electrode laterally surrounding the semiconductor channel on the sidewalls of the semiconductor channel; a gate dielectric layer separating the gate electrode from the semiconductor channel; and an upper conductor at the top of the semiconductor channel.

[0205] Example 2. The memory cell of Example 1, wherein the intermediate conductor and the semiconductor channel correspond to different regions of a common semiconductor layer.

[0206] Example 3. The memory cell of Example 1, wherein the intermediate conductor has a different material composition than the semiconductor channel.

[0207] Example 4. The memory cell of Example 1, wherein the intermediate conductor has the same material type as the gate electrode and / or the upper conductor.

[0208] Example 5. The memory cell of Example 1, wherein the insulator structure extends along a sidewall of the middle conductor and is in direct contact with both the lower conductor and the middle conductor.

[0209] Example 6. The memory cell of Example 1, wherein the upper conductor wraps around a top portion of the semiconductor channel from a sidewall of the semiconductor channel to a top surface of the semiconductor channel.

[0210] Example 7. The memory cell of Example 1, further comprising: an etch stop layer on a sidewall of the semiconductor channel, wherein the etch stop layer separates the upper conductor from the gate dielectric layer and also separates the upper conductor from the gate electrode.

[0211] Example 8. An integrated chip comprising: a first memory cell comprising a first resistor and a first transistor on top of the first resistor, wherein the first resistor comprises a first conductor and shares a second conductor with the first transistor, and wherein the second conductor overlies the first conductor and has a first tip extending toward the first conductor; and a second memory cell comprising a second resistor and a second transistor on top of the second resistor, wherein the second resistor comprises a third conductor and shares a fourth conductor with the second transistor, and wherein the fourth conductor overlies the third conductor and has a second tip extending toward the third conductor; wherein the first tip and the second tip have different heights.

[0212] Example 9. The integrated chip of Example 8, wherein the first transistor and the second transistor share a common gate electrode.

[0213] Example 10. The integrated chip according to Example 8 further includes: a first conductive line and a second conductive line, wherein the first conductive line and the second conductive line are flush with each other and overlie the first transistor; and a first through hole and a second through hole, extending from the first conductive line and the second conductive line to the gate electrode of the first transistor and the source / drain of the first transistor, respectively.

[0214] Example 11. The integrated chip according to Example 8 further includes: a first wire and a second wire, overlying the first transistor, wherein the top surface of the first wire is recessed relative to the bottom surface of the second wire; and a first conductive via and a second conductive via, extending from the first wire and the second wire to the gate electrode of the first transistor and the source / drain of the first transistor, respectively.

[0215] Example 12. The integrated chip according to Example 8 further includes: a gate all-around (GAA) transistor having a front side and a back side opposite to the front side; a first interconnect structure on the front side of the GAA transistor, wherein the first interconnect structure includes a conductive feature extending to the gate electrode of the GAA transistor; and a second interconnect structure on the back side of the GAA transistor, wherein the second interconnect structure surrounds and is electrically coupled to the first memory cell and the second memory cell.

[0216] Example 13. The integrated chip according to Example 8 further includes: an interconnect structure overlying the semiconductor substrate and including a plurality of conductive lines and a plurality of conductive vias stacked alternately, wherein the first conductor and the third conductor correspond to two conductive lines among the plurality of conductive lines.

[0217] Example 14. A method for forming a memory cell, comprising: patterning a first dielectric layer to form a trench, the trench exposing a lower conductor; depositing an insulator layer, the insulator layer filling the trench, wherein a seam is formed and sealed in the trench during the deposition of the insulator layer; etching back the insulator layer to remove the insulator layer from above the top surface of the first dielectric layer and open the seam; forming an intermediate conductor after the etching back, the intermediate conductor filling the unfilled portion of the trench and conforming thereto; forming a semiconductor channel on top of the intermediate conductor; forming a gate electrode surrounding the semiconductor channel; and forming an upper conductor on top of the semiconductor channel.

[0218] Example 15. The method of Example 14, wherein a width of the unfilled portion of the trench decreases toward the lower conductor to a point spaced above the lower conductor.

[0219] Example 16. A method according to Example 14, wherein the forming of the intermediate conductor includes: depositing a conductive layer, the conductive layer filling the unfilled portion of the groove; and performing planarization in the conductive layer to clear the conductive layer from the top of the first dielectric layer, wherein a portion of the conductive layer in the groove corresponds to the intermediate conductor.

[0220] Example 17. A method according to Example 14, wherein the forming of the semiconductor channel includes: depositing a semiconductor layer above the intermediate conductor; and patterning the semiconductor layer into a columnar structure on top of the intermediate conductor, wherein the columnar structure corresponds to the semiconductor channel.

[0221] Example 18. A method according to Example 14, wherein the forming of the intermediate conductor includes: depositing a sacrificial layer, the sacrificial layer filling the unfilled portion of the groove; and performing planarization in the sacrificial layer to clear the sacrificial layer from the top of the first dielectric layer; depositing an etch stop layer, the etch stop layer overlying the first dielectric layer and the sacrificial layer; patterning the etch stop layer to form an opening exposing the sacrificial layer; and replacing the sacrificial layer with a semiconductor material corresponding to the intermediate conductor.

[0222] Example 19. A method according to Example 14, wherein forming the gate electrode includes: depositing a conductive layer, the conductive layer overlying the semiconductor channel and lining the sidewalls of the semiconductor channel; and etching back the conductive layer so that the top surface of the conductive layer is recessed relative to the top surface of the semiconductor channel, wherein the portion of the conductive layer remaining on the sidewalls of the semiconductor channel corresponds to the gate electrode.

[0223] Example 20. The method according to Example 14 further includes depositing an etch stop layer, the etch stop layer overlying the top surface of the gate electrode, and wherein the forming of the upper conductor includes: depositing a conductive layer, the conductive layer overlying the semiconductor channel and the etch stop layer, and also on the sidewalls of the semiconductor channel; and patterning the conductive layer into the upper conductor.

Claims

1. A memory cell, comprising: Lower conductor; an intermediate conductor overlying the lower conductor and decreasing in width toward the lower conductor to reach points spaced above the lower conductor; an insulator structure between the lower conductor and the middle conductor; A semiconductor channel overlying the intermediate conductor; a gate electrode laterally surrounding the semiconductor channel on a sidewall of the semiconductor channel; a gate dielectric layer separating the gate electrode from the semiconductor channel; as well as The upper conductor is on top of the semiconductor channel.

2. The memory cell according to claim 1, wherein: The intermediate conductor and the semiconductor channel correspond to different regions of a common semiconductor layer.

3. The memory cell according to claim 1, wherein: The intermediate conductor has a different material composition than the semiconductor channel.

4. The storage unit according to claim 1, wherein: The intermediate conductor has the same material type as the gate electrode and / or the upper conductor.

5. The memory cell according to claim 1, wherein: The insulator structure extends along a sidewall of the center conductor and is in direct contact with both the lower conductor and the center conductor.

6. The memory cell according to claim 1, wherein: The upper conductor wraps around the top of the semiconductor channel from the sidewalls of the semiconductor channel to the top surface of the semiconductor channel.

7. The memory cell according to claim 1, further comprising: An etch stop layer is provided on a sidewall of the semiconductor channel, wherein the etch stop layer separates the upper conductor from the gate dielectric layer and also separates the upper conductor from the gate electrode.

8. An integrated chip comprising: a first memory cell comprising a first resistor and a first transistor on top of the first resistor, wherein the first resistor comprises a first conductor and shares a second conductor with the first transistor, and wherein the second conductor overlies the first conductor and has a first tip extending toward the first conductor; and a second memory cell comprising a second resistor and a second transistor on top of the second resistor, wherein the second resistor comprises a third conductor and shares a fourth conductor with the second transistor, and wherein the fourth conductor overlies the third conductor and has a second tip extending toward the third conductor; Wherein, the first tip and the second tip have different heights.

9. The integrated chip according to claim 8, wherein: The first transistor and the second transistor share a common gate electrode.

10. A method for forming a memory cell, comprising: patterning the first dielectric layer to form a trench, the trench exposing the lower conductor; depositing an insulator layer, the insulator layer filling the trench, wherein a seam is formed and sealed in the trench during the depositing of the insulator layer; etching back the insulator layer to clear the insulator layer from above the top surface of the first dielectric layer and open the seam; forming an intermediate conductor after the etch back, the intermediate conductor filling and conforming to the unfilled portion of the trench; forming a semiconductor channel on top of the intermediate conductor; forming a gate electrode surrounding the semiconductor channel; and An upper conductor is formed on top of the semiconductor channel.

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