Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a plurality of active regions which are located in the substrate and are separately arranged, a plurality of openings which expose part of the active regions, and a protective layer which covers the surface of the substrate between the openings; forming a semiconductor layer in the opening, wherein the surface of the semiconductor layer is not lower than the surface of the protective layer; forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor layer; sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending along a direction parallel to the substrate; wherein the initial bit line structure comprises the semiconductor layer and a first dielectric layer located on the semiconductor layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development and progress of technology, semiconductor devices are constantly moving towards miniaturization and high integration. As an important semiconductor device, dynamic random access memory (DRAM) is used in various electronic devices with its fast read and write speed. Dynamic random access memory includes multiple storage cells, each of which usually includes a transistor and a capacitor. The data stored in the capacitor is read through the transistor, or the data is written into the capacitor.

[0003] However, there are still many problems to be solved in the manufacturing process of semiconductor devices. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] A semiconductor structure is provided, the semiconductor structure comprising a substrate, a plurality of active regions located in the substrate and arranged separately, a plurality of openings exposing portions of the active regions, and a protective layer covering a surface of the substrate between the openings;

[0008] forming a semiconductor layer in the opening, wherein a surface of the semiconductor layer is not lower than a surface of the protective layer;

[0009] forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor layer;

[0010] The first dielectric layer and the semiconductor layer are sequentially etched to form a plurality of initial bit line structures extending in a direction parallel to the substrate; wherein the initial bit line structure comprises the semiconductor layer and a first dielectric layer located on the semiconductor layer.

[0011] In some embodiments, after sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending in a direction parallel to the substrate, the manufacturing method further includes:

[0012] forming an isolation layer, wherein the isolation layer fills the opening;

[0013] A second dielectric layer is formed, wherein the second dielectric layer covers the sidewalls of the initial bit line structure and covers the isolation layer and the protection layer.

[0014] In some embodiments, forming the isolation layer includes:

[0015] forming an isolation material layer covering the sidewalls and top of the initial bit line structure and filling the opening;

[0016] The isolation material layer covering the top and part of the sidewall of the initial bit line structure is removed by etching to form an isolation layer; wherein the surface of the isolation layer is substantially flush with the surface of the protection layer.

[0017] In some embodiments, the etching removes the isolation material layer covering the top and a portion of the sidewall of the initial bit line structure, and the etching liquid includes phosphoric acid.

[0018] In some embodiments, forming the second dielectric layer includes:

[0019] forming a second dielectric material layer covering the sidewalls and top of the initial bit line structure and covering the isolation layer and the protection layer;

[0020] The second dielectric material layer is planarized to form a second dielectric layer; wherein a surface of the second dielectric layer is substantially flush with a surface of the first dielectric layer.

[0021] In some embodiments, after forming the second dielectric layer, the manufacturing method further includes:

[0022] Etching back and removing the first dielectric layer of the initial bit line structure to expose the semiconductor layer of the initial bit line structure;

[0023] Removing part of the semiconductor layer of the initial bit line structure by etching back to form a first bit line groove; wherein the remaining semiconductor layer of the initial bit line structure forms a bit line contact layer, and the bit line contact layer is in contact with the active area; the surface of the bit line contact layer exposed at the bottom of the first bit line groove is substantially flush with the surface of the protection layer;

[0024] A bit line barrier layer and a bit line conductive layer are sequentially formed in the first bit line groove.

[0025] In some embodiments, in the etching back to remove the first dielectric layer of the initial bit line structure, the etching gas includes at least one of the following: carbon tetrafluoride CF4 and trifluoromethane CHF3;

[0026] In the etching back to remove a portion of the semiconductor layer of the initial bit line structure, the etching gas includes at least one of the following: hydrogen bromide HBr and chlorine Cl2.

[0027] In some embodiments, the step of sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove includes:

[0028] forming a bit line blocking layer in the first bit line groove;

[0029] forming a bit line conductive material layer in the first bit line groove;

[0030] The bit line conductive material layer is planarized to form a bit line conductive layer; wherein a surface of the bit line conductive layer is substantially flush with a surface of the second dielectric layer.

[0031] In some embodiments, after sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove, the manufacturing method further includes:

[0032] forming a third dielectric layer, wherein the third dielectric layer covers the second dielectric layer and the bit line conductive layer;

[0033] Etching and removing a portion of the third dielectric layer to form a second bit line groove; wherein the bottom of the second bit line groove exposes the bit line conductive layer;

[0034] A bit line insulating layer is formed in the second bit line groove.

[0035] In some embodiments, when etching to remove a portion of the third dielectric layer, the etching gas includes oxygen O2 and hexafluorobutadiene C4F6 and / or octafluorocyclobutane C4F8.

[0036] In some embodiments, forming a bit line insulating layer in the second bit line groove includes:

[0037] forming a bit line insulating material layer in the second bit line groove;

[0038] The bit line insulation layer material layer is planarized to form a bit line insulation layer; wherein the surface of the bit line insulation layer is substantially flush with the surface of the third dielectric layer.

[0039] In some embodiments, after forming the bit line insulating layer in the second bit line groove, the manufacturing method further includes:

[0040] The third dielectric layer and the second dielectric layer are removed by etching to form a plurality of bit line structures extending in a direction parallel to the substrate; wherein the bit line structures include a bit line contact layer, a bit line barrier layer, a bit line conductive layer and a bit line insulating layer stacked in sequence.

[0041] In some embodiments, in the etching to remove the third dielectric layer and the second dielectric layer, the etching liquid includes hydrofluoric acid.

[0042] In some embodiments, a height of the first dielectric layer along a direction perpendicular to the substrate is smaller than a height of the bit line insulating layer along a direction perpendicular to the substrate.

[0043] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method as described in the above technical solution.

[0044] The embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same. In the embodiment of the present disclosure, the first dielectric layer and the semiconductor layer are sequentially etched to form an initial bit line structure; in the subsequent process, a bit line barrier layer, a bit line conductive layer, and a bit line insulating layer are sequentially formed. Compared with sequentially etching the bit line insulating layer, the bit line conductive layer, the bit line barrier layer, and the bit line contact layer to form the bit line structure, the etching height of only etching the first dielectric layer and the semiconductor layer is smaller, which can effectively reduce the stress problem caused by excessive etching height, thereby effectively alleviating the problem of swinging of the bit line structure caused by excessive stress, and further forming storage node contact holes of uniform size between the bit line structures, thereby improving the electrical performance of the semiconductor device and improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figures 1A to 1G is a schematic diagram of a cross-sectional structure of an exemplary semiconductor device during the manufacturing process;

[0046] Figure 2 is a schematic diagram of a top view of a semiconductor device according to an example;

[0047] Figures 3A to 3G is a schematic cross-sectional structure diagram of another example of a semiconductor device during the manufacturing process;

[0048] Figure 4 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0049] FIG. 5A to FIG. 5K A schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0052] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0053] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0054] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0057] The dynamic random access memory includes a plurality of storage cells, each of which generally includes a transistor and a capacitor, wherein the gate of the transistor is connected to a word line, the drain of the transistor is connected to a bit line, the source of the transistor is connected to a first electrode plate of the capacitor, and the second electrode plate of the capacitor is connected to a common terminal. By applying a voltage to the word line, the transistor is turned on or off, and the data stored in the capacitor is read through the bit line, or the data is written into the capacitor through the bit line.

[0058] Here, directions that may be involved in the embodiments of the present disclosure are defined. An X direction and a Y direction parallel to the substrate are defined, the X direction may be the direction in which the word line structure extends, the Y direction may be the direction in which the bit line structure extends, and the X direction and the Y direction may be perpendicular to each other. A direction perpendicular to the substrate is defined as a Z direction, and the X direction, the Y direction, and the Z direction may be perpendicular to each other.

[0059] refer to Figures 1A to 1G , Figures 1A to 1G The cross-sectional structure diagram of an exemplary semiconductor device during the manufacturing process is shown in FIG. Figures 1A to 1G The XZ cross-sectional structure diagram of the semiconductor device is shown below. Figures 1A to 1G , a manufacturing process of a semiconductor device provided by an example is described in detail.

[0060] Figure 1A The schematically illustrated semiconductor structure 101 includes: a substrate 102, a plurality of active regions 103 located in the substrate 102 and arranged separately, an isolation structure 104 located between adjacent active regions 103, a plurality of openings 105 exposing portions of the active regions 103, and a protective layer 106 covering the surface of the substrate 102 located between the openings 105; wherein the protective layer 106 includes a first protective sublayer 107 and a second protective sublayer 108.

[0061] The semiconductor structure 101 also includes: a semiconductor layer 109, such as polysilicon, which fills the opening 105 and covers the surface of the protection layer 106; a bit line blocking material layer 110 covering the semiconductor layer 109, such as titanium nitride; a bit line conductive material layer 111 covering the bit line blocking material layer 110, such as metal tungsten; and a bit line insulating material layer 112 covering the bit line conductive material layer 111, such as silicon nitride.

[0062] like Figure 1A and Figure 1B As shown, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113 . Figure 1B It is shown that the sidewall of the bit line insulating layer 113 is substantially perpendicular to the surface of the substrate 102 , that is, the sidewall of the bit line insulating layer 113 is straight.

[0063] Of course, part of the bit line conductive material layer 111 will also be etched during the etching of the bit line insulating material layer 112. Since the etching selectivity of the bit line insulating material layer 112 and the bit line conductive material layer 111 is different, the sidewall of the etched part of the bit line conductive material layer 111 is not perpendicular to the surface of the substrate 102. More specifically, the sidewall of the etched part of the bit line conductive material layer 111 presents an inclined morphology that is narrow at the top and wide at the bottom.

[0064] like Figure 1B and Figure 1C As shown, the bit line conductive material layer 111 is etched along a direction perpendicular to the substrate 102 to form a bit line conductive layer 114 . Figure 1C It is shown that the sidewall of the bit line conductive layer 114 is substantially perpendicular to the surface of the substrate 102 , that is, the sidewall of the bit line conductive layer 114 is straight.

[0065] Of course, part of the bit line blocking material layer 110 will also be etched during the etching of the bit line conductive material layer 111. Since the etching selectivity of the bit line conductive material layer 111 and the bit line blocking material layer 110 is different, the sidewall of the etched part of the bit line blocking material layer 110 is not perpendicular to the surface of the substrate 102. More specifically, the sidewall of the etched part of the bit line blocking material layer 110 presents an inclined morphology that is narrow at the top and wide at the bottom.

[0066] like Figure 1C and Figure 1D As shown, the bit line barrier material layer 110 is etched along a direction perpendicular to the substrate 102 to form a bit line barrier layer 115 . Figure 1D It is shown that the sidewall of the bit line barrier layer 115 is substantially perpendicular to the surface of the substrate 102 , that is, the sidewall of the bit line barrier layer 115 is straight.

[0067] Of course, part of the semiconductor layer 109 will also be etched during the etching of the bit line blocking material layer 110. Due to the different etching selectivity of the bit line blocking material layer 110 and the semiconductor layer 109, the sidewall of the etched part of the semiconductor layer 109 is not perpendicular to the surface of the substrate 102. More specifically, the sidewall of the etched part of the semiconductor layer 109 presents an inclined morphology that is narrow at the top and wide at the bottom.

[0068] like Figure 1D and Figure 1E As shown, the semiconductor layer 109 is etched along a direction perpendicular to the substrate 102 to form a bit line contact layer 116 . Figure 1E The bit line structure 123 is schematically shown to include the first bit line structure 117 (eg Figure 1E The second bit line structure 118 (shown in the dashed box) Figure 1E The first bit line structure 117 includes a bit line contact layer 116, a bit line barrier layer 115, a bit line conductive layer 114 and a bit line insulating layer 113 in sequence, and the bit line contact layer 116 of the first bit line structure 117 is in direct contact with the active area 103 exposed by the opening 105; the second bit line structure 118 includes a bit line contact layer 116, a bit line barrier layer 115, a bit line conductive layer 114 and a bit line insulating layer 113 in sequence, and the bit line contact layer 116 of the second bit line structure 118 is in direct contact with the protective layer 106 on the surface of the substrate 102 between the openings 105. Here, the first bit line structure 117 may also be referred to as a self bit line (selfBL), and the second bit line structure 118 may also be referred to as a passing bit line (passing BL). Figure 1E In the illustrated cross-sectional structural diagram, the height of the bit line contact layer 116 of the first bit line structure 117 along the direction perpendicular to the substrate 102 is greater than the height of the bit line contact layer 116 of the second bit line structure 118 along the direction perpendicular to the substrate 102 .

[0069] because Figure 1E In the schematic cross-sectional structure diagram, both the first bit line structure 117 and the second bit line structure 118 include a bit line contact layer 116. Therefore, the side walls of the bit line barrier layer 115 of the first bit line structure 117 and the second bit line structure 118 formed by etching are substantially perpendicular to the surface of the substrate 102. Further, since the etching selectivity for the bit line contact layer 116 and the protection layer 106 is relatively high, for example, the etching selectivity for polysilicon and silicon nitride is relatively high, therefore, the side walls of the bit line contact layer 116 of the second bit line structure 118 formed by etching are substantially perpendicular to the surface of the substrate 102, and the protection layer 106 will not be substantially etched and damaged during the process of etching to form the bit line contact layer 116, and the active area 103 located below the protection layer 106 will not be damaged.

[0070] refer to Figure 2 , Figure 2The figure is a schematic diagram of a top view of a semiconductor device according to an example. Figure 2 The word line structure 124 and the bit line structure 123 are shown to be perpendicular to each other and parallel to the substrate. For example, the word line structure 124 can extend along the X direction, and the bit line structure 123 can extend along the Y direction. The bit line structure 123 can include a first bit line structure 117 and a second bit line structure 118. Figure 1E Can be regarded as along Figure 2 Schematic diagram of the cross-sectional structure along the AA direction.

[0071] It should be noted that the size of the bit line structure 123 along the X direction is relatively small, for example, 12 nm, and the depth-to-width ratio of the bit line structure 123 is relatively large, that is, the ratio between the size of the bit line structure 123 along the Z direction and the size of the bit line structure 123 along the X direction is relatively large, for example, about 10:1. In addition, the height of the bit line insulation layer 113 of the bit line structure 123 along the direction perpendicular to the substrate 102 is relatively large, for example, about 85 nm, and the stress is relatively large during the etching process to form the bit line insulation layer 113 of the bit line structure 123, and the problem of wiggling is easily generated during the etching process to form the bit line insulation layer 113 of the bit line structure 123. In other words, the bit line structure 123 cannot be strictly extended along the Y direction.

[0072] like Figure 1F As shown, a first cover layer 119, a second cover layer 120 and a third cover layer 121 are sequentially formed; wherein the first cover layer 119 covers the sidewalls and tops of the first bit line structure 117 and the second bit line structure 118, and covers the sidewalls and bottom of the opening 105. The material of the first cover layer 119 may be, for example, silicon nitride, the material of the second cover layer 120 may be, for example, silicon oxide, and the material of the third cover layer 121 may be, for example, silicon nitride.

[0073] like Figure 1G As shown, the third cover layer 121 , the second cover layer 120 , the first cover layer 119 and the protection layer 106 are sequentially etched between the adjacent first bit line structure 117 and the second bit line structure 118 until the active area 103 is exposed to form a storage node contact hole 122 .

[0074] It should be noted that the first bit line structure 117 and the second bit line structure 118 each include a bit line contact layer 116 , a bit line barrier layer 115 , a bit line conductive layer 114 and a bit line insulating layer 113 in sequence, which is not conducive to reducing the parasitic capacitance of the bit line structure 123 .

[0075] In addition, if the bit line structure 123 has a swing problem, the area of ​​the storage node contact holes 122 formed between the bit line structures 123 is uneven, and the storage node contact holes 122 with smaller areas are filled with conductive material. The contact area between the conductive material in the storage node contact holes 122 and the active area 103 is smaller, resulting in a larger read and write resistance, thereby affecting the electrical performance of the transistor.

[0076] based on Figures 1A to 1G The schematic cross-sectional structure diagram of a semiconductor device during the manufacturing process shows an improvement in the process of forming a bit line structure to reduce the parasitic capacitance of the bit line structure.

[0077] refer to Figures 3A to 3G , Figures 3A to 3G The cross-sectional structure diagram of another example semiconductor device during the manufacturing process. Figures 3A to 3G The XZ cross-sectional structure diagram of the semiconductor device is shown below. Figures 3A to 3G , a manufacturing process of a semiconductor device provided by another example is described in detail.

[0078] Figure 3A The semiconductor structure 201 shown schematically includes: a substrate 202, a plurality of active regions 203 located in the substrate 202 and arranged separately, an isolation structure 204 located between adjacent active regions 203, a plurality of openings 205 exposing portions of the active regions 203, and a protective layer 206 covering the surface of the substrate 202 located between the openings 205; wherein the protective layer 206 includes a first protective sublayer 207 and a second protective sublayer 208.

[0079] The semiconductor structure 201 also includes: a semiconductor layer 209, such as polysilicon, the semiconductor layer 209 fills the opening 205 and the surface of the semiconductor layer 209 is substantially flush with the surface of the protective layer 206; a bit line blocking material layer 210 covering the semiconductor layer 209, such as titanium nitride; a bit line conductive material layer 211 covering the bit line blocking material layer 210, such as metal tungsten; and a bit line insulating material layer 212 covering the bit line conductive material layer 211, such as silicon nitride.

[0080] like Figure 3A and Figure 3B As shown, the bit line insulating material layer 212 is etched along a direction perpendicular to the substrate 202 to form a bit line insulating layer 213 . Figure 3B It is shown that the sidewall of the bit line insulating layer 213 is substantially perpendicular to the surface of the substrate 202 , that is, the sidewall of the bit line insulating layer 213 is straight.

[0081] Of course, part of the bit line conductive material layer 211 will also be etched during the etching of the bit line insulating material layer 212. Since the etching selectivity of the bit line insulating material layer 212 and the bit line conductive material layer 211 is different, the sidewall of the etched part of the bit line conductive material layer 211 is not perpendicular to the surface of the substrate 202. More specifically, the sidewall of the etched part of the bit line conductive material layer 211 presents an inclined morphology that is narrow at the top and wide at the bottom.

[0082] like Figure 3B and Figure 3C As shown, the bit line conductive material layer 211 is etched along a direction perpendicular to the substrate 202 to form a bit line conductive layer 214 . Figure 3C It is shown that the sidewall of the bit line conductive layer 214 is substantially perpendicular to the surface of the substrate 202 , that is, the sidewall of the bit line conductive layer 214 is straight.

[0083] Of course, part of the bit line blocking material layer 210 will also be etched during the etching of the bit line conductive material layer 211. Since the etching selectivity of the bit line conductive material layer 211 and the bit line blocking material layer 210 is different, the sidewall of the etched part of the bit line blocking material layer 210 is not perpendicular to the surface of the substrate 202. More specifically, the sidewall of the etched part of the bit line blocking material layer 210 presents an inclined morphology that is narrow at the top and wide at the bottom.

[0084] like Figure 3C and Figure 3D As shown, the bit line blocking material layer 210 is etched along a direction perpendicular to the substrate 202 to form a bit line blocking layer 215 . Figure 3D It is shown that the sidewall of the bit line barrier layer 215 is not perpendicular to the surface of the substrate 202 , that is, the sidewall of the bit line barrier layer 215 presents an inclined morphology with a narrow upper portion and a wide lower portion.

[0085] Of course, part of the semiconductor layer 209 will also be etched during the etching of the bit line blocking material layer 210. Since the etching selectivity of the bit line blocking material layer 210 and the semiconductor layer 209 is different, the sidewall of the etched part of the semiconductor layer 209 is not perpendicular to the surface of the substrate 202. More specifically, the sidewall of the etched part of the semiconductor layer 209 presents an inclined morphology that is narrow at the top and wide at the bottom.

[0086] like Figure 3D and Figure 3E As shown, the semiconductor layer 209 is etched along a direction perpendicular to the substrate 202 to form a bit line contact layer 216 . Figure 3E The bit line structure 223 is shown to include the first bit line structure 217 (eg Figure 3E The second bit line structure 218 (shown in the dashed box) Figure 3EThe first bit line structure 217 includes a bit line contact layer 216, a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence, and the bit line contact layer 216 of the first bit line structure 217 is in direct contact with the active area 203 exposed by the opening 205; the second bit line structure 218 includes a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence, and the bit line barrier layer 215 of the second bit line structure 218 is in direct contact with the protective layer 206 on the surface of the substrate 202 between the opening 205.

[0087] and Figures 1A to 1G Compared with the semiconductor devices shown, Figures 3A to 3G The first bit line structure 217 of the semiconductor device of the example includes a bit line contact layer 216, a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence, and the second bit line structure 218 includes a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence. That is, Figures 3A to 3G The second bit line structure of the semiconductor device shown in the figure does not include a bit line contact layer, so that the parasitic capacitance of the bit line structure can be reduced. In a specific embodiment, the material of the bit line contact layer may include polysilicon, and the second bit line structure not including the bit line contact layer is called a passing BL polyless.

[0088] However, due to Figure 3E In the illustrated cross-sectional structural diagram, the first bit line structure 217 includes a bit line contact layer 216, while the second bit line structure 218 does not include a bit line contact layer. Therefore, the side wall of the bit line barrier layer 215 of the first bit line structure 217 formed by etching is basically perpendicular to the surface of the substrate 202, and the side wall of the bit line barrier layer 215 of the second bit line structure 218 formed by etching is not perpendicular to the surface of the substrate 202, that is, the side wall of the bit line barrier layer 215 of the second bit line structure 218 presents an inclined morphology that is narrow at the top and wide at the bottom. Furthermore, since the etching selectivity ratio of the bit line barrier layer 215 (for example, titanium nitride) and the protective layer 206 (including the first protective sublayer and the second protective sublayer, the first protective sublayer is for example silicon oxide, and the second protective sublayer is for example silicon nitride), for example, titanium nitride and silicon oxide, silicon nitride is not high enough, the sidewall of the bit line barrier layer 215 of the second bit line structure 218 formed by etching is not perpendicular to the surface of the substrate 202, and the second protective sublayer 208 and the first protective sublayer 207 under the bit line barrier layer 215 may be etched, and the active area 203 under the first protective sublayer 207 may even be exposed. In other words, the active area 203 may be damaged by etching.

[0089] In addition, during the process of etching to form the bit line barrier layer 215 , if a process with a high lateral etching rate is used, the neck of the bit line barrier layer 215 may be narrowed, or even the bit line structure 223 may be collapsed.

[0090] like Figure 3F As shown, a first covering layer 219 , a second covering layer 220 and a third covering layer 221 are formed in sequence; wherein the first covering layer 219 covers the sidewalls and tops of the first bit line structure 217 and the second bit line structure 218 , and covers the sidewalls and bottom of the opening 205 .

[0091] like Figure 3G As shown, the third cover layer 221 , the second cover layer 220 , the first cover layer 219 and the protection layer 206 are sequentially etched between the adjacent first bit line structure 217 and the second bit line structure 218 until the active area 203 is exposed to form a storage node contact hole 222 .

[0092] It should be noted that the depth-width ratio of the bit line structure 223 is relatively large, that is, the ratio between the size of the bit line structure 223 along the Z direction and the size of the bit line structure 223 along the X direction is relatively large. In addition, the height of the bit line insulating layer 213 of the bit line structure 223 along the direction perpendicular to the substrate 202 is relatively large, and the stress is relatively large during the process of etching to form the bit line insulating layer 213, and the problem of swinging is easily generated during the process of etching to form the bit line insulating layer 213 of the bit line structure 223.

[0093] In addition, since the sidewall of the bit line barrier layer 215 of the second bit line structure 218 presents an inclined morphology that is narrow at the top and wide at the bottom, and the second protection sublayer 208 and the first protection sublayer 207 below the second bit line structure 218 are also etched into an inclined morphology that is narrow at the top and wide at the bottom, the active area 203 may not be fully opened during the process of etching to form the storage node contact hole 222 between the adjacent first bit line structure 217 and the second bit line structure 218, resulting in a small contact area between the conductive material filled in the storage node contact hole 222 and the active area 203, resulting in a large read / write resistance, and further leading to the problem of read / write failure.

[0094] In view of this, an embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same.

[0095] refer to Figure 4 , Figure 4 The flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure is as follows. Figure 4 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0096] Step S401: providing a semiconductor structure, the semiconductor structure comprising a substrate, a plurality of active regions located in the substrate and disposed separately, a plurality of openings exposing portions of the active regions, and a protective layer covering a surface of the substrate between the openings;

[0097] Step S402: forming a semiconductor layer in the opening, wherein the surface of the semiconductor layer is not lower than the surface of the protective layer;

[0098] Step S403: forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor layer;

[0099] Step S404: sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending in a direction parallel to the substrate; wherein the initial bit line structure comprises a semiconductor layer and a first dielectric layer located on the semiconductor layer.

[0100] refer to FIG. 5A to FIG. 5K , FIG. 5A to FIG. 5K The cross-sectional structure diagram of the semiconductor device provided in the embodiment of the present disclosure during the manufacturing process. FIG. 5A to FIG. 5K , describing in detail the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.

[0101] In the embodiment of the present disclosure, in step S401 , a semiconductor structure 308 is provided, which includes a substrate 301 , a plurality of active regions 302 disposed discretely within the substrate 301 , a plurality of openings 307 exposing portions of the active regions 302 , and a protective layer 306 covering the surface of the substrate 301 between the openings 307 .

[0102] like Figure 5A As shown, the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure includes: providing a substrate 301; etching the substrate 301 to form a plurality of discretely arranged active areas 302; filling the grooves between any adjacent active areas 302; wherein the filling material located between the adjacent active areas 302 forms an isolation structure 303, and the filling material covering the surface of the substrate 301 forms a first protective sublayer 304; forming a second protective sublayer 305 covering the first protective sublayer 304; wherein the first protective sublayer 304 and the second protective sublayer 305 together form a protective layer 306.

[0103] In some embodiments, the substrate may include a semiconductor substrate; the material of the semiconductor substrate specifically includes a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material or other semiconductor materials known in the art. In a specific embodiment, the substrate may be a silicon substrate.

[0104] In some embodiments, the process of etching the substrate to form the active region may include, but is not limited to, a wet etching process, a dry etching process, or a combination thereof.

[0105] In some embodiments, the filling material may include but is not limited to at least one of oxides, nitrides, and oxynitrides, or a combination thereof. In a specific embodiment, the filling material may be a composite layer of silicon oxide, silicon nitride, and silicon oxide. However, this is not limited thereto. In actual processes, the filling material may also be other materials, which may be flexibly selected according to actual conditions and are not particularly limited here.

[0106] In some embodiments, the material of the first protection sublayer may include but is not limited to oxide, such as silicon oxide; the material of the second protection sublayer may include but is not limited to nitride, such as silicon nitride.

[0107] In some embodiments, the process of forming the first protective sublayer and the second protective sublayer may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof. In actual processes, the first protective sublayer and the second protective sublayer may also be formed using other conventional process technologies, which may be flexibly selected according to actual conditions and are not specifically limited here.

[0108] Continue to refer Figure 5A As shown, the second protection sublayer 305, the first protection sublayer 304 and the substrate 301 can be sequentially etched along a direction perpendicular to the substrate 301 to form an opening 307 that at least exposes a portion of the active region 302. The substrate 301, the multiple active regions 302 that are located in the substrate 301 and are separately arranged, the multiple openings 307 that expose a portion of the active regions 302, and the protection layer 306 that covers the surface of the substrate 301 between the openings 307 together form a semiconductor structure 308.

[0109] Here, the opening may have a cross-sectional shape that is wide at the top and narrow at the bottom, so that the bottom of the opening can be tightened around the active area exposed by the opening to avoid damaging the surrounding active area during the process of forming the opening. In this way, the reliability of the semiconductor device can be improved.

[0110] In some embodiments, the number of openings may be multiple. Figure 5A Only a partial cross-sectional structure diagram of the semiconductor device is shown. The number of openings can be flexibly selected according to the actual process, and the embodiment of the present disclosure does not impose any special limitation on the number of openings.

[0111] Still refer to Figure 5A As shown, in the embodiment of the present disclosure, in step S402, a semiconductor layer 309 is formed in the opening 307, and the semiconductor layer 309 at least fills the opening 307, that is, the surface of the semiconductor layer 309 is at least not lower than the surface of the protective layer 306. The surface of the semiconductor layer 309 is at least not lower than the surface of the protective layer 306, including the following two situations: in the first situation, the surface of the semiconductor layer 309 is substantially flush with the surface of the protective layer 306; in the second situation, the surface of the semiconductor layer 309 is higher than the surface of the protective layer 306.

[0112] In some embodiments, the semiconductor layer can fill the opening, and the surface of the semiconductor layer is substantially flush with the surface of the protective layer. Here, the surface of the semiconductor layer is substantially flush with the surface of the protective layer means that the height difference between the surface of the semiconductor layer and the surface of the protective layer in the direction perpendicular to the substrate meets the process error range. In a specific embodiment, the height difference between the surface of the semiconductor layer and the surface of the protective layer in the direction perpendicular to the substrate is 0.

[0113] In some other embodiments, the semiconductor layer may fill the opening, and the semiconductor layer covers the surface of the protection layer, that is, the surface of the semiconductor layer is higher than the surface of the protection layer. Figure 5A It illustrates the situation where the surface of the semiconductor layer is higher than the surface of the protective layer.

[0114] In some embodiments, the material of the semiconductor layer may include, but is not limited to, polysilicon.

[0115] Still refer to Figure 5A As shown, in the embodiment of the present disclosure, in step S403 , a first dielectric layer 310 is formed, and the first dielectric layer 310 covers the semiconductor layer 309 .

[0116] In some embodiments, the material of the first dielectric layer may include but is not limited to oxide, such as silicon oxide.

[0117] like Figure 5B As shown, in the embodiment of the present disclosure, in step S404, the first dielectric layer 310 and the semiconductor layer 309 are sequentially etched along a direction perpendicular to the substrate 301 to form a plurality of initial bit line structures 311 extending along a direction parallel to the substrate 301; wherein the initial bit line structure 311 includes the semiconductor layer 309 and the first dielectric layer 310 located on the semiconductor layer 309.

[0118] It should be noted that the semiconductor layer of the initial bit line structure is in contact with the active region. Figure 5B In the schematic cross-sectional structure diagram, a portion of the semiconductor layer of the initial bit line structure is in direct contact with the active area exposed by the opening, and another portion of the semiconductor layer of the initial bit line structure is in direct contact with the protective layer on the substrate surface between the openings. In other words, Figure 5BIt is shown that the height of the initial bit line structure in direct contact with the active region in the direction perpendicular to the substrate is greater than the height of the initial bit line structure in direct contact with the protection layer in the direction perpendicular to the substrate; more specifically, Figure 5B It is shown that the height of the semiconductor layer of the initial bit line structure directly in contact with the active region in the direction perpendicular to the substrate is greater than the height of the semiconductor layer of the initial bit line structure directly in contact with the protective layer in the direction perpendicular to the substrate. Figure 5B Only the schematic diagram of the cross-sectional structure in one cross-sectional direction is illustrated, and in the schematic diagrams of the cross-sectional structures in other cross-sectional directions, another part of the semiconductor layer of the initial bit line structure will also contact the active area.

[0119] In other embodiments, when the surface of the semiconductor layer and the surface of the protective layer are substantially flush, the semiconductor layer of a portion of the initial bit line structure in the cross-sectional structural schematic diagram is in direct contact with the active area exposed by the opening, and the first dielectric layer of another portion of the initial bit line structure is in direct contact with the protective layer on the substrate surface between the opening.

[0120] In the disclosed embodiment, the height of the first dielectric layer covering the semiconductor layer in a direction perpendicular to the substrate is relatively small, for example, about 10 nm. In the process of sequentially etching the first dielectric layer and the semiconductor layer to form an initial bit line structure, the etching height is relatively small, which can effectively alleviate the stress problem caused by excessive etching height, thereby effectively alleviating the problem of bit line structure swinging caused by excessive stress, and further, storage node contact holes of uniform size can be formed between the bit line structures, thereby improving the electrical performance of the semiconductor device and enhancing the reliability of the semiconductor device.

[0121] In the embodiment of the present disclosure, after step S404, the manufacturing method further includes:

[0122] An isolation layer 313 is formed, and the isolation layer 313 fills the opening 307;

[0123] A second dielectric layer 314 is formed, and the second dielectric layer 314 covers the sidewalls of the initial bit line structure 311 and covers the isolation layer 313 and the protection layer 306 .

[0124] like Figure 5C As shown, after forming the initial bit line structure 311 , the manufacturing method further includes forming an isolation material layer 312 covering the sidewalls and top of the initial bit line structure 311 and filling the opening 307 ; at this time, the isolation material layer 312 also covers the protection layer 306 on the surface of the substrate 301 between the openings 307 .

[0125] In some embodiments, the material of the isolation material layer may include but is not limited to nitride, such as silicon nitride.

[0126] In some embodiments, the process of forming the isolation material layer may include but is not limited to PVD, CVD, ALD or any combination thereof. The embodiment of the present disclosure does not specifically limit the process of forming the isolation material layer.

[0127] like Figure 5C and Figure 5D As shown, the isolation material layer 312 covering the top and part of the sidewall of the initial bit line structure 311 is etched away to form an isolation layer 313; wherein the isolation layer 313 still fills the opening 307, and the surface of the isolation layer 313 is substantially flush with the surface of the protective layer 306 on the surface of the substrate 301 between the opening 307.

[0128] Here, the isolation layer surface and the protection layer surface are substantially flush means that the height difference between the isolation layer surface and the protection layer surface in a direction perpendicular to the substrate meets the process error range. In a specific embodiment, the height difference between the isolation layer surface and the protection layer surface in a direction perpendicular to the substrate is 0. Figure 5D In the schematic cross-sectional structure diagram, the side walls exposed by each initial bit line structure have the same height in a direction perpendicular to the substrate.

[0129] In the embodiment of the present disclosure, a wet etching process may be used to etch away the isolation material layer covering the top and a portion of the sidewalls of the initial bit line structure. The etching liquid in the wet etching process may include phosphoric acid.

[0130] like Figure 5E As shown, after forming the isolation layer 313, the manufacturing method further includes forming a second dielectric material layer, wherein the second dielectric material layer covers the sidewalls and the top of the initial bit line structure 311, that is, the second dielectric material layer covers the sidewalls of the semiconductor layer 309 and the sidewalls of the first dielectric layer 310 of the initial bit line structure 311, and the second dielectric material layer covers the top of the first dielectric layer 310 of the initial bit line structure 311; of course, the second dielectric layer material layer also covers the surface of the protection layer 306 and the surface of the isolation layer 313 between adjacent initial bit line structures 311.

[0131] In some embodiments, the material of the second dielectric material layer may include but is not limited to oxide, such as silicon oxide.

[0132] Still refer to Figure 5E As shown, the second dielectric material layer is planarized to expose the first dielectric layer 310, and the remaining second dielectric material layer forms a second dielectric layer 314; wherein the surface of the second dielectric layer 314 is substantially flush with the surface of the first dielectric layer 310. In other words, the second dielectric layer 314 covers the sidewalls of the initial bit line structure 311 and exposes the top of the initial bit line structure 311, and the second dielectric layer 314 covers the surface of the protection layer 306 and the surface of the isolation layer 313 between adjacent initial bit line structures 311.

[0133] In some embodiments, the planarization process may include but is not limited to chemical mechanical polishing (CMP).

[0134] Here, the second dielectric layer surface is substantially flush with the first dielectric layer surface of the initial bit line structure, which means that the height difference between the second dielectric layer surface and the first dielectric layer surface in a direction perpendicular to the substrate meets the process error range. In a specific embodiment, the height difference between the second dielectric layer surface and the first dielectric layer surface in a direction perpendicular to the substrate is 0.

[0135] like Figure 5E and Fig. 5F As shown, after forming the second dielectric layer 314, the manufacturing method further includes: etching back to remove the first dielectric layer 310 of the initial bit line structure 311 along a direction perpendicular to the substrate 301 to expose the semiconductor layer 309 of the initial bit line structure 311; continuing to etching back to remove part of the semiconductor layer 309 of the initial bit line structure 311 along a direction perpendicular to the substrate 301 to form a first bit line groove 315; wherein the remaining semiconductor layer of the initial bit line structure 311 forms a bit line contact layer 316, and the bit line contact layer 316 is in direct contact with the active area 302 exposed by the opening 307; and the surface of the bit line contact layer 316 exposed at the bottom of the first bit line groove 315 is substantially flush with the surface of the protective layer 306.

[0136] Here, an etch back process (Etch Back) can be used to remove the first dielectric layer and part of the semiconductor layer of the initial bit line structure. It should be noted that, Figure 5E and Fig. 5F It is schematically shown that for an initial bit line structure directly contacting the active area, a portion of the semiconductor layer of the initial bit line structure is removed, and the remaining semiconductor layer of the initial bit line structure forms a bit line contact layer; Figure 5E and Fig. 5F It is also shown that for an initial bit line structure directly in contact with the protection layer, all semiconductor layers of the initial bit line structure are removed, and the bottom of the first bit line groove is formed to expose the surface of the protection layer.

[0137] It should be noted that the initial bit line structure extends along the Y direction. Figure 5E and Fig. 5F It is shown that the initial bit line structure directly contacting the active area is not always in direct contact with the active area during the extension along the Y direction. For the same initial bit line structure extending along the Y direction, a part of the initial bit line structure is in direct contact with the active area, and another part of the initial bit line structure is in direct contact with the protection layer.

[0138] Here, a portion of the bottom of the first bit line groove 315 exposes the semiconductor layer, another portion of the bottom of the first bit line groove 315 exposes the protection layer; and a sidewall of the first bit line groove 315 exposes the second dielectric layer.

[0139] In the embodiment of the present disclosure, the etching gas used to etch back and remove the first dielectric layer 310 of the initial bit line structure 311 includes at least one of the following: carbon tetrafluoride CF4 and trifluoromethane CHF3;

[0140] When etching back to remove a portion of the semiconductor layer 309 of the initial bit line structure 311 , the etching gas includes at least one of the following: hydrogen bromide HBr and chlorine Cl 2 .

[0141] In the disclosed embodiment, etching is divided into two stages. In the first etching stage, the first dielectric layer can be etched away to expose the semiconductor layer. In the second etching stage, part of the semiconductor layer (for example, polysilicon) can be etched away, and etching is performed using hydrogen bromide and / or chlorine gas, which has a relatively high etching selectivity for polysilicon and silicon oxide.

[0142] like Figure 5G As shown, after forming the first bit line groove 315, the manufacturing method further includes: forming a bit line barrier layer 317 in the first bit line groove 315, wherein the surface of the bit line barrier layer 317 is lower than the surface of the second dielectric layer 314; forming a conductive material layer in the first bit line groove 315, at this time, the conductive material layer can fill the first bit line groove 315 and cover the surface of the second dielectric layer 314 between the first bit line grooves 315; planarizing the bit line conductive material layer to expose the surface of the second dielectric layer 314, and the remaining bit line conductive material layer (that is, the bit line conductive material layer located in the first bit line groove) forms a bit line conductive layer 318; wherein the surface of the bit line conductive layer 318 is substantially flush with the surface of the second dielectric layer 314.

[0143] Here, the surface of the bit line conductive layer and the surface of the second dielectric layer being substantially flush means that the height difference between the surface of the bit line conductive layer and the surface of the second dielectric layer in a direction perpendicular to the substrate meets the process error range. In a specific embodiment, the height difference between the surface of the bit line conductive layer and the surface of the second dielectric layer in a direction perpendicular to the substrate is 0.

[0144] Here, the height of the first bit line groove along the direction perpendicular to the substrate is the sum of the heights of the bit line barrier layer and the bit line conductive layer along the direction perpendicular to the substrate; the size of the first bit line groove along the direction parallel to the substrate, the size of the bit line barrier layer along the direction parallel to the substrate and the size of the bit line conductive layer along the direction parallel to the substrate are the same.

[0145] In some embodiments, the process of forming the bit line barrier layer and the bit line conductive material layer may include but is not limited to PVD, CVD, ALD or any combination thereof. The embodiments of the present disclosure do not specifically limit the process of forming the bit line barrier layer and the bit line conductive material layer.

[0146] In some embodiments, the planarization process may include, but is not limited to, CMP.

[0147] In some embodiments, the material of the bit line barrier layer may include but is not limited to titanium nitride; the material of the bit line conductive layer may include but is not limited to metal tungsten.

[0148] like Figure 5H As shown, after the bit line barrier layer 317 and the bit line conductive layer 318 are formed in sequence, the manufacturing method further includes: forming a third dielectric layer 319 , wherein the third dielectric layer 319 covers the second dielectric layer 314 and the bit line conductive layer 318 .

[0149] In some embodiments, the material of the third dielectric layer may include but is not limited to oxide, such as silicon oxide. In a specific embodiment, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer may be the same.

[0150] In some embodiments, the process of forming the first dielectric layer, the second dielectric layer and the third dielectric layer may include but is not limited to PVD, CVD, ALD or any combination thereof. The embodiments of the present disclosure do not specifically limit the process of forming the first dielectric layer, the second dielectric layer and the third dielectric layer.

[0151] like Fig.5I As shown, a portion of the third dielectric layer 319 is etched away in a direction perpendicular to the substrate 301 to expose the bit line conductive layer 318, thereby forming a second bit line groove 320. The sidewall of the second bit line groove 320 exposes the third dielectric layer 319, and the bottom of the second bit line groove 320 exposes the bit line conductive layer 318.

[0152] Here, the first bit line groove and the second bit line groove have the same size in a direction parallel to the substrate, and the orthographic projections of the first bit line groove and the second bit line groove on the substrate overlap.

[0153] In the embodiment of the present disclosure, a dry etching process may be used to etch and remove a portion of the third dielectric layer 319 , wherein the etching gas in the dry etching process includes oxygen O 2 and hexafluorobutadiene C 4 F 6 and / or octafluorocyclobutane C 4 F 8 .

[0154] Here, in the dry etching process, O2 and C4F6; or, O2 and C4F8; or, O2, C4F6 and C4F8 can be used as etching gases.

[0155] like Figure 5JAs shown, a bit line insulation material layer is formed in the second bit line groove 320; the bit line insulation material layer is planarized to expose the surface of the third dielectric layer 319, and the remaining bit line insulation material layer (i.e., the bit line insulation material layer located in the second bit line groove) forms a bit line insulation layer 321; wherein the surface of the bit line insulation layer 321 is substantially flush with the surface of the third dielectric layer 319.

[0156] In some embodiments, the process of forming the bit line insulating material layer may include but is not limited to PVD, CVD, ALD or any combination thereof. The present disclosure does not specifically limit the process of forming the bit line insulating material layer.

[0157] In some embodiments, the planarization process includes, but is not limited to, CMP.

[0158] Here, the surface of the bit line insulation layer and the surface of the third dielectric layer are substantially flush, which means that the height difference between the surface of the bit line insulation layer and the surface of the third dielectric layer in the direction perpendicular to the substrate meets the process error range. In a specific embodiment, the height difference between the surface of the bit line insulation layer and the surface of the third dielectric layer in the direction perpendicular to the substrate is 0.

[0159] In some embodiments, the material of the bit line insulating layer may include, but is not limited to, nitride, such as silicon nitride.

[0160] like Figure 5J and Figure 5K As shown, after forming the bit line insulating layer 321, the manufacturing method further includes: etching and removing the third dielectric layer 319 and the second dielectric layer 314 to form a plurality of bit line structures 324 extending in a direction parallel to the substrate 301; wherein the bit line structures 324 include a bit line contact layer 316, a bit line blocking layer 317, a bit line conductive layer 318 and a bit line insulating layer 321 stacked in sequence. Figure 5K The bit line structure is schematically shown extending along the Y direction.

[0161] Here, the third dielectric layer and the second dielectric layer are removed by etching to expose the sidewalls of the bit line insulating layer, the bit line conductive layer and the bit line barrier layer, and to expose the isolation layer and the protection layer surface between adjacent bit line structures.

[0162] Figure 5K The cross-sectional structure schematic diagram shows that the bit line structure 324 includes a first bit line structure 322 (such as Figure 5K The second bit line structure 323 (shown in the dashed box) Figure 5KAs shown in the dotted line box, the first bit line structure 322 includes a bit line contact layer 316, a bit line barrier layer 317, a bit line conductive layer 318 and a bit line insulating layer 321 in sequence, wherein the bit line contact layer 316 is in contact with the active area 302; the second bit line structure 323 includes a bit line barrier layer 317, a bit line conductive layer 318 and a bit line insulating layer 321 in sequence, wherein the bit line barrier layer 317 is in contact with the protective layer 306.

[0163] It should be noted that the bit line structure 324 includes the first bit line structure 322 and the second bit line structure 323 , which does not mean that the semiconductor device includes two types of bit line structures. Figure 5K The diagram shows that the first bit line structure 322 is in direct contact with the active area 302 exposed by the opening 307 , which does not mean that the first bit line structure 322 is always in direct contact with the active area 302 during the process of extending along the Y direction; Figure 5K The diagram shows that the second bit line structure 323 is in direct contact with the protective layer 306 on the surface of the substrate 301 between the opening 307, which does not mean that the second bit line structure 323 is always in direct contact with the protective layer 306 during the extension along the Y direction. In the embodiment of the present disclosure, for the same bit line structure extending along the Y direction, a part of the bit line structure (i.e., the first bit line structure) includes a bit line contact layer, and another part of the bit line structure (i.e., the second bit line structure) does not include a bit line contact layer. For the same bit line structure extending along the Y direction, a part of the bit line structure (i.e., the first bit line structure) is in direct contact with the active area, and another part of the bit line structure (i.e., the second bit line structure) is in direct contact with the protective layer. In other words, for the same bit line structure extending along the Y direction, a part of the bit line structure is the first bit line structure, and another part of the bit line structure is the second bit line structure. Here, the second bit line structure does not include a bit line contact layer, which can reduce the parasitic capacitance of the bit line structure.

[0164] In the disclosed embodiment, the process of forming the second bit line structure can avoid damaging the active area, so that storage node contact holes of uniform size can be formed between the bit line structures, thereby improving the electrical performance of the semiconductor device and enhancing the reliability of the semiconductor device.

[0165] In the embodiment of the present disclosure, a wet etching process may be used to etch and remove the third dielectric layer and the second dielectric layer. In the wet etching process, the etching liquid may include hydrofluoric acid, such as dilute hydrofluoric acid (DHF).

[0166] In the embodiment of the present disclosure, a height of the first dielectric layer along a direction perpendicular to the substrate is smaller than a height of the bit line insulating layer along a direction perpendicular to the substrate.

[0167] In the embodiment of the present disclosure, the first dielectric layer and the semiconductor layer are sequentially etched to form an initial bit line structure; in the subsequent process, a bit line barrier layer, a bit line conductive layer, and a bit line insulating layer are sequentially formed. Compared with sequentially etching the bit line insulating layer, the bit line conductive layer, the bit line barrier layer, and the bit line contact layer to form the bit line structure, the etching height of only etching the first dielectric layer and the semiconductor layer is smaller, which can effectively reduce the stress problem caused by the excessive etching height, thereby effectively alleviating the problem of the bit line structure swinging caused by excessive stress.

[0168] An embodiment of the present disclosure provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method in the above technical solution.

[0169] The embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same. In the embodiment of the present disclosure, the first dielectric layer and the semiconductor layer are sequentially etched to form an initial bit line structure; in the subsequent process, a bit line barrier layer, a bit line conductive layer, and a bit line insulating layer are sequentially formed. Compared with sequentially etching the bit line insulating layer, the bit line conductive layer, the bit line barrier layer, and the bit line contact layer to form the bit line structure, the etching height of only etching the first dielectric layer and the semiconductor layer is smaller, which can effectively reduce the stress problem caused by excessive etching height, thereby effectively alleviating the problem of swinging of the bit line structure caused by excessive stress, and further forming storage node contact holes of uniform size between the bit line structures, thereby improving the electrical performance of the semiconductor device and improving the reliability of the semiconductor device.

[0170] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0171] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: A semiconductor structure is provided, the semiconductor structure comprising a substrate, a plurality of active regions located in the substrate and arranged separately, a plurality of openings exposing portions of the active regions, and a protective layer covering a surface of the substrate between the openings; forming a semiconductor layer in the opening, wherein a surface of the semiconductor layer is not lower than a surface of the protective layer; forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor layer; The first dielectric layer and the semiconductor layer are sequentially etched to form a plurality of initial bit line structures extending in a direction parallel to the substrate; wherein the initial bit line structure comprises the semiconductor layer and a first dielectric layer located on the semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending in a direction parallel to the substrate, the manufacturing method further comprises: forming an isolation layer, wherein the isolation layer fills the opening; A second dielectric layer is formed, wherein the second dielectric layer covers the sidewalls of the initial bit line structure and covers the isolation layer and the protection layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The forming of the isolation layer comprises: forming an isolation material layer covering the sidewalls and top of the initial bit line structure and filling the opening; The isolation material layer covering the top and part of the sidewall of the initial bit line structure is removed by etching to form an isolation layer; wherein the surface of the isolation layer is substantially flush with the surface of the protection layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The etching removes the isolation material layer covering the top and a portion of the sidewall of the initial bit line structure, and the etching liquid includes phosphoric acid.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The forming of the second dielectric layer comprises: forming a second dielectric material layer covering the sidewalls and top of the initial bit line structure and covering the isolation layer and the protection layer; The second dielectric material layer is planarized to form a second dielectric layer; wherein a surface of the second dielectric layer is substantially flush with a surface of the first dielectric layer.

6. The method for manufacturing a semiconductor device according to claim 2, wherein: After forming the second dielectric layer, the manufacturing method further comprises: Etching back and removing the first dielectric layer of the initial bit line structure to expose the semiconductor layer of the initial bit line structure; Removing part of the semiconductor layer of the initial bit line structure by etching back to form a first bit line groove; wherein the remaining semiconductor layer of the initial bit line structure forms a bit line contact layer, and the bit line contact layer is in contact with the active area; the surface of the bit line contact layer exposed at the bottom of the first bit line groove is substantially flush with the surface of the protection layer; A bit line barrier layer and a bit line conductive layer are sequentially formed in the first bit line groove.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: In the etching back to remove the first dielectric layer of the initial bit line structure, the etching gas includes at least one of the following: carbon tetrafluoride CF4 and trifluoromethane CHF3; In the etching back to remove a portion of the semiconductor layer of the initial bit line structure, the etching gas includes at least one of the following: hydrogen bromide HBr and chlorine Cl2.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The step of sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove comprises: forming a bit line blocking layer in the first bit line groove; forming a bit line conductive material layer in the first bit line groove; The bit line conductive material layer is planarized to form a bit line conductive layer; wherein a surface of the bit line conductive layer is substantially flush with a surface of the second dielectric layer.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: After sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove, the manufacturing method further comprises: forming a third dielectric layer, wherein the third dielectric layer covers the second dielectric layer and the bit line conductive layer; Etching and removing a portion of the third dielectric layer to form a second bit line groove; wherein the bottom of the second bit line groove exposes the bit line conductive layer; A bit line insulating layer is formed in the second bit line groove.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: In the etching process for removing a portion of the third dielectric layer, the etching gas includes oxygen O2 and hexafluorobutadiene C4F6 and / or octafluorocyclobutane C4F8.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The forming of a bit line insulating layer in the second bit line groove comprises: forming a bit line insulating material layer in the second bit line groove; The bit line insulation layer material layer is planarized to form a bit line insulation layer; wherein the surface of the bit line insulation layer is substantially flush with the surface of the third dielectric layer.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: After forming the bit line insulating layer in the second bit line groove, the manufacturing method further includes: The third dielectric layer and the second dielectric layer are removed by etching to form a plurality of bit line structures extending in a direction parallel to the substrate; wherein the bit line structures include a bit line contact layer, a bit line barrier layer, a bit line conductive layer and a bit line insulating layer stacked in sequence.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: In the etching to remove the third dielectric layer and the second dielectric layer, the etching liquid includes hydrofluoric acid.

14. The method for manufacturing a semiconductor device according to claim 9, wherein: A height of the first dielectric layer along a direction perpendicular to the substrate is smaller than a height of the bit line insulating layer along a direction perpendicular to the substrate.

15. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 14.

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