Memory, manufacturing method thereof and electronic equipment
By surrounding the gate electrode on the sidewalls of the semiconductor layer and stacking the memory cells vertically, the difficulties faced by the traditional DRAM process in the miniaturization process are solved, and higher storage density and control capabilities are achieved.
Patent Information
- Application Number
- CN202310882038.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-18
- Publication Date
- 2025-01-21
AI Technical Summary
Traditional DRAM processes face difficulties in miniaturization, and it is difficult to effectively improve storage density and control capabilities.
By surrounding the grid electrode on the side wall of the semiconductor layer, and forming a multi -layer vertical stacking unit on the substrate, the relative area of the grille electrode and the semiconductor layer is increased, thereby improving the space utilization and control capabilities of the memory.
This method effectively enhances the control ability of the grid electrode to the transistor, improves the space utilization rate of memory, and solves the difficulties faced by the traditional DRAM process in the process of miniaturizing.
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Figure CN119342803A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a memory and a manufacturing method thereof, and an electronic device. Background Art
[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.
[0003] Taking DRAM as an example, the conventional DRAM has multiple repeated "memory cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.
[0004] With the continuous development of dynamic random access memory (DRAM) technology, the miniaturization of DRAM process has become increasingly difficult. Summary of the invention
[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0006] The embodiment of the present disclosure provides a memory, comprising: a substrate, and a plurality of memory cells stacked in a direction perpendicular to the substrate; the memory cells comprising: a transistor;
[0007] The transistor includes a semiconductor layer, a first electrode, a second electrode and a gate electrode, the first electrode and the second electrode are connected through the semiconductor layer, the semiconductor layer, the first electrode and the second electrode are arranged in the same layer, the gate electrode surrounds the semiconductor layer, and a gate insulating layer is arranged between the gate electrode and the semiconductor layer.
[0008] In an exemplary embodiment, the semiconductor layer, the first electrode and the second electrode form a columnar structure parallel to the substrate.
[0009] In an exemplary embodiment, a cross section of the columnar structure in a direction perpendicular to the substrate is rectangular.
[0010] In an exemplary embodiment, the method further includes: a bit line, the bit line is parallel to the substrate, and the bit line is connected to the second electrode of the transistor.
[0011] In an exemplary embodiment, the bit line and the second electrode of the transistor are an integrated structure and include a same conductive material.
[0012] In an exemplary embodiment, the memory cell further includes: a capacitor including a first capacitor electrode and a second capacitor electrode insulated from each other, the first capacitor electrode being connected to the first electrode of the transistor.
[0013] In an exemplary embodiment, the first capacitor electrode and the first electrode of the transistor are an integral structure and include a same conductive material.
[0014] In an exemplary embodiment, the material of the semiconductor layer includes metal oxide.
[0015] In an exemplary embodiment, the device further includes: an isolation layer, wherein the isolation layer is perpendicular to the substrate and separates gate electrodes of adjacent memory cells.
[0016] In an exemplary embodiment, it further includes: an insulating dielectric layer and a semiconductor dielectric layer, wherein the insulating dielectric layer is arranged on a side of the storage unit away from the substrate, and the semiconductor dielectric layer is arranged on a side of the insulating dielectric layer away from the substrate.
[0017] The present disclosure also provides a method for manufacturing a memory, including:
[0018] forming conductive layers and insulating layers alternately arranged in a direction away from the substrate on a substrate;
[0019] Performing patterned etching to form a groove extending in a direction perpendicular to the substrate, wherein each layer of the conductive layer forms a patterned structure stacked on top of each other, and each layer of the patterned structure includes a bit line and a plurality of branches extending in a direction perpendicular to the bit line;
[0020] filling the trench with a dielectric layer;
[0021] Performing patterned etching to form a groove extending in a direction perpendicular to the substrate, wherein a sidewall of the groove exposes portions of the plurality of branches and a portion of the insulating layer;
[0022] Performing selective etching to remove the exposed branches to form a first cavity, and retaining some branches on both sides of the first cavity to form a first electrode and a second electrode respectively;
[0023] forming a semiconductor layer in the first cavity, wherein the semiconductor layer connects the first electrode and the second electrode;
[0024] Performing selective etching to remove the exposed insulating layer to form a second cavity, wherein the second cavity surrounds the side wall of the semiconductor layer;
[0025] An atomic layer deposition process is adopted to sequentially form a gate insulating layer and a gate electrode in the second cavity, so that the gate electrode surrounds the semiconductor layer, and the gate insulating layer is provided between the gate electrode and the semiconductor layer.
[0026] In an exemplary embodiment, after the gate insulating layer and the gate electrode are sequentially formed in the second cavity by an atomic layer deposition process, the method further includes:
[0027] An isolation layer extending in a direction perpendicular to the substrate is formed in the groove, and the isolation layer separates adjacent gate electrodes.
[0028] An embodiment of the present disclosure also provides an electronic device, comprising the aforementioned memory.
[0029] The memory of the disclosed embodiment increases the relative area between the gate electrode and the semiconductor layer by wrapping the gate electrode around the side wall of the semiconductor layer. The wrap-around gate can effectively enhance the control capability of the gate electrode over the transistor and improve the space utilization of the memory.
[0030] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.
[0031] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.
[0033] Figure 1a A schematic cross-sectional view of a memory device provided by an exemplary embodiment along a direction parallel to a substrate;
[0034] Figure 1b for Figure 1a A cross-sectional view along the a-a' direction;
[0035] Figure 1c for Figure 1a A cross-sectional view along the b-b' direction;
[0036] Figure 1d for Figure 1a Sectional view along c-c' direction;
[0037] Figure 1e for Figure 1a Cross-sectional view along the d-d' direction;
[0038] Figure 2a for Figure 1a A cross-sectional view along the a-a' direction after forming an insulating layer, a conductive layer and a capacitor during the manufacturing process of the memory shown;
[0039] Figure 2b for Figure 1a A cross-sectional view in the direction bb' after forming an insulating layer, a conductive layer and a capacitor in the manufacturing process of the memory shown;
[0040] Figure 2c for Figure 1a A cross-sectional view in the c-c' direction after forming an insulating layer, a conductive layer and a capacitor in the manufacturing process of the memory shown;
[0041] Figure 3a for Figure 1a A cross-sectional view along the bb' direction after a groove is formed during the manufacturing process of the memory shown;
[0042] Figure 3b for Figure 1a A cross-sectional view along the c-c' direction after a groove is formed during the manufacturing process of the memory shown;
[0043] Figure 4a for Figure 1a A cross-sectional view along the a-a' direction after a groove is formed during the manufacturing process of the memory shown;
[0044] Figure 4b for Figure 1a A cross-sectional view along the c-c' direction after a groove is formed during the manufacturing process of the memory shown;
[0045] Figure 5a for Figure 1a A cross-sectional view in the a-a' direction after a semiconductor film is formed during the manufacturing process of the memory shown;
[0046] Figure 5b for Figure 1a A cross-sectional view in the direction bb' after a semiconductor film is formed during the manufacturing process of the memory shown;
[0047] Figure 5c for Figure 1a A cross-sectional view in the c-c' direction after a semiconductor film is formed during the manufacturing process of the memory shown;
[0048] Figure 6a for Figure 1a A cross-sectional view along the direction bb' after the semiconductor film in the groove is removed during the manufacturing process of the memory shown;
[0049] Figure 6b for Figure 1aA cross-sectional view in the c-c' direction after the semiconductor film in the groove is removed during the manufacturing process of the memory shown;
[0050] Figure 7a for Figure 1a A cross-sectional view along the aa' direction after the second cavity is formed during the manufacturing process of the memory shown;
[0051] Figure 7b for Figure 1a A cross-sectional view along the c-c' direction after the second cavity is formed during the manufacturing process of the memory shown;
[0052] Figure 8a for Figure 1a A cross-sectional view along the a-a' direction after a gate insulating layer and a gate electrode are formed during the manufacturing process of the memory shown;
[0053] Figure 8b for Figure 1a A cross-sectional view in the c-c' direction after a gate insulating layer and a gate electrode are formed during the manufacturing process of the memory shown;
[0054] Fig. 9 for Figure 1a The cross-sectional view along the c-c' direction after forming an isolation layer during the manufacturing process of the memory is shown. DETAILED DESCRIPTION
[0055] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.
[0056] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.
[0057] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.
[0058] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.
[0059] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.
[0060] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0061] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.
[0062] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.
[0063] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
[0064] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
[0065] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.
[0066] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
[0067] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.
[0068] The embodiment of the present disclosure provides a memory, comprising: a substrate and a plurality of memory cells stacked in a direction perpendicular to the substrate; the memory cells comprising: a transistor;
[0069] The transistor includes a semiconductor layer, a first electrode, a second electrode and a gate electrode, the first electrode and the second electrode are connected through the semiconductor layer, the semiconductor layer, the first electrode and the second electrode are arranged in the same layer, the gate electrode surrounds the semiconductor layer, and a gate insulating layer is arranged between the gate electrode and the semiconductor layer.
[0070] The memory disclosed in the present invention is described below by way of some exemplary embodiments.
[0071] Figure 1a A schematic cross-sectional view of a memory device provided by an exemplary embodiment along a direction parallel to a substrate; Figure 1b for Figure 1a A cross-sectional view along the a-a' direction; Figure 1c for Figure 1a A cross-sectional view along the b-b' direction; Figure 1d for Figure 1a Sectional view along c-c' direction; Figure 1e for Figure 1a The cross-sectional view along the d-d' direction. Figure 1a As shown, the memory provided in this embodiment may include: multiple layers of memory cells stacked in a direction perpendicular to a substrate and a bit line 30, wherein the bit line 30 extends in a direction parallel to the substrate and is connected to one or more memory cells in the same layer.
[0072] In an exemplary embodiment, the memory cells in the same layer form an array distributed along the first direction D1 and the second direction D2 respectively. The bit line 30 is shared with the transistors in the same layer and the same column, and can be specifically connected to the second electrode of the transistor. The first direction D1 and the second direction D2 are both parallel to the substrate, and the first direction D1 and the second direction D2 intersect. In some embodiments, the first direction D1 and the second direction D2 can be perpendicular.
[0073] In an exemplary embodiment, transistors of adjacent memory cells in the same layer share one bit line 30 , and two adjacent memory cells are distributed in a mirror-symmetrical manner.
[0074] In an exemplary embodiment, the bit line 30 may extend along the second direction D2.
[0075] In an exemplary embodiment, the bit line 30 may be made of metal, such as tungsten.
[0076] The disclosed embodiment uses metal as a bit line, which is respectively connected to the channel or source and drain of different transistors, so that the contact between the bit line and the channel or source and drain is an ohmic contact.
[0077] In an exemplary embodiment, the memory cell may include: a transistor and a data storage element, wherein a first electrode of the transistor is connected to the data storage element.
[0078] In an exemplary embodiment, the data storage element is, for example, a capacitor, that is, a 1T1C storage structure is formed. However, the embodiments of the present disclosure are not limited thereto, and other transistors may be combined to form a 2T0C storage structure, and so on.
[0079] In an exemplary embodiment, if Figure 1a and Figure 1e As shown, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42 , and the first capacitor electrode 41 is connected to the first electrode of the transistor.
[0080] In an exemplary embodiment, the first capacitor electrode 41 may extend along the first direction D1 , a first end of the first capacitor electrode 41 is connected to the first electrode of the transistor, and a second end of the first capacitor electrode 41 extends in a direction opposite to the first direction D1 .
[0081] In an exemplary embodiment, the capacitor may further include a capacitor dielectric layer located between the first capacitor electrode 41 and the second capacitor electrode 42. The capacitor dielectric layer may be a composite film layer, and may include a transition layer and a capacitor insulating layer. The material of the transition layer may be titanium or titanium nitride, and the transition layer is in contact with the second capacitor electrode 42 to reduce the contact resistance of the second capacitor electrode 42. The material of the capacitor insulating layer may be a high-K dielectric material, and may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.
[0082] In an exemplary embodiment, the first capacitor electrode 41 may be made of metal, such as tungsten; and the second capacitor electrode 42 may be made of a conductive material, such as polysilicon.
[0083] In an exemplary embodiment, if Figure 1a , Figure 1b , Figure 1c and Figure 1d As shown, the transistor includes a first electrode 11, a second electrode 12, a gate electrode 13 and a semiconductor layer 14. The first electrode 11 and the second electrode 12 are connected through the semiconductor layer 14, and the gate electrode 13 and the semiconductor layer 14 are insulated from each other.
[0084] In an exemplary embodiment, the semiconductor layer 14, the first electrode 11 and the second electrode 12 form a columnar structure extending along the first direction D1, and the semiconductor layer 14, the first electrode 11 and the second electrode 12 are different regions of the columnar structure respectively, and the side surfaces of the semiconductor layer 14, the first electrode 11 and the second electrode 12 are substantially flush, forming a columnar structure with substantially flush side surfaces. The first electrode 11 and the second electrode 12 are located on opposite sides of the semiconductor layer 14 in the first direction D1, and the first electrode 11 and the second electrode 12 are made of the same material and prepared by the same preparation process; the material of the semiconductor layer 14 is different from that of the first electrode 11 and the second electrode 12; or, the semiconductor layer 14, the first electrode 11 and the second electrode 12 are made of the same material, and the first electrode 11 and the second electrode 12 are formed into a conductor material by a doping process.
[0085] In an exemplary embodiment, the cross section of the columnar structure perpendicular to the substrate is a rectangle. In some embodiments, the cross section of the columnar structure perpendicular to the substrate can be in other shapes, such as a circle, an ellipse, a diamond, a pentagon, a hexagon, etc.
[0086] In an exemplary embodiment, the first electrode 11 may extend along the first direction D1. The first electrode 11 is located on the side opposite to the first direction D1 of the semiconductor layer 14. The first end of the first electrode 11 is connected to the first end of the semiconductor layer 14, and the second end of the first electrode 11 is connected to the first end of the first capacitor electrode 41 of the capacitor.
[0087] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 may be an integrated structure and formed of the same conductive material, such as tungsten.
[0088] In an exemplary embodiment, the first electrode 11 may be a part of a first capacitor electrode 41 to which the first electrode 11 is connected, and the first end of the semiconductor layer 14 of the transistor is connected to the first capacitor electrode 41 .
[0089] In an exemplary embodiment, the second electrode 12 may extend along the first direction D1 and is located on one side of the semiconductor layer 14 in the first direction D1. A first end of the second electrode 12 is connected to a second end of the semiconductor layer 14 , and a second end of the second electrode 12 is connected to the bit line 30 .
[0090] In an exemplary embodiment, the bit line 30 and the second electrode 12 may be an integrated structure and formed of the same conductive material, such as tungsten.
[0091] In an exemplary embodiment, the second electrode 12 may be a part of a bit line 30 to which the second electrode 12 is connected, and the second end of the semiconductor layer 14 of the transistor is connected to the bit line 30 .
[0092] In an exemplary embodiment, the second electrodes 12 of the transistors of the memory cells in two adjacent columns in the same layer are connected to the same bit line 30. The second electrodes 12 of the transistors in two adjacent columns in the same layer and the bit line 30 may be an integrated structure.
[0093] In an exemplary embodiment, the first electrode 11 and the second electrode 12 of the same transistor may be located in the same conductive film layer. It can be understood that the first electrode 11 and the second electrode 12 are located in the same conductive film layer, and are formed by patterning a conductive film layer, and the conductive film layer is approximately parallel to the upper surface of the substrate. The first electrode 11 and the second electrode 12 may be arranged in the same layer. That is, the first electrode 11 and the second electrode 12 may be formed simultaneously by the same patterning process, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the first electrode 11 and the second electrode 12 may be manufactured separately by different patterning processes.
[0094] In an exemplary embodiment, the first electrode 11 and the second electrode 12 are made of the same material. The first electrode 11 and the second electrode 12 may both be made of metal, such as tungsten.
[0095] In an exemplary embodiment, the semiconductor layer 14 may extend along the first direction D1. The semiconductor layer 14 is located in the same film layer as the first electrode 11 and the second electrode 12, and the semiconductor layer 14 is arranged in the same layer as the first electrode 11 and the second electrode 12. The first end of the semiconductor layer 14 is connected to the first end of the first electrode 11, and the second end of the semiconductor layer 14 is connected to the first end of the second electrode 11. The extension direction of the semiconductor layer 14 is approximately parallel to the upper surface of the substrate.
[0096] In an exemplary embodiment, the material of the semiconductor layer 14 may be a metal oxide. The metal oxide may be indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, a metal oxide containing In and / or Sn, etc. When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the negative 15th power ampere, and 1E-10A refers to 10 to the negative 10th power ampere, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and the like, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.
[0097] In an exemplary embodiment, the gate electrode 13 may be wrapped around the side wall of the semiconductor layer 14. The wrapping may be understood as partially or completely wrapping around the semiconductor layer 14. In some embodiments, the wrapping may be completely wrapped around as a whole, and the cross section of the gate electrode 13 after wrapping along the direction perpendicular to the substrate is a closed ring, and the ring shape is adapted to the outer contour of the cross section of the semiconductor layer 14. Exemplarily, the cross section of the gate electrode 13 is, for example, a square structure. In some embodiments, the wrapping may be partially wrapped around, and the cross section after wrapping is not closed, but presents a ring shape. For example, a ring with an opening.
[0098] The memory of the disclosed embodiment can effectively enhance the control capability of the gate electrode 13 by surrounding the gate electrode 13 on the side wall of the semiconductor layer 14 to increase the relative area between the gate electrode 13 and the semiconductor layer 14 .
[0099] In an exemplary embodiment, the memory cell may further include: a gate insulating layer 21 . The gate insulating layer 21 is disposed between the gate electrode 13 and the sidewall of the semiconductor layer 14 , and the gate electrode 13 is connected to the semiconductor layer 14 through the gate insulating layer 21 .
[0100] In an exemplary embodiment, the material of the gate insulating layer 21 is not limited, and can be a high-K dielectric material, that is, a dielectric material with a dielectric constant K ≥ 3.9. The high-K dielectric material can include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.
[0101] In an exemplary embodiment, the memory further includes: an isolation layer, wherein the isolation layer extends in a direction perpendicular to the substrate to separate gate electrodes of adjacent memory cells to prevent the gate electrodes of adjacent memory cells from being short-circuited.
[0102] In an exemplary embodiment, the memory cell may further include: a word line. The word line is a lead line shared by a plurality of vertically stacked transistors, and is a line extending perpendicular to the substrate direction, and the word line is connected to the gate electrode of each transistor. The gate electrode 13 may be a part of the word line. Of course, the word line may also be two lines, respectively located on both sides of the channel, and the two sides are approximately perpendicular to the substrate.
[0103] In an exemplary embodiment, if Figure 1d As shown, the memory further includes: a semiconductor dielectric layer 81 and an insulating dielectric layer 82, wherein the semiconductor dielectric layer 81 is disposed on the side of the storage unit away from the substrate, and the insulating dielectric layer 82 is disposed on the side of the semiconductor dielectric layer 81 away from the substrate. The semiconductor dielectric layer 81 can be made of the same semiconductor material as the semiconductor layer 14 and manufactured by the same deposition process; the insulating dielectric layer 82 can be made of the same insulating material as the gate insulating layer 21 and manufactured by the same deposition process.
[0104] The technical solution of this embodiment is further explained below through the manufacturing process of the memory of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".
[0105] In this embodiment, each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.
[0106] In an exemplary embodiment, the memory may be any of the above-mentioned memories, and the manufacturing process of the memory may include:
[0107] Step 101, forming an insulating layer, a conductive layer and a capacitor.
[0108] Forming the insulating layer, the conductive layer and the capacitor includes: forming a conductive layer 31 and an insulating layer 32 alternately arranged in a direction away from the substrate on the substrate 101, etching the conductive layer 31 and the insulating layer 32 in a patterned manner through a mask to form a groove extending in a direction perpendicular to the substrate, each layer of the insulating layer 32 forms a first patterned structure stacked on each other and distributed in sequence, each layer of the conductive layer 31 forms a second patterned structure stacked on each other and distributed in sequence, each layer of the second patterned structure includes a bit line and a plurality of branches extending in a direction perpendicular to the bit line;
[0109] Subsequently, a dielectric layer 33 is deposited on the substrate 101, the dielectric layer 33 fills the trench and covers the conductive layer 31 and the insulating layer 32; wherein the material of the dielectric layer may be silicon nitride;
[0110] Subsequently, the insulating layer 32 is patterned and etched to remove a portion of the insulating layer 32, so that multiple branches of the conductive layer 31 are exposed away from one end of the bit line, so that the exposed multiple branches of the conductive layer 31 form a first capacitor electrode 41; subsequently, a capacitor insulating layer 43 and a transition layer 44 are formed on the exposed multiple branches of the conductive layer 31 through an atomic layer deposition process; subsequently, a second capacitor electrode 42 is formed, and the second capacitor electrode 42 is connected to the first capacitor electrode 41 through the capacitor insulating layer 43 and the transition layer 44, and the first capacitor electrode 41 and the second capacitor electrode 42 form a capacitor, such as Figure 2a , Figure 2b and Figure 2c As shown. Among them, Figure 2a for Figure 1a A cross-sectional view in the a-a' direction after forming an insulating layer, a conductive layer and a capacitor in the manufacturing process of the memory shown; Figure 2b for Figure 1a A cross-sectional view in the direction bb' after forming an insulating layer, a conductive layer and a capacitor in the manufacturing process of the memory shown; Figure 2c for Figure 1a The cross-sectional view along the c-c' direction after forming an insulating layer, a conductive layer and a capacitor during the manufacturing process of the memory is shown.
[0111] In an exemplary embodiment, the dielectric layer 33 may isolate the second capacitor electrode 42 of the capacitor.
[0112] In an exemplary embodiment, the material of the first capacitor electrode 41 can be tungsten, the material of the second capacitor electrode 42 can be polysilicon, the material of the transition layer 44 can be titanium or titanium nitride, and the material of the capacitor insulating layer 43 can be a high-K dielectric material, which can include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.
[0113] In an exemplary embodiment, the insulating layer and the conductive layer may be deposited using a chemical vapor deposition method.
[0114] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate. Of course, it may be any substrate that plays a supporting role, not just a base, but may be a substrate formed by peripheral circuits on the substrate.
[0115] In an exemplary embodiment, the insulating layer serves to isolate devices and may be a low-K dielectric layer, ie, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) and the like.
[0116] Step 102: forming a groove.
[0117] The forming of the groove includes: on the basis of the substrate 101 formed with the aforementioned pattern, patterning the dielectric layer 33 to form a groove 51 extending in a direction perpendicular to the substrate, the sidewall of the groove 51 exposes the portion of the plurality of branches of the conductive layer 31 located between the bit line 30 and the first capacitor electrode 41 and the portion of the insulating layer 32, and the sidewall of the groove 51 does not expose the bit line 30, so that the sidewall of the bit line 30 is covered by the dielectric layer 33, such as Figure 3a and Figure 3b As shown. Among them, Figure 3a for Figure 1a A cross-sectional view along the bb' direction after a groove is formed during the manufacturing process of the memory shown; Figure 3b for Figure 1a The cross-sectional view along the c-c' direction after a groove is formed during the manufacturing process of the memory is shown.
[0118] Step 103: forming a first cavity.
[0119] The forming of the first cavity comprises: on the basis of the substrate 101 formed with the aforementioned pattern, through the groove 51, by wet etching, lateral selective etching is performed on the exposed portions of the multiple branches of the conductive layer 31 located between the bit line 30 and the first capacitor electrode 41, and the portions of the multiple branches of the conductive layer 31 located between the bit line 30 and the first capacitor electrode 41 are removed by etching to form a first cavity 52, wherein the multiple branches of the conductive layer 31 between the first cavity 52 and the first capacitor electrode 41 all form the first electrodes 11 of different transistors, and the multiple branches of the conductive layer 31 between the first cavity 52 and the bit line 30 all form the second electrodes 12 of different transistors, such as Figure 4a and 4b As shown, the lateral isotropic etching refers to etching the material of the conductive layer 31 along a direction parallel to the substrate 101 . Figure 4a for Figure 1a A cross-sectional view along the a-a' direction after a groove is formed during the manufacturing process of the memory shown; Figure 4b for Figure 1a The cross-sectional view along the c-c' direction after a groove is formed during the manufacturing process of the memory is shown.
[0120] Step 104: forming a semiconductor thin film.
[0121] The semiconductor film formation includes: on the basis of the substrate 101 formed with the aforementioned pattern, a semiconductor film 53 is deposited in the groove and the first cavity, and the semiconductor film 53 fills the groove and the first cavity, such as Figure 5a , Figure 5b and Figure 5c As shown. Among them, Figure 5a for Figure 1a A cross-sectional view in the a-a' direction after a semiconductor film is formed during the manufacturing process of the memory shown; Figure 5b for Figure 1a A cross-sectional view in the direction bb' after a semiconductor film is formed during the manufacturing process of the memory shown; Figure 5c for Figure 1a The cross-sectional view along the c-c' direction after a semiconductor thin film is formed during the manufacturing process of the memory is shown.
[0122] Step 105 , removing the semiconductor film in the groove.
[0123] Removing the semiconductor film in the groove includes: on the basis of the substrate 101 formed with the aforementioned pattern, patterning the semiconductor film 53 in the groove 51 is etched, the semiconductor film 53 in the groove 51 is removed, and the semiconductor film in the first cavity is retained, the semiconductor film in the first cavity forms a semiconductor layer 14, and the groove exposes the sidewall of the semiconductor layer 14 in the first cavity, such as Figure 6a and Figure 6b As shown. Among them, Figure 6a for Figure 1a A cross-sectional view along the direction bb' after the semiconductor film in the groove is removed during the manufacturing process of the memory shown; Figure 6b for Figure 1a A cross-sectional view along the c-c' direction after the semiconductor film in the groove is removed during the manufacturing process of the memory shown.
[0124] Step 106: forming a second cavity.
[0125] The second cavity is formed by selectively etching the exposed insulating layer 32 through the groove 51 on the substrate 101 having the aforementioned pattern, and removing the insulating layer 32 connected to the semiconductor layer 14 in the first cavity by etching to form a second cavity 54, wherein the second cavity 54 surrounds the sidewall of the semiconductor layer 14 in the first cavity. Figure 7a and 7b As shown. Among them, Figure 7a for Figure 1a A cross-sectional view along the aa' direction after the second cavity is formed during the manufacturing process of the memory shown; Figure 7b for Figure 1a The cross-sectional view along the c-c' direction after the second cavity is formed during the manufacturing process of the memory is shown.
[0126] Step 107 , forming a gate insulating layer and a gate electrode.
[0127] The gate insulating layer and the gate electrode are formed by sequentially depositing a gate insulating film and a conductive film on the inner wall of the groove and the second cavity by an atomic layer deposition process on the substrate 101 having the aforementioned pattern, wherein the conductive film fills the groove and the second cavity, the gate insulating film on the semiconductor layer 14 in the second cavity forms a gate insulating layer 21, and the conductive film on the semiconductor layer 14 in the second cavity forms a gate electrode 13, such as Figure 8a and Figure 8b .in, Figure 8a for Figure 1a A cross-sectional view along the a-a' direction after a gate insulating layer and a gate electrode are formed during the manufacturing process of the memory shown; Figure 8b for Figure 1a The cross-sectional view along the c-c' direction after forming a gate insulating layer and a gate electrode during the manufacturing process of the memory is shown.
[0128] In an exemplary embodiment, the first electrode 11 , the second electrode 12 , the semiconductor layer 14 , and the gate electrode 13 form a transistor.
[0129] Step 107: forming an isolation layer.
[0130] The formation of the isolation layer includes: firstly, on the basis of the substrate 101 formed with the aforementioned pattern, etching back to remove the conductive film on the side of the aforementioned pattern away from the substrate; then, selectively etching the conductive film in the groove to remove the conductive film in the groove, and depositing to form an isolation layer 61 extending in a direction perpendicular to the substrate, wherein the isolation layer 61 separates the gate electrodes 13 in adjacent transistors, such as Fig. 9 As shown. Among them, Fig. 9 for Figure 1a The cross-sectional view along the c-c' direction after forming an isolation layer during the manufacturing process of the memory is shown.
[0131] Step 108, forming an external channel.
[0132] The forming of the external connection channel includes: on the basis of the substrate 101 formed with the aforementioned pattern, forming an external connection channel 71 extending in a direction perpendicular to the substrate 101 on the dielectric layer 33 away from the substrate 101, wherein a first end of the external connection channel 71 is connected to the gate electrode 13, and a second end of the external connection channel 71 extends in a direction away from the substrate and is connected to an external circuit, such as Figure 1b and Figure 1d described.
[0133] The manufacturing method of the memory of the embodiment of the present disclosure forms grooves to expose multiple branches of the conductive layer and the insulating layer, removes the conductive layer through lateral etching to form a first cavity, and forms a semiconductor layer in the first cavity; then removes the insulating layer through lateral etching again to form a second cavity, and forms a gate insulating layer and a gate electrode in the second cavity through an atomic deposition process, so that the gate electrode surrounds the side wall of the semiconductor layer, increasing the relative area between the gate electrode and the semiconductor layer, which can effectively enhance the control ability of the gate electrode and improve the space utilization of the memory.
[0134] The manufacturing method of the memory in the embodiment of the present disclosure has a simple preparation process and low production cost.
[0135] The present disclosure also provides an electronic device, including the memory described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.
[0136] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.
Claims
1. A memory, characterized in that: include: A substrate, and a plurality of storage units stacked in a direction perpendicular to the substrate; The storage unit comprises: a transistor; The transistor includes a semiconductor layer, a first electrode, a second electrode and a gate electrode, the first electrode and the second electrode are connected through the semiconductor layer, the semiconductor layer, the first electrode and the second electrode are arranged in the same layer, the gate electrode surrounds the semiconductor layer, and a gate insulating layer is arranged between the gate electrode and the semiconductor layer.
2. The memory according to claim 1, characterized in that: The semiconductor layer, the first electrode, and the second electrode form a columnar structure parallel to the substrate.
3. The memory according to claim 2, characterized in that: The cross section of the columnar structure in a direction perpendicular to the substrate is rectangular.
4. The memory according to claim 1, characterized in that: Also includes: A bit line is parallel to the substrate and connected to the second electrode of the transistor.
5. The memory according to claim 4, characterized in that: The bit line and the second electrode of the transistor are an integrated structure and include a same conductive material.
6. The memory according to claim 1, characterized in that: The memory cell further includes a capacitor including a first capacitor electrode and a second capacitor electrode insulated from each other, wherein the first capacitor electrode is connected to the first electrode of the transistor.
7. The memory according to claim 6, characterized in that: The first capacitor electrode and the first electrode of the transistor are an integrated structure and include a same conductive material.
8. The memory according to any one of claims 1 to 7, characterized in that: The material of the semiconductor layer includes metal oxide.
9. The memory according to any one of claims 1 to 7, characterized in that: Also includes: The isolation layer is perpendicular to the substrate and separates gate electrodes of adjacent memory cells.
10. The memory according to any one of claims 1 to 7, characterized in that: Also includes: A semiconductor dielectric layer and an insulating dielectric layer, wherein the insulating dielectric layer is arranged on a side of the storage unit away from the substrate, and the semiconductor dielectric layer is arranged on a side of the insulating dielectric layer away from the substrate.
11. A method for manufacturing a memory, characterized in that: include: forming conductive layers and insulating layers alternately arranged in a direction away from the substrate on a substrate; Performing patterned etching to form a groove extending in a direction perpendicular to the substrate, wherein each layer of the conductive layer forms a patterned structure stacked on top of each other, and each layer of the patterned structure includes a bit line and a plurality of branches extending in a direction perpendicular to the bit line; filling the trench with a dielectric layer; Performing patterned etching to form a groove extending in a direction perpendicular to the substrate, wherein a sidewall of the groove exposes portions of the plurality of branches and a portion of the insulating layer; Performing selective etching to remove the exposed branches to form a first cavity, and retaining some branches on both sides of the first cavity to form a first electrode and a second electrode respectively; forming a semiconductor layer in the first cavity, wherein the semiconductor layer connects the first electrode and the second electrode; Performing selective etching to remove the exposed insulating layer to form a second cavity, wherein the second cavity surrounds the side wall of the semiconductor layer; An atomic layer deposition process is adopted to sequentially form a gate insulating layer and a gate electrode in the second cavity, so that the gate electrode surrounds the semiconductor layer, and the gate insulating layer is provided between the gate electrode and the semiconductor layer.
12. The method for manufacturing a memory according to claim 11, characterized in that: After sequentially forming a gate insulating layer and a gate electrode in the second cavity by an atomic layer deposition process, the method further includes: An isolation layer extending in a direction perpendicular to the substrate is formed in the groove, and the isolation layer separates adjacent gate electrodes.
13. An electronic device, characterized in that: Comprising the memory as claimed in any one of claims 1 to 10.