Semiconductor device structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor device structure, a preparation method thereof and electronic equipment. The memory comprises a substrate, a transistor array and a plurality of capacitors. Wherein the transistor array is located on the substrate, the transistor array comprises a plurality of transistors, the plurality of transistors are respectively arranged at intervals along a first direction, a second direction and a third direction, the first direction is perpendicular to the upper surface of the substrate, the second direction and the third direction are parallel to the upper surface of the substrate, the second direction intersects with the third direction, and the first direction is perpendicular to the first direction. One electrode of at least one capacitor surrounds one transistor. According to the semiconductor device structure provided by the invention, the process can be simplified, and the size of the semiconductor device structure is relatively small, so that the space utilization rate is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor device structure and a preparation method thereof, and electronic equipment. Background Art

[0002] DRAM (Dynamic Random Access Memory) is a storage device that plays an important role in ultra-large-scale integrated circuits. The traditional DRAM storage unit consists of one transistor and one capacitor, i.e., a 1T1C structure. As the aspect ratio of the storage capacitor in DRAM increases exponentially with the process shrinkage, the DRAM process shrinkage becomes increasingly difficult. Current DRAMs generally have problems such as complex manufacturing processes, large device sizes, and low space utilization. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor device structure and its preparation method and electronic device to address the above technical problems, which can effectively optimize the preparation process of the semiconductor device structure, simplify the preparation process, and make the device size smaller, thereby improving space utilization.

[0004] On the one hand, some embodiments of the present application provide a semiconductor device structure, including: a substrate, a transistor array and a plurality of capacitors, wherein the transistor array is located on the substrate, the transistor array includes a plurality of transistors, the plurality of transistors are arranged at intervals along a first direction, a second direction and a third direction, respectively, the first direction is perpendicular to the upper surface of the substrate, the second direction and the third direction are both parallel to the upper surface of the substrate, and the second direction intersects with the third direction; wherein an electrode of at least one capacitor surrounds a transistor.

[0005] In the embodiment of the present application, by setting the electrode of the capacitor to surround the transistor, the process can be simplified and the size of the semiconductor device structure can be reduced, thereby improving space utilization.

[0006] In some embodiments, the transistor includes: a word line conductive layer, a gate dielectric layer, and a channel layer. The word line conductive layer extends along the second direction; the gate dielectric layer is located on the surface of the word line conductive layer; the channel layer is located on the surface of the gate dielectric layer away from the word line conductive layer; and one electrode of the capacitor is located on the surface of the channel layer.

[0007] In some embodiments, the channel layer surrounds the word line conductive layer; the capacitor includes a first electrode, a capacitor dielectric layer and a second electrode stacked sequentially from the inside to the outside; the second electrode of the capacitor surrounds the channel layer, wherein the channel layer also serves as the first electrode of the capacitor.

[0008] In some embodiments, the material of the channel layer includes: indium gallium zinc oxide.

[0009] In some embodiments, the semiconductor device structure further includes: a plurality of bit lines, the plurality of bit lines are stacked and spaced apart along a first direction and extend along a third direction; transistors spaced apart along a second direction are respectively located on opposite sides of the bit lines and contact the bit lines located on the same layer.

[0010] In some embodiments, the bit line contacts the channel layers of transistors located at the same layer on both sides thereof.

[0011] In the embodiment of the present application, a plurality of bit lines are stacked and spaced along the first direction, and transistors are arranged on opposite sides of the bit lines and in contact with the bit lines on the same layer. This is conducive to the integrated arrangement of transistors, capacitors and bit lines, and improves the arrangement density of semiconductor devices per unit wafer area.

[0012] In some embodiments, a plurality of capacitors are arranged corresponding to the transistors and surround the corresponding transistors respectively; and a plurality of capacitors located on the same side of the bit line share a second electrode.

[0013] In the embodiment of the present application, capacitors are arranged around corresponding transistors, and multiple capacitors on the same side of the bit line share a common second electrode, so as to further improve the device integration of the semiconductor device structure.

[0014] In some embodiments, the semiconductor device structure further includes: an external circuit structure, which is electrically connected to the capacitor.

[0015] In some embodiments, the external circuit structure is electrically connected to the second electrode of the capacitor.

[0016] On the other hand, some embodiments of the present application provide a method for preparing a semiconductor device structure, which is used to prepare the semiconductor device structure described in some of the aforementioned embodiments. The technical advantages possessed by the semiconductor device structure described in some of the aforementioned embodiments are also possessed by the preparation method, which will not be described in detail here. The preparation method comprises the following steps.

[0017] providing a substrate;

[0018] A plurality of first stacking structures are formed on the upper surface of the substrate; each of the first stacking structures includes a sacrificial layer and a conductive layer alternately stacked in sequence along a first direction; and the plurality of first stacking structures are arranged at intervals along a second direction and a third direction respectively;

[0019] removing the conductive layer in the first stacked structure to form a first gap;

[0020] forming a transistor in the first gap;

[0021] removing the sacrificial layer in the first stacked structure to form a second gap;

[0022] A second electrode of the capacitor is formed at least in the second gap, and the second electrode of the capacitor surrounds the transistor.

[0023] In some embodiments, forming a plurality of first stacked structures on the upper surface of the substrate includes the following steps.

[0024] Forming sacrificial layers and conductive layers alternately stacked in sequence along a first direction on the upper surface of the substrate;

[0025] The sacrificial layer and the conductive layer are etched to form a first stacked structure.

[0026] In some embodiments, the sacrificial layer and the conductive layer are etched to form the first stacking structure while also forming a second stacking structure, the second stacking structure extending along a third direction; the conductive layer retained in the second stacking structure forms a bit line, and the sacrificial layer retained in the second stacking structure forms an isolation dielectric layer for adjacent bit lines; the first stacking structures arranged at intervals along the second direction are located on opposite sides of the second stacking structure.

[0027] In some embodiments, after forming a plurality of first stacked structures on the upper surface of the substrate and before removing the conductive layer in the first stacked structures to form the first gap, the preparation method further includes the following steps.

[0028] forming a first isolation layer, wherein the first isolation layer fills the gaps between the first stacked structures arranged at intervals along the third direction and at least covers the first stacked structures;

[0029] The first isolation layer is etched to expose the conductive layer in the first stacked structure.

[0030] In some embodiments, after forming a transistor in the first gap and before removing the sacrificial layer in the first stacked structure to form a second gap, the preparation method further includes: etching the first isolation layer to form a release gap.

[0031] Correspondingly, removing the sacrificial layer in the first stacked structure to form the second gap includes: removing the sacrificial layer in the first stacked structure based on the release gap to form the second gap.

[0032] In some embodiments, forming a transistor in the first gap includes the following steps.

[0033] forming a channel layer on a surface of the first gap;

[0034] forming a gate dielectric layer on the surface of the channel layer;

[0035] A word line conductive layer is formed on the surface of the gate dielectric layer.

[0036] In the embodiment of the present application, the word line conductive layer is also used as a component of the transistor (such as a gate conductive layer), so as to reduce the number of devices in the semiconductor device structure and simplify the manufacturing process.

[0037] In some embodiments, forming a capacitor at least in the second gap comprises the following steps.

[0038] forming a capacitor dielectric layer on the surface of the second gap and the surface of the release gap;

[0039] A second electrode is formed on the surface of the capacitor dielectric layer; and the channel layer of the transistor serves as the first electrode of the capacitor.

[0040] In the embodiment of the present application, the channel layer of the transistor is also used as the first electrode of the capacitor, so that the manufacturing process is further simplified while ensuring reliable electrical connection between the capacitor and the transistor.

[0041] In some embodiments, the capacitor dielectric layer and the second electrode further cover the second stacked structure; after the second electrode is formed on the surface of the capacitor dielectric layer, the preparation method further includes the following steps.

[0042] forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer also fills the second gap and the release gap;

[0043] forming a first covering dielectric layer on the upper surface of the electrode connection layer;

[0044] An isolation groove is formed in the first covering dielectric layer, wherein the isolation groove penetrates the first covering dielectric layer, the electrode connecting layer, the second electrode and the capacitor dielectric layer along a first direction and is arranged corresponding to the second stacking structure;

[0045] A second isolation layer is formed in the isolation groove and on the upper surface of the first covering dielectric layer; the second isolation layer insulates and isolates the capacitors on two opposite sides of the second stacking structure along the second direction, and allows multiple capacitors on the same side of the second stacking structure to share a second electrode.

[0046] In some embodiments, after forming the second isolation layer in the isolation layer and on the upper surface of the first covering dielectric layer, the preparation method further includes the following steps.

[0047] forming a second covering dielectric layer on the upper surface of the second isolation layer;

[0048] forming a contact hole, wherein the contact hole penetrates the second covering dielectric layer, the second isolation layer and the first covering dielectric layer along a first direction to expose the electrode connection layer;

[0049] An external circuit structure is formed in the contact hole, and the external circuit structure is in contact with the electrode connection layer.

[0050] On the other hand, some embodiments of the present application also provide an electronic device, which uses the semiconductor device structure described in some of the above embodiments as its practical application. The technical advantages possessed by the semiconductor device structure described in some of the above embodiments are also possessed by the preparation method, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 A schematic structural diagram of a semiconductor device structure provided in some embodiments;

[0053] Figure 2 for Figure 1 A schematic cross-sectional view of the structure shown along the AA direction;

[0054] Figure 3 for Figure 1 Another schematic cross-sectional view of the structure shown along the AA direction;

[0055] Figure 4 for Figure 1 A schematic cross-sectional view of the structure shown along the BB direction;

[0056] Figure 5 for Figure 1 A schematic cross-sectional view of the structure shown along the CC direction;

[0057] Figure 6 for Figure 1 A schematic cross-sectional view of the structure shown along the DD direction;

[0058] Figure 7 A schematic flow chart of a method for preparing a semiconductor device structure provided in some embodiments;

[0059] Figure 8 A schematic flow chart of another method for preparing a semiconductor device structure provided in some embodiments;

[0060] Fig. 9 A schematic diagram of a flow chart of step S400 provided in some embodiments;

[0061] Fig.10 A schematic flow chart of another method for preparing a semiconductor device structure provided in some embodiments;

[0062] Fig.11 A schematic diagram of a flow chart of step S600 provided in some embodiments;

[0063] Fig.12 A schematic flow chart of another method for preparing a semiconductor device structure provided in some embodiments;

[0064] Fig.13 A schematic diagram of a structure obtained after executing step S210 provided in some embodiments;

[0065] Fig.14 and Fig.15 is a schematic diagram of a structure obtained after executing step S220 provided in some embodiments; wherein, Fig.15 is a top view of the structure obtained after step S220, Fig.14 is a front view of the structure obtained after step S220;

[0066] Fig.16 and Fig.17 is a schematic diagram of a structure obtained after executing step S250 provided in some embodiments; wherein, Fig.17 is a top view of the structure obtained after step S250, Fig.16 is a front view of the structure obtained after step S250;

[0067] Fig.18 A schematic diagram of a top view of a structure obtained after executing step S260 provided in some embodiments;

[0068] Fig.19 For along Fig.18 Schematic diagram of the cross section in the AA direction;

[0069] Fig. 20 For along Fig.18 Schematic diagram of the cross section in the BB direction;

[0070] Fig.21 For along Fig.18 Schematic diagram of the cross section in the CC direction;

[0071] Fig. 22 A structure obtained after executing step S300 provided in some embodiments is Fig.18 Schematic diagram of the cross section in the AA direction;

[0072] Fig.23 A structure obtained after executing step S300 provided in some embodiments is Fig.18 Schematic diagram of the cross section in the CC direction;

[0073] Fig.24 A structure obtained after executing step S410 is provided in some embodiments. Fig.18 Schematic diagram of the cross section in the AA direction;

[0074] Fig.25 A structure obtained after executing step S420 is provided in some embodiments. Fig.18 Schematic diagram of the cross section in the AA direction;

[0075] Fig.26 A structure obtained after executing step S430 is provided in some embodiments. Fig.18 Schematic diagram of the cross section in the AA direction;

[0076] Fig. 27 A structure obtained after executing step S430 is provided in some embodiments. Fig.18 Schematic diagram of the cross section in the CC direction;

[0077] Fig.28 A schematic diagram of a top view of a structure obtained after executing step S450 provided in some embodiments;

[0078] Fig.29 For along Fig.28 Schematic diagram of the cross section in the BB direction;

[0079] Fig.30 A structure obtained after executing step S500' is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the AA direction;

[0080] Fig.31 A structure obtained after executing step S500' is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the CC direction;

[0081] Fig.32 A structure obtained after executing step S610 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the AA direction;

[0082] Fig.33 In some embodiments, a structure obtained after executing step S610 is provided along Fig.28 Schematic diagram of the cross section in the BB direction;

[0083] Fig.34 In some embodiments, a structure obtained after executing step S610 is provided along Fig.28 Schematic diagram of the cross section in the CC direction;

[0084] Fig.35 A structure obtained after executing step S620 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the AA direction;

[0085] Fig.36 A structure obtained after executing step S620 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the BB direction;

[0086] Fig.37 In some embodiments, a structure obtained after executing step S620 is provided along Fig.28 Schematic diagram of the cross section in the CC direction;

[0087] Fig.38 A structure obtained after executing step S700 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the AA direction;

[0088] Fig.39 A structure obtained after executing step S700 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the BB direction;

[0089] Fig.40 A structure obtained after executing step S700 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the CC direction;

[0090] Fig.41 A structure obtained after executing step S800 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the AA direction;

[0091] Fig.42 A structure obtained after executing step S800 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the BB direction;

[0092] Fig.43 A structure obtained after executing step S800 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the CC direction;

[0093] Fig.44 A structure obtained after executing step S900 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the AA direction;

[0094] Fig.45 A structure obtained after executing step S900 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the BB direction;

[0095] Fig.46 A structure obtained after executing step S1000 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the AA direction;

[0096] Fig.47 A structure obtained after executing step S1000 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the BB direction;

[0097] Fig.48 A structure obtained after executing step S1000 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the CC direction;

[0098] Fig.49 A structure obtained after executing step S1200 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the AA direction;

[0099] Fig.50 A structure obtained after executing step S1200 provided in some embodiments is Fig.28 Schematic diagram of the cross section in the CC direction;

[0100] Fig.51 A structure obtained after executing step S1300 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the AA direction;

[0101] Fig.52 A structure obtained after executing step S1300 is provided in some embodiments. Fig.28 Schematic diagram of the cross section in the CC direction.

[0102] Description of reference numerals:

[0103] 10-substrate, 20-transistor, 201-channel layer, 202-gate dielectric layer, 203-word line conductive layer, 30-capacitor, 301-capacitor dielectric layer, 302-second electrode, 40-bit line, 50-external circuit structure, 60A-first stacking structure, 60B-second stacking structure, 61-sacrificial layer, 62-conductive layer, 71-first isolation layer, 72-second isolation layer, 80-electrode connection layer; 91-first covering dielectric layer, 92-second covering dielectric layer, G0-release gap, G1-first gap, G2-second gap, G3-isolation groove, G4-contact hole. DETAILED DESCRIPTION

[0104] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0105] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0106] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0107] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0108] Please combine Figures 1 to 6 It is understood that in some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes: a substrate 10, a transistor array, and a plurality of capacitors 30. The transistor array is located on the substrate 10, and the transistor array includes a plurality of transistors 20, and the plurality of transistors 20 are arranged in a first direction, a second direction, and a third direction, respectively, the first direction is perpendicular to the top of the substrate 10, the second direction and the third direction are parallel to the top surface of the substrate 10, and the second direction intersects with the third direction; wherein, one electrode of at least one capacitor 30 surrounds one transistor 20.

[0109] In the embodiment of the present application, by setting the electrode of the capacitor 30 to surround the transistor, the process can be simplified and the size of the semiconductor device structure can be reduced, thereby improving space utilization.

[0110] For example, the first direction is, for example, the Z direction, the second direction is, for example, the X direction, and the third direction is, for example, the Y direction. The first direction (Z direction) is perpendicular to the upper surface of the substrate 10, the second direction (X direction) and the third direction (Y direction) are both parallel to the upper surface of the substrate 10, and the second direction (X direction) intersects with the third direction (Y direction). In order to more clearly illustrate the composition of the semiconductor device provided by the present application, the following embodiments and drawings continue the definitions of the first direction, the second direction, and the third direction herein.

[0111] Here, the electrode of the capacitor 30 surrounds the transistor 20, which means that at least one electrode of the capacitor 30 surrounds the transistor 20, that is, the orthographic projection of one electrode of the transistor 20 on the YZ plane falls into the orthographic projection of the capacitor 20 on the YZ plane. In addition, in some embodiments, one or more capacitors 30 surround the corresponding transistor 20.

[0112] For example, the substrate 10 may be composed of, but not limited to, any combination of semiconductor materials, insulating materials, conductor materials, or their material types. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on insulator. This application is not limited by comparison.

[0113] Please continue reading Figure 2 and Figure 4 In some embodiments, the transistor 20 includes: a channel layer 201, a gate dielectric layer 202, and a word line conductive layer 203. The word line conductive layer 203 extends along the second direction (for example, the X direction); the gate dielectric layer 202 is located on the surface of the word line conductive layer 203; the channel layer 201 is located on the surface of the gate dielectric layer 202 away from the word line conductive layer 203; and one electrode of the capacitor 30 is located on the surface of the channel layer 201.

[0114] By way of example, the material of the word line conductive layer 203 includes: one or more of metal tungsten, metal titanium, metal aluminum, metal copper and metal nickel.

[0115] By way of example, the word line conductive layer 203 may be a single-layer structure, or may be a multi-layer structure including a plurality of different metal materials.

[0116] By way of example, the gate dielectric layer 202 covers a surface of the word line conductive layer 203 .

[0117] For example, the material of the gate dielectric layer 202 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium dioxide.

[0118] For example, the channel layer 201 covers a surface of the gate dielectric layer 202 away from the word line conductive layer 203 .

[0119] By way of example, the material of the channel layer 201 may include: single crystal silicon, polycrystalline silicon, silicon germanium, or indium tin zinc oxide.

[0120] It should be noted that a word line conductive layer 203 and its peripheral gate dielectric layer 202 and channel layer 201 may constitute a transistor 20 ; or a word line conductive layer 203 may be a gate shared by a string of transistors 20 .

[0121] For example, the capacitor 30 may include: a first electrode, a capacitor dielectric layer 301 and a second electrode 302 . The capacitor dielectric layer 301 surrounds at least a portion of the circumference of the channel layer 201 ; and the second electrode 302 surrounds the capacitor dielectric layer 301 .

[0122] Here, the channel layer 201 in contact with the capacitor dielectric layer 301 can also serve as one of the electrodes of the capacitor 30 (eg, the first electrode) to improve the integration of the semiconductor device.

[0123] See also Figure 2 and Figure 3 It is understood that in some embodiments, the size of the capacitor 30 along the second direction (e.g., the X direction) can also be adjusted, for example, so that the size of the capacitor 30 along the second direction is equal to or greater than the size of the transistor 20 along the second direction, so as to further increase the surface area of ​​the capacitor 30, thereby increasing the capacitance.

[0124] Please continue reading Figure 4 and 6 In some embodiments, the semiconductor device structure further includes: a plurality of bit lines 40, the plurality of bit lines 40 are stacked and spaced apart along a first direction (e.g., Z direction) and extend along a third direction (e.g., Y direction); transistors 20 spaced apart along a second direction (e.g., X direction) are respectively located on opposite sides of the bit lines 40 and are in contact with the bit lines 40 located on the same layer.

[0125] By way of example, the plurality of transistors 20 are respectively located on two opposite sides of the bit line 40 , and the channel layer 201 of the transistor 20 is also in contact with the bit line 40 to achieve electrical connection.

[0126] Please continue reading Figure 2 and Figure 5 In some embodiments, a plurality of capacitors 30 are disposed corresponding to the transistors 20 and surround the corresponding transistors 20 respectively; a plurality of capacitors 30 located on the same side of the bit line 40 share the second electrode 302 .

[0127] Here, the fact that the plurality of capacitors 30 share the second electrode 302 means that the second electrodes 302 of the plurality of capacitors 30 are electrically connected together.

[0128] For example, an electrode connection layer 80 may be provided to cover the surfaces of the second electrodes 302 of the plurality of capacitors 30 located on the same side of the bit line 40 , so as to achieve corresponding electrical connection.

[0129] In some embodiments, the semiconductor device structure further includes: an external circuit structure 50 ; the external circuit structure 50 is electrically connected to the capacitor 30 .

[0130] In some embodiments, the external circuit structure 50 is electrically connected to the second electrode 302 of the capacitor 30 .

[0131] For example, the external circuit structure 50 may be a conductive plug, which may lead out the corresponding capacitor 30 to facilitate electrical connection with an external control circuit, thereby realizing functions such as current writing.

[0132] See also Figure 7 Some embodiments of the present application also provide a method for preparing a semiconductor device structure, which is used to prepare the semiconductor device structure described in some of the above embodiments. The technical advantages possessed by the semiconductor device structure described in some of the above embodiments are also possessed by the preparation method, which will not be described in detail here. The preparation method includes steps S100 to S600.

[0133] S100 , providing a substrate.

[0134] S200, forming a plurality of first stacking structures on the upper surface of the substrate; each of the first stacking structures includes sacrificial layers and conductive layers alternately stacked in sequence along a first direction; and the plurality of first stacking structures are arranged at intervals along a second direction and a third direction, respectively.

[0135] S300 , removing the conductive layer in the first stacked structure to form a first gap.

[0136] S400 , forming a transistor in the first gap.

[0137] S500 , removing the sacrificial layer in the first stacked structure to form a second gap.

[0138] S600 , forming a second electrode of the capacitor at least in the second gap, wherein the second electrode of the capacitor surrounds the transistor.

[0139] See also Figure 8 In some embodiments, step S200 may include steps S210 to S220.

[0140] S210 , forming sacrificial layers and conductive layers alternately stacked in sequence along a first direction on an upper surface of the substrate.

[0141] S220, etching the sacrificial layer and the conductive layer to form a first stacked structure.

[0142] Please continue reading Figure 8 In some embodiments, after step S220 and before step S300, the preparation method further includes steps S250 to S260.

[0143] S250 , forming a first isolation layer, wherein the first isolation layer fills the gaps between the first stacked structures arranged at intervals along the third direction and at least covers the first stacked structures.

[0144] S260, etching the first isolation layer to expose the conductive layer in the first stacked structure.

[0145] It should be noted that, in some embodiments, while executing the aforementioned step S220, a second stacking structure is also synchronously formed, and the second stacking structure extends along a third direction (for example, the Y direction); the conductive layer retained in the second stacking structure forms a bit line, and the sacrificial layer retained in the second stacking structure forms an isolation dielectric layer for adjacent bit lines; the first stacking structures arranged at intervals along the second direction (for example, the X direction) are located on opposite sides of the second stacking structure.

[0146] Correspondingly, in step S250, the first isolation layer also covers the second stacking structure; in step S260, the first isolation layer located at one end of the first stacking structure away from the second stacking structure along the second direction is etched to expose the conductive layer in the first stacking structure.

[0147] See also Fig. 9 In some embodiments, step S400 includes steps S410 to S430.

[0148] S410 , forming a channel layer on a surface of the first gap.

[0149] S420, forming a gate dielectric layer on the surface of the channel layer.

[0150] S430, forming a word line conductive layer on the surface of the gate dielectric layer.

[0151] Here, the word line conductive layer also fills up the first gap, and the word line conductive layer also serves as a gate conductive layer.

[0152] See also Fig.10 In some embodiments, after executing step S400 and before executing step S500, the preparation method further includes:

[0153] S450, etching the first isolation layer to form a release gap.

[0154] Correspondingly, the preparation method further comprises:

[0155] S500 ′, removing the sacrificial layer in the first stacked structure based on the release gap to form a second gap.

[0156] See also Fig.11 In some embodiments, step S600 includes steps S610 to S620.

[0157] S610, forming a capacitor dielectric layer on a surface of the second gap and a surface of the release gap.

[0158] S620, forming a second electrode on the surface of the capacitor dielectric layer; the channel layer of the transistor serves as the first electrode of the capacitor.

[0159] Here, the second electrode, the capacitor dielectric layer and the first electrode (ie, a portion of the channel layer of the transistor) together form a capacitor surrounding the transistor.

[0160] See also Fig.12 In some embodiments, the capacitor dielectric layer and the second electrode further cover the second stacked structure. After step S600, the preparation method further includes steps S700 to S1300.

[0161] S700, forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer also fills the second gap and the release gap.

[0162] S800 , forming a first covering dielectric layer on the upper surface of the electrode connection layer.

[0163] S900 , forming an isolation trench in the first covering dielectric layer, wherein the isolation trench penetrates the first covering dielectric layer, the electrode connection layer, the second electrode and the capacitor dielectric layer along a third direction and is arranged corresponding to the second stacking structure.

[0164] S1000, forming a second isolation layer in the isolation groove and on the upper surface of the first covering dielectric layer; the second isolation layer insulates and isolates the capacitors on two opposite sides of the second stacking structure along the second direction, and allows multiple capacitors on the same side of the second stacking structure to share a second electrode.

[0165] S1100 , forming a second covering dielectric layer on an upper surface of the second isolation layer.

[0166] S1200 , forming a contact hole, wherein the contact hole penetrates the second covering dielectric layer, the second isolation layer and the first covering dielectric layer along a first direction to expose the electrode connection layer.

[0167] S1300, forming an external circuit structure in the contact hole, wherein the external circuit structure is in contact with the electrode connection layer.

[0168] In addition, in the above embodiments of the present application, unless otherwise clearly stated herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0169] In order to more clearly illustrate the method for preparing the semiconductor device structure in some of the above embodiments, the following embodiments are combined with Figure 12 to Figure 52 The preparation methods of some semiconductor device structures are described in detail.

[0170] In step S100, refer to Fig.12 S100 and Fig.13 , providing a substrate 10.

[0171] For example, the substrate 10 may be composed of, but not limited to, any combination of semiconductor materials, insulating materials, conductor materials, or their material types. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on insulator. This application is not limited by comparison.

[0172] In step S200, refer to Fig.12 S200 and Figures 13 to 15 , a plurality of first stacking structures 60A are formed on the upper surface of the substrate 10; each first stacking structure 60A includes a sacrificial layer 61 and a conductive layer 62 alternately stacked in sequence along a first direction (for example, the Z direction); the plurality of first stacking structures 60A are arranged at intervals along a second direction (for example, the X direction) and a third direction (for example, the Y direction).

[0173] Specifically, a portion of the plurality of first stacked structures 60A are arranged at intervals along the second direction, and another portion of the first stacked structures 60A are arranged at intervals along the third direction.

[0174] Illustratively, step S200 includes steps S210 to S220.

[0175] In step S210, refer to Figure 8 S210 and Fig.13 , a sacrificial layer 61 and a conductive layer 62 are formed on the upper surface of the substrate 10 and are alternately stacked in sequence along a first direction (eg, Z direction).

[0176] For example, the material of the sacrificial layer 61 may include, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride.

[0177] For example, the material of the conductive layer 62 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0178] In one example, the material of the sacrificial layer 61 is, for example, silicon oxide; the material of the conductive layer 62 is, for example, metal tungsten.

[0179] In step S220, refer to Figure 8 S220 and Figure 14 to Figure 15 , the sacrificial layer 61 and the conductive layer 62 are etched to form a first stacked structure 60A.

[0180] Here, while the first stack structure 60A is being formed, the second stack structure 60B may also be formed simultaneously.

[0181] For example, the second stacked structure 60B extends along a third direction (e.g., the Y direction); the conductive layer 62 retained in the second stacked structure 60B forms a bit line 40, and the sacrificial layer 61 retained in the second stacked structure 60B forms an isolation dielectric layer for adjacent bit lines 40; the first stacked structures 60A arranged at intervals along the second direction (e.g., the X direction) are located on opposite sides of the second stacked structure 60B.

[0182] For example, an initial stacking structure consisting of sacrificial layers 61 and conductive layers 62 alternately stacked in sequence along a first direction (for example, the Z direction) can be first formed on the substrate 10, and then the first stacking structure 60A and the second stacking structure 60B can be synchronously obtained by patterning the initial stacking structure; specifically, the first stacking structure 60A and the second stacking structure 60B can be synchronously obtained by etching the initial stacking structure.

[0183] In step S250, refer to Figure 8 S250 and Figure 16 to Figure 17 , forming a first isolation layer 71, the first isolation layer 71 fills the gaps between the first stacked structures 60A arranged at intervals along the third direction (eg, the Y direction) and at least covers the first stacked structures 60A.

[0184] When the second stacked structure 60B is formed, the first isolation layer 71 also covers the second stacked structure 60B.

[0185] For example, a first isolation layer 71 covering the first stacked structure 60A, the second stacked structure 60B and the exposed surface of the substrate 10 may be formed by processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporative growth, molecular beam epitaxy or vapor phase film formation.

[0186] For example, the material of the first isolation layer 71 may include but is not limited to: silicon oxide, silicon nitride or silicon oxynitride. In one example, the material of the first isolation layer 71 is, for example, silicon nitride.

[0187] In step S260, refer to Figure 8 S260 and Figures 18 to 21 , the first isolation layer 71 is etched to expose the conductive layer 62 in the first stacked structure 60A.

[0188] Here, the first isolation layers 71 located on two opposite sides of the first stack structure 60A along the third direction (eg, the Y direction) need to be retained so that subsequent steps can be performed smoothly.

[0189] For example, a photolithography process can be used to form a patterned mask layer on the surface of the first isolation layer 71, and the patterned mask layer has an opening pattern that exposes one end of the first stacked structure 60A away from the bit line 40 along the second direction (for example, the X direction). The first isolation layer 71 is etched based on the opening pattern to expose the conductive layer 62 in the first stacked structure 60A.

[0190] In step S300, refer to Fig.12 S300 and Figure 22 to Figure 23 , the conductive layer 62 in the first stacked structure 60A is removed to form a first gap G1.

[0191] For example, a wet etching process may be used to etch and remove one end of the exposed conductive layer 62 , and parameters such as etching time may be adjusted to facilitate controlling the extension length of the obtained first gap G1 along the second direction (eg, X direction).

[0192] It should be noted that, since this step does not involve further direct processing of the first isolation layer 71, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be referred to as Fig. 20 understand.

[0193] In step S400, refer to Fig.12 S400 and Figure 24 to Figure 27 , a transistor 20 is formed in the first gap G1.

[0194] Illustratively, step S400 includes steps S410 to S430.

[0195] In step S410, refer to Fig. 9 S410 and Fig.24 , a channel layer 201 is formed on the surface of the first gap G1.

[0196] For example, the channel layer 201 may be formed to cover the surface of the first gap G1 by using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy or vapor phase film formation.

[0197] For example, the material of the channel layer 201 may include but is not limited to: single crystal silicon, polycrystalline silicon, germanium silicon or indium tin zinc oxide. In one example, the material of the channel layer 201 is, for example, indium tin zinc oxide.

[0198] In step S420, refer to Fig. 9 S420 and Fig.25 , a gate dielectric layer 202 is formed on the surface of the channel layer 201 .

[0199] For example, the gate dielectric layer 202 may be formed to cover the surface of the channel layer 201 by using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy or vapor phase film formation.

[0200] For example, the material of the gate dielectric layer 202 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, or hafnium dioxide.

[0201] In step S430, refer to Fig. 9 S430 and Figure 26 to Figure 27 , a word line conductive layer 203 is formed on the surface of the gate dielectric layer 202 .

[0202] Here, the word line conductive layer 203 also fills the first gap G1 and also serves as a gate conductive layer. The channel layer 201 , the gate dielectric layer 202 and the word line conductive layer 203 together constitute the transistor 20 , wherein the channel layer 201 also serves as a first electrode of the capacitor 30 .

[0203] For example, the word line conductive layer 203 covering the surface of the channel layer 201 and filling the first gap G1 may be formed by a process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or evaporation.

[0204] For example, the material of the word line conductive layer 203 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0205] It should be noted that since step S400 (including step S410 to step S430) does not involve further direct processing of the first isolation layer 71, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can refer to Fig.19 understand.

[0206] It should be further explained that one transistor 20 may be formed in one first gap G1; or a string of transistors 20 may be formed in one first gap G1, and a string of multiple transistors 20 in the same first gap G1 share the same word line conductive layer 203 as a common gate.

[0207] In step S450, refer to Fig.12 S450 and Figure 28 to Figure 29 , the first isolation layer 71 is etched to form a release gap G0.

[0208] Here, it is necessary to etch and remove portions of the first isolation layer 71 located on two opposite sides of the first stack structure 60A along the third direction (eg, the Y direction).

[0209] For example, a photolithography process can be used to form a patterned mask layer on the surface of the first isolation layer 71. The patterned mask layer has an opening pattern that exposes the first stacking structure 60A on two opposite sides along a third direction (for example, the Y direction). The first isolation layer 71 is etched based on the opening pattern to obtain a release gap G0.

[0210] It should be noted that, since this step does not involve further direct processing of the first stacked structure 60A, the cross-sectional schematic diagram of the structure obtained after executing this step along the AA direction can be referred to as Fig.26 understand.

[0211] In step S500', refer to Fig.12 S500' and Figure 30 to Figure 31 , the sacrificial layer 61 in the first stacked structure 60A is removed based on the release gap G0 to form a second gap G2.

[0212] Here, the second gap G2 also exposes a portion of the surface of the channel layer 201. Optionally, ion implantation may be performed on the exposed surface of the channel layer 201 to further enhance its conductivity, thereby improving the electrical performance of the semiconductor device.

[0213] For example, a wet etching process may be used to etch and remove the exposed sacrificial layer 61 along a third direction (eg, Y direction) based on the release gap G0 to form the second gap G2 .

[0214] For example, the orthographic projection of the second gap G2 on the substrate 10 falls within the orthographic projection of the first gap G1 on the substrate 10 in the same first stacked structure 60A.

[0215] It should be noted that since this step does not involve further direct processing of the release gap G0, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be referred to as Fig.29 understand.

[0216] In step S600 , a second electrode 302 of the capacitor 30 is formed at least in the second gap G2 . The second electrode 302 of the capacitor 30 surrounds the transistor 20 .

[0217] Illustratively, step S600 includes steps S610 to S620.

[0218] In step S610, refer to Fig.12 S610 and Figure 32 to Figure 34 A capacitor dielectric layer 301 is formed on the surface of the second gap G2 and the surface of the release gap G0.

[0219] For example, the capacitor dielectric layer 301 may be formed by covering the surface of the second gap G2 and the surface of the release gap G0 using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy or vapor phase film formation.

[0220] For example, the capacitor dielectric layer 301 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0221] In step S620, refer to Fig.12 S620 and Figure 35 to Figure 37 , a second electrode 302 is formed on the surface of the capacitor dielectric layer 301 ; the channel layer 201 of the transistor 20 serves as the first electrode of the capacitor 30 .

[0222] Here, the second electrode 302 , the capacitor dielectric layer 301 and the first electrode (ie, a portion of the channel layer 201 of the transistor 20 ) together form a capacitor 30 surrounding the transistor 20 .

[0223] For example, the second electrode 302 covering the surface of the capacitor dielectric layer 301 may be formed by, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or evaporation processes.

[0224] For example, the material of the second electrode 302 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0225] In step S700, refer to Fig.12 S700 and Figures 38 to 40, an electrode connection layer 80 is formed on the surface of the second electrode 302 , and the electrode connection layer 80 also fills the second gap G2 and the release gap G0 .

[0226] For example, processes such as but not limited to chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy or vapor phase film formation can be used to form an electrode connection layer 80 that covers the surface of the second electrode 302 and fills the second gap G2 and releases the gap G0.

[0227] Here, the electrode connection layer 80 can electrically connect the second electrodes 302 of the plurality of capacitors 30 together, so as to increase the charge capacity and perform subsequent charge and discharge control.

[0228] For example, the material of the electrode connection layer 80 may include but is not limited to metal materials or semiconductor materials.

[0229] By way of example, the material of the electrode connection layer 80 may be, for example, doped polysilicon.

[0230] In step S800, refer to Fig.12 S800 and Figure 41 to Figure 43 , a first covering dielectric layer 91 is formed on the upper surface of the electrode connecting layer 80 .

[0231] Illustratively, the first cover layer 91 may include a single-layer structure or a multi-layer structure.

[0232] For example, the first covering dielectric layer 91 covering the upper surface of the electrode connection layer 80 may be formed by, but not limited to, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy or vapor phase film formation.

[0233] For example, the material of the first cover dielectric layer 91 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0234] In step S900, refer to Fig.12 S900 and Figure 44 to Figure 45 An isolation groove G3 is formed in the first covering dielectric layer 91. The isolation groove G3 also penetrates the first covering dielectric layer 91, the electrode connecting layer 80, the second electrode 302 and the capacitor dielectric layer 301 along the first direction (for example, the Z direction), and is arranged corresponding to the second stacking structure 60B.

[0235] Here, the isolation trench G3 and the second stacking structure 60B are arranged correspondingly, which means that the orthographic projection of the isolation trench G3 on the substrate 10 coincides with or substantially coincides with the orthographic projection of the second stacking structure 60B on the substrate 10 .

[0236] For example, a photolithography process can be used to form a patterned mask layer on the first covering layer 91, and the patterned mask layer has an opening pattern that defines the formation position of the isolation groove G3. Based on the opening pattern, the first covering dielectric layer 91, the electrode connection layer 80, the second electrode 302 and the capacitor dielectric layer 301 are etched in sequence, and the first isolation layer 71 is used as an etching stop layer to obtain the isolation groove G3.

[0237] It should be noted that, since this step does not involve further direct processing of the film layer structure located above the first stacked structure 60A, the cross-sectional schematic diagram of the structure obtained after executing this step along the CC direction can be referred to as Fig.43 understand.

[0238] In step S1000, refer to Fig.12 S1000 and Figure 46 to Figure 48 A second isolation layer 72 is formed in the isolation groove G3 and on the upper surface of the first covering dielectric layer 91; the second isolation layer 72 insulates and isolates the capacitors 30 on opposite sides of the second stacking structure 60B along the second direction (for example, the X direction), and allows multiple capacitors 30 located on the same side of the second stacking structure 60B to share the second electrode 302.

[0239] For example, the second isolation layer 72 filling the isolation groove G3 and covering the upper surface of the first covering dielectric layer 91 may be formed by processes such as but not limited to chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy or vapor phase film formation.

[0240] For example, the material of the second isolation layer 72 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass. In one example, the material of the second isolation layer 72 is, for example, silicon oxide.

[0241] In step S1100, refer to Fig.12 S1100 and Fig.49 , a second covering dielectric layer 92 is formed on the upper surface of the second isolation layer 72 .

[0242] By way of example, the second cover dielectric layer 92 may include a single-layer structure or a multi-layer structure.

[0243] For example, the second covering dielectric layer 92 covering the upper surface of the second isolation layer 72 may be formed by, but not limited to, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy or vapor phase film formation.

[0244] For example, the material of the second cover dielectric layer 92 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borosilicate glass. In one example, the material of the second isolation layer 72 is, for example, silicon nitride.

[0245] In step S1200, refer to Fig.12 S1200 and Figures 49 to 50 , forming a contact hole G4, which penetrates the second covering dielectric layer 92, the second isolation layer 72 and the first covering dielectric layer 91 along a first direction (eg, Z direction), exposing the electrode connection layer 80.

[0246] For example, a photolithography process can be used to form a patterned mask layer on the second covering layer 92. The patterned mask layer has an opening pattern that defines the formation position of the contact hole G4. Based on the opening pattern, the second covering dielectric layer 92, the second isolation layer 72 and the first covering dielectric layer 91 are etched in sequence, and the electrode connection layer 80 is used as an etching stop layer to obtain the contact hole G4.

[0247] It should be noted that, since this step does not involve further direct processing of the first isolation layer 71, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be referred to as Fig.47 understand.

[0248] In step S1300, refer to Fig.12 S1300 and Figure 51 to Figure 52 , an external circuit structure 50 is formed in the contact hole G4, and the external circuit structure 50 is in contact with the electrode connection layer 80.

[0249] For example, the external circuit structure 50 may be a conductive plug, which may lead out the corresponding capacitor 30 to facilitate electrical connection with an external control circuit, thereby realizing functions such as current writing.

[0250] For example, the material of the external circuit structure 50 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper or metal nickel.

[0251] By way of example, the external circuit structure 50 may be a single-layer structure or a multi-layer structure.

[0252] It should be noted that, since this step does not involve further direct processing of the first isolation layer 71, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be referred to as Fig.47 understand.

[0253] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0254] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0255] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A semiconductor device structure, characterized in that: include: substrate; A transistor array is located on the substrate; the transistor array includes a plurality of transistors, and the plurality of transistors are arranged at intervals along a first direction, a second direction, and a third direction; the first direction is perpendicular to the upper surface of the substrate; the second direction and the third direction are both parallel to the upper surface of the substrate, and the second direction intersects the third direction; A plurality of capacitors; wherein an electrode of at least one of the capacitors surrounds one of the transistors.

2. The semiconductor device structure according to claim 1, characterized in that: The transistor comprises: A word line conductive layer extending along the second direction; A gate dielectric layer, located on a surface of the word line conductive layer; A channel layer is located on a surface of the gate dielectric layer away from the word line conductive layer; and one electrode of the capacitor is located on a surface of the channel layer.

3. The semiconductor device structure according to claim 2, characterized in that: The channel layer surrounds the word line conductive layer; the capacitor comprises a first electrode, a capacitor dielectric layer and a second electrode stacked sequentially from the inside to the outside; the second electrode of the capacitor surrounds the channel layer, wherein the channel layer also serves as the first electrode of the capacitor.

4. The semiconductor device structure according to claim 3, characterized in that: The material of the channel layer includes: indium gallium zinc oxide.

5. The semiconductor device structure according to claim 4, characterized in that: The semiconductor device structure also includes: a plurality of bit lines, which are stacked and spaced apart along the first direction and extend along the third direction; the transistors spaced apart along the second direction are respectively located on opposite sides of the bit lines and are in contact with the bit lines located on the same layer.

6. The semiconductor device structure according to claim 5, characterized in that: The bit line contacts the channel layers of the transistors located at the same layer on both sides thereof.

7. The semiconductor device structure according to claim 6, characterized in that: The plurality of capacitors are arranged corresponding to the transistors and surround the corresponding transistors respectively; the plurality of capacitors located at the same side of the bit line share the second electrode.

8. The semiconductor device structure according to claim 7, characterized in that: The semiconductor device structure further includes an external circuit structure, and the external circuit structure is electrically connected to the capacitor.

9. The semiconductor device structure according to any one of claims 1 to 8, characterized in that: The external circuit structure is electrically connected to the second electrode of the capacitor.

10. A method for preparing a semiconductor device structure, characterized in that: include: providing a substrate; forming a plurality of first stacking structures on the upper surface of the substrate; Each of the first stacked structures includes sacrificial layers and conductive layers alternately stacked in sequence along the first direction; A plurality of the first stacking structures are arranged at intervals along the second direction and the third direction respectively; removing the conductive layer in the first stacked structure to form a first gap; forming a transistor in the first gap; removing the sacrificial layer in the first stacked structure to form a second gap; A second electrode of a capacitor is formed at least in the second gap, and the second electrode of the capacitor surrounds the transistor.

11. The method for preparing a semiconductor device structure according to claim 10, wherein forming a plurality of first stacked structures on the upper surface of the substrate comprises: forming a sacrificial layer and a conductive layer alternately stacked in sequence along the first direction on the upper surface of the substrate; The sacrificial layer and the conductive layer are etched to form the first stacked structure.

12. The method for manufacturing a semiconductor device structure according to claim 11, wherein the etching of the sacrificial layer and the conductive layer to form the first stacking structure also forms a second stacking structure, and the second stacking structure extends along the third direction; The conductive layer retained in the second stack structure forms a bit line, and the sacrificial layer retained in the second stack structure forms an isolation dielectric layer adjacent to the bit line; The first stacking structures arranged at intervals along the second direction are located on two opposite sides of the second stacking structure.

13. The method for preparing a semiconductor device structure according to claim 12, after forming a plurality of first stacked structures on the upper surface of the substrate and before removing the conductive layer in the first stacked structures to form the first gap, further comprising: forming a first isolation layer, wherein the first isolation layer fills the gaps between the first stacked structures arranged at intervals along the third direction and at least covers the first stacked structures; The first isolation layer is etched to expose the conductive layer in the first stacked structure.

14. The method for preparing a semiconductor device structure according to claim 13, After forming a transistor in the first gap and before removing the sacrificial layer in the first stacked structure to form a second gap, the method further includes: Etching the first isolation layer to form a release gap; The removing the sacrificial layer in the first stacked structure to form the second gap includes: removing the sacrificial layer in the first stacked structure based on the release gap to form the second gap.

15. The method for manufacturing a semiconductor device structure according to claim 14, wherein forming a transistor in the first gap comprises: forming a channel layer on a surface of the first gap; forming a gate dielectric layer on a surface of the channel layer; A word line conductive layer is formed on the surface of the gate dielectric layer.

16. The method for manufacturing a semiconductor device structure according to claim 14, wherein forming a capacitor at least in the second gap comprises: forming a capacitor dielectric layer on a surface of the second gap and a surface of the release gap; forming a second electrode on the surface of the capacitor dielectric layer; The channel layer of the transistor serves as a first electrode of the capacitor.

17. The method for preparing a semiconductor device structure according to claim 16, wherein the capacitor dielectric layer and the second electrode also cover the second stacked structure; after forming the second electrode on the surface of the capacitor dielectric layer, the method further comprises: forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer also fills the second gap and the release gap; forming a first covering dielectric layer on the upper surface of the electrode connection layer; forming an isolation groove in the first covering dielectric layer, wherein the isolation groove penetrates the first covering dielectric layer, the electrode connecting layer, the second electrode and the capacitor dielectric layer along the first direction and is arranged corresponding to the second stacking structure; forming a second isolation layer in the isolation trench and on the upper surface of the first covering dielectric layer; The second isolation layer insulates and isolates the capacitors on two opposite sides of the second stacking structure along the second direction, and enables a plurality of the capacitors located on the same side of the second stacking structure to share a second electrode.

18. The method for preparing a semiconductor device structure according to claim 17, after forming a second isolation layer in the isolation layer and on the upper surface of the first covering dielectric layer, further comprising: forming a second covering dielectric layer on the upper surface of the second isolation layer; forming a contact hole, wherein the contact hole penetrates the second covering dielectric layer, the second isolation layer and the first covering dielectric layer along the first direction to expose the electrode connection layer; An external circuit structure is formed in the contact hole, and the external circuit structure is in contact with the electrode connection layer.

19. An electronic device, characterized in that: include: The semiconductor device structure according to any one of claims 1 to 9.

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