Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction; a first word line between the first edge portion and the second edge portion and extending in a second direction intersecting the first direction; a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction; and a storage node contact on the second edge portion, in which the first edge portion includes a first top surface and a second top surface, and the second top surface of the first edge portion is closer to the second edge portion than the first top surface of the first edge portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0094022 filed on July 19, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0004] Semiconductor devices are becoming increasingly important in the electronics industry due to their small size, multifunctionality and / or low cost. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both storage elements and logic elements, etc.

[0005] As the demand for electronic devices with fast speed and / or low power consumption continues to increase, semiconductor devices may require fast operating speed and / or low operating voltage. In order to meet this requirement, it may be necessary to increase the integration density of semiconductor devices.

[0006] The information disclosed in this background technology section has been known or inferred by the inventor before or during the implementation of the embodiments of the present application, or is technical information obtained during the implementation of the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the invention

[0007] One or more example embodiments of the present disclosure provide a method of easily manufacturing a highly integrated semiconductor device and a semiconductor device manufactured thereby.

[0008] One or more example embodiments of the present disclosure provide a semiconductor device having improved electrical characteristics and reliability characteristics and a method of manufacturing the semiconductor device.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0010] According to an aspect of an example embodiment, a semiconductor device may include: a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction; a first word line extending between the first edge portion and the second edge portion and in a second direction intersecting the first direction; a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction; and a storage node contact on the second edge portion, wherein the first edge portion includes a first top surface and a second top surface, the second top surface of the first edge portion is closer to the second edge portion than the first top surface of the first edge portion, and the first top surface of the first edge portion is at a height higher than a height of the second top surface of the first edge portion.

[0011] According to an aspect of an example embodiment, a semiconductor device may include: a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction; a word line between the first edge portion and the second edge portion and extending in a second direction intersecting the first direction; a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction; and a storage node contact on the second edge portion, wherein the first edge portion includes an upper portion and a lower portion, and the upper portion of the first edge portion is recessed in the second direction so that a width of the upper portion of the first edge portion in the second direction is less than a width of the lower portion of the first edge portion in the second direction.

[0012] According to an aspect of an example embodiment, a semiconductor device may include: an active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction; a word line extending between the first edge portion and the second edge portion and in a second direction intersecting the first direction; a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction; and a storage node contact on the second edge portion, wherein the first edge portion includes a first side surface and a second side surface, the second side surface of the first edge portion is closer to the second edge portion than the first side surface of the first edge portion, the first side surface of the first edge portion has a linear profile, and the second side surface of the first edge portion has a stepped profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1A is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0015] Figure 1BThe present invention is a diagram showing one or more embodiments of the present invention. Figure 1A An enlarged plan view of a portion of a semiconductor device;

[0016] FIG. 2A to FIG. 2E According to one or more embodiments of the present disclosure, Figure 1A A cross-sectional view corresponding to line AA′, line BB′, line CC′, line DD′ and line EE′;

[0017] FIG. 3A to FIG. 3F is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0018] Figure 4 According to one or more embodiments of the present disclosure Figure 1A A cross-sectional view corresponding to line CC′;

[0019] Figure 5 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0020] FIG. 6A to FIG. 6D According to one or more embodiments of the present disclosure, Figure 5 A cross-sectional view corresponding to line AA′, line BB′, line CC′ and line DD′;

[0021] Fig. 7A and Figure 7B According to one or more embodiments of the present disclosure, Figure 1A A cross-sectional view corresponding to line BB′ and line DD′;

[0022] Figure 8 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0023] Fig. 9A and Fig. 9B According to one or more embodiments of the present disclosure, Figure 8 A cross-sectional view corresponding to line DD′ and line EE′;

[0024] Fig. 10A and Fig. 10B According to one or more embodiments of the present disclosure Figure 1A A cross-sectional view corresponding to line DD′ and line EE′;

[0025] Fig.11 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0026] FIG. 12A to FIG. 12D According to one or more embodiments of the present disclosure, Fig.11A cross-sectional view corresponding to line AA′, line BB′, line DD′ and line EE′;

[0027] Fig.13 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0028] FIG. 14A to FIG. 14E According to one or more embodiments of the present disclosure, Fig.13 A cross-sectional view corresponding to line AA′, line BB′, line CC′, line DD′ and line EE′;

[0029] Fig.15 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0030] FIG. 16A to FIG. 16D According to one or more embodiments of the present disclosure, Fig.15 A cross-sectional view corresponding to line AA′, line BB′, line CC′ and line DD′;

[0031] Fig.17 According to one or more embodiments of the present disclosure Fig.15 A cross-sectional view corresponding to the line AA′;

[0032] Fig.18 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0033] FIG. 19A to FIG. 19E According to one or more embodiments of the present disclosure, Fig.18 A cross-sectional view corresponding to line AA′, line BB′, line CC′, line DD′ and line EE′;

[0034] Fig. 20 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure;

[0035] Fig.21 According to one or more embodiments of the present disclosure Fig. 20 A cross-sectional view corresponding to the line AA′;

[0036] Figures 22 to 33E is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0037] Figures 34 to 39C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0038] Fig.40is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0039] Figures 41 to 44D is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0040] Fig.45A and Fig.45B is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0041] Fig.46 and Fig.47 is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0042] Figures 48 to 51C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0043] FIG. 52A to FIG. 52E is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0044] Figure 53 to Figure 56C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0045] Fig.57 and Fig.58 is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure; and

[0046] Figures 59A to 59C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same components in the accompanying drawings use the same reference numerals, and repeated descriptions thereof will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms.

[0048] As used herein, expressions such as "at least one of..." follow a list of elements and modify the entire list of elements rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0049] It will be understood that when an element or layer is referred to as being "on," "over," "up," "below," "under," "below," "connected to," or "coupled to" another element or layer, it can be directly on, over, over, under, under, below, directly connected to or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "over," "up," "below," "under," "below," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0050] Figure 1A is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. Figure 1B The present invention is a diagram showing one or more embodiments of the present invention. Figure 1A An enlarged plan view of a portion of a semiconductor device. FIG. 2A to FIG. 2E According to one or more embodiments of the present disclosure, Figure 1A Cross-sectional views corresponding to line AA′, line BB′, line CC′, line DD′ and line EE′.

[0051] refer to Figure 1A as well as FIG. 2A to FIG. 2E , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate (eg, a silicon wafer, a germanium wafer, or a silicon-germanium wafer).

[0052] The device isolation pattern STI may be provided in the substrate 100 to define an active pattern ACT. In an embodiment, a plurality of active patterns ACT may be provided. The active pattern ACT may include a portion of the substrate 100 surrounded by the device isolation pattern STI. Unless otherwise specified, the term "substrate 100" may refer to the remaining portion of the substrate 100 excluding the aforementioned portion of the substrate 100. The device isolation pattern STI may be formed of at least one insulating material (e.g., silicon oxide (SiO 2 ) and silicon nitride (SiN)) are formed or include the at least one insulating material. The device isolation pattern STI may be a single layer made of a single material, or may be a composite layer including two or more materials.

[0053] Each of the active patterns ACT may be a pattern elongated in a first direction D1 parallel to the bottom surface of the substrate 100. The active patterns ACT may be spaced apart from each other in a second direction D2 and a third direction D3 parallel to the bottom surface of the substrate 100 and non-parallel to each other. The first direction D1, the second direction D2, and the third direction D3 may not be parallel to each other. The active pattern ACT may protrude in a fourth direction D4 perpendicular to the bottom surface of the substrate 100. In an embodiment, the active pattern ACT may be formed of or include silicon (e.g., single crystal silicon).

[0054] The active pattern ACT may include a first edge portion E1 and a second edge portion E2 spaced apart from each other in the first direction D1 and a center portion CA therebetween. The first edge portion E1 and the second edge portion E2 may be ends of the active pattern ACT that are opposite to each other in the first direction D1. The center portion CA may be disposed below a word line WL that is disposed to cross the active pattern ACT and will be described below. The word line WL may be vertically located above the center portion CA of the active pattern ACT. The center portion CA of the active pattern ACT may be spaced apart from each other in the second direction D2 and the third direction D3.

[0055] Each of the first and second edge portions E1 and E2 and the central portion CA may include an impurity region doped with impurities (eg, n-type impurities or p-type impurities) The impurity region may function as one of a source region, a drain region, and a channel region of a transistor.

[0056] The active patterns ACT adjacent to each other may be arranged side by side in one of the second direction D2 and the third direction D3 or a direction opposite to the second direction D2 and the third direction D3. The expression "adjacent ones of the active patterns ACT are arranged side by side in a specific direction" may indicate that the first edge portions E1 of the active patterns ACT adjacent to each other are arranged in a specific direction.

[0057] refer to Figure 1B , a first active pattern ACT1, a second active pattern ACT2, a third active pattern ACT3, and a fourth active pattern ACT4 may be provided. The first active pattern ACT1 and the second active pattern ACT2 adjacent to each other may be arranged side by side in the second direction D2. The fourth active pattern ACT4 and the third active pattern ACT3 adjacent to each other may be arranged side by side in the second direction D2. The first active pattern ACT1 and the fourth active pattern ACT4 adjacent to each other may be arranged side by side in the third direction D3. The second active pattern ACT2 and the third active pattern ACT3 adjacent to each other may be arranged side by side in the third direction D3.

[0058] The second edge portion E2 of the fourth active pattern ACT4, the first edge portion E1 of the first active pattern ACT1, the second edge portion E2 of the third active pattern ACT3, and the first edge portion E1 of the second active pattern ACT2 may be sequentially disposed in the second direction D2. The first edge portion E1 of the first active pattern ACT1 may be inserted between the second edge portion E2 of the fourth active pattern ACT4 and the second edge portion E2 of the third active pattern ACT3. The second edge portion E2 of the third active pattern ACT3 may be inserted between the first edge portion E1 of the first active pattern ACT1 and the first edge portion E1 of the second active pattern ACT2.

[0059] According to an embodiment of the present disclosure, since the active patterns ACT are arranged side by side as described above, the arrangement of elements in the semiconductor device can be simplified. Therefore, the patterning process performed to manufacture the semiconductor device can have a reduced difficulty, and thus the semiconductor device can be manufactured more easily. In addition, since the elements can be arranged in a relatively simple manner, the integration density of the semiconductor device can also be improved.

[0060] Return to reference Figure 1A as well as FIG. 2A to FIG. 2E , the first edge portion E1 of the active pattern ACT may have a first top surface E1a and a second top surface E1b, the second top surface E1b being located at a height lower than that of the first top surface E1a. The second top surface E1b of the first edge portion E1 may be closer to the second edge portion E2 than the first top surface E1a. The second edge portion E2 may have a first top surface E2a and a second top surface E2b, the second top surface E2b being located at a height lower than that of the first top surface E2a. The second top surface E2b of the second edge portion E2 may be closer to the first edge portion E1 than the first top surface E2a. The first top surface E1a of the first edge portion E1 may be located at a height lower than that of the first top surface E2a of the second edge portion E2. The second top surface E1b of the first edge portion E1 may be located at substantially the same height as the second top surface E2b of the second edge portion E2.

[0061] The first edge portion E1 of the active pattern ACT may have a first side surface ES1 and a second side surface ES2, the second side surface ES2 being closer to the second edge portion E2 than the first side surface ES1 of the first edge portion E1. The second edge portion E2 of the active pattern ACT may have a first side surface ES1 and a second side surface ES2, the second side surface ES2 being closer to the first edge portion E1 than the first side surface ES1 of the second edge portion E2. The first side surface ES1 of each of the first edge portion E1 and the second edge portion E2 may have a linear profile. In an embodiment, the first side surface ES1 of each of the first edge portion E1 and the second edge portion E2 may extend linearly toward the substrate 100. The second side surface ES2 of each of the first edge portion E1 and the second edge portion E2 may have a stepped profile. The second side surface ES2 of the first edge portion E1 may include a second top surface E1b of the first edge portion E1. The second side surface ES2 of the second edge portion E2 may include a second top surface E2b of the second edge portion E2. Due to the stepped profile, each of the first edge portion E1 and the second edge portion E2 may have a concave portion RP. The concave portions RP of the first edge portion E1 and the second edge portion E2 may be concave in directions opposite to each other.

[0062] Each of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may include an upper portion E1y or E2y and a lower portion E1x or E2x. The upper portion E1y and the lower portion E1x of the first edge portion E1 may be two separate portions connected without an interface therebetween, and the upper portion E2y and the lower portion E2x of the second edge portion E2 may be two separate portions connected without an interface therebetween.

[0063] Compared with the lower portion E1x of the first edge portion E1, the upper portion E1y of the first edge portion E1 may be deeply recessed in the second direction D2. That is, the width of the upper portion E1y of the first edge portion E1 in the second direction D2 may be smaller than the width of the lower portion E1x of the first edge portion E1 in the second direction D2. Compared with the lower portion E2x of the second edge portion E2, the upper portion E2y of the second edge portion E2 may be deeply recessed in the direction opposite to the second direction D2. That is, the width of the upper portion E2y of the second edge portion E2 in the direction opposite to the second direction D2 may be smaller than the width of the lower portion E2x of the second edge portion E2 in the direction opposite to the second direction D2. The top surface of the upper portion E1y of the first edge portion E1 may include the first top surface E1a of the first edge portion E1. The top surface of the lower portion E1x of the first edge portion E1 may include the second top surface E1b of the first edge portion E1. The top surface of the upper portion E2y of the second edge portion E2 may include the first top surface E2a of the second edge portion E2. The top surface of the lower portion E2 x of the second edge portion E2 may include a second top surface E2 b of the second edge portion E2 .

[0064] The concave portion RP of the first edge portion E1 may be defined by the upper portion E1y and the second top surface E1b of the first edge portion E1. The concave portion RP of the second edge portion E2 may be defined by the upper portion E2y and the second top surface E2b of the second edge portion E2.

[0065] The upper portion E1y and the lower portion E1x of the first edge portion E1 may contact each other at the first height LV1. The upper portion E2y and the lower portion E2x of the second edge portion E2 may contact each other at the first height LV1. When measured in the second direction D2, the width W1 of the upper portion E1y of the first edge portion E1 at the first height LV1 may be smaller than the width W2 of the lower portion E1x at the first height LV1. When measured in the second direction D2, the width W3 of the upper portion E2y of the second edge portion E2 at the first height LV1 may be smaller than the width W4 of the lower portion E2x at the first height LV1.

[0066] According to an embodiment of the present disclosure, the upper portion E1y of the first edge portion E1 of the active pattern ACT may be deeply recessed in the second direction D2 compared to the lower portion E1x of the first edge portion E1. That is, the width of the upper portion E1y of the first edge portion E1 in the second direction D2 may be smaller than the width of the lower portion E1x of the first edge portion E1 in the second direction D2. Therefore, the first edge portion E1 may be placed at a relatively far position from the storage node contact BC, which will be described below, and in this case, the interference problem between the first edge portion E1 and the storage node contact BC may be prevented. In addition, compared to the lower portion E2x of the second edge portion E2, the upper portion E2y of the second edge portion E2 of the active pattern ACT may be deeply recessed in the direction opposite to the second direction D2. That is, the width of the upper portion E2y of the second edge portion E2 in the direction opposite to the second direction D2 may be smaller than the width of the lower portion E2x of the second edge portion E2 in the direction opposite to the second direction D2. Therefore, the second edge portion E2 can be placed relatively far from the bit line BL, which will be described below, and in this case, the interference problem between the second edge portion E2 and the bit line BL can be prevented. Therefore, the electrical characteristics and reliability characteristics of the semiconductor device can be improved.

[0067] The active insulation pattern AI may be disposed on the first edge portion E1 and the second edge portion E2 of the active pattern ACT. The active insulation pattern AI may include a first active insulation pattern AI1 on the first edge portion E1 and a second active insulation pattern AI2 on the second edge portion E2. As an example, the active insulation pattern AI may contact the device isolation pattern STI without an interface therebetween, but the present disclosure is not limited to this example.

[0068] The first active insulation pattern AI1 may fill the concave portion RP of the first edge portion E1. The first active insulation pattern AI1 may be disposed on the top surface E1b of the lower portion Elx of the first edge portion E1 and the side surface of the upper portion E1y of the first edge portion E1. The first active insulation pattern AI1 may be interposed between the lower portion E1x of the first edge portion E1 and the bit line BL.

[0069] The second active insulation pattern AI2 may fill the concave portion RP of the second edge portion E2. The second active insulation pattern AI2 may be disposed on the top surface E2b of the lower portion E2x of the second edge portion E2 and the side surface of the upper portion E2y of the second edge portion E2. The second active insulation pattern AI2 may be interposed between the lower portion E2x of the second edge portion E2 and the storage node contact portion BC.

[0070] The active insulating pattern AI may be formed of or include an insulating material. As an example, the active insulating pattern AI may be formed of silicon oxide (SiO2 ) and silicon nitride (SiN), or includes silicon oxide (SiO 2 ) and at least one of silicon nitride (SiN).

[0071] The word line WL may be disposed to cross the active pattern ACT and the device isolation pattern STI. The word line WL may be inserted between the first active insulation pattern AI1 on the first edge portion E1 of the active pattern ACT and the second active insulation pattern AI2 on the second edge portion E2 of the active pattern ACT. In an embodiment, a plurality of word lines WL may be disposed. The word lines WL may extend in the second direction D2 and may be spaced apart from each other in the third direction D3. The word line WL may be disposed on the central portion CA of the active pattern ACT and between the first edge portion E1 and the second edge portion E2. The central portion CA may be a portion of the active pattern ACT located below the word line WL. The first edge portion E1 may be a protruding portion of the active pattern ACT extending from the central portion CA in the third direction D3. The second edge portion E2 may be another protruding portion of the active pattern ACT extending from the central portion CA in the direction opposite to the third direction D3. Each word line WL may extend in the second direction D2 to cross the central portion CA of the active pattern ACT arranged side by side in the second direction D2.

[0072] Each word line WL may include a gate electrode GE, a gate dielectric pattern GI, and a gate capping pattern GC. The gate electrode GE may run through the active pattern ACT and the device isolation pattern STI in the second direction D2. The gate dielectric pattern GI may be inserted between the gate electrode GE and the active pattern ACT, and between the gate electrode GE and the device isolation pattern STI. The gate capping pattern GC may be disposed on the gate electrode GE to cover or at least partially cover the top surface of the gate electrode GE. The gate electrode GE may include a conductive material. As an example, the gate electrode GE may be a single layer made of a single material, or may be a composite layer including two or more materials. The gate dielectric pattern GI may be made of silicon oxide (SiO 2 ) or a high-k dielectric material or includes silicon oxide (SiO 2 ) or at least one of a high-k dielectric material. A high-k dielectric material may be defined as a material having a dielectric constant higher than that of silicon oxide. In an embodiment, the gate capping pattern GC may be formed of or include silicon nitride (SiN).

[0073] The word line WL may have a first top surface W1a and a second top surface W2a. The first top surface W1a of the word line WL may be a portion of the top surface of the word line WL disposed below the bit line BL, and the second top surface W2a may be another portion of the top surface of the word line WL. The second top surface W2a of the word line WL may be disposed below the fence pattern FN, which will be described below. The first top surface W1a and the second top surface W2a of the word line WL may be located at different heights from each other. The first top surface W1a of the word line WL may be located at a lower height than the second top surface W2a. The first top surface W1a of the word line WL may be located at substantially the same height as the first top surface E1a of the first edge portion E1 of the active pattern ACT. The second top surface W2a of the word line WL may be located at substantially the same height as the first top surface E2a of the second edge portion E2.

[0074] refer to Figure 1B , the first word line WL1 and the second word line WL2 may be disposed to be spaced apart from each other in the third direction D3. The first word line WL1 may be disposed on the central portion CA of the first active pattern ACT1 and the central portion CA of the second active pattern ACT2, and may extend in the second direction D2. The second word line WL2 may be disposed on the central portion CA of the fourth active pattern ACT4 and the central portion CA of the third active pattern ACT3, and may extend in the second direction D2. The second edge portion E2 of the fourth active pattern ACT4, the first edge portion E1 of the first active pattern ACT1, the second edge portion E2 of the third active pattern ACT3, and the first edge portion E1 of the second active pattern ACT2 may be sequentially disposed between the first word line WL1 and the second word line WL2 in the second direction D2.

[0075] Return to reference Figure 1A as well as FIG. 2A to FIG. 2E , the lower storage node contact BCx may be disposed on the second edge portion E2 of the active pattern ACT. For example, the lower storage node contact BCx may be inserted between the bit lines BL adjacent to each other along the second direction D2 and between the fence patterns FN adjacent to each other in the third direction D3. The lower storage node contact BCx may contact the second edge portion E2 of the active pattern ACT. The lower storage node contact BCx may be spaced apart from the second top surface E2b of the second edge portion E2 by the second active insulating pattern AI2. In an embodiment, the lower storage node contact BCx may be formed of or include at least one of silicon (e.g., doped polysilicon) and a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0076] In an embodiment, a plurality of lower storage node contacts BCx may be provided. The lower storage node contacts BCx may be spaced apart from each other in the second direction D2 and the third direction D3. The lower storage node contacts BCx adjacent to each other in the second direction D2 may be spaced apart from each other, with the bit line BL interposed therebetween. The lower storage node contacts BCx adjacent to each other in the third direction D3 may be spaced apart from each other, with the fence pattern FN interposed therebetween.

[0077] refer to Figure 1B , the first lower storage node contact BCx1, the second lower storage node contact BCx2, the third lower storage node contact BCx3, and the fourth lower storage node contact BCx4 may be disposed to be spaced apart from each other in the second direction D2 and the third direction D3. The first lower storage node contact BCx1, the second lower storage node contact BCx2, the third lower storage node contact BCx3, and the fourth lower storage node contact BCx4 may be sequentially disposed in a clockwise direction. The first lower storage node contact BCx1, the second lower storage node contact BCx2, the third lower storage node contact BCx3, and the fourth lower storage node contact BCx4 may be disposed on the second edge portion E2 of the first active pattern ACT1, the second edge portion E2 of the second active pattern ACT2, the second edge portion E2 of the third active pattern ACT3, and the second edge portion E2 of the fourth active pattern ACT4, respectively. In a plan view, the third lower storage node contact BCx3 and the fourth lower storage node contact BCx4 may be inserted between the first word line WL1 and the second word line WL2. In a plan view, the second and third lower storage node contacts BCx2 and BCx3 may be interposed between the first and second bit lines BL1 and BL2 , which will be described below.

[0078] Return to reference Figure 1A as well as FIG. 2A to FIG. 2E , the fence pattern FN may be disposed on the word line WL. For example, the fence pattern FN may be inserted between the bit lines BL adjacent to each other in the second direction D2 and between the lower storage node contacts BCx adjacent to each other in the third direction D3. The bottom surface of the fence pattern FN may be located at a height higher than the bottom surface of the bit line BL.

[0079] In an embodiment, a plurality of fence patterns FN may be provided. The fence patterns FN may be spaced apart from each other in the second direction D2 and the third direction D3. The fence patterns FN adjacent to each other in the second direction D2 may be spaced apart from each other, with the bit line BL inserted therebetween. The fence patterns FN adjacent to each other in the third direction D3 may be spaced apart from each other, with the lower storage node contact BCx inserted therebetween. In an embodiment, the fence pattern FN may be made of silicon oxide (SiO 2), silicon nitride (SiN), silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) or includes at least one of them.

[0080] The buffer pattern BP may cover or at least partially cover the top surface of the lower storage node contact BCx and the top surface of the fence pattern FN. The buffer pattern BP may be inserted between the bit lines BL adjacent to each other along the second direction D2. The buffer pattern BP may be formed of or include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buffer pattern BP may be a single layer made of a single material, or may be a composite layer including two or more materials. The buffer pattern BP may be a composite layer including a lower buffer pattern and an upper buffer pattern.

[0081] The bit line trench region BTR may be defined between the lower storage node contacts BCx adjacent to each other in the second direction D2 and between the fence patterns FN. The bit line trench region BTR may extend along the third direction D3 on the first edge portion E1 of the active pattern ACT. The upper portion of the first edge portion E1 of the active pattern ACT may be recessed to a specific depth based on the bit line trench region BTR. The bit line trench region BTR may not overlap with the second edge portion E2.

[0082] In an embodiment, a plurality of bit line trench regions BTR may be provided. The bit line trench regions BTR may be spaced apart from each other in the second direction D2. The bit line trench regions BTR adjacent to each other in the second direction D2 may be spaced apart from each other with the lower storage node contact BCx or the fence pattern FN interposed therebetween.

[0083] refer to Figure 1B , the first bit line trench region BTR1 and the second bit line trench region BTR2 may be disposed to be spaced apart from each other in the second direction D2. The first bit line trench region BTR1 may be disposed on the first edge portion E1 of the first active pattern ACT1 and the first edge portion E1 of the fourth active pattern ACT4, and may extend in the third direction D3. The second bit line trench region BTR2 may be disposed on the first edge portion E1 of the second active pattern ACT2 and the first edge portion E1 of the third active pattern ACT3, and may extend in the third direction D3.

[0084] Return to reference Figure 1A as well as FIG. 2A to FIG. 2E, the bit line BL may be disposed in the bit line trench region BTR and on the first edge portion E1 of the active pattern ACT. The bit line BL may contact the first edge portion E1 of the active pattern ACT. Therefore, the resistance between the bit line BL and the first edge portion E1 of the active pattern ACT may be reduced, and thus, the electrical characteristics of the semiconductor device may be improved. The bottom surface of the bit line BL may be located at a height lower than the first top surface E2a of the second edge portion E2 of the active pattern ACT. The bit line BL may be spaced apart from the second top surface E1b of the first edge portion E1 by the first active insulating pattern AI1. In an embodiment, a plurality of bit lines BL may be provided. The bit lines BL may be spaced apart from each other in the second direction D2, and may extend in the third direction D3.

[0085] The bit line BL may be a composite layer including two or more materials. As an example, the bit line BL may include a lower bit line BLx and an upper bit line BLy. The upper bit line BLy may extend in the third direction D3. The lower bit line BLx may be inserted between the first edge portion E1 and the upper bit line BLy.

[0086] As an example, the lower bit line BLx may include at least one of a first barrier pattern and a first silicide pattern, the first barrier pattern may be used to prevent diffusion of a material in the upper bit line BLy, and the first silicide pattern may be used to improve the contact resistance property between the upper bit line BLy and the first edge portion E1. As an example, the lower bit line BLx may be formed of or include at least one of a metal silicide material (e.g., a silicide material containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co) and a metal nitride material (e.g., a nitride material containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co). The upper bit line BLy may be formed of or include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0087] refer to Figure 1B, the first bit line BL1 and the second bit line BL2 may be arranged to be spaced apart from each other in the second direction D2. The first bit line BL1 may be arranged in the first bit line groove region BTR1. The second bit line BL2 may be arranged in the second bit line groove region BTR2. The first bit line BL1 may be arranged on the first edge portion E1 of the first active pattern ACT1 and the first edge portion E1 of the fourth active pattern ACT4, and may extend in the third direction D3. The second bit line BL2 may be arranged on the first edge portion E1 of the second active pattern ACT2 and the first edge portion E1 of the third active pattern ACT3, and may extend in the third direction D3. In a plan view, the second edge portion E2 of the second active pattern ACT2 and the second edge portion E2 of the third active pattern ACT3 may be inserted between the first bit line BL1 and the second bit line BL2.

[0088] The bit line capping pattern BCP may be disposed in the bit line trench region BTR and on the top surface of the bit line BL. The bit line capping pattern BCP may extend in the third direction D3 together with the bit line BL. In an embodiment, a plurality of bit line capping patterns BCP may be provided. The bit line capping patterns BCP may be spaced apart from each other in the second direction D2. The bit line capping pattern BCP may consist of a single layer or a plurality of layers. As an example, the bit line capping pattern BCP may include a first capping pattern, a second capping pattern, and a third capping pattern stacked sequentially. Each of the first to third capping patterns may be formed of or include silicon nitride (SiN). In an embodiment, the bit line capping pattern BCP may include four or more capping patterns stacked.

[0089] The bit line spacer BSP may be disposed in the bit line groove region BTR and on the side surface of the bit line BL and the side surface of the bit line capping pattern BCP. The bit line spacer BSP may cover or at least partially cover the side surface of the bit line BL, the side surface of the bit line capping pattern BCP and the inner side surface of the bit line groove region BTR. The bit line spacer BSP may also cover or at least partially cover the side surface of the lower storage node contact BCx. The bit line spacer BSP may extend along the third direction D3 on the side surface of the bit line BL. The top surface of the bit line spacer BSP may be located at a height substantially the same as the top surface of the buffer pattern BP. In an embodiment, a plurality of bit line spacers BSP may be provided. The bit line spacers BSP may be spaced apart from each other in the second direction D2. In each bit line groove region BTR, two bit line spacers BSP adjacent to each other in the second direction D2 may be spaced apart from each other, with one of the bit lines BL inserted therebetween. The bit line spacer BSP may be made of silicon oxide (SiO 2The bit line spacer BSP may be formed of at least one of silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) or include at least one of the above. The bit line spacer BSP may be a single layer made of a single material, or may be a composite layer including two or more materials.

[0090] The mold pattern MP may be disposed on the buffer pattern BP, the bit line capping pattern BCP, and the bit line spacer BSP. The mold pattern MP may be disposed to surround the landing pad LP, which will be described below. The mold pattern MP may be inserted between landing pads LP adjacent to each other. In a plan view, the mold pattern MP may be disposed to have a grid shape with contact holes CH to be described below. The mold pattern MP may be made of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN) or includes at least one of them.

[0091] The contact hole CH may be disposed on the second edge portion E2 of the active pattern ACT. The contact hole CH may be disposed to penetrate the mold pattern MP and the buffer pattern BP. The upper portion of the lower storage node contact BCx, the upper portion of the bit line capping pattern BCP, and the upper portion of the bit line spacer BSP may be recessed to a specific depth based on the contact hole CH. The contact hole CH may also be offset from the lower storage node contact BCx in the second direction D2 or in the opposite direction thereof. A portion of the contact hole CH may be vertically located above the bit line BL. A portion of the contact hole CH may be vertically located above the lower storage node contact BCx. In an embodiment, a plurality of contact holes CH may be provided. The contact holes CH may be linearly arranged along the second direction D2, and may be arranged in a zigzag shape along the third direction D3.

[0092] The upper storage node contact BCy may be disposed in the contact hole CH. The upper storage node contact BCy may be disposed on the lower storage node contact BCx and may contact the lower storage node contact BCx. The upper storage node contact BCy may be electrically connected to the corresponding second edge portion E2 in the second edge portion E2 of the active pattern ACT through the corresponding lower storage node contact BCx in the lower storage node contact BCx. The upper storage node contact BCy may also be offset from the lower storage node contact BCx in the second direction D2 or in the opposite direction thereof. A portion of the upper storage node contact BCy may be vertically located above the bit line BL. The upper storage node contact BCy may contact the bit line capping pattern BCP and the bit line spacer BSP. The upper storage node contact BCy and the lower storage node contact BCx may form a storage node contact BC. The lowermost surface of the upper storage node contact BCy may be located at a height lower than the top surface of the lower storage node contact BCx.

[0093] In an embodiment, a plurality of upper storage node contacts BCy may be provided. The upper storage node contacts BCy may be provided in the contact holes CH, respectively. The upper storage node contacts BCy may be spaced apart from each other in the second direction D2 and the third direction D3. Similar to the contact holes CH, the upper storage node contacts BCy may be arranged linearly along the second direction D2, and may be arranged in a zigzag shape along the third direction D3.

[0094] The landing pad LP may be disposed on the upper storage node contact BCy in the contact hole CH. The landing pad LP may be vertically located above the upper storage node contact BCy. The landing pad LP may be electrically connected to the second edge portion E2 of the active pattern ACT through the upper storage node contact BCy and the lower storage node contact BCx, respectively. In an embodiment, a plurality of landing pads LP may be provided. The landing pads LP may be spaced apart from each other in the second direction D2 and the third direction D3. The landing pad LP may be formed of or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). In an embodiment, a second silicide pattern SC may also be disposed between the landing pad LP and the upper storage node contact BCy. The second silicide pattern SC may be formed of or include at least one metal silicide material (e.g., containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). In an embodiment, the second barrier pattern may be inserted between the landing pad LP and other elements to prevent the material in the landing pad LP from diffusing into the adjacent elements. As an example, the second barrier pattern may be formed of or include at least one of a metal nitride material (e.g., a nitride material containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co).

[0095] The data storage pattern DSP may be disposed on the landing pad LP. In an embodiment, a plurality of data storage patterns DSP may be provided. The data storage patterns DSP may be spaced apart from each other in the second direction D2 and the third direction D3. The data storage patterns DSP may be electrically connected to the second edge portion E2 of the active pattern ACT through the landing pad LP and the storage node contact BC, respectively.

[0096] In an embodiment, the data storage pattern DSP may be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device may be a dynamic random access memory (DRAM) device. In an embodiment, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor device may be a magnetic random access memory (MRAM) device. In an embodiment, the data storage pattern DSP may be formed of or include a phase change material or a variable resistance material. In this case, the semiconductor device may be a phase change random access memory (PRAM) device or a resistance random access memory (ReRAM) device. However, the present disclosure is not limited to these examples, and the data storage pattern DSP may include various structures and / or materials configured to store data.

[0097] In the following, reference will be made to Figures 3A to 21 Other embodiments of the present disclosure are described in more detail. In the following description, for the sake of brevity of description, previously described elements may be identified by the same reference numerals without repeated description.

[0098] FIG. 3A to FIG. 3F is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure.

[0099] refer to FIG. 3A to FIG. 3F , the active pattern ACT may have various profiles in a plan view. The active patterns ACT may be arranged in such a manner that they are spaced apart from each other in the second direction D2 and the third direction D3 and have a profile elongated in the first direction D1. The first edge portion E1 and the second edge portion E2 of the active pattern ACT may be symmetrical or asymmetrical about the central portion CA.

[0100] refer to Figure 3A , the profiles of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be symmetrical about the center portion CA. In a plan view, the first edge portion E1 of the active pattern ACT may be a protrusion extending from the word line WL in the third direction D3, and the second edge portion E2 may be a protrusion extending from the word line WL in the opposite direction of the third direction D3. Each of the first edge portion E1 and the second edge portion E2 may have a shape elongated in a direction between the first direction D1 and the third direction D3. Due to the elongated shape of the first edge portion E1, the contact area between the first edge portion E1 and the bit line BL may be increased, and thus the contact resistance therebetween may be improved. Similarly, due to the elongated shape of the second edge portion E2, the contact area between the second edge portion E2 and the storage node contact BC may be increased, and thus the contact resistance therebetween may be improved.

[0101] refer to Figure 3B , the profiles of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be symmetrical about the central portion CA. The active pattern ACT may have a shape elongated in the first direction D1. The side surface of the active pattern ACT may have a substantially linear profile. Therefore, the technical difficulty in the process of patterning the active pattern ACT may be reduced, and thus the semiconductor device may be easily manufactured.

[0102] refer to Figure 3C , the profiles of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be asymmetrical with respect to the central portion CA. Figure 3A Compared with the second edge portion E2, Figure 3C The second edge portion E2 may further include a protruding portion extending in a direction opposite to the second direction D2. In this case, the contact area between the second edge portion E2 and the storage node contact BC may be increased, and thus the contact resistance property therebetween may be improved. Figure 3A Compared with the first edge portion E1, Figure 3C The first edge portion E1 may further include a protruding portion extending in the second direction D2.

[0103] refer to Figure 3D , the profiles of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be asymmetrical with respect to the central portion CA. Figure 3B Compared with the second edge portion E2, Figure 3D The second edge portion E2 may further include a protruding portion extending in a direction opposite to the second direction D2. In this case, the contact area between the second edge portion E2 and the storage node contact BC may be increased, and thus the contact resistance property therebetween may be improved. Figure 3B Compared with the first edge portion E1, Figure 3D The first edge portion E1 may further include a protruding portion extending in the second direction D2.

[0104] refer to Figure 3E , the profiles of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be asymmetrical with respect to the central portion CA. Figure 3B Compared with the first edge portion E1, Figure 3E The first edge portion E1 may further include a protruding portion extending in the third direction D3. In this case, the contact area between the first edge portion E1 and the bit line BL may be increased, and thus the contact resistance property therebetween may be improved. Figure 3B Compared with the second edge portion E2, Figure 3E The second edge portion E2 may further include a protruding portion extending in an opposite direction to the third direction D3.

[0105] refer to Figure 3F , the profiles of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be asymmetrical with respect to the central portion CA. Figure 3B Compared with the first edge portion E1, Figure 3F The first edge portion E1 may further include a protruding portion extending in the third direction D3. In this case, the contact area between the first edge portion E1 and the bit line BL may be increased, and thus the contact resistance property therebetween may be improved. Figure 3B Compared with the second edge portion E2, Figure 3F The second edge portion E2 may further include a protruding portion extending in the opposite direction of the third direction D3. In this case, the contact area between the second edge portion E2 and the storage node contact BC may be increased, and thus the contact resistance property therebetween may be improved. The protruding length of the second edge portion E2 may be greater than the protruding length of the first edge portion E1.

[0106] Figure 4 According to one or more embodiments of the present disclosure Figure 1A Cross-sectional view corresponding to line CC′.

[0107] refer to Figure 4 , the word line WL may extend into the bit line BL. In an embodiment, the gate capping pattern GC may also extend into the bit line BL. The gate capping pattern GC may be inserted between the lower bit lines BLx. The first top surface W1a of the word line WL (e.g., the top surface of the gate capping pattern GC) may be located at a height higher than the top surface of the lower bit line BLx. Therefore, the distance between the upper bit line BLy and the gate electrode GE may be increased, and thus the electrical interference problem between the upper bit line BLy and the gate electrode GE may be reduced. Therefore, the electrical characteristics of the semiconductor device may be improved.

[0108] Figure 5 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 6A to FIG. 6D According to one or more embodiments of the present disclosure, Figure 5 Cross-sectional views corresponding to line AA′, line BB′, line CC′ and line DD′.

[0109] refer to Figures 5 to 6D, the first top surfaces E1a and E2a of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be located at a height higher than the uppermost surface STIa of the device isolation pattern STI. The second top surfaces E1b and E2b of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be located at substantially the same height as the uppermost surface STIa of the device isolation pattern STI, but the present disclosure is not limited to this example. For example, the second top surfaces E1b and E2b of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be located at a height higher or lower than the uppermost surface STIa of the device isolation pattern STI.

[0110] The active pad XO may be arranged to cover and surround the side surfaces of the first edge portion E1 and the second edge portion E2 of the active pattern ACT. The active pad XO may include a first active pad XO1 and a second active pad XO2, the first active pad XO1 being arranged to cover or at least partially cover the side surface of the first edge portion E1, and the second active pad XO2 being arranged to cover or at least partially cover the side surface of the second edge portion E2. The active pad XO may include an impurity region doped with impurities (e.g., n-type impurities or p-type impurities). The impurity region of the active pad XO together with the impurity region of the active pattern ACT may be used as one of the source region, the drain region, and the channel region of the transistor. Therefore, in a plan view, the source region or the drain region of the transistor may have an increased area. The active pad XO may be formed of the same material as the active pattern ACT or include the same material as the active pattern ACT. As an example, the active pad XO may be formed of or include at least one of silicon (eg, single crystal silicon), germanium, or silicon-germanium.

[0111] The pad insulating pattern XI may be disposed on the uppermost surface STIa of the device isolation pattern STI. The pad insulating pattern XI may be inserted between the first active pad XO1 and the second active pad XO2. The pad insulating pattern XI may include an insulating material. As an example, the pad insulating pattern XI may be made of silicon oxide (SiO 2 ) and silicon nitride (SiN) or include at least one of them.

[0112] The bit line BL may contact the first active pad XO1. The bit line BL may be electrically connected to the first active pad XO1 and the first edge portion E1 of the active pattern ACT. Since the first active pad XO1 is provided, the contact area between the bit line BL and the source region or the drain region may be increased, and thus the contact resistance therebetween may be improved.

[0113] The lower storage node contact BCx may contact the second active pad XO2. The storage node contact BC may be electrically connected to the second active pad XO2 and the second edge portion E2 of the active pattern ACT. Since the second active pad XO2 is provided, the contact area between the storage node contact BC and the source region or the drain region may be increased, and thus the contact resistance therebetween may be improved.

[0114] In the embodiments, reference Figures 5 to 6D The active pattern ACT of the described semiconductor device may include reference FIG. 3A to FIG. 3F One of the active patterns ACT of the semiconductor device is described.

[0115] Fig. 7A and Figure 7B According to one or more embodiments of the present disclosure, Figure 1A A cross-sectional view corresponding to line BB′ and line DD′.

[0116] refer to Fig. 7A and Figure 7B , the bottom surface BCxb of the lower storage node contact BCx may be located at a height lower than the first top surface E2a of the second edge portion E2 of the active pattern ACT. The lower storage node contact BCx may cover or at least partially cover the upper portion E2y of the second edge portion E2. As an example, the lower storage node contact BCx may contact the side surface of the upper portion E2y of the second edge portion E2. FIG. 2A to FIG. 2E Compared with the semiconductor device of FIG. 1 , the contact area between the lower storage node contact BCx and the second edge portion E2 of the active pattern ACT can be increased. Therefore, the lower storage node contact BCx can be easily electrically connected to the second edge portion E2 of the active pattern ACT, and the electrical characteristics of the semiconductor device can be improved.

[0117] Figure 8 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. Fig. 9A and Fig. 9B According to one or more embodiments of the present disclosure, Figure 8 A cross-sectional view corresponding to line DD′ and line EE′.

[0118] refer to Figures 8 to 9B , the fence pattern FN may not be provided. The word line WL may extend in the third direction D3 and the fourth direction D4 between the lower storage node contacts BCx adjacent to each other in the third direction D3. The second top surface W2a of the word line WL may be located at substantially the same height as the top surface of the lower storage node contact BCx. The word line WL may contact the buffer pattern BP. The word lines WL may be spaced apart from each other in the third direction D3, with the lower storage node contact BCx interposed therebetween.

[0119] The bit line trench region BTR may be disposed in the word line WL (eg, in the gate capping pattern GC). The bit line trench region BTR may be disposed to cross the word line WL in the third direction D3. In each word line WL, the bit line trench regions BTR may be spaced apart from each other in the second direction D2.

[0120] Fig. 10A and Fig. 10B According to one or more embodiments of the present disclosure Figure 1A A cross-sectional view corresponding to line DD′ and line EE′.

[0121] refer to Fig. 10A and Fig. 10B , the fence pattern FN may be disposed to penetrate the buffer pattern BP. The top surface of the fence pattern FN may be located at substantially the same height as the top surface of the buffer pattern BP, the top surface of the bit line capping pattern BCP, and the top surface of the bit line spacer BSP. The top surface of the fence pattern FN may contact the bottom surface of the mold pattern MP.

[0122] Fig.11 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 12A to FIG. 12D They are respectively Fig.11 Cross-sectional views corresponding to line AA′, line BB′, line DD′ and line EE′.

[0123] refer to Figures 11 to 12D , the fence pattern FN and the lower storage node contact BCx may not be provided.

[0124] The second edge portion E2 of the active pattern ACT may contact the upper storage node contact BCy and the buffer pattern BP. The first top surface E2a of the second edge portion E2 of the active pattern ACT may be located at a height higher than the top surface of the bit line BL. The first top surface E2a of the second edge portion E2 of the active pattern ACT may be located at a height higher than the lowermost surface of the upper storage node contact BCy.

[0125] The second active insulating pattern AI2 may contact the upper storage node contact BCy. The word line WL may contact the buffer pattern BP. The second top surface W2a of the word line WL may be located at a height higher than the top surface of the bit line BL and the lowermost surface of the upper storage node contact BCy.

[0126] Fig.13 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 14A to FIG. 14E According to one or more embodiments of the present disclosure, Fig.13 Cross-sectional views corresponding to line AA′, line BB′, line CC′, line DD′ and line EE′.

[0127] refer to Figures 13 to 14E , the fence pattern FN and the lower storage node contact BCx may not be provided. The second edge portion E2 of the active pattern ACT, the second active insulation pattern AI2, and the word line WL may be provided to have the same Figures 11 to 12D The features in the embodiments are basically the same or similar features.

[0128] In a plan view, the contact holes CH may be inserted between the bit lines BL adjacent to each other in the second direction D2. The contact holes CH may be arranged two-dimensionally in the second direction D2 and the third direction D3. For example, the contact holes CH in a row may be arranged side by side in the second direction D2, and the contact holes CH in a column may be arranged side by side in the third direction D3. Figures 11 to 12D Compared with the semiconductor device of the present invention, the contact hole CH may vertically overlap the second edge portion E2 of the active pattern ACT with an increased area. Figures 11 to 12D Compared with the semiconductor device described above, even when there is a misalignment problem in the contact hole CH, the second edge portion E2 of the active pattern ACT can be easily connected to the upper storage node contact BCy.

[0129] An upper storage node contact BCy and a second silicide pattern SC may be disposed in a lower portion of the contact hole CH.

[0130] The landing pad LP may include a lower landing pad LPx disposed in an upper portion of the contact hole CH and an upper landing pad LPy disposed on the lower landing pad LPx. The lower landing pad LPx may be disposed to have a Figures 1A to 2E The features of the landing pad LP described above are the same or similar features. The upper landing pad LPy may be offset from the lower landing pad LPx in the second direction D2 or the opposite direction thereof. A portion of the upper landing pad LPy may be vertically located above the bit line BL, and in some examples, vertically overlaps the bit line BL. In an embodiment, a plurality of upper landing pads LPy may be provided. The upper landing pads LPy may be linearly arranged along the second direction D2, and may be arranged in a zigzag shape along the third direction D3. The lower landing pad LPx and the upper landing pad LPy may be formed of or include materials that are the same or different from each other. However, the present disclosure is not limited to this example, and the structure and material of the landing pad LP may be modified in various ways within the range that is generally changeable by a person skilled in the art.

[0131] The filling pattern FIL may be arranged to surround the upper landing pad LPy. The filling pattern FIL may be inserted between the upper landing pads LPy adjacent to each other. In a plan view, the filling pattern FIL may have a grid shape with holes, and the upper landing pads LPy may be arranged to fill the holes. The filling pattern FIL may be arranged to penetrate the upper landing pad LPy. In an embodiment, the filling pattern FIL may be made of silicon nitride (SiN), silicon oxide (SiO 2 ) and silicon oxynitride (SiON) or include at least one of them. In embodiments, the fill pattern FIL may include an empty space having an air layer (eg, an air gap).

[0132] Fig.15 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 16A to FIG. 16D According to one or more embodiments of the present disclosure, Fig.15 Cross-sectional views corresponding to line AA′, line BB′, line CC′ and line DD′. Fig.17 According to one or more embodiments of the present disclosure Fig.15 A cross-sectional view corresponding to line AA′. Fig.18 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 19A to FIG. 19E According to one or more embodiments of the present disclosure, Fig.18 Cross-sectional views corresponding to line AA′, line BB′, line CC′, line DD′ and line EE′.

[0133] refer to Figures 15 to 19E , the lower landing pad LPx may be disposed on the lower storage node contact BCx. The lower landing pad LPx may contact the top surface of the lower storage node contact BCx. The lower landing pad LPx may be inserted between the bit line capping patterns BCP adjacent to each other along the second direction D2. The lower landing pad LPx may be inserted between the fence patterns FN adjacent to each other along the third direction D3.

[0134] A plurality of lower landing pads LPx may be provided. The lower landing pads LPx may be spaced apart from each other in the second direction D2 and the third direction D3. Lower landing pads LPx adjacent to each other in the second direction may be spaced apart from each other with the bit line capping pattern BCP interposed therebetween. Lower landing pads LPx adjacent to each other in the third direction D3 may be spaced apart from each other with the fence pattern FN interposed therebetween.

[0135] refer to FIG. 16A to FIG. 16D , a top surface of the lower landing pad LPx may be located at substantially the same height as a top surface of the bit line capping pattern BCP. Fig.17 and FIG. 19A to FIG. 19E, a top surface of the lower landing pad LPx may be located at a lower height than a top surface of the bit line capping pattern BCP.

[0136] The upper storage node contact BCy and the second silicide pattern SC may not be provided.

[0137] refer to Figures 15 to 16D , the mold pattern MP may not be provided. The upper landing pad LPy may be provided on the lower landing pad LPx. The upper landing pad LPy may contact the bit line capping pattern BCP, the bit line spacer BSP, and the lower landing pad LPx. The upper landing pad LPy and the filling pattern FIL may be provided to have the same Figures 13 to 14E The features in the embodiments are basically the same or similar features.

[0138] refer to Fig.17 , a lower bonding pad LPx may be inserted between the buffer pattern BP and the lower storage node contact BCx. An upper bonding pad LPy may be disposed in the contact hole CH. The upper bonding pad LPy may be disposed to fill the contact hole CH. The upper bonding pad LPy may contact the bit line capping pattern BCP and the bit line spacer BSP. The upper bonding pad LPy may contact the lower bonding pad LPx at a height lower than the bottom surface of the mold pattern MP. The top surface of the upper bonding pad LPy may be located at substantially the same height as the top surface of the mold pattern MP. The lowermost surface of the upper bonding pad LPy may be located at a height lower than the top surface of the lower bonding pad LPx.

[0139] refer to Figures 18 to 19E , the mold pattern MP may not be provided. The interlayer insulating layer ILD may be provided on the substrate 100. For example, the interlayer insulating layer ILD may be provided on the bit line capping pattern BCP and the buffer pattern BP. The interlayer insulating layer ILD may be formed of or include at least one of silicon nitride, silicon oxide, or silicon oxynitride. In an embodiment, the interlayer insulating layer ILD may include an empty region. The contact hole CH may be provided to penetrate the interlayer insulating layer ILD, and in a plan view, the interlayer insulating layer ILD may have a grid shape with the contact hole CH.

[0140] The bottom electrode BE may be disposed on the lower landing pad LPx. The bottom electrode BE may include a lower portion BEx lower than a contact height CLV and an upper portion BEy higher than the contact height CLV. The contact height CLV may be defined as the vertical height of the top surface of the interlayer insulating layer ILD. The lower portion BEx and the upper portion BEy of the bottom electrode BE may contact each other at the contact height CLV without an interface therebetween, but the present disclosure is not limited to this example.

[0141] The lower portion BEx of the bottom electrode BE may be disposed in the contact hole CH. The lower portion BEx of the bottom electrode BE may fill the inner space of the contact hole CH. The lower portion BEx of the bottom electrode BE may contact the bit line capping pattern BCP, the bit line spacer BSP, and the lower landing pad LPx. The lowermost surface of the lower portion BEx of the bottom electrode BE may be located at a height lower than the top surface of the lower landing pad LPx.

[0142] The upper portion BEy of the bottom electrode BE may be disposed on the lower portion BEx of the bottom electrode BE. The upper portion BEy of the bottom electrode BE may have a columnar shape. The upper portion BEy of the bottom electrode BE may have a hollow cylindrical shape with one closed end. Alternatively, the upper portion BEy of the bottom electrode BE may include a columnar lower portion and a hollow cylindrical upper portion.

[0143] In an embodiment, a plurality of bottom electrodes BE may be provided. The bottom electrodes BE may be spaced apart from each other in the second direction D2 and the third direction D3. In an embodiment, in a plan view, the bottom electrodes BE may be arranged in a honeycomb shape. Specifically, each of the bottom electrodes BE may be placed at the center of a hexagon defined by the other six bottom electrodes BE. However, the present disclosure is not limited to this example.

[0144] The top electrode TE may be disposed on the bottom electrode BE. For example, the top electrode TE may cover or at least partially cover the top surface of the upper portion BEy of the bottom electrode BE, and may surround and cover the side surface of the upper portion BEy of the bottom electrode BE. The top electrode TE may be disposed to fill the space between the upper portions BEy of the bottom electrode BE.

[0145] Each of the bottom electrode BE and the top electrode TE may include a conductive material. For example, each of the bottom electrode BE and the top electrode TE may be formed of or include at least one of doped silicon (Si), doped silicon germanium (SiGe), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), a metal nitride material (e.g., a nitride material containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, or Ag, titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN)), a conductive oxide material (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 ), BSRO((Ba, Sr)RuO 3 )、CRO(CaRuO 3) and LSCo) and metal silicide materials. Each of the bottom electrode BE and the top electrode TE may be a single layer made of a single material, or may be a composite layer including two or more materials.

[0146] The dielectric layer DL may be interposed between the top electrode TE and each upper portion BEy of the bottom electrode BE and between the top electrode TE and the interlayer insulating layer ILD. The dielectric layer DL may be disposed to conformally cover the upper portion BEy of the bottom electrode BE. The dielectric layer DL may be made of a metal oxide (e.g., HfO 2 、ZrO 2 、Al 2 O 3 ,La 2 O 3 、 2 O 3 and TiO 2 ) and perovskite dielectric materials (e.g., STO (SrTiO 3 )、BST((Ba, Sr)TiO 3 ), BaTiO3, PZT and PLZT) or includes at least one of them.

[0147] Fig. 20 is a plan view showing a semiconductor device according to one or more embodiments of the present disclosure. Fig.21 According to one or more embodiments of the present disclosure Fig. 20 A cross-sectional view corresponding to line AA′.

[0148] refer to Fig. 20 and Fig.21 , the contact hole CH can be set to have Figures 13 to 14E In a plan view, the upper storage node contact portion BCy, the second silicide pattern SC, and the lower landing pad LPx may be inserted between the bit lines BL adjacent to each other along the second direction D2. Figures 13 to 14E Unlike the embodiments of the present invention, the upper landing pad LPy and the filling pattern FIL may not be provided.

[0149] The data storage pattern DSP may be disposed on the lower landing pad LPx and may be aligned with the lower landing pad LPx. In an embodiment, the data storage pattern DSP may contact the lower landing pad LPx. Therefore, the data storage pattern DSP may be arranged two-dimensionally along the second direction D2 and the third direction D3. As an example, the data storage patterns DSP in a row may be arranged side by side along the second direction D2, and the data storage patterns DSP in a column may be arranged side by side along the third direction D3.

[0150] In the following, reference will be made to Figures 22 to 59CThe method for manufacturing a semiconductor device according to an embodiment of the present disclosure is described in more detail. In the following description, for the sake of simplicity, previously described elements may be identified by the same reference numerals without being repeated. Therefore, repeated descriptions of aspects similar to the above aspects may be omitted.

[0151] Figures 22 to 33E is a diagram showing a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. In detail, Fig. 22 , Fig.24 , Fig.26 , Fig.28 , Fig.30 and Fig.32 is a plan view illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Fig.23 , Fig.25A , Fig.27A , Fig.29A , Fig.31A and Fig.33A According to one or more embodiments of the present disclosure, Fig. 22 , Fig.24 , Fig.26 , Fig.28 , Fig.30 and Fig.32 A cross-sectional view corresponding to line AA′. Fig.25B , Fig.27B , Fig.29B , Fig.31B and Fig.33B According to one or more embodiments of the present disclosure, Fig.24 , Fig.26 , Fig.28 , Fig.30 and Fig.32 The cross-sectional view corresponding to the line BB′. Fig.25C , Fig.27C , Fig.29C , Fig. 31C and Fig.33C According to one or more embodiments of the present disclosure, Fig.24 , Fig.26 , Fig.28 , Fig.30 and Fig.32 Cross-sectional view corresponding to line CC′. Fig.25D , Fig.27D , Fig.29D , Fig.31D and Fig.33D According to one or more embodiments of the present disclosure, Fig.24 , Fig.26 , Fig.28 , Fig.30 and Fig.32 The cross-sectional view corresponding to the line DD′. Fig.25E , Fig.27E , Fig.29E , Fig.31E and Fig.33E According to one or more embodiments of the present disclosure, Fig.24 , Fig.26 , Fig.28 , Fig.30 and Fig.32 The cross-sectional view corresponding to the line EE′.

[0152] refer to Fig. 22 and Fig.23 , a substrate 100 may be prepared. A sacrificial line SL may be formed on the substrate 100. In an embodiment, the formation of the sacrificial line SL may include: forming an active mold layer on the substrate 100, partially removing the active mold layer to form an active mold line AML, and forming the sacrificial line SL in an empty area formed by partially removing the active mold layer. During the removal process of the active mold layer, the upper portion of the substrate 100 may be recessed to a certain depth. The bottom surface of the sacrificial line SL may be located at a height lower than the uppermost surface 100a of the substrate 100. The active mold line AML may be formed of or include silicon nitride (SiN). The sacrificial line SL may be formed of or include at least one carbon-containing material (e.g., a spin-on hard mask (SOH) and an amorphous carbon layer (ACL)).

[0153] The active mold lines AML and the sacrificial lines SL may extend in the third direction D3 on the substrate 100. The active mold lines AML and the sacrificial lines SL may be alternately disposed in the second direction D2.

[0154] The sacrificial mask pattern SMP may be formed on the top surface of the sacrificial line SL to extend in the third direction D3. The sacrificial mask pattern SMP may be formed on the top surface of some but not all of the sacrificial lines SL. The sacrificial lines SL under the sacrificial mask pattern SMP will be referred to as first sacrificial lines SL1, and the other sacrificial lines SL will be referred to as second sacrificial lines SL2. The first sacrificial lines SL1 and the second sacrificial lines SL2 may be alternately disposed along the second direction D2.

[0155] refer to Figures 24 to 25E, an active insulation line AIL may be formed on the substrate 100. In an embodiment, the formation of the active insulation line AIL may include: sequentially removing the second sacrificial line SL2 and the sacrificial mask pattern SMP, and forming the active insulation line AIL to fill the empty area formed by removing the second sacrificial line SL2. The sacrificial mask pattern SMP may prevent the first sacrificial line SL1 from being removed during the removal process of the second sacrificial line SL2. The active insulation line AIL may extend along the third direction D3 on the substrate 100. The active insulation line AIL may be inserted between the active molding lines AML adjacent to each other along the second direction D2.

[0156] The active mask pattern AMP may be formed on the substrate 100. In an embodiment, the active mask pattern AMP may be formed of or include polysilicon. In an embodiment, the formation of the active mask pattern AMP may include: forming an active mask layer on the substrate 100; performing a first patterning process on the active mask layer to form an active mask line; and performing a second patterning process on the active mask line to form the active mask pattern AMP.

[0157] During the first patterning process, the active mask layer may be divided into a plurality of active mask lines elongated in the first direction D1. Each of the side surfaces of the active mask lines may have a wavy profile. In an embodiment, each of the side surfaces of the active mask lines may have a linear profile. The active mask lines may be spaced apart from each other in the third direction D3. The first patterning process may include performing an exposure process once. Alternatively, the first patterning process may include performing two or more exposure processes; that is, the first patterning process may be performed using a multiple patterning technique.

[0158] During the second patterning process, each of the active mask lines may be divided into a plurality of active mask patterns AMP spaced apart from each other in the first direction D1. As a result of the first and second patterning processes, the active mask patterns AMP may be formed to have a shape similar to the reference pattern in a plan view. FIG. 3A to FIG. 3F The profiles of the active patterns ACT described are the same or similar profiles.

[0159] The profile of the active pattern ACT may be variously changed according to the profile and arrangement of the active mask pattern AMP to be described below. For example, the final profile of the active pattern ACT may be different from the profile of the active mask pattern AMP according to the profile and arrangement of the active mask pattern AMP. FIG. 3A to FIG. 3F The outlines shown are identical.

[0160] refer to Figures 26 to 27E, a removal process using the active mask pattern AMP as an etching mask may be performed on a portion of the active mold line AML, a portion of the first sacrificial line SL1, and a portion of the active insulation line AIL. In this case, the remaining portion of the active mold line AML may form the active mold pattern AMLP spaced apart from each other in the first direction D1 and the third direction D3.

[0161] The active insulation line AIL may include an upper active insulation line AILy and a lower active insulation line AILx. The upper active insulation line AILy may be an upper portion of the active insulation line AIL that is patterned during a removal process performed on the active insulation line AIL, and the lower active insulation line AILx may be a lower portion of the active insulation line AIL that is not patterned. The upper active insulation line AILy may be inserted between active mold patterns AMLP that are adjacent to each other in the first direction D1. In a plan view, the active mold patterns AMLP that are adjacent to each other in the first direction D1 and the upper active mold pattern AMLP disposed between the active mold patterns AMLP may have a reference pattern. FIG. 3A to FIG. 3F The profiles of the described active patterns ACT are substantially the same or similar profiles.

[0162] Thereafter, the active mask pattern AMP and the first sacrificial line SL1 may be sequentially removed from the substrate 100 .

[0163] refer to Figures 28 to 29E , a removal process may be performed on the active mold pattern AMLP, the active insulation line AIL, and the substrate 100, so that the active pattern ACT and the active insulation pattern AI may be formed. In an embodiment, the removal process may include an etching process using the active mold pattern AMLP and the upper active insulation line AILy as an etching mask. As a result of the removal process, the lower active insulation line AILx may be divided into active insulation patterns AI spaced apart from each other in the third direction D3. The upper portion of the central portion CA of the active pattern ACT may be recessed by the active insulation pattern AI.

[0164] The first line trench region LTR1 and the second line trench region LTR2 may be formed between the active patterns ACT by a removal process. The first line trench region LTR1 may extend along the first direction D1 between the active patterns ACT. The second line trench region LTR2 may extend along the third direction D3 between the active patterns ACT. A device isolation pattern STI may be formed to fill the first line trench region LTR1 and the second line trench region LTR2.

[0165] refer to Figures 30 to 31E, the word line WL may be formed to cross the active pattern ACT and the device isolation pattern STI. The word line WL may be formed to penetrate the active insulation pattern AI. Therefore, each of the active insulation patterns AI may be divided into first and second active insulation patterns AI1 and AI2 spaced apart from each other in the first direction D1.

[0166] The formation of the word line WL may include: forming a mask pattern on the active pattern ACT and the device isolation pattern STI; performing an anisotropic etching process using the mask pattern to form a trench region crossing the active pattern ACT and the device isolation pattern STI; and filling the trench region with the word line WL. The word line WL may be formed on the central portion CA of the active pattern ACT and between the first edge portion E1 and the second edge portion E2.

[0167] In an embodiment, filling the trench area with a word line WL may include: conformally depositing a gate dielectric pattern GI on an inner surface of the trench area; filling the trench area with a conductive layer; performing an etch back and / or polishing process on the conductive layer to form a gate electrode GE; and forming a gate capping pattern GC on the gate electrode GE to fill the remainder of the trench area.

[0168] The lower storage node contact BCx and the fence pattern FN may be formed on the substrate 100 to be alternately arranged along the third direction D3. The lower storage node contact BCx may be formed to extend along the second direction D2 on the second edge portion E2 of the active pattern ACT. The fence pattern FN may be formed to extend along the second direction D2 on the center portion CA of the active pattern ACT. In an embodiment, the formation of the lower storage node contact BCx and the fence pattern FN may include: forming a lower storage node contact layer to cover or at least partially cover the substrate 100; and forming the fence pattern FN to divide the lower storage node contact layer into lower storage node contacts BCx spaced apart from each other in the third direction D3. Next, the buffer pattern BP may be formed to cover or at least partially cover the substrate 100.

[0169] The bit line mask pattern BMP may be formed on the buffer pattern BP. The bit line mask pattern BMP may include a plurality of mask patterns spaced apart from each other in the second direction D2 and extending in the third direction D3. The bit line mask pattern BMP may be formed on the second edge portion E2 of the active pattern ACT.

[0170] refer to Figures 32 to 33E, a bit line trench region BTR may be formed by an etching process using the bit line mask pattern BMP as an etching mask. The buffer pattern BP, the lower storage node contact BCx, the fence pattern FN, the upper portion of the word line WL, the upper portion of the first active insulation pattern AI1, and the upper portion of the first edge portion E1 of the active pattern ACT may be removed by the etching process, and the bit line trench region BTR may be defined in the region removed by the etching process. The bit line trench region BTR may be formed on the first edge portion E1 of the active pattern ACT. The first top surface E1a of the first edge portion E1 of the active pattern ACT may be exposed to the outside through the bottom surface of the bit line trench region BTR.

[0171] Each of the lower storage node contacts BCx may be divided into lower storage node contacts BCx spaced apart from each other in the second direction D2 by the bit line trench region BTR. Each of the fence patterns FN may be divided into fence patterns FN spaced apart from each other in the second direction D2 by the bit line trench region BTR. During the process of forming the bit line trench region BTR, a portion of the top surface of the word line WL may also be recessed. Therefore, the top surface of the word line WL may be classified into a first top surface W1a and a second top surface W2a.

[0172] The bit line spacer BSP may be formed in the bit line trench region BTR. The bit line spacer BSP may be formed to cover or at least partially cover the inner side surface of the bit line trench region BTR. In an embodiment, a pair of bit line spacers BSP may be formed to cover or at least partially cover the opposite inner side surfaces of the bit line trench region BTR, respectively. The bit line spacer BSP may not cover at least a portion of the first edge portion E1 of the active pattern ACT. Between the pair of bit line spacers BSP, the first top surface E1a of the first edge portion E1 of the active pattern ACT may be exposed to the outside.

[0173] The lower bit line BLx may be formed on the exposed first top surface E1a of the first edge portion E1 of the active pattern ACT. The upper bit line BLy may be formed on the lower bit line BLx. The lower bit line BLx and the upper bit line BLy together may form the bit line BL. As an example, the lower bit line BLx may be formed by a selective epitaxial growth (SEG) process, in which the first top surface E1a of the first edge portion E1 of the active pattern ACT is used as a seed layer. As a result of the SEG process, the lower bit line BLx may be selectively grown on the first top surface E1a of the first edge portion E1 of the active pattern ACT. The lower bit line BLx and the upper bit line BLy may be sequentially formed. In an embodiment, after the bit line BL is formed, an additional process for distinguishing the lower bit line BLx from the upper bit line BLy may be performed. Thereafter, a bit line capping pattern BCP may be formed on the bit line BL to fill the remainder of each bit line trench region BTR. The mold pattern MP may be formed to cover the entire top surface of the substrate 100.

[0174] Return to reference Figure 1A as well as FIG. 2A to FIG. 2E , the contact hole CH may be formed to penetrate the mold pattern MP. In an embodiment, the formation of the contact hole CH may include: forming a mask pattern including holes to cover or at least partially cover the top surface of the mold pattern MP; and performing a removal process on the mold pattern MP, in which the mask pattern is used as an etching mask. The holes may be arranged linearly along the second direction D2, and may be arranged in a zigzag shape along the third direction D3. As another example, referring to Fig. 20 and Fig.21 , the holes in a row may be formed to be arranged side by side along the second direction D2, and the holes in a column may be formed to be arranged side by side along the third direction D3.

[0175] The upper storage node contact BCy may be formed in the contact hole CH, respectively. The second silicide pattern SC may be formed on the upper storage node contact BCy in the contact hole CH. In an embodiment, a second barrier pattern may be formed together with the second silicide pattern SC. Thereafter, a landing pad LP may be formed to fill the remainder of each contact hole CH. The top surface of the landing pad LP may be located at substantially the same height as the top surface of the mold pattern MP and be coplanar with the top surface of the mold pattern MP. Next, the data storage patterns DSP may be formed on the landing pads LP, respectively.

[0176] Figures 34 to 39C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Fig.35 yes Fig.34 Cross-sectional view along line AA′. Fig.37 yes Fig.36 Cross-sectional view along line AA′. FIG. 39A to FIG. 39C They are Fig.38 Cross-sectional view along line AA′, line BB′ and line EE′.

[0177] refer to Fig.34 and Fig.35 , a substrate 100 may be provided, and an active insulation line AIL may be formed on the substrate 100. In an embodiment, the formation of the active insulation line AIL may include: forming an active mold layer on the substrate 100; partially removing the active mold layer; and forming the active insulation line AIL to fill an empty area formed by partially removing the active mold layer. During the removal process of the active mold layer, the upper portion of the substrate 100 may be recessed to a certain depth. The bottom surface of the active insulation line AIL may be located at a height lower than the uppermost surface 100a of the substrate 100.

[0178] Thereafter, the remaining portion of the active mold layer may be removed from the substrate 100. Thus, the uppermost surface 100a of the substrate 100 may be exposed to the outside. The active spacer layer ASL may be formed to cover or at least partially cover the exposed uppermost surface 100a of the substrate 100 and the top and side surfaces of the active insulation line AIL. The active spacer layer ASL may include an insulating material.

[0179] refer to Fig.36 and Fig.37 , a removal process may be performed on the active spacer layer ASL. Here, a portion of the active spacer layer ASL may remain on the side surface of the active insulation line AIL to form an active spacer AS. The active spacer AS may extend in the third direction D3. Active spacers AS adjacent to each other in the second direction D2 may be formed at both sides of the active insulation line AIL. During the removal process, a portion of the uppermost surface 100a of the substrate 100 may be re-exposed (re-opened).

[0180] Next, the sacrificial line SL may be formed to cover or at least partially cover the exposed uppermost surface 100a of the substrate 100. The sacrificial line SL may be formed to be interposed between the active spacers AS adjacent to each other in the second direction D2.

[0181] The active mask pattern AMP may be formed on the substrate 100. Technical features of the active mask pattern AMP and a method of forming the active mask pattern AMP may be similar to those of reference 1. Figures 24 to 25E Similar to those in the described embodiments.

[0182] The sacrificial line SL may be removed from the top surface of the substrate 100. In an embodiment, the sacrificial line SL may also be removed during the process of forming the active mask pattern AMP. In another embodiment, after forming the active mask pattern AMP, a removal process may be performed on the sacrificial line SL alone.

[0183] refer to Figures 38 to 39C , a removal process using the active mask pattern AMP as an etching mask may be performed on a portion of the active insulation line AIL and a portion of the active spacer AS. Therefore, each active spacer AS may be divided into active spacers AS spaced apart from each other in the third direction D3. The active spacers AS may be spaced apart from each other in the first direction D1.

[0184] The active insulation line AIL may include an upper active insulation line AILy and a lower active insulation line AILx. The upper active insulation line AILy and the lower active insulation line AILx may be provided to have the same Figures 26 to 27E The upper active insulation line AILy may be inserted between active spacers AS adjacent to each other in the first direction D1. In an embodiment, in a plan view, the active spacers AS adjacent to each other in the first direction D1 and the upper active insulation line AILy disposed between the active spacers AS may have the same shape as the reference numerals. FIG. 3A to FIG. 3F The profiles of the active patterns ACT described are the same or similar profiles.

[0185] A removal process may be performed on the active spacer AS, the active insulation line AIL, and the substrate 100, and thus the active pattern ACT and the active insulation pattern AI may be formed. In an embodiment, the removal process may include an etching process using the active spacer AS and the upper active insulation line AILy as an etching mask. The active pattern ACT and the active insulation pattern AI may be provided to have a thickness similar to that of the active spacer AS. Fig.28 and Fig.29E The features in the embodiments are basically the same or similar features.

[0186] Thereafter, the above-described manufacturing method can be used to form a reference Figure 1A as well as FIG. 2A to FIG. 2E A semiconductor device is described.

[0187] Fig.40 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Fig.40 is corresponding to Fig.32 Cross-sectional view along line CC′.

[0188] refer to Fig.32 and Fig.40 , in reference Figures 32 to 33EDuring the formation of the described bit line trench region BTR, the gate capping pattern GC may be formed to protrude above the first active insulation pattern AI1 and the gate dielectric pattern GI. The top surface GCa of the gate capping pattern GC may be located at a height higher than the top surface of the first active insulation pattern AI1 and the top surface GIa of the gate dielectric pattern GI. The etching selectivity between the gate capping pattern GC and adjacent elements (e.g., the active pattern ACT, the first and second active insulation patterns AI1 and AI2, and the gate dielectric pattern GI, etc.) may be used to control the process. When forming the bit line trench region BTR, the gate capping pattern GC may be removed less than the adjacent elements, and therefore, the gate capping pattern GC may protrude above the adjacent elements. Thereafter, the above-described manufacturing method may be used to form the reference Figure 4 A semiconductor device is described.

[0189] Figures 41 to 44D is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 42A to FIG. 42D Along Fig.41 Cross-sectional views taken along lines AA′, BB′, CC′ and DD′. FIG. 44A to FIG. 44D Along Fig.43 Cross-sectional views taken along lines AA′, BB′, CC′ and DD′.

[0190] refer to Figures 41 to 42D , in reference Figures 28 to 29E After the formation of the active pattern ACT, the active insulation pattern AI, and the device isolation pattern STI described above, a removal process may be performed on the device isolation pattern STI. As an example, the active pattern ACT may include reference FIG. 3A to FIG. 3F During the removal process, the active insulating pattern AI may also be removed, and a side surface of an upper portion of each of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be exposed to the outside.

[0191] The active pad XO may be formed to surround the exposed side surface of the upper portion of each of the first and second edge portions E1 and E2 of the active pattern ACT. Thereafter, a pad insulation pattern XI may be formed on the device isolation pattern STI and between the active patterns ACT.

[0192] refer to Figures 43 to 44D The word line WL may be formed to cross the active pattern ACT, the device isolation pattern STI, and the active pad XO. The formation of the word line WL may be similar to the reference pattern ACT. Figures 30 to 31E The formation in the described embodiment is similar. During the formation of the word line WL, the active pad XO may be divided into a first active pad XO1 and a second active pad XO2.

[0193] Thereafter, the above-described manufacturing method can be used to form a reference Figures 5 to 6D A semiconductor device is described. Fig.45A and Fig.45B They are respectively Fig.30 A cross-sectional view corresponding to line BB′ and line DD′.

[0194] Fig.45A and Fig.45B is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure.

[0195] refer to Fig.45A and Fig.45B , in reference Figures 30 to 31E After the formation of the word line WL described, a removal process may be performed on the upper portion of each of the device isolation pattern STI, the first active insulation pattern AI1 and the second active insulation pattern AI2, and the gate dielectric pattern GI. Each of the device isolation pattern STI, the first active insulation pattern AI1 and the second active insulation pattern AI2, and the gate dielectric pattern GI may have an etching selectivity relative to adjacent elements (e.g., the active pattern ACT, the gate capping pattern GC, etc.). Therefore, during the removal process, the adjacent elements may not be removed or may be removed less. Therefore, the upper portion of each of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may have a side surface exposed to the outside.

[0196] Thereafter, the above-described manufacturing method can be used to form a reference Fig. 7A and Figure 7B A semiconductor device is described.

[0197] Fig.46 and Fig.47 is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Fig.47 is along Fig.46 A cross-sectional view taken along line DD′.

[0198] refer to Fig.46 and Fig.47 , in reference Figures 28 to 29E After the described formation of the active patterns ACT, the active insulation patterns AI, and the device isolation patterns STI and before forming the word lines WL, a lower storage node contact layer may be formed on the substrate 100 .

[0199] Next, the word line WL may be formed to intersect the active pattern ACT, the active insulation pattern AI, and the device isolation pattern STI. The word line WL may be formed to penetrate the lower storage node contact layer. Therefore, the lower storage node contact portion BCx may be formed to be spaced apart from each other in the third direction D3 and extend in the second direction D2. The formation of the word line WL may be similar to the reference pattern ACT. Figures 30 to 31E The formation in the described embodiments is similar.

[0200] Thereafter, the above-described manufacturing method can be used to form a reference Figures 8 to 9B A semiconductor device is described.

[0201] Figures 48 to 51C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 49A to FIG. 49C Along Fig.48 Cross-sectional views taken along lines CC′, DD′ and EE′. FIG. 51A to FIG. 51C Along Fig.50 Cross-sectional views taken along lines CC′, DD′ and EE′.

[0202] refer to Figures 48 to 49C , in reference Figures 30 to 31E After the described formation of the word lines WL, a lower storage node contact layer BCxL may be formed on the substrate 100. Next, a buffer pattern BP and a bit line mask pattern BMP may be sequentially formed on the lower storage node contact layer BCxL.

[0203] refer to Figures 50 to 51C , the bit line trench region BTR may be formed on the first edge portion E1 of the active pattern ACT. The formation of the bit line trench region BTR may be similar to the reference Figures 32 to 33E The formation in the described embodiment is similar. During the formation of the bit line trench region BTR, the lower storage node contact layer BCxL may be divided into lower storage node contacts BCx spaced apart from each other in the second direction D2 and extending in the third direction D3.

[0204] Next, a bit line spacer BSP, a bit line BL, and a bit line capping pattern BCP may be sequentially formed, and a method of forming each of them may be the same as that described in reference. Figures 32 to 33E The methods in the described embodiments are similar.

[0205] Next, a fence pattern FN may be formed between the bit lines BL adjacent to each other in the second direction D2. In an embodiment, the formation of the fence pattern FN may include: performing a partial removal process on the lower storage node contact BCx and the buffer pattern BP; and forming the fence pattern FN in an empty region of the lower storage node contact BOx and the buffer pattern BP formed by the partial removal process. During the formation of the fence pattern FN, each lower storage node contact BCx may be divided into lower storage node contacts BOx spaced apart from each other in the third direction D3.

[0206] Thereafter, the above-described manufacturing method can be used to form a reference Fig. 10A and Fig. 10B A semiconductor device is described.

[0207] FIG. 52A to FIG. 52E is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Figures 52A to 52E They are respectively Fig.11 or Fig.13 Cross-sectional views corresponding to line AA′, line BB′, line CC′, line DD′ and line EE′.

[0208] refer to Fig.11 or Fig.13 as well as FIG. 52A to FIG. 52E , in reference Figures 30 to 31E After the formation of the word line WL is described, reference may be omitted. Figures 30 to 31E The process of forming the lower storage node contact BCx described above, and the buffer pattern BP may be formed to cover or at least partially cover the substrate 100. Each of the first active insulation pattern AI1 and the second active insulation pattern AI2 may be formed to have a thickness greater than Figures 28 to 29E Therefore, the second top surfaces E1b and E2b of the first edge portion E1 and the second edge portion E2 of the active pattern ACT may be formed at a height greater than that of the first edge portion E1 and the second edge portion E2 of the active pattern ACT. Figures 28 to 29E The height of the embodiment is at a low height.

[0209] After forming the buffer pattern BP, the bit line BL, the bit line capping pattern BCP, the mold pattern MP, the upper storage node contact BCy, and the data storage pattern DSP can be sequentially formed using the above-mentioned manufacturing method without an additional process for forming the lower storage node contact BCx, and in this case, the semiconductor device can be formed to have a reference Figures 11 to 12D The structure of the description.

[0210] In the examples, for reference Figures 13 to 14E The semiconductor device described herein may have a manufacturing process that is different from the above-described manufacturing method in some steps after the buffer pattern BP is formed.

[0211] refer to Figures 13 to 14E , a bit line trench region BTR, a bit line spacer BSP, a bit line BL, a bit line capping pattern BCP, and a mold pattern MP may be sequentially formed, and the formation of each of them may be similar to that of the reference Figures 32 to 33E The formation in the described embodiments is similar.

[0212] Next, contact holes CH may be formed between the bit lines BL adjacent to each other in the second direction D2. During the process of forming the contact holes CH, the upper portion of the second edge portion E2 of the active pattern ACT may be recessed to a certain depth and may be exposed to the outside. In an embodiment, the contact holes CH in a row may be formed to be arranged side by side in the second direction D2, and the contact holes CH in a column may be formed to be arranged side by side in the third direction D3.

[0213] The upper storage node contact BCy and the second silicide pattern SC may be formed in the contact hole CH. Next, a lower landing pad LPx may be formed to fill the remaining portion of the contact hole CH.

[0214] Thereafter, an upper landing pad LPy may be formed on the lower landing pad LPx. The formation of the upper landing pad LPy may include: sequentially forming an upper landing pad layer and a mask pattern to cover or at least partially cover the top surface of the lower landing pad LPx; and removing the upper landing pad layer by an anisotropic etching process using the mask pattern as an etching mask to form the upper landing pad LPy.

[0215] Next, a filling pattern FIL may be formed in a region formed by removing the upper landing pad layer. The filling pattern FIL may be formed to surround each of the upper landing pads LPy. Data storage patterns DSP may be formed on the upper landing pads LPy, respectively.

[0216] Figure 53 to Figure 56C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 54A to FIG. 54C Along Fig.53 Cross-sectional views taken along lines AA′, CC′ and DD′. FIG. 56A to FIG. 56C Along Fig.55 Cross-sectional views taken along lines AA′, CC′ and DD′.

[0217] refer to Figure 53 to Figure 54C , in reference Figures 30 to 31E After the described formation of the word lines WL, a lower storage node contact layer and a lower bonding layer may be disposed and sequentially stacked on the substrate 100 .

[0218] The fence pattern FN may be formed on the word line WL to extend in the second direction D2. The fence pattern FN may be formed to penetrate the lower storage node contact layer and the lower landing layer. Therefore, the lower storage node contact portions BCx may be formed to be spaced apart from each other in the third direction D3 and to extend in the second direction D2, and the lower landing pads LPx may be formed to be spaced apart from each other in the third direction D3 and to extend in the second direction D2.

[0219] refer to Figures 55 to 56C , you can omit the reference Figures 32 to 33E The process of forming the buffer pattern BP described above. The bit line trench region BTR, the bit line spacer BSP, the bit line BL, and the bit line capping pattern BCP may be sequentially formed, and the method of forming each of them may be the same as that of the reference Figures 32 to 33E During the formation of the bit line trench region BTR, each lower storage node contact BCx and each lower landing pad LPx may be divided into lower storage node contacts BCx spaced apart from each other in the second direction D2 and lower landing pads LPx spaced apart from each other in the second direction D2, respectively.

[0220] After this, the reference can be omitted Figures 32 to 33E The process of forming the mold pattern MP described above can be omitted. Figure 1A as well as FIG. 2A to FIG. 2E A process of forming the upper storage node contact BCy and the second silicide pattern SC is described.

[0221] The upper landing pad layer LPL may be formed to cover or at least partially cover the top surface of the substrate 100. The landing pad mask pattern LMP may be formed on the upper landing pad layer LPL. In a plan view, the arrangement of the landing pad mask pattern LMP may be the same as that of the reference numeral 140. Figure 1A as well as FIG. 2A to FIG. 2E The arrangement of the contact holes CH is described similarly. The landing pad mask patterns LMP may be linearly arranged along the second direction D2, and may be arranged in a zigzag shape along the third direction D3.

[0222] refer to Figures 15 to 16D , the upper landing pad LPy may be formed by etching the upper landing pad layer LPL using the landing pad mask pattern LMP as an etch mask.

[0223] Next, a filling pattern FIL may be formed from an empty area formed by removing the upper landing pad LPy. The filling pattern FIL may be formed to surround each of the upper landing pads LPy. Data storage patterns DSP may be formed on the upper landing pads LPy, respectively.

[0224] Fig.57 and Fig.58is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Fig.58 is along Fig.57 A cross-sectional view taken along line AA′.

[0225] refer to Fig.57 and Fig.58 , in reference Figures 55 to 56C After the described formation of the bit line capping pattern BCP, a mold pattern MP may be formed on the substrate 100 .

[0226] refer to Fig.17 and Fig.18 , the contact hole CH may be formed to penetrate the mold pattern MP. The formation of the contact hole CH may be similar to that of the reference Figure 1A as well as FIG. 2A to FIG. 2E The formation in the described embodiments is similar.

[0227] After this, the reference can be omitted Figure 1A as well as FIG. 2A to FIG. 2E A process of forming the upper storage node contact BCy and the second silicide pattern SC is described.

[0228] The upper landing pads LPy may be formed to fill the corresponding remaining portions of the contact holes CH. The top surfaces of the upper landing pads LPy may be located at substantially the same height as the top surfaces of the mold patterns MP and be coplanar with the top surfaces of the mold patterns MP. The data storage patterns DSP may be formed on the upper landing pads LPy, respectively.

[0229] Figures 59A to 59C is a diagram illustrating a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Figures 59A to 59C They are respectively Fig.53 Cross-sectional views corresponding to line AA′, line CC′ and line DD′.

[0230] refer to Fig.53 as well as Figures 59A to 59C , in reference Figure 53 to Figure 54C After the described formation of the lower landing pad LPx, a buffer pattern BP may be formed on the lower landing pad LPx.

[0231] The bit line trench region BTR, the bit line spacer BSP, the bit line BL, and the bit line capping pattern BCP may be sequentially formed, and a method of forming each of them may be the same as that of the reference Figures 32 to 33E The method in the described embodiment is similar. Reference may be omitted Figures 32 to 33E A process of forming the mold pattern MP is described. Thereafter, an interlayer insulating layer ILD may be formed on the substrate 100 .

[0232] refer to Figures 18 to 19EThe contact hole CH may be formed to penetrate the interlayer insulating layer ILD. The formation of the contact hole CH may be similar to that of the reference Figure 1A as well as FIG. 2A to FIG. 2E The formation in the described embodiments is similar.

[0233] After this, the reference can be omitted Figure 1A as well as FIG. 2A to FIG. 2E A process of forming each of the upper storage node contact BCy, the second silicide pattern SC, and the landing pad LP is described.

[0234] The bottom electrode BE may be formed on the contact hole CH. Forming the bottom electrode BE may include: forming a bottom electrode layer to fill the contact hole CH and cover or at least partially cover the top surface of the interlayer insulating layer ILD; and removing a portion of the bottom electrode layer to form the bottom electrode BE. The bottom electrode BE may include a lower portion BEx and an upper portion BEy.

[0235] The dielectric layer DL may be formed to conformally cover or at least partially cover the top surface of the interlayer insulating layer ILD and the upper portion BEy of the bottom electrode BE. Thereafter, the top electrode TE may be formed between and on the upper portion BEy of the bottom electrode BE.

[0236] According to the embodiments of the present disclosure, the arrangement of elements in a semiconductor device can be simplified. Therefore, the patterning process performed to manufacture the semiconductor device can reduce the difficulty, and thus the semiconductor device can be manufactured more easily. In addition, since the elements can be arranged in a relatively simple manner, the integration density of the semiconductor device can also be improved.

[0237] According to an embodiment of the present disclosure, each of the first edge portion and the second edge portion of the active pattern may include a recessed area. Therefore, the first edge portion may be placed at a relatively far position from the storage node contact, and the second edge portion may be placed at a relatively far position from the bit line. Therefore, electrical interference problems between the first edge portion and the storage node contact and electrical interference problems between the second edge portion and the bit line may be prevented. Therefore, electrical characteristics and reliability characteristics of the semiconductor device may be improved.

[0238] Each embodiment provided in the above description is not exclusive of association with one or more features of another example or another embodiment that is also provided herein or that is not provided herein but is consistent with the present disclosure.

[0239] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction; a first word line extending between the first edge portion and the second edge portion and in a second direction intersecting the first direction; a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction; as well as a storage node contact portion, on the second edge portion, wherein the first edge portion includes a first top surface and a second top surface, wherein the second top surface of the first edge portion is closer to the second edge portion than the first top surface of the first edge portion, and wherein the first top surface of the first edge portion is at a height higher than a height of the second top surface of the first edge portion.

2. The semiconductor device according to claim 1, wherein The second edge portion includes a first top surface and a second top surface, wherein the second top surface of the second edge portion is closer to the first edge portion than the first top surface of the second edge portion, and wherein the first top surface of the second edge portion is at a height higher than a height of the second top surface of the second edge portion.

3. The semiconductor device according to claim 2, wherein: A bottom surface of the bit line is at a height lower than that of the first top surface of the second edge portion.

4. The semiconductor device according to claim 2, further comprising: a first active insulation pattern on the second top surface of the first edge portion; as well as A second active insulation pattern is on the second top surface of the second edge portion.

5. The semiconductor device according to claim 1, wherein The storage node contact is vertically above a portion of the bit line.

6. The semiconductor device according to claim 1, wherein The first edge portion includes an upper portion and a lower portion, and The upper portion of the first edge portion is recessed in the second direction, so that a width of the upper portion of the first edge portion in the second direction is smaller than a width of the lower portion of the first edge portion in the second direction.

7. The semiconductor device according to claim 1, wherein The first edge portion includes a first side surface and a second side surface, wherein the second side surface of the first edge portion is closer to the second edge portion than the first side surface of the first edge portion, wherein the first side surface of the first edge portion has a linear profile, and Wherein, the second side surface of the first edge portion has a stepped profile.

8. The semiconductor device according to claim 1, further comprising: a second active pattern adjacent to the first active pattern in the second direction; a third active pattern adjacent to the second active pattern in the third direction; as well as a fourth active pattern, adjacent to the first active pattern in the third direction, wherein the second edge portion of the fourth active pattern, the first edge portion of the first active pattern, the second edge portion of the third active pattern, and the first edge portion of the second active pattern are sequentially arranged in the second direction.

9. The semiconductor device according to claim 8, wherein: The semiconductor device further includes a second word line adjacent to the first word line in the third direction, wherein the first word line crosses the first active pattern and the second active pattern, and The second word line crosses the third active pattern and the fourth active pattern.

10. A semiconductor device comprising: a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction; a word line extending between the first edge portion and the second edge portion and in a second direction intersecting the first direction; a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction; as well as a storage node contact portion, on the second edge portion, wherein the first edge portion comprises an upper portion and a lower portion, and The upper portion of the first edge portion is recessed in the second direction, so that a width of the upper portion of the first edge portion in the second direction is smaller than a width of the lower portion of the first edge portion in the second direction.

11. The semiconductor device according to claim 10, wherein: The upper portion of the first edge portion and the lower portion of the first edge portion are directly connected without an interface between the upper portion of the first edge portion and the lower portion of the first edge portion.

12. The semiconductor device according to claim 10, wherein: The upper portion of the first edge portion contacts the lower portion of the first edge portion at a first height, and Wherein, at the first height in the second direction, a width of the upper portion of the first edge portion is smaller than a width of the lower portion of the first edge portion.

13. The semiconductor device according to claim 10, wherein: The first edge portion includes a first side surface and a second side surface, wherein the second side surface of the first edge portion is closer to the second edge portion than the first side surface of the first edge portion, wherein the first side surface of the first edge portion has a linear profile, and Wherein, the second side surface of the first edge portion has a stepped profile.

14. The semiconductor device according to claim 10, wherein: The second edge portion includes an upper portion and a lower portion, and The upper portion of the second edge portion is recessed in a fourth direction opposite to the second direction, so that a width of the upper portion of the second edge portion in the fourth direction is smaller than a width of the lower portion of the second edge portion in the fourth direction.

15. The semiconductor device according to claim 14, further comprising: a first active insulation pattern on a side surface of the upper portion of the first edge portion; as well as A second active insulation pattern is on a side surface of the upper portion of the second edge portion.

16. The semiconductor device according to claim 10, further comprising: a second active pattern adjacent to the first active pattern in the second direction; a third active pattern adjacent to the second active pattern in the third direction; as well as a fourth active pattern adjacent to the first active pattern in the third direction, and wherein the second edge portion of the fourth active pattern, the first edge portion of the first active pattern, the second edge portion of the third active pattern, and the first edge portion of the second active pattern are sequentially arranged in the second direction.

17. A semiconductor device comprising: an active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction; a word line extending between the first edge portion and the second edge portion and in a second direction intersecting the first direction; a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction; as well as a storage node contact portion, on the second edge portion, wherein the first edge portion includes a first side surface and a second side surface, wherein the second side surface of the first edge portion is closer to the second edge portion than the first side surface of the first edge portion, wherein the first side surface of the first edge portion has a linear profile, and Wherein, the second side surface of the first edge portion has a stepped profile.

18. The semiconductor device according to claim 17, wherein: The first edge portion includes a concave portion. 19 . The semiconductor device of claim 18 , further comprising a first active insulation pattern filling the concave portion of the first edge portion.

20. The semiconductor device according to claim 17, wherein The second edge portion includes a first side surface and a second side surface, wherein the second side surface of the second edge portion is closer to the first edge portion than the first side surface of the second edge portion, wherein the first side surface of the second edge portion has a linear profile, and Wherein, the second side surface of the second edge portion has a stepped profile.

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