Semiconductor structure
By designing the third part of the line structure in the semiconductor storage device, the shallow groove isolation structure is used as a support to solve the problem of easily tilt or bending of the bit line, and improves the yield of the semiconductor structure.
Patent Information
- Application Number
- CN202411295452.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-01-21
AI Technical Summary
In semiconductor memory devices, the bit lines in the peripheral region are prone to tilt or bend, resulting in short circuits of adjacent bit lines and reducing yield.
Design a semiconductor structure, where the line structure includes the third part, and the third part is located above the shallow groove isolation structure. Its width is greater than the width of the second part. It provides solid support and optimizing stress distribution to prevent the bit line tilt or bending.
Through the support and traction effect of the third part, it effectively prevent the tilt or bending of the line structure, avoid short circuit of adjacent position lines, and improve the yield of semiconductor structure.
Smart Images
Figure CN119342811A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art
[0002] As various electronic products develop towards miniaturization, the design of dynamic random access memory (DRAM) is also gradually developing towards high integration. In the related art, the substrate of a semiconductor memory device usually includes a storage area and a peripheral circuit area, wherein both the storage area and the peripheral area are provided with a bit line (BL), which is used to connect to the source or drain of the transistor in the storage area to store or output data information through the bit line.
[0003] However, the bit lines located in the peripheral area are prone to tilt or bend, and even cause adjacent bit lines to be connected to each other and short-circuit, thereby reducing the yield of the semiconductor memory device. Summary of the invention
[0004] In view of the above problems, an embodiment of the present application provides a semiconductor structure, which can prevent or even avoid the tilting of the bit line structure, thereby improving the yield of the semiconductor structure.
[0005] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:
[0006] An embodiment of the present application provides a semiconductor structure, which includes:
[0007] a substrate including an active region defined by a shallow trench isolation structure;
[0008] A plurality of word line structures are located in the substrate, the word line structures cross the active area and extend in a second direction;
[0009] A plurality of bit line structures are located on the substrate and extend in a first direction intersecting with the second direction, each of the bit line structures comprising:
[0010] A first portion spanning the active area and the word line structure;
[0011] The third part is located above the shallow trench isolation structure;
[0012] a second part, wherein two ends of the second part directly contact the first part and the third part respectively;
[0013] In the second direction, the width of the second portion is smaller than the width of the first portion and the width of the third portion.
[0014] In a possible implementation manner, a width of the first portion is smaller than a width of the third portion.
[0015] In a possible implementation manner, the width is a maximum width, or the width is an average width.
[0016] In a possible implementation manner, in the second direction, at least one side of the third portion protrudes from the second portion of the bit line structure.
[0017] In a possible implementation manner, in the second direction, both sides of the third part protrude from the second part.
[0018] In a possible implementation manner, along a direction perpendicular to the substrate, a top surface of the third portion is lower than a top surface of the second portion; or a top surface of the third portion is flush with a top surface of the second portion.
[0019] In a possible implementation manner, a shape projected by the third part on the substrate includes a polygon, a circle, or an ellipse.
[0020] In a possible implementation manner, along the first direction and away from the first part of the bit line structure, the size of the third part in the second direction tends to increase first and then decrease.
[0021] In a possible implementation manner, in the second direction, at least one side of the first part protrudes beyond the second part.
[0022] In a possible implementation, the distance between adjacent third parts is a first distance L1, and the distance between adjacent first parts is a second distance L2;
[0023] The first distance L1 is greater than the second distance L2.
[0024] In a possible implementation manner, a ratio of the first distance L1 to the second distance L2 is 1 to 1.5.
[0025] In a possible implementation, the semiconductor structure further includes a dummy bit line structure, and the dummy bit line structure is arranged on one side of the bit line structure in the second direction;
[0026] In the first direction, the third portion includes a first end and a second end that are oppositely disposed, and the first end is connected to the second portion;
[0027] The dummy bit line structure is located in the first direction and at an end facing the third portion, at a connection between the first portion and the second portion of the bit line structure, or between the first end and the second end.
[0028] In a possible implementation, a first contact plug is disposed between the first parts of adjacent bit line structures;
[0029] In the first direction, the first contact plug located at the outermost edge has a fourth distance L4 from the third portion of the bit line structure; and the first contact plug has a preset width W4;
[0030] A ratio of the fourth distance L4 to the preset width W4 is greater than 4.
[0031] In the semiconductor structure provided in the embodiment of the present application, the bit line structure includes a third part, the third part is located above the shallow trench isolation structure, and the width of the third part is greater than the width of the second part. In this way, the third part is supported by the shallow trench isolation structure, and the width of the third part is greater than the width of the second part, so that the third part has a more stable support and optimized stress distribution, and then the third part has a pulling effect on the second part, preventing the second part from tilting or bending, thereby avoiding the adjacent bit line structures from being connected to each other and short-circuiting, thereby improving the yield of the semiconductor structure.
[0032] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0034] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 1 ;
[0035] Figure 2 For along Figure 1 Sectional view in the AA direction;
[0036] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 2 ;
[0037] Figure 4 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 3 ;
[0038] Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 4 ;
[0039] Figure 6 For along Figure 5 Cross-sectional view in the BB direction;
[0040] Figure 7 For along Figure 5 Cross-sectional view in CC direction;
[0041] Figure 8 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 5 ;
[0042] Fig. 9 For along Figure 8 Cross-sectional view in the middle DD direction;
[0043] Fig.10 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 6 ;
[0044] Fig.11 For along Fig.10 Cross-sectional view along the EE direction.
[0045] Description of reference numerals:
[0046] 100: substrate; 110: first region; 120: second region; 121: first sub-region; 122: second sub-region; 130: active region; 140: shallow trench isolation structure; 150: insulating column;
[0047] 200: bit line structure; 210: first part; 220: second part; 230: third part; 240: bit line conductive layer; 250: bit line insulating layer; 260: isolation sidewall; 270: bit line contact plug;
[0048] 300: word line structure; 310: dielectric layer; 320: barrier layer; 330: conductive layer; 340: insulating layer;
[0049] 400: dummy bit line structure;
[0050] 500: first contact plug;
[0051] 600: Second contact plug. DETAILED DESCRIPTION
[0052] With the development of science and technology, semiconductor integrated circuits are more inclined towards small-size design and high-density arrangement. Based on this, in order to further reduce the width of the bit line structure, the bit line structure usually has a smaller width in the peripheral circuit area. This will cause the bit line structure in the peripheral circuit area to have a larger aspect ratio, which in turn makes the bit line structure prone to tilting or bending, and even causes adjacent bit line structures to be short-circuited and connected to each other, thereby reducing the yield of the semiconductor structure.
[0053] In view of the above technical problems, an embodiment of the present application provides a semiconductor structure, wherein the bit line structure includes a third part, the third part is located above the shallow trench isolation structure, and the width of the third part is greater than the width of the second part. In this way, the third part is supported by the shallow trench isolation structure, and the width of the third part is greater than the width of the second part, so that the third part has a more stable support and optimized stress distribution, and the third part has a pulling effect on the second part to prevent the second part from tilting or bending, thereby avoiding the short circuit caused by the connection between adjacent bit line structures, and improving the yield of the semiconductor structure.
[0054] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application.
[0055] For the convenience of explanation and to help understand the semiconductor structure provided by this application, please refer to the attached Figure 1 and attached Figure 2 , the figure shows spatial reference directions such as a first direction D1, a second direction D2, a third direction D3 and a fourth direction D4, wherein the first direction D1 and the second direction D2 are substantially parallel to the surface of the substrate 100, and the third direction D3 is substantially perpendicular to the surface of the substrate 100. The third direction D3 may also be referred to as a vertical direction herein, and the first direction D1, the second direction D2 and the fourth direction D4 may also be referred to as horizontal directions.
[0056] The overall structure of the semiconductor structure is described below in conjunction with the accompanying drawings.
[0057] Please refer to the attached Figure 1 and attached Figure 2, an embodiment of the present application provides a semiconductor structure, which includes a substrate 100. The substrate 100 is used as a main bearing component of the semiconductor structure, and is used to bear components disposed thereon. The substrate 100 may be any substrate 100 suitable for manufacturing semiconductor elements, such as a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto.
[0058] The substrate 100 includes an active region 130, wherein the active region 130 is defined by a shallow trench isolation structure (STI for short), and the active region 130 may extend along a fourth direction D4. The fourth direction D4 may be a direction different from the first direction D1 and the second direction D2, but is located in the same plane, wherein the fourth direction D4 has an inclined angle with the first direction D1 and the second direction D2, respectively, that is, the active region 130 is inclined relative to the first direction D1 and the second direction D2.
[0059] It should be understood that in the present embodiment, there may be multiple active areas 130, and the multiple active areas 130 are arranged in an array. Among them, the shallow trench isolation structure 140 can separate the multiple active areas 130 to ensure that the active areas 130 are independent of each other. Exemplarily, a shallow trench is formed in the substrate 100 through a patterning process, and a shallow trench isolation structure 140 is formed in the shallow trench, so that a plurality of active areas 130 separated by the shallow trench isolation structure 140 are defined on the substrate 100. Among them, the patterning process can be a self-aligned double patterning (Self-Aligned Double Patterning, referred to as SADP) process or a self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, referred to as SAQP) process.
[0060] In some embodiments, the shallow trench isolation structure 140 can be made of an insulating material, and the shallow trench isolation structure 140 can also be a stacked structure. Exemplarily, the shallow trench isolation structure 140 includes a first isolation layer, a second isolation layer and a third isolation layer stacked, wherein the first isolation layer is arranged on the inner wall of the shallow trench, the second isolation layer is arranged on the first isolation layer, and the third isolation layer is arranged on the second isolation layer, and fills the area surrounded by the second isolation layer. The materials of the first isolation layer and the third isolation layer can be the same or different. For example, the materials of the first isolation layer and the third isolation layer both include silicon oxide, and the material of the second isolation layer includes silicon nitride, so that the shallow trench isolation structure 140 is an "ONO" structure. Such a setting can enhance the isolation effect of the shallow trench isolation structure 140, so that each active area 130 is independent of each other. It should be understood that the drawings provided in this embodiment only point out the position of the shallow trench isolation structure 140, and the specific film layers are not all shown.
[0061] Please continue to refer to the attached Figure 1 and attached Figure 2 The semiconductor structure further includes a plurality of word line structures 300, which are located in the substrate 100 and are spaced apart along the first direction D1. The word line structures 300 cross the active area 130 and extend in the second direction D2. The second direction D2 may intersect with the first direction D1. For example, in the same plane, the second direction D2 may be perpendicular to the first direction D1.
[0062] Each word line structure 300 connects a plurality of active areas 130 spaced apart along the second direction D2, so that each word line structure 300 connects a plurality of transistors (not shown in the figure) spaced apart along the second direction D2, thereby simplifying the circuit design of the semiconductor structure, reducing the complexity and length of wiring, and thereby improving the operating speed and efficiency of the semiconductor structure.
[0063] Please refer to the attached Figure 2 , the word line structure 300 may include a dielectric layer 310, a barrier layer 320, a conductive layer 330 and an insulating layer 340. In this embodiment, the word line structure is a buried structure, so it is usually necessary to form a groove in the substrate 100 during the preparation process, and the groove extends along the second direction D2 and crosses a plurality of active areas 130 arranged along the second direction D2. Among them, the dielectric layer 310 covers the inner wall of the groove; the barrier layer 320 is arranged on the dielectric layer 310, and the top surface of the barrier layer 320 is lower than the top surface of the dielectric layer 310; the conductive layer 330 is arranged on the barrier layer 320 and fills the area surrounded by the barrier layer 320; the insulating layer 340 is arranged on the conductive layer 330 and connected to the inner wall of the dielectric layer 310.
[0064] The material of the dielectric layer 310 includes silicon oxide, the material of the barrier layer 320 includes titanium nitride, the material of the conductive layer 330 includes tungsten, and the material of the insulating layer 340 includes silicon nitride. The barrier layer 320 is used to prevent the conductive material in the conductive layer 330 from diffusing into the substrate 100, thereby improving the performance of the semiconductor structure. It should be understood that the portion of the word line structure 300 located in the active area 130 can constitute a gate structure of a transistor.
[0065] Please refer to the attached Figure 5 To Attachment Fig.11 The semiconductor structure further includes a plurality of bit line structures 200, and the plurality of bit line structures 200 are located on the substrate 100. The plurality of bit line structures 200 are arranged at intervals along the second direction D2 and extend along the first direction D1. It should be noted that when the semiconductor structure is a semiconductor memory device, the bit line structure 200 is used to connect one of the source and the drain of the transistor.
[0066] Each bit line structure 200 includes a first portion 210, a second portion 220, and a third portion 230. The first portion 210 crosses the active area 130 and the word line structure 300, the third portion 230 is located above the shallow trench isolation structure 140, and two ends of the second portion 220 directly contact the first portion 210 and the third portion 230 respectively. In other words, the second portion 220 is disposed between the first portion 210 and the third portion 230, and is used to connect the first portion 210 and the third portion 230.
[0067] In the second direction, the width of the second portion 220 is smaller than the width of the first portion 210 and the width of the third portion 230. In other words, the width of the third portion 230 is larger than the width of the second portion 220. In this embodiment, the third portion 230 is supported by the shallow trench isolation structure 140, and the width of the third portion 230 is larger than the width of the second portion 220, so that the third portion 230 has a more stable support and optimized stress distribution, thereby causing the third portion 230 to have a pulling effect on the second portion 220, preventing the second portion 220 from tilting or bending, thereby avoiding the adjacent bit line structures 200 from being connected to each other and short-circuiting, thereby improving the yield of the semiconductor structure. It should be noted that in this embodiment, the width refers to the average width. Under the premise that the width of the second portion 220 is smaller than the width of the first portion 210 and the width of the third portion 230, the width of the first portion 210 and the width of the second portion 220, and the width of the first portion 210 and the width of the third portion 230 can also have other implementations. Exemplarily, the width of the first portion 210 is smaller than the width of the third portion 230, but larger than the width of the second portion 220. The first portion 210 spans the active region 130 and the word line structure 300, and its smaller width can optimize the current density distribution, reduce the current concentration effect, and reduce the risk of electromigration, thereby improving the reliability and life of the semiconductor structure.
[0068] It should be noted that the width described in this embodiment can be selected according to the shape of the bit line structure 200. In one example, when the bit line structure 200 is a regular shape, for example, the bit line structure 200 is a strip shape with equal width, the width of the bit line structure 200 can be the width at any position. In another example, when the bit line structure 200 is an irregular shape, the width can be the maximum width, or the width can be the average width.
[0069] In addition, the positions of the first portion 210, the second portion 220, and the third portion 230 of the bit line structure 200 are related to the partitioning of the substrate 100. For example, the substrate 100 may include a first region 110 and a second region 120, the first region 110 and the second region 120 are adjacent to each other, wherein the first region 110 is used to set a memory cell, and the second region 120 may be a peripheral circuit region, providing necessary control and interface functions.
[0070] At least the first portion 210 is located in the first region 110, that is, the first portion 210 may be located on the first region 110, or the first portion 210 and part of the second portion 220 may be located in the first region 110. The third portion 230 is located in the second region 120. Since the second region 120 is a peripheral circuit region, the number of semiconductor devices included in the region is relatively small. Therefore, in this embodiment, the width of the third portion 230 is the largest, and the pulling force of the third portion 230 on the second portion 220 can be increased as much as possible, thereby reducing or even avoiding the tilt of the bit line structure 200.
[0071] In one possible implementation, please refer to the attached Figure 3 and attached Figure 4 In the second direction D2, at least one side of the third portion 230 protrudes from the second portion 220 of the bit line structure 200. In one example, one side of the third portion 230 protrudes from the second portion 220 of the bit line structure 200 to attach Figure 3 For example, the rear side of the third part 230 protrudes from the second part 220, or the front side of the third part 230 protrudes from the second part 220. In another example, please refer to the attached Figure 4 In the second direction D2, both sides of the third portion 230 protrude from the second portion 220.
[0072] The shape of the third portion 230 can be arranged according to the layout direction of the adjacent bit line structures 200. When the distance between the adjacent bit line structures 200 in the second direction D2 is large, both sides of the third portion 230 can be protruded from the second portion 220, so that the area of the third portion 230 can be increased as much as possible, providing a larger contact area and supporting force, enhancing the mechanical stability of the bit line structure 200, dispersing mechanical stress, and reducing the risk of deformation or fracture of the bit line structure 200. When the distance between the adjacent bit line structures 200 in the second direction D2 is small, one side of the third portion 230 can be protruded from the second portion 220 of the bit line structure 200.
[0073] In any two adjacent bit line structures 200, the two third portions 230 may be located on the same side or on different sides. For example, in any two adjacent bit line structures 200, the two bit line structures 200 are centrally symmetrically arranged. That is, the two third portions 230 are located on different sides.
[0074] In order to facilitate the detailed description of any two adjacent bit line structures 200, the second region 120 may be further refined. For example, the second region 120 includes a first sub-region 121 and a second sub-region 122. The first sub-region 121 and the second sub-region 122 are respectively arranged on both sides of the first region 110 in the first direction D1 and connected to the first region 110. It should be understood that in this embodiment, the second region 120 is not limited to being arranged only on both sides of the first region 110 in the first direction D1, and can also be arranged on at least one side of the first region 110 in the second direction D2, and can be freely arranged according to the actual structure of the semiconductor structure.
[0075] In any two adjacent bit line structures 200, the third portion 230 of one bit line structure 200 is located in the first sub-region 121, and the third portion 230 of the other bit line structure 200 is located in the second sub-region 122. In other words, the two adjacent third portions 230 are staggered, and on the premise of increasing the area of the third portions 230 as much as possible, the distance between the adjacent third portions 230 can also be increased, thereby reducing the parasitic capacitance generated between the adjacent bit line structures 200, thereby improving the performance of the semiconductor structure.
[0076] In a possible implementation, along a direction perpendicular to the substrate 100, the top surface of the third portion 230 is lower than the top surface of the second portion 220; or, the top surface of the third portion 230 is flush with the top surface of the second portion 220. In this embodiment, the third portion 230 is also equivalent to a protective sidewall, and the third portion 230 can provide additional support for the side surface of the second portion 220 in the first direction D1, reduce or even avoid the second portion 220 from tilting along the first direction D1, thereby improving the yield of the semiconductor structure.
[0077] It should be noted that the shape of the third portion 230 can be regular or irregular. For example, the projection shape of the third portion 230 on the substrate 100 includes a polygon, a circle or an ellipse. When the projection shape of the third portion 230 on the substrate 100 is a polygon, the third portion 230 can be a quadrilateral, a pentagon or other.
[0078] This embodiment can optimize the shape design of the third part 230 and take advantage of its regular or irregular shape to effectively improve design flexibility, optimize space utilization, enhance mechanical stability, and thus improve the overall performance and reliability of the semiconductor structure.
[0079] Please continue to refer to the attached Figure 1, along the first direction and away from the first part 210 of the bit line structure 200, the size of the third part 230 in the second direction tends to increase first and then decrease. By limiting the size of the third part 230 in the second direction, this embodiment can better optimize the stress distribution, gradually disperse and absorb the stress, reduce the stress concentration point, thereby reducing the risk of deformation and fracture of the bit line structure 200 and enhancing the stability of the semiconductor structure. In addition, in the direction away from the first part 210 of the bit line structure 200, the third part 230 tends to decrease, and the parasitic capacitance generated between the third parts 230 of adjacent bit line structures 200 can also be reduced.
[0080] In this embodiment, the width of the first part 210 is also greater than the width of the second part 220, which can be achieved by at least one side of the first part 210 protruding out of the second part 220 in the second direction, so as to reduce the resistance of the first part 210, thereby increasing the signal transmission speed, reducing signal delay and distortion, and improving the signal integrity and transmission performance of the semiconductor structure.
[0081] Please continue to refer to the attached Figure 4 , the distance between adjacent third parts 230 is the first distance L1, and the distance between adjacent first parts 210 is the second distance L2; the first distance L1 is greater than the second distance L2, and illustratively, the ratio of the first distance L1 to the second distance L2 is 1 to 1.5, or the first distance L1 is between 1 and 1.5 times the second distance L2, for example, the ratio of the first distance L1 to the second distance L2 is 1.0, 1.1, 1.2, 1.3, 1.4 or 1.5. The larger first distance L1 can provide more space for arranging peripheral circuits and other functional modules, while the smaller second distance L2 can improve the integration of storage units, achieve high-density arrangement, and facilitate the development of semiconductor structures towards integration and miniaturization.
[0082] In other embodiments, the distance between adjacent third portions 230 and the distance between adjacent second portions 220 may also be limited. For example, please refer to the attached Figure 4 The distance between adjacent second parts 220 is a third distance L3, the third distance L3 is greater than the first distance L1, and the first distance L1 is greater than the second distance L2.
[0083] The adjacent first portions 210 may be aligned at the ends on the same side, or in other ways. Fig.10 In two adjacent bit line structures 200, the connection between the first part 210 and the second part 220 is staggered with the end of the first part 210 away from the second part 220. In this way, the location of each bit line structure 200 can be reasonably arranged according to the specific structure of the semiconductor structure.
[0084] In one possible implementation, please refer to the attached Figure 1 , Attachment Figure 5 , Attachment Figure 8 , Attachment Fig. 9 , Attachment Fig.10 And attached Fig.11 The semiconductor structure further includes a dummy bit line structure 400, which is disposed on one side of the bit line structure 200 in the second direction D2, for example, with an attached Figure 1 Taking the illustrated orientation as an example, the dummy bit line structure 400 is disposed above the bit line structure 200 .
[0085] It is important to understand that Fig. 9 It is attached Figure 8 The sectional view along the DD direction in the figure is only for illustration and does not show the isolation sidewalls 260 on both sides of the third part 230. Fig.11 It is attached Fig.10 The cross-sectional view along the EE direction is only for illustration and does not show the isolation spacer on one side of the dummy bit line structure 400 and the isolation spacer 260 on both sides of the first portion 210 and the second portion 220 .
[0086] In the first direction D1, the third portion 230 includes a first end portion and a second end portion that are oppositely disposed, and the first end portion is connected to the second portion 220; Figure 5 The end of the dummy bit line structure 400 facing the third portion 230 is located between the connection between the first portion 210 and the second portion 220 of the bit line structure 200. Alternatively, please refer to the attached Figure 8 and attached Fig.10 , an end of the dummy bit line structure 400 facing the third portion 230 is located between the first end and the second end.
[0087] In other embodiments, the end of the dummy bit line structure 400 facing the third portion 230 may also be aligned with the end of the second portion 220 away from the first portion 210. It should be understood that the first end may be understood as the end of the third portion 230 facing the second portion 220, and the second end may be understood as the end of the third portion 230 away from the second portion 220.
[0088] In some embodiments, the width of the dummy bit line structure 400 in the second direction D2 is greater than the width of the bit line structure 200 in the second direction D2, so that the area of the dummy bit line structure 400 can be increased. The width may be a maximum width or an average width.
[0089] In this embodiment, the dummy bit line structure 400 and the bit line structure 200 can be formed in the same manufacturing process. Figure 7The dummy bit line structure 400 and the bit line structure 200 both include a bit line conductive layer 240, a bit line insulating layer 250 and an isolation sidewall 260. The bit line conductive layer 240 is disposed on the substrate 100; the bit line insulating layer 250 is disposed on the bit line conductive layer 240 to prevent the bit line conductive layer 240 from being electrically connected to other conductive components disposed on the bit line insulating layer 250; the isolation sidewall 260 covers the side surfaces of the bit line conductive layer 240 and the bit line insulating layer 250 to prevent electrical connection between adjacent bit line structures 200.
[0090] It should be noted that, in this embodiment, the bit line conductive layer 240 can be a single-layer structure or a stacked structure, such as a stacked structure of tungsten, titanium nitride, doped polysilicon, etc., and this embodiment is not specifically limited here. In addition, the material of the bit line insulating layer 250 includes silicon nitride, and the isolation sidewall 260 can be an "ON structure" or an "ONO structure".
[0091] The bit line conductive layer 240 of the first portion 210 may be connected to the source region or the drain region of the substrate 100 through the bit line contact plug 270. The bit line contact plug 270 is in contact with the substrate 100, which can significantly reduce the contact resistance between the bit line conductive layer 240 and the source region or the drain region, thereby helping to improve the current transmission efficiency of the semiconductor structure, reduce power consumption, and improve the overall performance and efficiency of the semiconductor structure.
[0092] In one possible implementation, please refer to the attached Figure 1 , Attachment Figure 2 And attached Figure 6 A first contact plug 500 is disposed between the first portions 210 of the adjacent bit line structures 200. The first contact plug 500 may contain other materials such as tungsten, polysilicon, titanium nitride, etc. The first contact plug 500 is used to connect a capacitor (not shown) to the other of the source region or the drain region of the substrate 100. For example, when the first contact plug 500 is connected to the drain region of the substrate 100, the capacitor is also connected to the drain region of the substrate 100 accordingly.
[0093] In the first direction D1, the first contact plug 500 closest to the bit line structure 200 (i.e., the first contact plug 500 located at the outermost edge) has a fourth distance L4 from the third portion 230 of the bit line structure 200; and the first contact plug 500 has a preset width W4; the fourth distance L4 is greater than 4 times the preset width W4, or in other words, the ratio of the fourth distance L4 to the preset width W4 is greater than 4.
[0094] A plurality of insulating pillars 150 are also disposed between the first contact plug 500 at the outermost edge and the third portion 230. Figure 1In the first region, a first contact plug 500 is disposed around the first portion 210 of the bit line structure 200, while no first contact plug is disposed around the second portion 220 and the third portion 230 of the bit line structure 200, but an insulating column 150 is disposed. It can be seen that the environments around the first portion 210, the second portion 220 and the third portion 230 of the bit line structure 200 are different. In order to improve the uniformity of the environments around the first portion 210, the second portion 220 and the third portion 230, the present application adopts the method of increasing the width of the third portion 230 in the second direction D2, that is, the width of the third portion 230 in the second direction D2 is greater than the width of the first portion 210 and the width of the second portion 220, and even the maximum width of the third portion 230 can be greater than the maximum width of the first contact plug 500. In this way, since the material contained in the third portion 230 is partially the same as that of the first contact plug 500, the uniformity of the environments around the first portion 210, the second portion 220 and the third portion 230 can be improved.
[0095] In some other embodiments, the semiconductor structure further includes a second contact plug 600, which is disposed on the first portion 210 and located on a side of the first portion 210 away from the second portion 220. The second contact plug 600 is used to realize electrical connection between the bit line structure 200 and an interconnection layer (not shown in the figure).
[0096] Compared with the technical solution in which the second contact plug 600 is set in the third part 230, the current will not pass through the second part 220 with a smaller size during the transmission from the interconnection layer to the bit line structure 200, thereby avoiding increasing the resistance value during the current transmission process. The lower resistance value improves the current transmission efficiency, reduces power consumption, and improves the overall performance and efficiency of the semiconductor structure.
[0097] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.
[0098] It should be noted that the phrases "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. mentioned in the specification indicate that the described embodiments may include certain features, structures or characteristics, but not every embodiment may include the certain features, structures or characteristics. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when describing certain features, structures or characteristics in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such features, structures or characteristics in conjunction with other embodiments, whether explicitly or not explicitly described.
[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor structure, characterized in that: include: a substrate including an active region defined by a shallow trench isolation structure; A plurality of word line structures are located in the substrate, the word line structures cross the active area and extend in a second direction; A plurality of bit line structures are located on the substrate and extend in a first direction intersecting with the second direction, each of the bit line structures comprising: A first portion spanning the active area and the word line structure; The third part is located above the shallow trench isolation structure; a second part, wherein two ends of the second part directly contact the first part and the third part respectively; In the second direction, the width of the second portion is smaller than the width of the first portion and the width of the third portion.
2. The semiconductor structure according to claim 1, characterized in that: The width of the first portion is smaller than the width of the third portion.
3. The semiconductor structure according to claim 1, characterized in that: The width is a maximum width, or the width is an average width.
4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: In the second direction, at least one side of the third portion protrudes from the second portion of the bit line structure.
5. The semiconductor structure according to claim 4, characterized in that: In the second direction, both sides of the third portion protrude from the second portion.
6. The semiconductor structure according to any one of claims 1 to 3, characterized in that: Along a direction perpendicular to the substrate, a top surface of the third portion is lower than a top surface of the second portion; or a top surface of the third portion is flush with a top surface of the second portion.
7. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The projection shape of the third part on the substrate includes a polygon, a circle or an ellipse.
8. The semiconductor structure according to claim 7, characterized in that: Along the first direction and away from the first portion of the bit line structure, the size of the third portion in the second direction increases first and then decreases.
9. The semiconductor structure according to any one of claims 1 to 3, characterized in that: In the second direction, at least one side of the first portion protrudes from the second portion.
10. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The distance between adjacent third parts is a first distance L1, and the distance between adjacent first parts is a second distance L2; The first distance L1 is greater than the second distance L2.
11. The semiconductor structure according to claim 10, characterized in that: The ratio of the first distance L1 to the second distance L2 is 1 to 1.
5.
12. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a dummy bit line structure, and the dummy bit line structure is arranged on one side of the bit line structure in the second direction; In the first direction, the third portion includes a first end and a second end that are oppositely disposed, and the first end is connected to the second portion; The dummy bit line structure is located in the first direction and at an end facing the third portion, at a connection between the first portion and the second portion of the bit line structure, or between the first end and the second end.
13. The semiconductor structure according to any one of claims 1 to 3, characterized in that: A first contact plug is disposed between the first portions of adjacent bit line structures; In the first direction, the first contact plug located at the outermost edge has a fourth distance L4 from the third portion of the bit line structure; and the first contact plug has a preset width W4; A ratio of the fourth distance L4 to the preset width W4 is greater than 4.