Semiconductor common unit structure, block structure, memory device structure and preparation method

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor common unit structure, a block structure, a memory device structure and a preparation method, the semiconductor common unit structure comprises a first memory unit and a second memory unit, the first memory unit and the second memory unit are distributed side by side in a mirroring manner along a first direction, the first storage unit and the second storage unit share the same source-drain unit layer, and the first direction is parallel to the surface of the substrate; each of the first memory unit and the second memory unit comprises a first transistor and a second transistor, and a fourth source-drain region of the second transistor in the first memory unit and a fourth source-drain region of the second transistor in the second memory unit are respectively connected to two opposite surfaces of the source-drain unit layer. The memory device structure disclosed by the invention is relatively high in memory density, relatively short in manufacturing process flow of the memory device structure and relatively low in manufacturing cost.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor common unit structure, a block structure, a storage device structure, and a preparation method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. Traditional DRAM storage cells usually include transistors and capacitors. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information is written into the capacitor. This structure needs to continuously refresh the charge in the capacitor to ensure that the data is not lost, and the charge in the capacitor needs to be released when reading, and then rewritten after the reading is completed, which consumes a lot of power. At the same time, due to the large area occupied by the manufacturing process of the capacitor, size miniaturization becomes a problem.

[0003] The two-transistor capacitorless dynamic random access memory (2Transistor 0Capacitor, 2T0C) uses two vertical structure transistors as the unit structure, where the drain of one transistor is connected to the gate of the other transistor, and the gate capacitance is used to store charge and change the transistor transconductance to store information. This structure can increase the storage density by continuously increasing the number of stacked layers in the vertical direction without reducing the critical size. However, each layer of devices needs to be completed before the next layer of devices can be made, which has a long process flow and high cost.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure provides a semiconductor common unit structure, a block structure, a storage device structure and a preparation method, which can simplify the process flow, reduce manufacturing costs and improve storage density.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor common unit structure, which is prepared on a substrate.

[0007] include:

[0008] a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit are arranged side by side in a mirror image along a first direction, the first storage unit and the second storage unit share a same source-drain unit layer, and the first direction is parallel to a surface of the substrate;

[0009] The first storage unit and the second storage unit both include:

[0010] a first transistor, located above the top surface of the substrate, the first transistor comprising: a first gate, a first gate dielectric layer and a first semiconductor layer, the first gate extending along the first direction, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, the first semiconductor layer covering the surface of the first gate dielectric layer, and the first semiconductor layer comprising a first source and drain region, a first channel region and a second source and drain region sequentially distributed along the first direction;

[0011] a second transistor, arranged side by side with the first transistor along the first direction, the second transistor comprising a second gate, a second gate dielectric layer and a second semiconductor layer, the second gate extending along the first direction, the second gate dielectric layer conformally covering the sidewall of the second gate and the end of the second gate away from the first transistor, the second semiconductor layer covering the surface of the second gate dielectric layer, and the second semiconductor layer comprising a third source and drain region, a second channel region and a fourth source and drain region sequentially arranged along the first direction; the second source and drain region is conductively connected to the second gate;

[0012] The fourth source-drain region in the first memory cell and the fourth source-drain region in the second memory cell are respectively connected to two opposite sides of the source-drain unit layer.

[0013] In an exemplary embodiment of the present disclosure, the plane where the source-drain unit layer is located is perpendicular to the first direction, and the source-drain unit layer includes a first conductive barrier layer, a conductive metal layer, and a second conductive barrier layer stacked in sequence along the first direction; the fourth source-drain region in the first storage unit is connected to the first conductive barrier layer, and the fourth source-drain region in the second storage unit is connected to the second conductive barrier layer.

[0014] In an exemplary embodiment of the present disclosure, the materials of the first conductive barrier layer and the second conductive barrier layer are both titanium nitride, and the material of the conductive metal layer is tungsten.

[0015] In an exemplary embodiment of the present disclosure, materials of the first gate and the second gate are both indium zinc oxide, and materials of the first semiconductor layer and the second semiconductor layer are both indium gallium zinc oxide.

[0016] According to one aspect of the present disclosure, there is provided a semiconductor common block structure, which is prepared on a substrate and includes:

[0017] A plurality of semiconductor common unit structures as described above located on the substrate, wherein the plurality of semiconductor common unit structures are arranged along a second direction and a third direction, wherein the second direction is parallel to the substrate and intersects with the first direction, and the third direction is perpendicular to the first direction and the second direction;

[0018] a plurality of word lines extending along the second direction and arranged along the first direction and the third direction, each of the word lines being connected to an end portion of a row of the first gate electrodes arranged along the second direction in the same plane and not covered by the first gate dielectric layer;

[0019] a plurality of first bit lines extending along the third direction and arranged along the first direction and the second direction, each of the first bit lines covering an outer periphery of a row of the first source and drain regions arranged along the third direction in the same plane;

[0020] a plurality of second bit lines extending along the third direction and arranged along the first direction and the second direction, each of the second bit lines covering an outer periphery of a row of the third source and drain regions arranged along the third direction in the same plane;

[0021] A source-drain layer is formed by sequentially connecting all the source-drain unit layers in the same plane end to end.

[0022] In an exemplary embodiment of the present disclosure, materials of the word line, the first bit line and the second bit line are all conductive materials, and the conductive materials are independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium and titanium nitride.

[0023] In an exemplary embodiment of the present disclosure, the word line, the first bit line and the second bit line each include a conductive barrier material layer and a metal material layer, the conductive barrier material layer is made of titanium nitride, and the metal material layer is made of tungsten.

[0024] According to one aspect of the present disclosure, there is provided a semiconductor memory device structure, comprising:

[0025] A substrate and a plurality of semiconductor common block structures as described above located on the substrate, wherein the plurality of semiconductor common block structures are arranged along the first direction;

[0026] Two adjacent semiconductor common block structures are arranged independently of each other.

[0027] According to one aspect of the present disclosure, a method for preparing a semiconductor memory device structure is provided, comprising the following steps:

[0028] providing a substrate;

[0029] Alternatingly depositing insulating material layers and semiconductor material layers on the substrate in sequence to form a stacked structure;

[0030] Performing patterning on the stacked structure to form a patterned stacked structure, wherein the pattern of the patterned stacked structure includes a plurality of first patterns extending along a first direction and spaced apart along a second direction, and a plurality of second patterns extending along the second direction and spaced apart along the first direction; the first direction is parallel to the surface of the substrate, the second direction is parallel to the substrate and intersects with the first direction; the first pattern overlaps with the second pattern;

[0031] A plurality of first openings are formed along a third direction penetrating the patterned stacked structure, the first openings being arranged in one-to-one correspondence with the second patterns, and the first openings divide the corresponding second pattern into two sub-patterns which are distributed side by side in a mirror image along the first direction; the third direction is perpendicular to the first direction and the second direction, and the first openings are parallel to the plane where the second direction and the third direction are located;

[0032] Part of the semiconductor material layer is etched away laterally toward both sides through the first opening to form a plurality of first transistor and word line accommodating grooves, wherein the first transistor and word line accommodating grooves include a row of first transistor accommodating grooves extending along the first direction and arranged along the second direction, and a word line accommodating groove extending along the second direction and connected to the row of first transistor accommodating grooves;

[0033] A first semiconductor layer, a first gate dielectric layer and a first gate material layer are sequentially deposited in the first transistor and word line accommodating groove; the first semiconductor layer covers the sidewall and bottom surface of the first transistor and word line accommodating groove, the first gate dielectric layer conformally covers the surface of the first semiconductor layer, and the first gate material layer fills the remaining space of the first transistor and word line accommodating groove;

[0034] The first gate material layer deposited in the word line accommodating groove is etched away to form a first gate of a first transistor, and then the word line accommodating groove is filled with word line material to form a word line and the first transistor located in the first transistor accommodating groove, wherein the word line is in contact with the first gate; the first transistor comprises the first gate, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, and the first semiconductor layer conformally covering the first gate dielectric layer, and the first semiconductor layer on the first gate comprises a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction;

[0035] forming a plurality of second openings penetrating the patterned stacked structure along the third direction, wherein the second openings are located at a middle position between two adjacent first openings, and the second openings are parallel to a plane where the second direction and the third direction are located;

[0036] Part of the insulating material layer is etched away laterally on both sides through the second opening to form a second gate of the second transistor, and then a second gate dielectric layer and a second semiconductor layer are deposited in sequence, wherein the second gate dielectric layer conformally covers the sidewall of the second gate and the end of the second gate away from the first transistor, the second semiconductor layer covers the surface of the second gate dielectric layer, and the second semiconductor layer includes a third source and drain region, a second channel region, and a fourth source and drain region sequentially distributed along the first direction;

[0037] Filling insulating material between adjacent second transistors to close the second opening; forming a plurality of third openings penetrating the insulating material along the third direction, wherein the third openings are located within the second openings and expose the fourth source and drain regions in the second transistors, and the third openings are parallel to the second direction and the plane where the third direction is located;

[0038] forming a source-drain layer in the third opening;

[0039] A plurality of first bit line accommodating holes and second bit line accommodating holes extending along the third direction are formed, a first bit line is formed in the first bit line accommodating hole, and a second bit line is formed in the second bit line accommodating hole; each of the first bit lines is coated on the periphery of a row of the first source and drain regions arranged in the same plane along the third direction, and each of the second bit lines is coated on the periphery of a row of the third source and drain regions arranged in the same plane along the third direction.

[0040] In an exemplary embodiment of the present disclosure, before the step of forming a plurality of first openings penetrating the patterned stacked structure along the third direction, the method further includes:

[0041] The gaps in the patterned stacked structure are filled with insulating material.

[0042] In an exemplary embodiment of the present disclosure, after forming the word line and before forming the second opening, the method further includes:

[0043] The first opening is filled with insulating material.

[0044] In an exemplary embodiment of the present disclosure, forming a source-drain layer in the third opening includes:

[0045] forming a conductive barrier layer conformally covering the inner wall and bottom of the third opening;

[0046] A conductive metal layer is deposited in the third opening, and the conductive metal layer fills the remaining space of the third opening.

[0047] In the semiconductor shared unit structure disclosed in the present invention, the first storage unit and the second storage unit can be distributed laterally on the substrate surface in a direction parallel to the substrate. During the manufacturing process, the first storage unit and the second storage unit can be formed at the same time. In this process, there is no need to wait for the first storage unit to be manufactured before forming the second storage unit. The manufacturing process is short and the manufacturing cost is low. Since the first storage unit and the second storage unit share the same source-drain unit layer, the signal paths and conditions received by the two are consistent, which helps to reduce the reading errors and data inconsistency caused by signal transmission differences; it can also reduce the area of ​​the region where the first storage unit and the second storage unit are located, improve the device integration, and thus improve the storage density of the memory.

[0048] In the semiconductor common block structure disclosed in the present invention, in each layer, the word line corresponding to the first storage unit and the word line corresponding to the second storage unit extend along the second direction and are arranged along the first direction, so that the semiconductor common block structure is stacked along the first direction, maximizing the utilization of the substrate area and increasing the storage density.

[0049] The storage device structure disclosed in the present invention is a dual-transistor capacitor-free dynamic random access memory. The two transistors in the storage unit are located above the substrate and are arranged horizontally. The channel is parallel to the substrate direction. The storage density is increased by vertical stacking. Compared with the existing vertical structure dual-transistor capacitor-free dynamic random access memory that increases the storage density by vertical stacking, the height of each layer in the storage device structure disclosed in the present invention is greatly reduced, and the storage density is higher.

[0050] Compared with the preparation method of the existing vertical structure dual transistor capacitor-free dynamic random access memory which needs to prepare the storage function layer layer by layer to achieve vertical stacking and increase the storage density, the preparation method of the semiconductor memory device structure disclosed in the present invention prepares all the vertical stacking layers at the same time; compared with the preparation method of the existing vertical structure dual transistor capacitor-free dynamic random access memory in which the write bit line layer and the read bit line layer are formed separately, the preparation method of the semiconductor memory device structure disclosed in the present invention prepares all the first bit lines and the second bit lines at the same time; compared with the word line layer of the existing vertical structure dual transistor capacitor-free dynamic random access memory in which the storage function layer is prepared layer by layer, all the word lines in the preparation method of the semiconductor memory device structure disclosed in the present invention are also prepared at the same time. Therefore, the preparation method of the semiconductor memory device structure disclosed in the present invention has a shorter process flow and lower manufacturing cost.

[0051] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0053] Figure 1 Schematic diagram of a semiconductor shared unit structure in an embodiment of the present disclosure.

[0054] Figure 2 Schematic diagram of a semiconductor common block structure in an embodiment of the present disclosure.

[0055] Figure 3 is an equivalent circuit diagram of the semiconductor common block structure in the embodiment of the present disclosure.

[0056] Figure 4 Schematic diagram of the structure of a semiconductor memory device in an embodiment of the present disclosure.

[0057] Figure 5 It is a schematic diagram of a substrate, a stacked structure, a protective layer, a first mask layer and a development pattern in an embodiment of the present disclosure.

[0058] Figure 6 Schematic diagram of a patterned stacked structure in an embodiment of the present disclosure.

[0059] Figure 7 It is a schematic diagram of the structure after completing step S4 in the embodiment of the present disclosure.

[0060] Figure 8 It is a schematic diagram of the structure after completing step S210 in the embodiment of the present disclosure.

[0061] Fig. 9 FIG. 4 is a schematic diagram of a second mask layer and a second photoresist layer in an embodiment of the present disclosure.

[0062] Fig.10 It is a schematic diagram of the structure after completing step S5 in the embodiment of the present disclosure.

[0063] Fig.11 In the embodiment of the present disclosure, Fig.10 Cross-sectional view taken along the AA direction.

[0064] Fig.12 for Fig.11 The structure in FIG. 1 is a schematic diagram of completing the first semiconductor layer, the first gate dielectric layer and the first gate material layer.

[0065] Fig.13 for Fig.12 The structure in FIG. 1 is a schematic diagram of the structure after completing step S6.

[0066] Fig.14 for Fig.13 The structure in FIG. 1 is a schematic diagram of the structure after completing step S7.

[0067] Fig.15 It is a schematic diagram of the structure after completing step S220 in the embodiment of the present disclosure.

[0068] Fig.16 It is a schematic diagram of the structure after completing step S8 in the embodiment of the present disclosure.

[0069] Fig.17 It is a schematic diagram of an embodiment of the present disclosure after a portion of the insulating material layer is etched away laterally toward both sides through the second opening.

[0070] Fig.18 For along Fig.17 The cross-sectional structure taken along the AA direction is a schematic diagram of the second gate dielectric layer and the second semiconductor layer.

[0071] Fig.19 for Fig.18 Schematic diagram of the structure in which the space between adjacent second transistors is filled with insulating material.

[0072] Fig. 20 for Fig.19 The structure in FIG. 1 is a schematic diagram of the structure after completing step S10.

[0073] Fig.21 for Fig. 20 The structure in FIG. 1 is a schematic diagram of the structure after completing step S11.

[0074] Fig. 22 FIG. 4 is a schematic diagram of a first bit line accommodating hole and a second bit line accommodating hole in an embodiment of the present disclosure.

[0075] Fig.23 In the embodiment of the present disclosure, Fig. 22 Cross-section view cut by the dashed line.

[0076] Fig.24 It is a schematic diagram of the structure after completing step S12 in the embodiment of the present disclosure.

[0077] Description of reference numerals:

[0078] 1. substrate; 2. first storage unit; 3. second storage unit; 4. source-drain layer; 410. source-drain unit layer; 41. first conductive barrier layer; 42. conductive metal layer; 43. second conductive barrier layer; 10. first transistor; 101. first gate; 1011. first gate material layer; 102. first gate dielectric layer; 103. first semiconductor layer; 20. second transistor; 201. second gate; 202. second gate dielectric layer; 203. second semiconductor layer; 5. word line; 51. conductive barrier material layer; 52. metal material layer; 6. first bit line; 601. first bit line receiving hole; 7. second bit line ;701, second bit line accommodating hole;8, insulating material;81, third opening;9, protective layer;30, stacked structure;301, insulating material layer;302, semiconductor material layer;40, patterned stacked structure;401, first pattern;402, second pattern;4021, sub-pattern;403, first opening;404, first transistor accommodating groove;405, word line accommodating groove;406, second opening;50, developing pattern;60, second photoresist layer;6001, first developing area;100, first mask layer;200, second mask layer;x, first direction;y, second direction;z, third direction. DETAILED DESCRIPTION

[0079] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0080] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0081] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", "third" and "fourth" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0082] With the rapid development of the semiconductor industry, the storage density requirements for memory are increasing. However, the traditional 1T1C (i.e., one transistor and one capacitor) structure faces severe challenges in improving storage density. The reduction of its key dimensions is limited by the lithography capability limit of the lithography machine, and it is difficult to continue to shrink. At the same time, it is difficult to achieve three-dimensional stacking in the 1T1C structure, and the improvement of storage density is therefore severely restricted by the key dimensions. In order to break through this bottleneck, those skilled in the art will turn their research focus to the 2T0C (i.e., two transistors, no capacitor) structure. In the existing vertically structured 2T0C DRAM memory, the transistor channel in the storage unit is perpendicular to the substrate, and a significant improvement in storage density is achieved by stacking the storage functional layers in sequence. However, the structural process flow of the sequentially stacked storage functional layers is long and the manufacturing cost is high.

[0083] Based on this, an embodiment of the present disclosure provides a semiconductor common unit structure, which is prepared on a substrate. Figure 1 A schematic diagram of a semiconductor common unit structure disclosed in the present invention is shown, Figure 1 As shown, the semiconductor shared unit structure includes a first storage unit 2 and a second storage unit 3, the first storage unit 2 and the second storage unit 3 are arranged side by side in a mirror image along a first direction x, the first storage unit 2 and the second storage unit 3 share the same source-drain unit layer 410, and the first direction x is parallel to the surface of the substrate;

[0084] The first storage unit 2 and the second storage unit 3 both include a first transistor 10 and a second transistor 20.

[0085] in:

[0086] The first transistor 10 is located above the top surface of the substrate, and the first transistor 10 includes: a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103, the first gate 101 extends along a first direction x, the first gate dielectric layer 102 conformally covers the sidewall and one end of the first gate 101, the first semiconductor layer 103 covers the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 includes a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction x;

[0087] The second transistor 20 and the first transistor 10 are arranged side by side along the first direction x, the second transistor 20 comprises a second gate 201, a second gate dielectric layer 202 and a second semiconductor layer 203, the second gate 201 extends along the first direction x, the second gate dielectric layer 202 conformally covers the sidewall of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 comprises a third source and drain region, a second channel region and a fourth source and drain region sequentially arranged along the first direction x; the second source and drain region is conductively connected to the second gate 201;

[0088] The fourth source-drain region in the first memory cell 2 and the fourth source-drain region in the second memory cell 3 are respectively connected to two opposite surfaces of the source-drain unit layer 410 .

[0089] In the semiconductor shared unit structure disclosed in the present invention, the first storage unit 2 and the second storage unit 3 can be distributed laterally on the surface of the substrate 1 in a direction parallel to the substrate 1. During the manufacturing process, the first storage unit 2 and the second storage unit 3 can be formed at the same time. In this process, there is no need to wait for the first storage unit 2 to be manufactured before forming the second storage unit 3. The manufacturing process is short and the manufacturing cost is low. At the same time, since the first storage unit 2 and the second storage unit 3 share the same source-drain unit layer 410, the signal paths and conditions received by the two are consistent, which helps to reduce the reading errors and data inconsistency caused by differences in signal transmission; it can also reduce the area of ​​the region where the first storage unit 2 and the second storage unit 3 are located, improve the device integration, and thus improve the storage density of the memory.

[0090] The following is a detailed description of the various parts and specific details of the semiconductor common unit structure disclosed in the present invention:

[0091] The substrate (not shown in the figure) may be a flat plate structure, for example, it may be a flat plate structure. The substrate may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but it is not limited to silicon or other semiconductor materials, and the shape and material of the substrate are not particularly limited here.

[0092] The first memory cell 2 and the second memory cell 3 may be formed on a substrate, and both the first memory cell 2 and the second memory cell 3 may be 2T0C (i.e., including two transistors and no capacitor) structures, and the first memory cell 2 and the second memory cell 3 may be distributed side by side in a mirror image along the first direction x, and the first memory cell 2 and the second memory cell 3 may share the same source-drain unit layer 410, which may reduce the area of ​​the region where the first memory cell 2 and the second memory cell 3 are located, improve the device integration, and thus improve the storage density of the memory. In an exemplary embodiment of the present disclosure, the first direction x may be parallel to the surface of the substrate.

[0093] In an exemplary embodiment of the present disclosure, the first storage unit 2 and the second storage unit 3 each include a first transistor 10 and a second transistor 20, wherein:

[0094] The first transistor 10 is located above the top surface of the substrate. The first transistor 10 may be a CAA (Channel-All-Around) structure transistor, and the channel is parallel to the plane where the substrate is located, and may extend along the first direction x. Figure 1 As shown, the first transistor 10 may include: a first gate 101, a first gate dielectric layer 102 and a first semiconductor layer 103. The first gate 101 may be in a strip shape and may extend along a first direction x. The material of the first gate 101 may be a conductive material, for example, the material of the first gate 101 may be indium zinc oxide (IZO) or polysilicon. The first gate dielectric layer 102 may conformally cover the sidewall and one end of the first gate 101. The material of the first gate dielectric layer 102 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. Of course, it may also be other materials, which are not listed here one by one. The first semiconductor layer 103 may conformally cover the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 may include a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction x, wherein the first source and drain region is located on a side of the first channel region away from the source and drain unit layer 410, and the second source and drain region is located on a side of the first channel region close to the source and drain unit layer 410. The material of the first semiconductor layer 103 and the material of the first gate 101 may be matched with each other; for example, when the material of the first gate 101 is indium zinc oxide (IZO), the material of the first semiconductor layer 103 may be indium gallium zinc oxide (IGZO); when the material of the first gate 101 is polycrystalline silicon, the material of the first semiconductor layer 103 may be single crystal silicon.

[0095] Optionally, the material of the first semiconductor layer 103 of the present invention is indium gallium zinc oxide (IGZO). Compared with the traditional method of using single crystal silicon as the material of the first semiconductor layer 103, the present invention uses indium gallium zinc oxide (IGZO) as the material of the first semiconductor layer 103. This is because the off-state current of the IGZO thin film transistor (Thin Film Transistor-TFT) is extremely small, and its use in 2T0C DRAM storage cells can significantly reduce the leakage rate, help reduce device power consumption, and improve device reliability.

[0096] The second transistor 20 may also be located above the top surface of the substrate. The second transistor 20 may be a CAA structure transistor and the channel is parallel to the plane where the substrate is located, and may extend along the first direction x. The second transistor 20 may be arranged side by side with the first transistor 10 along the first direction x, that is, the second transistor 20 and the first transistor 10 are laterally distributed on the surface of the substrate. The second transistor 20 may include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 may be in a strip shape and may extend along the first direction x. For example, the second gate 201 and the first gate 101 may be arranged in sequence along the first direction x. The material of the second gate 201 may be a conductive material, for example, it may be indium zinc oxide (IZO) or polysilicon. In some embodiments of the present disclosure, the material of the second gate 201 is the same as that of the first gate 101. For example, the materials of the second gate 201 and the first gate 101 may both be indium zinc oxide (IZO). The second gate dielectric layer 202 can conformally cover the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10. The material of the second gate dielectric layer 202 can be a material with a high dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof, and of course, it can also be other materials, which are not listed here. It should be noted that the material of the second gate dielectric layer 202 can be the same as that of the first gate dielectric layer 102. The second semiconductor layer 203 may conformally cover the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source-drain region, a second channel region, and a fourth source-drain region sequentially distributed along the first direction x, wherein the third source-drain region is located on a side of the second channel region away from the source-drain unit layer 410, and the fourth source-drain region is located on a side of the second channel region close to the source-drain unit layer 410; the material of the second semiconductor layer 203 and the material of the second gate 201 may be matched with each other; for example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 may be indium gallium zinc oxide (IGZO); when the material of the second gate 201 is polycrystalline silicon, the material of the second semiconductor layer 203 may be single crystal silicon. In some embodiments of the present disclosure, the material of the second semiconductor layer 203 may be the same as that of the first semiconductor layer 103, for example, the material of the second semiconductor layer 203 and the material of the first semiconductor layer 103 may both be indium gallium zinc oxide.

[0097] In an exemplary embodiment of the present disclosure, the first transistor 10 may be a write transistor, the second transistor 20 may be a read transistor, the second source and drain region of the first transistor 10 is electrically connected to the second gate 201 of the second transistor 20, and the charge in the gate capacitance of the second transistor 20 (i.e., the read transistor) is changed by the first transistor 10 (i.e., the write transistor), thereby affecting the resistance state between the source and drain of the second transistor 20 (i.e., the read transistor), thereby achieving the distinction between "0" and "1", and the specific principle is as follows:

[0098] In the process of writing "1", a positive voltage (greater than the threshold voltage Vth) is added to the write word line WWL to turn on the first transistor 10 (i.e., the write transistor), and a positive voltage is added to the write bit line WBL to inject charge into the gate capacitance (i.e., the storage node) of the second transistor 20 (i.e., the read transistor); after the charge injection, the positive voltage applied to the write word line WWL and the positive voltage applied to the write bit line WBL are removed to save the "1" state. In the process of reading "1", a read voltage is added to the drain of the second transistor 20 (i.e., the read transistor). Since there is a certain charge stored in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a relatively low resistance state, and a relatively large current is obtained, which is then amplified and identified by the peripheral circuit to complete the process of reading "1". In the process of writing "0", a positive voltage (greater than the threshold voltage Vth) is added to the write word line WWL to turn on the first transistor 10 (i.e., the write transistor), and a negative voltage is added to the write bit line WBL to extract charge from the gate capacitance (i.e., the storage node) of the second transistor 20 (i.e., the read transistor); after the charge is extracted, the positive voltage applied to the write word line WWL and the negative voltage applied to the write bit line WBL are removed to save the "0" state. In the process of reading "0", a read voltage is added to the drain of the second transistor 20 (i.e., the read transistor). Since there is no charge in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a higher resistance state, and a smaller current is obtained, which is then amplified and identified by the peripheral circuit to complete the process of reading "0".

[0099] In an exemplary embodiment of the present disclosure, the source-drain unit layer 410 may extend in a direction perpendicular to the substrate, that is, the plane where the source-drain unit layer 410 is located is perpendicular to the first direction x, and the fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 are respectively connected to two opposite surfaces of the source-drain unit layer 410 distributed along the first direction x. Such a design can ensure that the signal paths and conditions received by the first storage unit 2 and the second storage unit 3 are consistent, which helps to reduce reading errors and data inconsistencies caused by differences in signal transmission.

[0100] In some embodiments of the present disclosure, please continue to refer to Figure 1 As shown, the source-drain unit layer 410 may include a first conductive barrier layer 41, a conductive metal layer 42, and a second conductive barrier layer 43 sequentially stacked along a first direction x, that is, the first conductive barrier layer 41, the conductive metal layer 42, and the second conductive barrier layer 43 form a sandwich structure. The fourth source-drain region in the first memory cell 2 may be in contact with and connected to a surface of the first conductive barrier layer 41 away from the conductive metal layer 42, and the fourth source-drain region in the second memory cell 3 may be in contact with and connected to a surface of the second conductive barrier layer 43 away from the conductive metal layer 42.

[0101] The material of the conductive metal layer 42 may be a metal material with good conductivity, for example, it may be tungsten. The material of the first conductive barrier layer 41 may be a conductive material with ion blocking function, and the material of the second conductive barrier layer 43 may also be a conductive material with ion blocking function, for example, the materials of the first conductive barrier layer 41 and the second conductive barrier layer 43 may both be titanium nitride. The first conductive barrier layer 41 and the second conductive barrier layer 43 may prevent the metal ions in the conductive metal layer 42 from diffusing into other surrounding structures, which helps to reduce the probability of coupling or short circuit between the source-drain unit layer 410 and other structures, and improve the reliability of the device.

[0102] The present disclosure also provides a semiconductor common block structure, Figure 2 A schematic diagram of a semiconductor common block structure disclosed in the present invention is shown, Figure 2 As shown, the semiconductor common block structure can be prepared on a substrate 1, and the semiconductor common block structure may include a plurality of semiconductor common unit structures in any of the above embodiments, a plurality of word lines 5, a plurality of first bit lines 6, a plurality of second bit lines 7, and a source-drain layer 4 located on the substrate 1, wherein:

[0103] The plurality of semiconductor common unit structures are arranged along a second direction y and a third direction z, wherein the second direction y is parallel to the substrate 1 and intersects with the first direction x, and the third direction z is perpendicular to the first direction x and the second direction y;

[0104] A plurality of word lines 5 extend along the second direction y and are arranged along the first direction x and the third direction z, and each word line 5 is connected to an end portion of a row of first gate electrodes 101 arranged along the second direction y in the same plane and not covered by the first gate dielectric layer 102;

[0105] A plurality of first bit lines 6 extend along a third direction z and are arranged along a first direction x and a second direction y, and each first bit line 6 covers an outer periphery of a row of first source and drain regions arranged along the third direction z in the same plane;

[0106] A plurality of second bit lines 7 extend along the third direction z and are arranged along the first direction x and the second direction y, and each second bit line 7 covers the periphery of a row of third source and drain regions arranged along the third direction z in the same plane;

[0107] A source-drain layer 4 is formed by connecting all source-drain unit layers 410 in the same plane end to end in sequence.

[0108] In the semiconductor shared block structure disclosed in the present invention, a plurality of memory cells (e.g., first memory cells 2 or second memory cells 3) arranged along the second direction y can share the same word line 5, a plurality of first memory cells 2 arranged along the third direction z can share the same first bit line 6, and a plurality of second memory cells 3 arranged along the third direction z can share the same second bit line 7. Selecting a word line 5 and a first bit line 6 can select a first transistor 10 (i.e., a write transistor). By sharing the same word line 5, first bit line 6, and second bit line 7, the number of metal interconnects is reduced, so that more memory cells can be accommodated in the same area, which not only improves the physical storage density of the memory, but also reduces the parasitic capacitance and resistance between the connection lines, which helps to reduce power consumption. At the same time, since the number of metal interconnects is reduced, the steps of photolithography, etching, etc. in the manufacturing process are simplified, which helps to reduce production complexity and cost.

[0109] The following is a detailed description of the various parts and specific details of the semiconductor common block structure disclosed in the present invention:

[0110] like Figure 2 As shown, multiple semiconductor common unit structures can be arranged along the second direction y and the third direction z. For example, multiple semiconductor common unit structures can form multiple common unit structure groups arranged along the third direction z, and each common unit structure group can include multiple semiconductor common unit structures arranged along the second direction y.

[0111] The second direction y is parallel to the substrate 1 and intersects with the first direction x. For example, the second direction y may be perpendicular to the first direction x, and the third direction z is perpendicular to the first direction x and the second direction y. It should be noted that parallel can be absolutely parallel or approximately parallel; similarly, perpendicular can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable in the manufacturing process. In the present disclosure, the angle deviation may be caused by the limitation of the manufacturing process, so that the angle between the first direction x (or the second direction y) and the surface of the substrate 1 has a certain deviation, or the angle between the third direction z and the first direction x (or the second direction y) shows a certain deviation. As long as the angle deviation is within the preset range, the first direction x (or the second direction y) can be considered to be parallel to the substrate 1; or, the third direction z can be considered to be perpendicular to the first direction x (or the second direction y). For example, the preset range may be 10°, that is, when the angle between the first direction x (or the second direction y) and the surface of the substrate 1 is less than or equal to 10°, the first direction x (or the second direction y) may be considered to be parallel to the surface of the substrate 1; when the angle between the third direction z and the first direction x (or the second direction y) is greater than or equal to 80° and less than or equal to 100°, the third direction z may be considered to be perpendicular to the first direction x (or the second direction y).

[0112] The word line 5 may be in a strip shape and may extend along the second direction y. Each common cell structure group may include two word lines 5, and the two word lines 5 may be spaced apart along the first direction x, wherein one word line 5 may be in contact with and connected to all ends of a row of first gate electrodes 101 arranged along the second direction y in all first storage cells 2 in the same common cell structure group that are not covered by the first gate dielectric layer 102; the other word line 5 may be in contact with and connected to all ends of a row of first gate electrodes 101 arranged along the second direction y in all second storage cells 3 in the same common cell structure group that are not covered by the first gate dielectric layer 102. The word lines 5 connected to the first storage cells 2 in a plurality of common cell structure groups arranged along the third direction z may be spaced apart along the third direction z.

[0113] Please continue to see Figure 2 As shown, the first bit line 6 may be in a strip shape and may extend along the third direction z. The semiconductor common block structure disclosed in the present invention may include a plurality of bit line groups spaced apart along the second direction y, each bit line group may include two first bit lines 6, and the two first bit lines 6 may be spaced apart along the first direction x, wherein one first bit line 6 may be wrapped around the periphery of a row of first source and drain regions arranged along the third direction z in each first storage unit 2 in a plurality of common unit structure groups arranged along the third direction z; another first bit line 6 may be wrapped around the periphery of a row of first source and drain regions arranged along the third direction z in each second storage unit 3 in a plurality of common unit structure groups arranged along the third direction z. It should be noted that different semiconductor common unit structures arranged along the second direction y are respectively provided with a corresponding bit line group, and each first bit line 6 in different bit line groups may be spaced apart and distributed in parallel along the second direction y.

[0114] Please continue to see Figure 2 As shown, the second bit line 7 may be in a strip shape and may extend along the third direction z. Each bit line group may include two second bit lines 7, and the two second bit lines 7 may be spaced apart along the first direction x, wherein one second bit line 7 may be wrapped around the periphery of a row of third source and drain regions arranged along the third direction z in each first storage unit 2 in a plurality of shared unit structure groups arranged along the third direction z; the other second bit line 7 may be wrapped around the periphery of a row of third source and drain regions arranged along the third direction z in each second storage unit 3 in a plurality of shared unit structure groups arranged along the third direction z. It should be noted that each second bit line 7 in different bit line groups may be spaced apart and distributed in parallel along the second direction y.

[0115] In an exemplary embodiment of the present disclosure, the materials of the word line 5, the first bit line 6 and the second bit line 7 are all conductive materials, and the conductive materials can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium and titanium nitride. For example, the word line 5, the first bit line 6 and the second bit line 7 can all include a conductive barrier material layer and a metal material layer; taking the word line 5 as an example, the metal material layer can be strip-shaped and extend along the second direction y, and the conductive barrier material layer can at least conformally cover the upper surface, the lower surface and the surface of the metal material layer close to the first gate 101 in the metal material layer that are distributed in the third direction z, that is, the first gate 101 is in contact with the conductive barrier material layer in the word line 5, and the conductive barrier material layer can prevent the metal ions in the metal material layer from diffusing into other surrounding structures, which helps to reduce the risk of short circuit or coupling and improve the reliability of the device. In some embodiments of the present disclosure, the material of the conductive barrier material layer can be titanium nitride, and the material of the metal material layer can be tungsten, and the titanium nitride can be used to prevent the tungsten ions from diffusing into the first gate 101.

[0116] In an exemplary embodiment of the present disclosure, Figure 2 and Figure 3 As shown, all source-drain unit layers 410 located in the same plane in the multiple semiconductor shared unit structures are connected end to end in sequence to form a source-drain layer 4. The specific details and beneficial effects of the source-drain layer 4 have been described in detail in the corresponding embodiment of the semiconductor shared unit structure, so they are not repeated here. It should be noted that the two first bit lines 6 in the same bit line group are distributed along the source-drain layer 4 in a mirror-symmetrical manner, and the two second bit lines 7 in the same bit line group are distributed along the source-drain layer 4 in a mirror-symmetrical manner; at the same time, the two word lines 5 in the same shared unit structure group are distributed along the source-drain layer 4 in a mirror-symmetrical manner.

[0117] The present disclosure also provides a semiconductor memory device structure, such as Figure 4 As shown, the semiconductor memory device structure includes a substrate 1 and a plurality of semiconductor common block structures as in any of the above embodiments located on the substrate 1, wherein the plurality of semiconductor common block structures are arranged along a first direction x; and two adjacent semiconductor common block structures are independently arranged. For example, adjacent semiconductor common block structures in the semiconductor memory device structure are spaced apart. Other details and beneficial effects of the semiconductor memory device structure disclosed in the present invention have been described in detail in the embodiments of the corresponding semiconductor common block structure and semiconductor common unit structure, and therefore, will not be repeated here.

[0118] A semiconductor common block structure is defined to include two semiconductor storage block structures distributed in a mirror-symmetrical manner along the source-drain layer 4: a first semiconductor storage block structure and a second semiconductor storage block structure, wherein the first semiconductor storage block structure and the second semiconductor storage block structure share a source-drain layer.

[0119] The specific reading and writing principles of the semiconductor memory device structure provided by the present disclosure are as follows:

[0120] When writing: selecting a word line 5 and a first bit line 6 can select a storage unit (including a first transistor 10 (i.e., a write transistor) and a second transistor 10 (i.e., a read transistor)), and by applying voltages to the selected word line 5 and the selected first bit line 6 respectively to turn on the first transistor 10 (i.e., the write transistor), charge can be injected into or extracted from the gate capacitance of the second transistor 10 (i.e., the read transistor), thereby realizing a write operation.

[0121] When reading: when a storage unit (including a first transistor 10 (i.e., a write transistor) and a second transistor 10 (i.e., a read transistor)) is selected for reading, all first transistors 10 in the semiconductor storage block structure where the selected storage unit is located are turned on except for the first transistor 10 corresponding to the selected storage unit, and charges are extracted from the gate capacitances of all second transistors 10 (i.e., read transistors) except the selected storage unit, and then all first transistors 10 (i.e., write transistors) are turned off; a read voltage is applied to a second bit line 7 and a source-drain layer 4 corresponding to the selected storage unit to implement the read operation of the selected storage unit.

[0122] It should be understood that after each read operation, a refresh operation needs to be performed on the semiconductor memory block structure where the selected memory cell is located to restore the storage data of the semiconductor memory block structure before the read operation.

[0123] The storage device structure disclosed in the present invention is a dual-transistor capacitor-free dynamic random access memory. The two transistors in the storage unit are located above the substrate and are arranged horizontally. The channel is parallel to the substrate direction. The storage density is increased by vertical stacking. Compared with the existing vertical structure dual-transistor capacitor-free dynamic random access memory that increases the storage density by vertical stacking, the height of each layer in the storage device structure disclosed in the present invention is greatly reduced, and the storage density is higher.

[0124] The present disclosure also provides a method for preparing a semiconductor memory device structure, which is used to form the semiconductor memory device structure in any of the above embodiments. The preparation method may include steps S1 to S12, wherein:

[0125] Step S1, providing a substrate 1;

[0126] Step S2, alternately depositing insulating material layers 301 and semiconductor material layers 302 on the substrate 1 in sequence to form a stacked structure 30;

[0127] Step S3, patterning the stacked structure 30 to form a patterned stacked structure 40, wherein the pattern of the patterned stacked structure 40 includes a plurality of first patterns 401 extending along the first direction x and spaced apart along the second direction y, and a plurality of second patterns 402 extending along the second direction y and spaced apart along the first direction x; the first direction x is parallel to the surface of the substrate 1, and the second direction y is parallel to the substrate 1 and intersects with the first direction x; the first pattern 401 overlaps with the second pattern 402;

[0128] Step S4, forming a plurality of first openings 403 penetrating the patterned stacked structure 40 along a third direction z, wherein the first openings 403 are arranged in one-to-one correspondence with the second patterns 402, and the first openings 403 divide the corresponding second pattern 402 into two sub-patterns 4021 that are mirror-imaged and arranged side by side along the first direction x; the third direction z is perpendicular to the first direction x and the second direction y, and the first openings 403 are parallel to the plane where the second direction y and the third direction z are located;

[0129] Step S5, etching away a portion of the semiconductor material layer 302 laterally toward both sides through the first opening 403 to form a plurality of first transistors 10 and word line accommodating grooves 405, wherein the first transistors 10 and word line accommodating grooves 405 include a row of first transistor accommodating grooves 404 extending along the first direction x and arranged along the second direction y, and a word line accommodating groove 405 extending along the second direction y and connecting the row of first transistor accommodating grooves 404;

[0130] Step S6, depositing the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer 1011 in sequence in the first transistor 10 and the word line accommodating groove 405; the first semiconductor layer 103 covers the sidewall and bottom surface of the first transistor 10 and the word line accommodating groove 405, the first gate dielectric layer 102 conformally covers the surface of the first semiconductor layer 103, and the first gate material layer 1011 fills the remaining space of the first transistor 10 and the word line accommodating groove 405;

[0131] Step S7, etching away the first gate material layer 1011 deposited in the word line accommodating groove 405 to form the first gate 101 of the first transistor 10, and then filling the word line accommodating groove 405 with word line 5 material to form word line 5 and form the first transistor 10 located in the first transistor accommodating groove 404, the word line 5 is in contact with the first gate 101; the first transistor 10 includes a first gate 101, a first gate dielectric layer 102 conformally covering the sidewall and one end of the first gate 101, and a first semiconductor layer 103 conformally covering the first gate dielectric layer 102, the first semiconductor layer 103 includes a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction x;

[0132] Step S8, forming a plurality of second openings 406 penetrating the patterned stacked structure 40 along the third direction z, wherein the second openings 406 are located in the middle between two adjacent first openings 403, and the second openings 406 are parallel to the plane where the second direction y and the third direction z are located;

[0133] Step S9, etching away a portion of the insulating material layer 301 laterally toward both sides through the second opening 406 to form a second gate 201 of the second transistor 20, and then sequentially depositing a second gate dielectric layer 202 and a second semiconductor layer 203, wherein the second gate dielectric layer 202 conformally covers the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10, and the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source and drain region, a second channel region, and a fourth source and drain region sequentially distributed along the first direction x;

[0134] Step S10, filling the insulating material 8 between adjacent second transistors 20 to close the second opening 406; forming a plurality of third openings 81 penetrating the insulating material 8 along the third direction z, the third openings 81 being located inside the second openings 406, and the third openings 81 exposing the fourth source and drain regions in the second transistor 20, and the third openings 81 being parallel to the plane where the second direction y and the third direction z are located;

[0135] Step S11, forming a source-drain layer 4 in the third opening 81;

[0136] Step S12, forming a plurality of first bit line accommodating holes 601 and second bit line accommodating holes 701 extending along a third direction z, forming a first bit line 6 in the first position accommodating hole, and forming a second bit line 7 in the second bit line accommodating hole 701; each first bit line 6 is coated on the periphery of a row of first source and drain regions arranged along the third direction z in the same plane, and each second bit line 7 is coated on the periphery of a row of third source and drain regions arranged along the third direction z in the same plane.

[0137] Compared to the existing vertical structure dual transistor capacitor-free dynamic random access memory preparation method that needs to prepare the storage function layer layer by layer to achieve vertical stacking and increase storage density, in the preparation method of the semiconductor memory device structure disclosed in the present invention, all vertical stacking layers are prepared at the same time; compared to the preparation method in which the write bit line layer and the read bit line layer are formed separately in the existing vertical structure dual transistor capacitor-free dynamic random access memory, in the preparation method of the semiconductor memory device structure disclosed in the present invention, all first bit lines and second bit lines are prepared at the same time; compared to the existing vertical structure dual transistor capacitor-free dynamic random access memory, in which the word line layer of the storage function layer is prepared layer by layer, in the preparation method of the semiconductor memory device structure disclosed in the present invention, all word lines are also prepared at the same time. Therefore, the preparation method of the semiconductor memory device structure disclosed in the present invention has a shorter process flow and lower manufacturing cost.

[0138] The steps and specific details of the method for preparing the semiconductor memory device structure disclosed in the present invention are described in detail below:

[0139] In step S1 , a substrate 1 is provided.

[0140] like Figure 5 As shown, the substrate 1 may be a flat plate structure, for example, it may be a flat plate structure. The substrate 1 may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not particularly limited here.

[0141] In step S2 , insulating material layers 301 and semiconductor material layers 302 are alternately deposited on the substrate 1 in sequence to form a stacked structure 30 .

[0142] Please continue to refer to Figure 2, the stacked structure 30 may include multiple insulating material layers 301 and multiple semiconductor material layers 302, and the multiple insulating material layers 301 and the multiple semiconductor material layers 302 may be alternately distributed in a direction perpendicular to the substrate 1 (i.e., the third direction z). In an exemplary embodiment of the present disclosure, the material of the insulating material layer 301 may be silicon oxide, and the material of the semiconductor material layer 302 may be indium zinc oxide (IZO). The insulating material layer 301 and the semiconductor material layer 302 may be alternately deposited on the substrate 1 in sequence by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that the film layer in contact with the substrate 1 in the stacked structure 30 is the insulating material layer 301, and at the same time, the film layer farthest from the substrate 1 in the stacked structure 30 is also the insulating material layer 301.

[0143] In an exemplary embodiment of the present disclosure, after forming the stacked structure 30, a protective layer 9 may be formed on the surface of the stacked structure 30, and the protective layer 9 may prevent the insulating material layer 301 at the top of the stacked structure 30 from being damaged during subsequent etching. The material of the protective layer 9 is different from that of the insulating material layer 301, and the material thereof may be silicon nitride.

[0144] In step S3, the stacking structure 30 is patterned to form a patterned stacking structure 40, and the pattern of the patterned stacking structure 40 includes a plurality of first patterns 401 extending along a first direction x and spaced apart along a second direction y, and a plurality of second patterns 402 extending along the second direction y and spaced apart along the first direction x; the first direction x is parallel to the surface of the substrate 1, and the second direction y is parallel to the substrate 1 and intersects with the first direction x; the first pattern 401 overlaps with the second pattern 402.

[0145] The stacked structure 30 can be patterned by etching. Figure 4 As shown, a first mask layer 100 may be formed on a side of the stacked structure 30 away from the substrate 1. For example, when a protective layer 9 is formed on the surface of the stacked structure 30, the first mask layer 100 may be formed on the surface of the protective layer 9. Subsequently, a first photoresist layer may be formed on the surface of the first mask layer 100. The first photoresist layer may be exposed and developed to form a developed pattern 50. The developed pattern 50 corresponds to the first pattern 401 and the second pattern 402. Figure 6 As shown, the protective layer 9 and the stacked structure 30 can be anisotropically etched using the development pattern 50 as a mask to form a patterned stacked structure 40. It should be noted that after forming the patterned stacked structure 40, the development pattern 50 and the first mask layer 100 can be removed to expose the surface of the protective layer 9.

[0146] In some embodiments of the present disclosure, the first pattern 401 and the second pattern 402 are both in strip shape, and the second direction y is perpendicular to the first direction x. In this case, the second pattern 402 is distributed perpendicularly to the first pattern 401 .

[0147] In step S4, a plurality of first openings 403 are formed along the third direction z penetrating the patterned stacked structure 40. The first openings 403 are arranged one-to-one corresponding to the second patterns 402. The first openings 403 divide the corresponding second pattern 402 into two sub-patterns 4021 that are mirror-distributed side by side along the first direction x. The third direction z is perpendicular to the first direction x and the second direction y, and the first openings 403 are parallel to the planes where the second direction y and the third direction z are located.

[0148] The patterned stacked structure 40 may be etched to form a first opening 403 extending along the second direction y and penetrating the second pattern 402 along the third direction z; the number of the first openings 403 may be multiple, and the multiple first openings 403 are arranged one-to-one with the multiple second patterns 402, and different first openings 403 are spaced apart and parallel to each other along the first direction x. In the embodiment of the present disclosure, the structure after completing step S4 is as follows: Figure 7 shown.

[0149] In an exemplary embodiment of the present disclosure, before forming a plurality of first openings 403 penetrating the patterned stacked structure 40 along the third direction z, the method for preparing the semiconductor memory device structure of the present disclosure may further include:

[0150] Step S210 , filling the gaps in the patterned stacked structure 40 with insulating material 8 .

[0151] The insulating material 8 may be the same material as the insulating material layer 301, for example, the insulating material 8 may be silicon oxide. The insulating material 8 may be filled in the patterned stacking structure 40 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the insulating material 8 may fill the gaps in the patterned stacking structure 40. The surface of the insulating material 8 away from the substrate 1 may then be planarized to provide a flat process reference for subsequent processes. For example, the surface of the insulating material 8 away from the substrate 1 may be polished by a chemical mechanical polishing process so that the top surface of the filled insulating material 8 is flush with the surface of the patterned stacking structure 40. When the top of the patterned stacking structure 40 is a protective layer 9, the surface of the insulating material 8 away from the substrate 1 may be flush with the surface of the protective layer 9 away from the substrate 1. In the embodiment of the present disclosure, the structure after completing step S210 is as follows: Figure 8 shown.

[0152] In some embodiments of the present disclosure, Fig. 9 As shown, before forming the first opening 403, a protective material may be deposited on the surface of the structure formed by the insulating material 8 and the protective layer 9 to form a new protective layer 9 (the new protective layer 9 is composed of the original protective layer 9 on the top of the patterned stacked structure 40 and the newly deposited protective material). The protective material is the same as the material of the original protective layer 9 on the top of the patterned stacked structure 40. For example, the protective material may be silicon nitride. A second mask layer 200 may be formed on the surface of the new protective layer 9, and a second photoresist layer 60 may be formed on the surface of the second mask layer 200. The second photoresist layer 60 is exposed and developed to form a plurality of first development areas 6001 extending along the second direction y and spaced apart along the first direction x. In the first direction x, each first development area 6001 is located in the middle area of ​​each second pattern 402. The second mask layer 200 and the second pattern 402 may be etched in the first developing area 6001 to form a first opening 403 in the patterned stacked structure 40 ; the first opening 403 divides the second pattern 402 into two sub-patterns 4021 that are mirror-distributed along the first direction x.

[0153] It should be noted that after forming the first opening 403, the second photoresist layer 60 and the second mask layer 200 may be removed to expose the surface of the protective layer 9. The structure after removing the second photoresist layer 60 and the second mask layer 200 is as follows: Figure 7 shown.

[0154] In step S5, part of the semiconductor material layer 302 is etched away laterally toward both sides through the first opening 403 to form a plurality of first transistor and word line accommodating grooves, the first transistor and word line accommodating grooves comprising a row of first transistor accommodating grooves 404 extending along the first direction x and arranged along the second direction y, and a word line accommodating groove 405 extending along the second direction y and connecting the row of first transistor accommodating grooves 404.

[0155] The semiconductor material layer 302 on both sides of the first opening 403 can be etched by an isotropic etching process to form a plurality of first transistor and word line accommodating grooves arranged along a third direction z. The word line accommodating groove 405 in the first transistor and word line accommodating groove is located in the area where the sub-pattern 4021 of the second pattern 402 is located, and the semiconductor material layer 302 in the area corresponding to the sub-pattern 4021 of the second pattern 402 can be completely etched away to form the word line accommodating groove 405; the first transistor accommodating groove 404 is located in the area where the first pattern 401 is located, and when the semiconductor material layer 302 is etched, the semiconductor material layer 302 corresponding to the first pattern 401 is not completely etched, and the depth of the first transistor accommodating groove 404 is less than half the length of the first pattern 401 between two adjacent first openings 403. During the etching process, the etching depth of the first transistor accommodating groove 404 can be controlled by controlling the etching time. In the embodiment of the present disclosure, the structure after completing step S5 is as follows: Fig.10 shown; along Fig.10 The structure cut in the AA direction is as follows Fig.11 shown.

[0156] In step S6, a first semiconductor layer 103, a first gate dielectric layer 102 and a first gate material layer 1011 are sequentially deposited in the first transistor and word line accommodating groove; the first semiconductor layer 103 covers the side wall and the bottom surface of the first transistor and word line accommodating groove, the first gate dielectric layer 102 conformally covers the surface of the first semiconductor layer 103, and the first gate material layer 1011 fills the remaining space of the first transistor and word line accommodating groove.

[0157] The material of the first semiconductor layer 103 may be indium gallium zinc oxide (IGZO) or single crystal silicon. The material of the first gate dielectric layer 102 may be a material with a high dielectric constant, for example, the material may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. The material of the first gate material layer 1011 may be indium zinc oxide (IZO) or polycrystalline silicon. It should be noted that the material of the first gate material layer 1011 matches the material of the first semiconductor layer 103; for example, when the material of the first semiconductor layer 103 is indium gallium zinc oxide (IGZO), the material of the first gate material layer 1011 is indium zinc oxide (IZO); when the material of the first semiconductor layer 103 is single crystal silicon, the material of the first gate material layer 1011 is polycrystalline silicon.

[0158] In some embodiments of the present disclosure, Fig.12As shown, the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer 1011 can be sequentially deposited on the side of the protective layer 9 away from the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this process, the first semiconductor layer 103 can conformally cover the inner wall of the first transistor and word line accommodating groove. For the convenience of the process, the first semiconductor layer 103 can also cover the surface of the protective layer 9 and the side walls of each insulating material layer 301 exposed in the first opening 403; the first gate dielectric layer 102 can conformally cover the surface of the first semiconductor layer 103, and the first gate material layer 1011 is located on the surface of the first gate dielectric layer 102, and can fill the remaining space of the first transistor and word line accommodating groove. In this process, in order to ensure that the first gate material layer 1011 can fill the remaining space of the first transistor and word line accommodating groove, the first gate material layer 1011 can simultaneously fill the first opening 403. Then, the first gate material layer 1011 in the first opening 403 and the first gate material layer 1011 on the top of the protection layer 9 can be removed. The structure after completing step S6 in the embodiment of the present disclosure is as follows. Fig.13 shown.

[0159] In step S7, the first gate material layer 1011 deposited in the word line accommodating groove 405 is etched away to form the first gate 101 of the first transistor 10, and then the word line accommodating groove 405 is filled with word line material to form a word line 5 and a first transistor 10 located in the first transistor accommodating groove 404, and the word line 5 is in contact with the first gate 101; the first transistor 10 includes a first gate 101, a first gate dielectric layer 102 conformally covering the sidewall and one end of the first gate 101, and a first semiconductor layer 103 conformally covering the first gate dielectric layer 102, and the first semiconductor layer 103 includes a first source and drain region, a first channel region, and a second source and drain region distributed in sequence along the first direction x.

[0160] The first gate material layer 1011 can be etched back by isotropic etching to remove the first gate material layer 1011 in the word line accommodating groove 405, and the first gate material layer 1011 in the first transistor accommodating groove 404 is used as the first gate 101 of the first transistor 10, the first gate dielectric layer 102 covered on the surface of the first gate 101 is used as the first gate dielectric layer 102 of the first transistor 10, and the first semiconductor layer 103 covered on the surface of the first gate dielectric layer 102 is used as the active region of the first transistor 10, and the active region can be divided into a first source and drain region, a first channel region, and a second source and drain region distributed in sequence along the first direction x, wherein the region in the active region close to the word line accommodating groove 405 can be used as the first source and drain region. The first gate 101, the first gate dielectric layer 102, and the first semiconductor layer 103 can together constitute the first transistor 10.

[0161] After forming the first gate 101, a word line material may be filled into the word line accommodating groove 405 to form a word line 5. The word line material may be a conductive material, and the conductive material may be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. In the embodiment of the present disclosure, the structure after completing step S7 is as follows: Fig.14 shown.

[0162] In an exemplary embodiment of the present disclosure, please continue to refer to Fig.13 As shown, the word line 5 may include a conductive barrier material layer 51 and a metal material layer 52, wherein the conductive barrier material layer 51 may be located on the sidewall and bottom of the word line accommodating groove 405, that is, the conductive barrier material layer 51 may be in contact with the first gate 101 at the bottom of the word line accommodating groove 405. The metal material layer 52 may fill the remaining space in the word line accommodating groove 405. It should be noted that in the process of forming the conductive barrier material layer 51, the conductive barrier material layer may be deposited on the top of the protective layer 9 and the sidewall of the first opening 403 for process convenience, and the metal material layer 52 may also fill the first opening 403; then the metal material layer 52, the conductive barrier material layer 51, the first gate dielectric layer 102, and the first semiconductor layer 103 located on the top of the protective layer 9 and in the first opening 403 may be removed; and the conductive barrier material layer 51 and the metal material layer 52 remaining in the word line accommodating groove 405 are used as the word line 5.

[0163] In an exemplary embodiment of the present disclosure, after forming the word line 5, the method for preparing the semiconductor memory device structure of the present disclosure may further include:

[0164] Step S220 , filling the first opening 403 with insulating material 8 .

[0165] The insulating material 8 filled in the first opening 403 may be the same as the material of the insulating material layer 301. For example, the insulating material 8 may be silicon oxide. The insulating material 8 may be filled in the first opening 403 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this process, for the convenience of the process, the insulating material 8 may cover the surface of the protective layer 9 at the same time. The insulating material 8 may then be subjected to chemical mechanical polishing, so that the surface of the insulating material 8 away from the substrate 1 is flush with the surface of the protective layer 9 away from the substrate 1. In the embodiment of the present disclosure, the structure after completing step S220 is as follows: Fig.15 shown.

[0166] In an exemplary embodiment of the present disclosure, after the first opening 403 is filled with the insulating material 8, a protective material may be deposited on the surface of the insulating material 8 and the protective layer 9 to form a new protective layer 9. The new protective layer 9 is composed of the original protective layer 9 and the newly deposited protective material.

[0167] In step S8 , a plurality of second openings 406 penetrating the patterned stacked structure 40 along the third direction z are formed. The second openings 406 are located in the middle between two adjacent first openings 403 . The second openings 406 are parallel to the plane where the second direction y and the third direction z are located.

[0168] After the first opening 403 is filled with the insulating material 8, step S8 may be performed. The patterned stacked structure 40 may be anisotropically etched to form a plurality of second openings 406 extending along the second direction y and penetrating the patterned stacked structure 40 along the third direction z. A second opening 406 may be formed between every two first openings 403; and in the first direction x, the second opening 406 is located in the middle of two adjacent first openings 403. In the embodiment of the present disclosure, the structure after completing step S8 is as follows: Fig.16 shown.

[0169] For example, a third mask layer may be formed on the surface of the new protective layer 9, a third photoresist layer may be formed on the surface of the third mask layer, the third photoresist layer may be etched to form a plurality of second development areas, the second development areas may be strip-shaped and may extend along the second direction y, a second development area may be formed between every two first openings 403 on the patterned stacked structure 40, and the orthographic projection of the second development area on the patterned stacked structure 40 is located in the middle of two adjacent first openings 403. The third mask layer and the patterned stacked structure 40 may be anisotropically etched in the second development area to form a second opening 406 penetrating the patterned stacked structure 40 along the third direction z. After the second opening 406 is formed, the third photoresist layer and the third mask layer may be removed.

[0170] In step S9, part of the insulating material layer 301 is etched laterally to both sides through the second opening 406 to form the second gate 201 of the second transistor 20, and then the second gate dielectric layer 202 and the second semiconductor layer 203 are deposited in sequence, the second gate dielectric layer 202 conformally covers the side wall of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source and drain region, a second channel region and a fourth source and drain region distributed in sequence along the first direction x.

[0171] like Fig.17As shown, the insulating material layer 301 on both sides of the second opening 406 can be etched by an isotropic etching process to expose the side walls of the semiconductor material layer 302 on both sides of the second opening 406. It should be noted that when etching the insulating material layer 301, the insulating material layer 301 corresponding to the first pattern 401 is not completely etched, and the length of the exposed semiconductor material layer 302 is less than half of the length of the insulating material layer 301 between two adjacent first openings 403. The exposed portion of the semiconductor layer after etching the insulating material layer 301 can be used as the second gate 201 of the second transistor 20. It should be noted that in Fig.16 In order to clearly show the structure of the second gate 201 , only one row of the second gates 201 distributed along the second direction y is shown. It can be understood that there are multiple rows of second gates 201 distributed at intervals in the second direction y.

[0172] like Fig.18 As shown, a second gate dielectric layer 202 and a second semiconductor layer 203 may be sequentially formed on the surface of the second gate 201 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, wherein the material of the second gate dielectric layer 202 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. The material of the second semiconductor layer 203 may correspond to the material of the second gate 201, for example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 is indium gallium zinc oxide (IGZO); when the material of the second gate 201 is polycrystalline silicon, the material of the second semiconductor layer 203 is single crystal silicon. The second semiconductor layer 203 may be used as the active region of the second transistor 20, and the active region of the second transistor 20 may be divided into a third source and drain region, a second channel region and a fourth source and drain region sequentially distributed along the first direction x, wherein the region in the active region of the second transistor 20 close to the word line accommodating groove 405 may be used as the third source and drain region. The second gate 201 , the second gate dielectric layer 202 , and the second semiconductor layer 203 may together constitute the second transistor 20 .

[0173] In step S10, the insulating material 8 is filled between adjacent second transistors 20 to close the second opening 406; a plurality of third openings 81 are formed that penetrate the insulating material 8 along the third direction z, the third openings 81 are located within the second openings 406, and the third openings 81 expose the fourth source and drain regions in the second transistor 20, and the third openings 81 are parallel to the planes where the second direction y and the third direction z are located.

[0174] like Fig.19As shown, after the second transistors 20 are formed, the insulating material 8 can be filled between adjacent second transistors 20 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. At this time, the insulating material 8 fills each second opening 406. In this process, for the convenience of the process, the insulating material 8 can be deposited on the top of the protective layer 9 at the same time. After the second openings 406 are filled with the insulating material 8, the insulating material 8 located on the top of the protective layer 9 can be removed, and the insulating material 8 can be anisotropically etched along the third direction z to form a third opening 81 extending along the second direction y and penetrating the insulating material 8 along the third direction z in the area corresponding to each second opening 406. The third opening 81 can expose each fourth source and drain region located at the end of the second gate 201 in each second transistor 20. In the embodiment of the present disclosure, the structure after completing step S10 is as shown Fig. 20 shown.

[0175] In step S11 , a source-drain layer 4 is formed in the third opening 81 .

[0176] The material of the source-drain layer 4 may be a conductive material, for example, it may be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. The source-drain layer 4 may fill the third opening 81 and may be in contact with the fourth source-drain region of the second transistor 20. In the embodiment of the present disclosure, the structure after completing step S11 is as follows: Fig.21 shown.

[0177] In an exemplary embodiment of the present disclosure, forming the source-drain layer 4 in the third opening 81 (ie, step S11) includes steps S310 and S320, wherein:

[0178] Step S310 , forming a conductive barrier layer conformally covering the inner wall and the bottom of the third opening 81 .

[0179] The material of the conductive barrier layer may be a conductive material having an ion blocking function, for example, it may be titanium nitride or tantalum nitride. The conductive barrier layer may be formed on the sidewall and bottom of the third opening 81 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the portion of the conductive barrier layer located on one sidewall of the third opening 81 may be used as the first conductive barrier layer 41, and the conductive barrier layer located on the other sidewall of the third opening 81 may be used as the second conductive barrier layer 43. The first conductive barrier layer 41 and the second conductive barrier layer 43 may be connected through the conductive barrier layer located at the bottom of the third opening 81. Of course, the conductive barrier layer may also be formed by other methods, and the method for forming the conductive barrier layer is not particularly limited here.

[0180] Step S320 , depositing a conductive metal layer 42 in the third opening 81 , so that the conductive metal layer 42 fills the remaining space of the third opening 81 .

[0181] The material of the conductive metal layer 42 may be a metal material with good conductivity, for example, tungsten. The metal material may be deposited in the third opening 81 having the conductive barrier layer by chemical vapor deposition, physical vapor deposition or atomic layer deposition, thereby forming the conductive metal layer 42. The conductive metal layer 42 and the conductive barrier layer may together constitute the source-drain layer 4, and the conductive barrier layer may prevent the metal ions in the conductive metal layer 42 from diffusing into other surrounding structures, thereby helping to improve the reliability of the device.

[0182] In step S12, a plurality of first bit line accommodating holes 601 and second bit line accommodating holes 701 extending along a third direction z are formed, a first bit line 6 is formed in the first bit line accommodating hole 601, and a second bit line 7 is formed in the second bit line accommodating hole 701; each first bit line 6 is coated on the periphery of a row of first source and drain regions arranged along the third direction z in the same plane, and each second bit line 7 is coated on the periphery of a row of third source and drain regions arranged along the third direction z in the same plane.

[0183] In an exemplary embodiment of the present disclosure, after the source-drain layer 4 is formed, a protective material can be deposited on the structure formed by the source-drain layer 4 and the protective layer 9 to form a new protective layer 9 (the new protective layer 9 is composed of the original protective layer 9 and the newly deposited protective material), and the protective material is the same as the material of the original protective layer 9.

[0184] A fourth mask layer and a fourth photoresist layer may be formed on the surface of the new protective layer 9, and the fourth photoresist layer may be etched to form a plurality of third development areas in an array, and the third development areas may be rectangular, square, circular or elliptical, etc. The fourth mask layer, the protective layer 9, the patterned stacked structure 40, and the insulating material 8 filled in the patterned stacked structure 40 may be anisotropically etched in the third development area to form a plurality of first bit line accommodating holes 601 spaced apart along the second direction y and extending along the third direction z and a plurality of second bit line accommodating holes 701 spaced apart along the second direction y and extending along the third direction z, the first bit line accommodating holes 601 may expose the surface of each first active area arranged along the third direction z, and the second bit line accommodating holes 701 may expose the surface of each third active area arranged along the third direction z. After forming each first bit line accommodating hole 601 and each second bit line accommodating hole 701, the fourth photoresist layer and the fourth mask layer may be removed. In the embodiment of the present disclosure, the first bit line accommodating hole 601 and the second bit line accommodating hole 701 are as shown in FIG. Fig. 22 and Fig.23 shown.

[0185] A first bit line 6 may be formed in each first bit line accommodating hole 601, and a second bit line 7 may be formed in each second bit line accommodating hole 701. The materials of the first bit line 6 and the second bit line 7 may be conductive materials, and the conductive materials may be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. The first bit line 6 may be coated on the periphery of a row of first source and drain regions arranged along the third direction z in the same plane, and each second bit line 7 may be coated on the periphery of a row of third source and drain regions arranged along the third direction z in the same plane.

[0186] In an exemplary embodiment of the present disclosure, forming the first bit line 6 and the second bit line 7 may include: forming a conductive barrier material layer that conformally covers the first bit line accommodating hole 601 and the second bit line accommodating hole 701, filling the first bit line accommodating hole 601 and the second bit line accommodating hole 701 with the conductive barrier material layer with a metal material to form a metal material layer, wherein the material of the conductive barrier material layer is titanium nitride, and the material of the metal material layer is tungsten, and titanium nitride can be used to prevent tungsten ions from diffusing into other surrounding structures, thereby helping to improve the reliability of the device. In the embodiment of the present disclosure, the structure after completing step S12 is as follows Fig.24 shown.

[0187] It should be noted that, although the steps of the method for preparing the semiconductor memory device structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0188] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor common unit structure, prepared on a substrate, characterized in that: include: a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit are arranged side by side in a mirror image along a first direction, the first storage unit and the second storage unit share a same source-drain unit layer, and the first direction is parallel to a surface of the substrate; The first storage unit and the second storage unit both include: a first transistor, located above the top surface of the substrate, the first transistor comprising: a first gate, a first gate dielectric layer and a first semiconductor layer, the first gate extending along the first direction, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, the first semiconductor layer covering the surface of the first gate dielectric layer, and the first semiconductor layer comprising a first source and drain region, a first channel region and a second source and drain region sequentially distributed along the first direction; a second transistor, arranged side by side with the first transistor along the first direction, the second transistor comprising a second gate, a second gate dielectric layer and a second semiconductor layer, the second gate extending along the first direction, the second gate dielectric layer conformally covering the sidewall of the second gate and the end of the second gate away from the first transistor, the second semiconductor layer covering the surface of the second gate dielectric layer, and the second semiconductor layer comprising a third source and drain region, a second channel region and a fourth source and drain region sequentially arranged along the first direction; the second source and drain region is conductively connected to the second gate; The fourth source-drain region in the first memory cell and the fourth source-drain region in the second memory cell are respectively connected to two opposite sides of the source-drain unit layer.

2. The semiconductor common unit structure according to claim 1, characterized in that: The plane where the source-drain unit layer is located is perpendicular to the first direction, and the source-drain unit layer includes a first conductive barrier layer, a conductive metal layer, and a second conductive barrier layer stacked in sequence along the first direction; the fourth source-drain region in the first storage unit is connected to the first conductive barrier layer, and the fourth source-drain region in the second storage unit is connected to the second conductive barrier layer.

3. The semiconductor common unit structure according to claim 2, characterized in that: The first conductive barrier layer and the second conductive barrier layer are both made of titanium nitride, and the conductive metal layer is made of tungsten.

4. The semiconductor common unit structure according to claim 1, characterized in that: The materials of the first gate and the second gate are both indium zinc oxide, and the materials of the first semiconductor layer and the second semiconductor layer are both indium gallium zinc oxide.

5. A semiconductor common block structure, prepared on a substrate, characterized in that: include: A plurality of semiconductor common unit structures according to any one of claims 1 to 4 located on the substrate, wherein the plurality of semiconductor common unit structures are arranged along a second direction and a third direction, wherein the second direction is parallel to the substrate and intersects with the first direction, and the third direction is perpendicular to the first direction and the second direction; a plurality of word lines extending along the second direction and arranged along the first direction and the third direction, each of the word lines being connected to an end portion of a row of the first gate electrodes arranged along the second direction in the same plane and not covered by the first gate dielectric layer; a plurality of first bit lines extending along the third direction and arranged along the first direction and the second direction, each of the first bit lines covering an outer periphery of a row of the first source and drain regions arranged along the third direction in the same plane; a plurality of second bit lines extending along the third direction and arranged along the first direction and the second direction, each of the second bit lines covering an outer periphery of a row of the third source and drain regions arranged along the third direction in the same plane; A source-drain layer is formed by sequentially connecting all the source-drain unit layers in the same plane end to end.

6. The semiconductor common block structure according to claim 5, characterized in that: Materials of the word line, the first bit line, and the second bit line are all conductive materials, and the conductive materials are independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride.

7. The semiconductor common block structure according to claim 5, characterized in that: The word line, the first bit line, and the second bit line all include a conductive barrier material layer and a metal material layer. The conductive barrier material layer is made of titanium nitride, and the metal material layer is made of tungsten.

8. A semiconductor memory device structure, characterized in that: include: A substrate and a plurality of semiconductor common block structures according to any one of claims 5 to 7 located on the substrate, wherein the plurality of semiconductor common block structures are arranged along the first direction; Two adjacent semiconductor common block structures are arranged independently of each other.

9. A method for preparing a semiconductor memory device structure, characterized in that: The following steps are involved: providing a substrate; Alternatingly depositing insulating material layers and semiconductor material layers on the substrate in sequence to form a stacked structure; Performing patterning on the stacked structure to form a patterned stacked structure, wherein the pattern of the patterned stacked structure includes a plurality of first patterns extending along a first direction and spaced apart along a second direction, and a plurality of second patterns extending along the second direction and spaced apart along the first direction; the first direction is parallel to the surface of the substrate, the second direction is parallel to the substrate and intersects with the first direction; the first pattern overlaps with the second pattern; forming a plurality of first openings penetrating the patterned stacked structure along a third direction, wherein the first openings are arranged in one-to-one correspondence with the second patterns, and the first openings divide the corresponding second pattern into two sub-patterns that are distributed side by side in a mirror-image manner along the first direction; The third direction is perpendicular to the first direction and the second direction, and the first opening is parallel to the plane where the second direction and the third direction are located; Part of the semiconductor material layer is etched away laterally toward both sides through the first opening to form a plurality of first transistor and word line accommodating grooves, wherein the first transistor and word line accommodating grooves include a row of first transistor accommodating grooves extending along the first direction and arranged along the second direction, and a word line accommodating groove extending along the second direction and connected to the row of first transistor accommodating grooves; A first semiconductor layer, a first gate dielectric layer and a first gate material layer are sequentially deposited in the first transistor and word line accommodating groove; the first semiconductor layer covers the sidewall and bottom surface of the first transistor and word line accommodating groove, the first gate dielectric layer conformally covers the surface of the first semiconductor layer, and the first gate material layer fills the remaining space of the first transistor and word line accommodating groove; The first gate material layer deposited in the word line accommodating groove is etched away to form a first gate of a first transistor, and then the word line accommodating groove is filled with word line material to form a word line and the first transistor located in the first transistor accommodating groove, wherein the word line is in contact with the first gate; the first transistor comprises the first gate, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, and the first semiconductor layer conformally covering the first gate dielectric layer, and the first semiconductor layer on the first gate comprises a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction; forming a plurality of second openings penetrating the patterned stacked structure along the third direction, wherein the second openings are located at a middle position between two adjacent first openings, and the second openings are parallel to a plane where the second direction and the third direction are located; Part of the insulating material layer is etched away laterally on both sides through the second opening to form a second gate of the second transistor, and then a second gate dielectric layer and a second semiconductor layer are deposited in sequence, wherein the second gate dielectric layer conformally covers the sidewall of the second gate and the end of the second gate away from the first transistor, the second semiconductor layer covers the surface of the second gate dielectric layer, and the second semiconductor layer includes a third source and drain region, a second channel region, and a fourth source and drain region sequentially distributed along the first direction; Filling insulating material between adjacent second transistors to close the second opening; forming a plurality of third openings penetrating the insulating material along the third direction, wherein the third openings are located within the second openings and expose the fourth source and drain regions in the second transistors, and the third openings are parallel to the second direction and the plane where the third direction is located; forming a source-drain layer in the third opening; forming a plurality of first bit line accommodating holes and second bit line accommodating holes extending along the third direction, forming a first bit line in the first bit line accommodating holes, and forming a second bit line in the second bit line accommodating holes; Each of the first bit lines covers the periphery of a row of the first source and drain regions arranged along the third direction in the same plane, and each of the second bit lines covers the periphery of a row of the third source and drain regions arranged along the third direction in the same plane.

10. The method for preparing a semiconductor memory device structure according to claim 9, characterized in that: Before the step of forming a plurality of first openings penetrating the patterned stacked structure along the third direction, the method further includes: The gaps in the patterned stacked structure are filled with insulating material.

11. The method for preparing a semiconductor memory device structure according to claim 9, characterized in that: After forming the word line and before forming the second opening, the method further includes: The first opening is filled with insulating material.

12. The method for preparing a semiconductor memory device structure according to claim 9, characterized in that: Forming a source-drain layer in the third opening includes: forming a conductive barrier layer conformally covering the inner wall and bottom of the third opening; A conductive metal layer is deposited in the third opening, and the conductive metal layer fills the remaining space of the third opening.

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