Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a bit line structure, a gate electrode structure, an etching stop layer and an interlayer dielectric layer. The substrate includes a first region and a second region. The bit line structure is disposed on the substrate and located in the first region. The gate structure is disposed on the substrate and located in the second region. An etch stop layer is disposed on the substrate covering a top surface and sidewalls of the bit line structure and sidewalls of the gate structure. An interlayer dielectric layer overlies the bit line structure and the gate structure, where the interlayer dielectric layer physically contacts the etch stop layer overlying the top surface of the bit line structure and the top surface of the gate structure. Therefore, both the bit line structure and the gate structure can have better structural reliability, so that the semiconductor device can achieve more optimized component efficiency.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor memory device and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor memory devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology needs to be further improved to effectively improve the performance and reliability of related storage devices. Summary of the invention

[0003] One of the purposes of the present invention is to provide a semiconductor device and a method for manufacturing the same, by setting etching stop layers with different coverage degrees in different regions, and / or by simultaneously thinning the thickness of the cover layer in a specific region during the implementation of a specific process (such as a planarization process or a back etching process, etc.), thereby reducing the height difference of components in different regions of the semiconductor device, improving the structural reliability of the semiconductor device, and enabling the semiconductor device to achieve more optimized component efficiency and operating performance.

[0004] To achieve the above-mentioned purpose, one embodiment of the present invention provides a semiconductor device, which includes a substrate, a bit line structure, a gate structure, an etching stop layer and an interlayer dielectric layer. The substrate includes a first region and a second region. The bit line structure is arranged on the substrate and is located in the first region. The gate structure is arranged on the substrate and is located in the second region. The etching stop layer is arranged on the substrate, covering the top surface and sidewalls of the bit line structure, and the sidewalls of the gate structure. The interlayer dielectric layer covers the bit line structure and the gate structure, wherein the interlayer dielectric layer physically contacts the etching stop layer covering the top surface of the bit line structure, and the top surface of the gate structure.

[0005] To achieve the above-mentioned purpose, one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. A substrate is provided, wherein the substrate comprises a first region and a second region. A bit line structure is formed on the substrate, located in the first region. A gate structure is formed on the substrate, located in the second region. An etch stop layer is formed, covering the top surface and side walls of the bit line structure, and the side walls of the gate structure. An interlayer dielectric layer is formed, covering the bit line structure and the gate structure, wherein the interlayer dielectric layer physically contacts the etch stop layer covering the top surface of the bit line structure, and the top surface of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of this embodiment and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figure 1 to Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, wherein:

[0008] Figure 1 is a cross-sectional schematic diagram of a semiconductor device in one embodiment; and

[0009] Figure 2 is another cross-sectional schematic diagram of a semiconductor device in one embodiment;

[0010] Figures 3 to 10 The figure is a schematic diagram of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein:

[0011] Figure 3 is a schematic cross-sectional view of a semiconductor device after forming a first semiconductor layer;

[0012] Figure 4 is a schematic cross-sectional view of a semiconductor device after a bit line opening is formed;

[0013] Figure 5 is a schematic cross-sectional view of the semiconductor device after forming the second semiconductor layer;

[0014] Figure 6 is a schematic cross-sectional view of a semiconductor device after a covering material layer is formed;

[0015] Figure 7 is a schematic cross-sectional view of a semiconductor device after an etching stop material layer is formed;

[0016] Figure 8 is a schematic cross-sectional view of a semiconductor device after a planarization process is performed;

[0017] Fig. 9 is a schematic cross-sectional view of a semiconductor device after an etching stop layer is formed;

[0018] Fig.10 is a schematic cross-sectional view of a semiconductor device after an interlayer dielectric layer is formed;

[0019] Figure 11 to Figure 12 FIG. 1 is a schematic diagram of steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention, wherein:

[0020] Fig.11 is a schematic cross-sectional view of a semiconductor device after an etch-back process is performed;

[0021] Fig.12 It is a schematic cross-sectional view of a semiconductor device after an etching stop layer is formed.

[0022] Description of reference numerals:

[0023] 10 Semiconductor devices

[0024] 100 Substrate

[0025] 100A Zone 1

[0026] 100B Second District

[0027] 102 Shallow Trench Isolation

[0028] 104 Doping region

[0029] 110 Dielectric layer

[0030] 110t Top

[0031] 112 Oxide layer

[0032] 114 Nitride layer

[0033] 116 Oxide layer

[0034] 118 gate dielectric layer

[0035] 118t Top

[0036] 120-bit line structure

[0037] 120s Sidewall

[0038] 120t Top

[0039] 122 first conductor layer

[0040] 122t Top

[0041] 124 First Cover Layer

[0042] 126 Semiconductor layer

[0043] 126t Top

[0044] 128, 148 Barrier layer

[0045] 130, 150 metal layer

[0046] 132-bit line plug

[0047] 140 Gate structure

[0048] 140t Top

[0049] 140s Sidewall

[0050] 142 Second conductor layer

[0051] 142t Top

[0052] 144 Second Cover Layer

[0053] 146 top semiconductor layer

[0054] 146t Top

[0055] 152 bottom semiconductor layer

[0056] 152t Top

[0057] 160 bit line spacers

[0058] 160t Top

[0059] 162, 172 gap wall

[0060] 164, 174 gap wall

[0061] 180, 182, 184 Etch stop layer

[0062] 190, 192, 194 Insulation layer

[0063] 196 Interlayer dielectric layer

[0064] 200 Buried Gate Structure

[0065] 202 dielectric layer

[0066] 204 Gate dielectric layer

[0067] 206 Gate

[0068] 208 Covering

[0069] 210 Insulation structure

[0070] 212, 214 plug

[0071] 216 Metal wire

[0072] 218 gate dielectric material layer

[0073] 224 Covering material layer

[0074] 224t Top

[0075] 226 second semiconductor material layer

[0076] 228 Barrier Material Layer

[0077] 230 Metal material layer

[0078] 252 first semiconductor material layer

[0079] 280 Etch stop material layer

[0080] 290 Insulation material layer

[0081] HM1, HM2, HM3 mask layers

[0082] OP Opening

[0083] P1 First plane

[0084] P2 Second plane

[0085] T1, T2, T3, T4 thickness DETAILED DESCRIPTION

[0086] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the components and effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0087] Please refer to Figure 1 to Figure 2 , which is a cross-sectional schematic diagram of a semiconductor device 10 in a preferred embodiment of the present invention. First, Figure 1As shown, the semiconductor device 10 includes a substrate 100, a bit line structure 120, a gate structure 140, an etching stop layer 180, and an interlayer dielectric layer 186. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.) or a silicon-on-insulator (SOI) substrate, etc., and at least two regions are defined on the substrate 100, such as a first region 100A with a relatively high component density (such as a storage region of the semiconductor device 10) and a second region 100B with a relatively low component density (such as a peripheral region of the semiconductor device 10), wherein the second region 100B is, for example, disposed on one side of the first region 100A, such as Figure 1 In addition, at least one shallow trench isolation (STI) 102 is formed in the substrate 100 to define a plurality of active areas (AA) on the substrate 100 .

[0088] The bit line structure 120 and the gate structure 140 are both disposed on the substrate 100, wherein the bit line structure 120 is located in the first region 100A, and the gate structure 140 is located in the second region 100B. The etching stop layer 180 is also disposed on the substrate 100, wherein the etching stop layer 182 disposed in the first region 100A covers the bit line structure 120 and the substrate 100 as a whole, including covering the top surface 120t and the sidewall 120s of the bit line structure 120, and the etching stop layer 184 disposed in the second region 100B covers the sidewall 140s of the gate structure 140 and the substrate 100. The interlayer dielectric layer 196 is further disposed on the etching stop layer 180, and covers the bit line structure 120 and the gate structure 140 as a whole. It should be noted that, since the etching stop layer 184 disposed in the second area 100B does not cover the top surface 140t of the gate structure 140, the interlayer dielectric layer 196 physically contacts the top surface 140t of the gate structure 140, and physically contacts the etching stop layer 182 covering the top surface 120t of the bit line structure 120. In this way, the bit line structure 120 disposed in the first area 100A and the gate structure 140 disposed in the second area 100B can both have a more improved structural reliability, so that the semiconductor device 10 can achieve a more optimized component performance.

[0089] In one embodiment, the bit line structure 120 includes a first conductor layer 122 and a first cap layer 124 (for example, including insulating materials such as silicon oxide, silicon nitride or silicon oxynitride) stacked in sequence on the dielectric layer 110, and the first conductor layer 122 preferably includes a composite layer structure, for example, further including a semiconductor layer 126 (for example, including semiconductor materials such as polysilicon), a barrier layer 128 (for example, including conductive barrier materials such as titanium and / or titanium nitride) and a metal layer 130 (for example, including low-resistance metal materials such as tungsten, aluminum or copper) stacked in sequence from bottom to top on the top surface 110t of the dielectric layer 110, but the present invention is not limited thereto. At least one bit line contact 132 (BLC) is further disposed below the bit line structure 120. The bit line plug 132, for example, passes through the dielectric layer 110, partially extends into the substrate 100 of the first region 100A and is located between two adjacent buried gate structures 200, so that the bit line structure 120 can be electrically connected to the active region located in the first region 100A through the bit line plug 132 disposed thereunder. Preferably, the semiconductor layer 126 in the first conductive layer 122 is, for example, integrally formed with the bit line plug 132 and includes the same semiconductor material (for example, including polysilicon, etc.), but not limited thereto. The dielectric layer 110 also preferably has a composite layer structure, for example, including an oxide layer 112-nitride layer 114-oxide layer 116 (oxide-nitride-oxide, ONO) structure, but not limited thereto. In addition, the buried gate structure 200 is disposed in the substrate 100 below the dielectric layer 110 , and includes in detail a dielectric layer 202 , a gate dielectric layer 204 , a gate 206 , and a cap layer 208 disposed in sequence, but is not limited thereto.

[0090] On the other hand, the gate structure 140 includes in detail a second conductor layer 142 and a second cap layer 144 (for example, including insulating materials such as silicon oxide, silicon nitride or silicon oxynitride) stacked in sequence on the gate dielectric layer 118, and the second conductor layer 142 preferably includes a composite layer structure, for example, also including a bottom semiconductor layer 152 (for example, including semiconductor materials such as doped polycrystalline silicon and doped amorphous silicon), a top semiconductor layer 146 (for example, including semiconductor materials such as doped polycrystalline silicon and doped amorphous silicon), a barrier layer 148 (for example, including conductive barrier materials such as titanium and / or titanium nitride) and a metal layer 150 (for example, including low-resistance metal materials such as tungsten, aluminum or copper) stacked in sequence from bottom to top on the top surface 118t of the gate dielectric layer 118. In one embodiment, the second cap layer 144 and the first cap layer 124 preferably include the same insulating material, the metal layer 150 in the second conductor layer 142 and the metal layer 130 in the first conductor layer 122 preferably include the same metal material, the barrier layer 148 in the second conductor layer 142 and the barrier layer 128 in the first conductor layer 122 preferably include the same conductive barrier material, and the top semiconductor layer 146 in the second conductor layer 142 and the semiconductor layer 126 in the first conductor layer 122 preferably include the same semiconductor material, but not limited thereto. In another embodiment, the gate dielectric layer 118 and the oxide layer 112 in the dielectric layer 110 preferably include the same material and thickness, but not limited thereto.

[0091] It should be noted that, when the arrangement plane of the second conductor layer 142 in the second region 100B (i.e., the top surface 118t of the gate dielectric layer 118) is lower than the arrangement plane of the first conductor layer 122 in the first region 100A (i.e., the top surface 110t of the dielectric layer 110), since the second conductor layer 142 additionally includes the bottom semiconductor layer 152, the top surface 142t of the second conductor layer 142 is higher than the top surface 122t of the first conductor layer 122. In addition, the top surface 126t of the semiconductor layer 126 in the first conductor layer 122 is preferably higher than the top surface 152t of the bottom semiconductor layer 152 in the second conductor layer 142 and lower than the top surface 146t of the top semiconductor layer 146 in the second conductor layer 142, and the thickness T2 of the top semiconductor layer 146 is preferably equal to the thickness T1 of the semiconductor layer 126 on the dielectric layer 110, but is not limited thereto. In addition, since the thickness T3 of the first capping layer 124 disposed above the first conductor layer 122 is greater than the thickness T4 of the second capping layer 144 disposed above the second conductor layer 142, the top surface of the second capping layer 144 (i.e., the top surface 140t of the gate structure 140) is lower than the top surface of the first capping layer 124 (i.e., the top surface 120t of the bit line structure 120).

[0092] For example Figure 1As shown, the semiconductor device 10 further includes an insulating layer 190 disposed on the substrate 100, a bit line spacer 160 disposed on the sidewall 120s of the bit line structure 120, and a gate spacer 170 disposed on the sidewall 140s of the gate structure 140. The insulating layer 190 is, for example, disposed between the bit line structure 120 and the gate structure 140. The insulating layer 192 disposed in the first region 100A only covers the etching stop layer 182 disposed on the bit line spacer 160, and has a first plane P1 flush with the etching stop layer 182 covering the top surface 120t of the bit line structure 120, while the insulating layer 194 disposed in the second region 100B completely covers the etching stop layer 184 disposed in the second region 100B, and has a second plane P2 flush with the etching stop layer 184 and the top surface 140t of the gate structure 140. That is, the insulating layer 192 disposed in the first region 100A and the insulating layer 194 disposed in the second region 100B respectively have top surfaces of different heights, and the first plane P1 in the first region 100A is preferably higher than the second plane P2 in the second region 100B.

[0093] The bit line spacer 160 is, for example, disposed between the bit line structure 120 and the etching stop layer 182 disposed in the first region 100A, and specifically includes a spacer 162 (for example, including silicon nitride, silicon carbonitride) and a spacer 164 (for example, including silicon oxide, silicon oxynitride) sequentially stacked on the sidewall 120s of the bit line structure 120, but the present invention is not limited thereto. The etching stop layer 182 disposed in the first region 100A further covers the bit line spacer 160 as a whole, and can physically contact the top surface 160t of the bit line spacer 160. The gate spacer 170 is, for example, disposed between the gate structure 140 and the etching stop layer 184 disposed in the second region 100B, and specifically includes a spacer 172 (for example, including silicon nitride, silicon carbonitride) and a spacer 174 (for example, including silicon oxide, silicon oxynitride) sequentially stacked on the sidewall 140s of the gate structure 140, but the present invention is not limited thereto. In one embodiment, the spacers 162 of the bit line spacers 160 and the spacers 172 of the gate spacers 170 preferably include the same material and thickness, and the spacers 164 of the bit line spacers 160 and the spacers 174 of the gate spacers 170 also include the same material and thickness, but not limited thereto.

[0094] Under this configuration, the semiconductor device 10 of the present embodiment can be used as a dynamic random access memory (DRAM) device, and the buried gate structure 200 and the bit line structure 120 in the first region 100A respectively serve as a buried word line (WL) and a bit line (BL) of the semiconductor device 10 to receive or transmit a voltage signal from the substrate 100. According to the semiconductor device 10 of the present embodiment, although the gate structure 140 in the second region 100B additionally includes a bottom semiconductor layer 152 and has a second conductor layer 142 that is relatively high overall, a second cap layer 144 with a reduced thickness is provided on the second conductor layer 142, so that the top surface of the second cap layer 144 (i.e., the top surface 140t of the gate structure 140) is lower than the top surface of the first cap layer 124 (i.e., the top surface 120t of the bit line structure 120), and the etching stop layer 184 provided in the second region 100B does not cover the top surface of the second cap layer 144. In this way, the top surface 140t of the gate structure 140 disposed in the second area 100B can be correspondingly lower than the top surface 120t of the bit line structure 120 disposed in the first area 100A, and the interlayer dielectric layer 196 further disposed physically contacts the top surface 140t of the gate structure 140, and the etching stop layer 182 covering the top surface 120t of the bit line structure 120, thereby, the bit line structure 120 and the gate structure 140 respectively disposed in the first area 100A and the second area 100B can both have a more improved structural reliability, so that the semiconductor device 10 can achieve a more optimized operating performance.

[0095] In addition, the semiconductor device 10 of this embodiment may further be provided with plugs 212 and 214 electrically connected to the bit line structure 120 and the gate structure 140, and a metal wire 216 connecting the plugs 212 and 214. Figure 2 As shown, after forming the semiconductor device 10 shown in FIG. 1 , plugs 212 and 214 are additionally disposed in the first region 100A and the second region 100B, respectively, and metal wires 216 are disposed in the first region 100A and the second region 100B simultaneously. The plug 212 disposed in the first region 100A penetrates the interlayer dielectric layer 196, the etching stop layer 182 and the first cap layer 124, and physically contacts the first conductor layer 122 of the bit line structure 120, so as to be electrically connected to the bit line structure 120, while the plug 214 disposed in the second region 100B penetrates the interlayer dielectric layer 196, the insulating layer 194 and the etching stop layer 184, and physically contacts the doped regions 104 disposed on both sides of the gate structure 140, so as to be electrically connected to both sides of the gate structure 140.

[0096] It should be noted that the semiconductor device 10 is also provided with a plurality of insulating structures 210 that penetrate the metal wire 216 and the interlayer dielectric layer 196 and partially extend into the insulating layer 194, the second cap layer 144 or the etching stop layer 184, so as to cut the metal wire 216 disposed in the second area 100B into a plurality of segments. In this way, the segments can be alternately arranged with each insulating structure 210 in the horizontal direction, so as to be used as wires (metal lines) electrically connected to different components. In one embodiment, the insulating structure 210 includes, for example, an insulating material such as silicon nitride or silicon carbonitride, and the plugs 212, 214 and the metal wire 216 include, for example, a metal material with a low resistance such as aluminum, titanium, copper or tungsten, preferably including tungsten, but not limited thereto. Thus, the plugs 212, 214 and the metal wire 216 are configured to form a first layer of metal interconnection lines (M0 interconnection) electrically connected to the bit line structure 120 and the gate structure 140, respectively. Furthermore, the metal wire 216 disposed above the gate structure 140 is effectively isolated by the insulating structure 210 to avoid problems such as short circuits, thereby further optimizing the operating performance of the semiconductor device 10 of this embodiment.

[0097] In order to enable a person skilled in the art to implement the semiconductor device 10 according to the aforementioned embodiment of the present invention, a method for manufacturing the semiconductor device 10 is further described below.

[0098] See also Figures 3 to 10 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device in a preferred embodiment of the present invention. First, Figure 3 As shown, a substrate 100 is provided, and shallow trench isolation 102 is formed in the first region 100A and the second region 100B of the substrate 100 to define active regions respectively. In one embodiment, the shallow trench isolation 102 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 by etching, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride, etc.), but the present invention is not limited thereto. Next, a plurality of buried gate structures 200 located in the substrate 100 and a dielectric layer 110 covering the substrate 100 are sequentially formed in the first region 100A, and a gate dielectric material layer 218 is formed in the second region 100B. In one embodiment, the manufacturing method of the buried gate structure 200 includes but is not limited to the following steps, such as first forming a plurality of trenches (not shown) in the substrate 100 that can simultaneously pass through the active area and the shallow trench isolation 102, and then, sequentially forming a dielectric layer 202 covering the entire surface of the trench, a gate dielectric layer 204 covering the surface of the lower half of the trench, a gate 206 filling the lower half of the trench, and a cap layer 208 filling the upper half of the trench in the trench, but is not limited to this.

[0099] The dielectric layer 110, for example, entirely covers the surface of the substrate 100 in the first region 100A, while the gate dielectric material layer 218 entirely covers the surface of the substrate 100 in the second region 100B. The gate dielectric material layer 218, for example, includes insulating materials such as silicon oxide or silicon oxynitride, and preferably includes the same insulating material and film thickness as the oxide layer 116 in the dielectric layer 110, but is not limited thereto. In one embodiment, the method for manufacturing the dielectric layer 110 and the gate dielectric material layer 218 includes but is not limited to the following steps, for example, firstly forming a first oxide material layer (not shown), a nitride material layer (not shown) and a second oxide material layer (not shown) on the substrate 100 in sequence to cover the first region 100A and the second region 100B as a whole, and then removing the second oxide material layer and the nitride material layer covering the second region 100B, so that the remaining first oxide material layer in the second region 100B forms the gate dielectric material layer 218, and the first oxide material layer, the nitride material layer and the second oxide material layer in the first region 100A are simultaneously formed as shown in FIG. Figure 3 The dielectric layer 110 shown includes an oxide layer 112, a nitride layer 114 and an oxide layer 116 stacked in sequence on the substrate 100, but is not limited thereto. Alternatively, the first oxide material layer, the nitride material layer and the second oxide material layer covering the second region 100B may be completely removed, and then the gate dielectric material layer 218 may be re-formed.

[0100] For example Figure 3 As shown, a first semiconductor material layer 252 is formed on the top surface of the dielectric layer 110 in the first area 100A and the top surface of the gate dielectric material layer 218 in the second area 100B. The first semiconductor material layer 252 includes, for example, semiconductor materials such as polycrystalline silicon and doped amorphous silicon, but is not limited thereto. It should be noted that since only the gate dielectric material layer 218 is formed on the substrate 100 in the second area 100B, the formed first semiconductor material layer 252 has top surfaces that are not flush with each other in the first area 100A and the second area 100B. Then, a mask layer HM1 is formed in the second area 100B, which entirely covers the first semiconductor material layer 252 formed in the second area 100B.

[0101] like Figure 4 As shown, with the help of Figure 3The mask layer HM1 shown in the figure is covered by an etching process to completely remove the first semiconductor material layer 252 formed in the first area 100A, and then the mask layer HM1 is completely removed. That is, after the etching process, only the first semiconductor material layer 252 formed on the gate dielectric material layer 218 is retained. Then, another etching process is performed with the help of another mask layer (not shown) to partially remove the dielectric layer 110 in the first area 100A and the substrate 100 thereunder, and an opening OP that can partially expose the substrate 100 is formed between two adjacent buried gate structures 200, defining the following: Figure 1 After the bit line plug 132 is formed, the other mask layer is completely removed.

[0102] like Figure 5 As shown, a second semiconductor material layer 226 is simultaneously formed on the first area 100A and the second area 100B, so that the second semiconductor material layer 226 formed in the first area 100A fills the opening OP and further covers the dielectric layer 110, and the second semiconductor material layer 226 formed in the second area 100B directly covers the first semiconductor material layer 252. The second semiconductor material layer 226, for example, includes semiconductor materials such as doped polysilicon and doped amorphous silicon, and preferably includes the same semiconductor material as the first semiconductor material layer 252, but is not limited thereto. It should be noted that since the second semiconductor material layer 226 formed in the first area 100A and the second area 100B are respectively located on the dielectric layer 110 and the first semiconductor material layer 252, the second semiconductor material layer 226 formed in the first area 100A and the second area 100B respectively have top surfaces that are not flush with each other. In one embodiment, the second semiconductor material layer 226 formed on the dielectric layer 110 has, for example, a thickness T1, and the second semiconductor material layer 226 formed on the first semiconductor material layer 252 has, for example, a thickness T2 and a relatively high top surface, and the thickness T1 is preferably equal to the thickness T2, but is not limited thereto.

[0103] like Figure 6As shown, a barrier material layer 228 (e.g., including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal material layer 230 (e.g., including metal materials with low resistance such as tungsten, aluminum or copper) and a capping material layer 224 (e.g., including insulating materials such as silicon oxide, silicon nitride or silicon oxynitride) are formed in sequence from bottom to top on the first area 100A and the second area 100B simultaneously, completely covering the second semiconductor material layer 226 in the first area 100A and the second area 100B. In one embodiment, the capping material layer 224 formed in the first area 100A and the second area 100B preferably has the same thickness T3, but is not limited thereto. It should be noted that, since a first semiconductor material layer 252 is additionally formed in the second area 100B, the barrier material layer 228, the metal material layer 230 and the capping material layer 224 formed in the first area 100A and the second area 100B respectively have top surfaces that are not flush with each other.

[0104] like Figure 7 As shown, the capping material layer 224, the metal material layer 230, the barrier material layer 228, the second semiconductor material layer 226, the first semiconductor material layer 252 and the dielectric layer 110 thereunder in the first area 100A and the second area 100B are simultaneously subjected to a patterning process, so that the semiconductor layer 126, the barrier layer 128, the metal layer 130 and the first capping layer 124 stacked in sequence from bottom to top on the top surface 110t of the dielectric layer 110 are formed in the first area 100A, and at the same time, the gate dielectric layer 118, the bottom semiconductor layer 152, the top semiconductor layer 146, the barrier layer 148, the metal layer 150 and the capping material layer 224 stacked in sequence from bottom to top are formed in the second area 100B. Thus, the semiconductor layer 126, the barrier layer 128 and the metal layer 130 in the first region 100A together form the first conductor layer 122, and the first conductor layer 122 and the first cap layer 124 stacked in sequence together form the bit line structure 120. In addition, the semiconductor layer 126 filling the opening OP also simultaneously forms the bit line plug 132 formed integrally with the semiconductor layer 126 in the bit line structure 120. On the other hand, the bottom semiconductor layer 152, the top semiconductor layer 146, the barrier layer 148 and the metal layer 150 in the second region 100B together form the second conductor layer 142, and the capping material layer 224 covers the second conductor layer 142. Among them, the top surface 142t of the second conductor layer 142 in the second area 100B is higher than the top surface 122t of the first conductor layer 122 in the first area 100A, and the top surface 224t of the capping material layer 224 in the second area 100B is also higher than the top surface 124t of the first capping layer 124 in the first area 100A (i.e., the top surface 120t of the bit line structure 120).

[0105] Next, a bit line spacer 160 is formed on the sidewall 120s of the bit line structure 120 in the first region 100A, and a gate spacer 170 is formed on the sidewalls of the second conductive layer 142 and the capping material layer 224 in the second region 100B. In one embodiment, the method for manufacturing the bit line spacers 160 and the gate spacers 170 includes but is not limited to the following steps, for example, using the same process to form a first spacer material layer (for example, including silicon nitride, silicon carbonitride) and a second spacer material layer (for example, including silicon oxide, silicon oxynitride) that respectively cover the bit line structure 120 in the first area 100A, the second conductor layer 142 in the second area 100B, and the capping material layer 224, and after performing a back etching process on the first spacer material layer and the second spacer material layer, spacers 162 and spacers 164 stacked in sequence are formed on the sidewalls 120s of the bit line structure 120 to form the bit line spacers 160 together, and spacers 172 and spacers 174 are formed on the sidewalls of the second conductor layer 142 and the capping material layer 224 to form the gate spacers 170 together. In this operation, the spacers 162 of the bit line spacers 160 and the spacers 172 of the gate spacers 170 preferably include the same material and thickness, and the spacers 164 of the bit line spacers 160 and the spacers 174 of the gate spacers 170 also include the same material and thickness, but not limited thereto.

[0106] For example Figure 7 As shown, an etch stop material layer 280 and an insulating material layer 290 are simultaneously formed in the first area 100A and the second area 100B. The etch stop material layer 280 and the insulating material layer 290 are integrally covered on the bit line structure 120 in the first area 100A, and the second conductor layer 142 and the capping material layer 224 in the second area 100B. It should be noted that, since a bottom semiconductor layer 152 is additionally formed in the second area 100B, the formed etch stop material layer 280 has top surfaces that are not flush with each other in the first area 100A and the second area 100B, respectively, wherein the etch stop material layer 280 formed in the second area 100B has a relatively higher top surface.

[0107] like Figure 8As shown, a planarization process is performed to partially remove the insulating material layer 290 formed in the first area 100A and the second area 100B, and partially remove the etching stop material layer 280 formed in the second area 100B, thereby exposing the top surface 224t of the capping material layer 244. It should be noted that since the first area 100A has a relatively high component density, the planarization process uses the etching stop material layer 280 formed in the first area 100A as a stop layer, so that the etching stop material layer 280 with a relatively high setting position but in a sporadic configuration in the second area 100B is removed. In this way, after the planarization process is performed, the insulating material layer 290 in the first area 100A and the second area 100B, and the etching stop material layer 280 formed in the first area 100A and the second area 100B have top surfaces flush with each other.

[0108] like Fig. 9 As shown, a mask layer HM2 is formed in the first area 100A, and an etch-back process is performed on the mask layer HM2 to partially remove the insulating material layer 290, the etching stop material layer 280, the gate spacer 170 and the capping material layer 244 in the second area 100B, and an insulating layer 194, an etching stop layer 184, a gate spacer 170 and a second capping layer 144 are formed in the second area 100B. The second capping layer 144 has a relatively small thickness T4. In this way, the second conductor layer 142 and the second capping layer 144 stacked in sequence on the gate dielectric layer 118 together form the gate structure 140. It should be noted that the insulating layer 194 formed in the second area 100B covers the etching stop layer 184 and has a second plane P2 flush with the top surface 140t of the etching stop layer 184 and the gate structure 140. On the other hand, after the etch-back process is performed, the etching stop material layer 280 and the insulating material layer 290 in the first region 100A simultaneously form the insulating layer 192 and the etching stop layer 182 .

[0109] Thus, the Figure 1The insulating layer 190 and the etching stop layer 180 are formed as shown, wherein the insulating layer 190 includes an insulating layer 192 formed in the first area 100A and an insulating layer 194 formed in the second area 100B, and the etching stop layer 180 includes an etching stop layer 182 formed in the first area 100A and an etching stop layer 184 formed in the second area 100B. The insulating layer 192 has a first plane P1 flush with the etching stop layer 182 covering the top surface 120t of the bit line structure 120, and the insulating layer 194 has a second plane P2 flush with the etching stop layer 184 and the top surface 140t of the gate structure 140, and the first plane P1 is lower than the second plane P2. The etch stop layer 182 covers the substrate 100 in the first region 100A and the top surface 120 t and sidewall 120 s of the bit line structure 120 . The etch stop layer 184 covers the substrate 100 in the second region 100B and the sidewall 140 s of the gate structure 140 .

[0110] like Fig.10 As shown, the mask layer HM2 is removed, and then an interlayer dielectric material layer 296 is simultaneously formed in the first area 100A and the second area 100B, which integrally covers the top surface of the insulating layer 192 and the etching stop layer 182 in the first area 100A, and covers the top surface of the insulating layer 194, the etching stop layer 184, the gate spacer 170 and the gate structure 140 in the second area 100B. The interlayer dielectric material layer 296 formed in the first area 100A and the second area 100B has top surfaces flush with each other. Fig.10 The interlayer dielectric material layer 296 shown in the figure is then subjected to an etch-back process to form a Figure 1 The interlayer dielectric layer 196 is shown. Thus, the manufacturing of the semiconductor device 10 in this embodiment is completed.

[0111] According to the manufacturing method of the semiconductor device 10 of this embodiment, a bottom semiconductor layer 152 is additionally formed in the second area 100B, so that the second conductor layer 142 has a relatively high top surface 142t, and the capping material layer 244 thereon has a relatively high top surface 224t. Then, when the insulating layer 194 and the etching stop layer 184 are formed in the second area 100B, the thickness T3 of the capping material layer 244 is simultaneously thinned, thereby forming a second capping layer 144 with a relatively small thickness T4. Thus, the top surface 140t of the gate structure 140 formed in the second area 100B can be correspondingly lower than the top surface 120t of the bit line structure 120 formed in the first area 100A, and the interlayer dielectric layer 196 further formed subsequently, which physically contacts the top surface 140t of the gate structure 140, and the etching stop layer 182 covering the top surface 120t of the bit line structure 120, enables the bit line structure 120 and the gate structure 140 respectively formed in the first area 100A and the second area 100B to have more improved structural reliability, so that the semiconductor device 10 can achieve more optimized operating performance.

[0112] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the method for manufacturing the semiconductor device of the present invention may also have other aspects and is not limited to the above. Other embodiments or variations of the method for manufacturing the semiconductor device of the present invention will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments, and no longer repeats the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0113] See also Figure 11 to Figure 12 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 in another preferred embodiment of the present invention. The method for manufacturing the semiconductor device 10 in this embodiment is substantially the same as the method for manufacturing the semiconductor device 10 in the aforementioned embodiment, the main difference being that in the implementation of Figure 8 During the planarization process shown, an etch stop material layer 280 formed in the second region 100B and disposed at a relatively high position is first used as a stop layer.

[0114] In detail, Fig.11As shown, when the planarization process of this embodiment is performed, the insulating material layer 290 in the second area 100B is partially removed until it is flush with the etching stop material layer 280 in the second area 100B, and then the insulating material layer 290 in the second area 100B is further removed by over-etching of the polishing slurry to form a concave top surface, and the insulating material layer 290 in the first area 100A is removed until the etching stop material layer 280 in the first area 100BA is exposed. In other words, the planarization process in this embodiment does not remove the etching stop material layer 280 covering the top surface 244t of the capping material layer 244. In this way, after the planarization process is performed, the insulating material layer 290 in the second area 100B has a concave top surface, and the etching stop material layers 280 formed in the first area 100A and the second area 100B have top surfaces that are not flush with each other.

[0115] like Fig.12 As shown, a mask layer HM3 is formed in the first area 100A, and an etch-back process is performed on the mask layer HM2 to partially remove the insulating material layer 290, the etching stop material layer 280, the gate spacer 170 and the capping material layer 244 in the second area 100B, and an insulating layer 194, an etching stop layer 184, a gate spacer 170 and a second cap layer 144 are formed in the second area 100B. The second cap layer 144 has a relatively small thickness T4. In this way, the second conductor layer 142 and the second cap layer 144 stacked in sequence on the gate dielectric layer 118 together form the gate structure 140. Among them, the insulating layer 194 formed in the second area 100B also has a second plane P2 flush with the etching stop layer 184 and the top surface 140t of the gate structure 140. On the other hand, after the etch-back process, the etching stop material layer 280 and the insulating material layer 290 in the first region 100A simultaneously form the insulating layer 192 and the etching stop layer 182 . The insulating layer 192 also has a first plane P1 that is lower than the second plane P2 .

[0116] Subsequently, as in the above embodiment Fig.10 As shown, after the interlayer dielectric material layer 296 is simultaneously formed in the first area 100A and the second area 100B, an etch-back process is performed to form a dielectric layer 296 as shown in FIG. Figure 1 The interlayer dielectric layer 196 is shown, and the fabrication of the semiconductor device 10 in this embodiment is completed.

[0117] In general, the semiconductor device and the manufacturing method of the present invention reduce the height difference of components in different regions of the semiconductor device and improve the structural reliability of the components by setting etching stop layers with different coverage in different regions and / or simultaneously thinning the thickness of the cap layer in a specific region during the implementation of a specific process (such as a planarization process or a back etching process, etc.). As a result, the components (such as memory cells and other components) formed subsequently can be formed on a relatively flat setting plane, effectively optimizing the component performance and operating performance of the semiconductor device.

[0118] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate including a first region and a second region; A bit line structure, disposed on the substrate and located in the first region; A gate structure, disposed on the substrate and located in the second region; An etching stop layer, disposed on the substrate, covering the top surface and sidewalls of the bit line structure and the sidewalls of the gate structure; as well as An interlayer dielectric layer covers the bit line structure and the gate structure, wherein the interlayer dielectric layer physically contacts the etching stop layer covering the top surface of the bit line structure and the top surface of the gate structure.

2. The semiconductor device according to claim 1, wherein: Also includes: An insulating layer is disposed on the substrate and located between the bit line structure and the gate structure, wherein the insulating layer includes a first plane located in the first region and a second plane located in the second region, and the first plane is higher than the second plane.

3. The semiconductor device according to claim 1, wherein: The bit line structure further includes a first conductor layer and a first cap layer which are sequentially arranged, and the gate structure further includes a second conductor layer and a second cap layer which are sequentially arranged.

4. The semiconductor device according to claim 3, characterized in that A top surface of the second conductor layer is higher than a top surface of the first conductor layer.

5. The semiconductor device according to claim 3, characterized in that A top surface of the second cover layer is lower than a top surface of the first cover layer.

6. The semiconductor device according to claim 3, characterized in that The first conductor layer includes a semiconductor layer, a barrier layer and a metal layer stacked in sequence, and the second conductor layer includes a bottom semiconductor layer, a top semiconductor layer, a barrier layer and a metal layer stacked in sequence, wherein the top surface of the semiconductor layer in the first conductor layer is higher than the top surface of the bottom semiconductor layer in the second conductor layer.

7. The semiconductor device according to claim 6, characterized in that The thickness of the first cover layer is greater than the thickness of the second cover layer.

8. The semiconductor device according to claim 6, characterized in that Also includes: At least one bit line plug is disposed below the bit line structure and partially extends into the substrate, wherein the semiconductor layer in the first conductor layer and the at least one bit line plug are integrally formed.

9. The semiconductor device according to claim 1, wherein: Also includes: A bit line spacer is disposed on a bit line sidewall of the bit line structure and between the bit line structure and the etching stop layer covering the bit line structure; as well as The gate spacer is arranged on the bit line sidewall of the gate structure and between the gate structure and the etching stop layer arranged on the sidewall of the gate structure.

10. The semiconductor device according to claim 9, characterized in that The etching stop layer covering the bit line structure physically contacts the top surface of the bit line spacer.

11. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a bit line structure on the substrate, located in the first region; forming a gate structure on the substrate, located in the second region; forming an etching stop layer to cover the top surface and sidewalls of the bit line structure and the sidewalls of the gate structure; as well as An interlayer dielectric layer is formed to cover the bit line structure and the gate structure, wherein the interlayer dielectric layer physically contacts the etching stop layer covering the top surface of the bit line structure and the top surface of the gate structure.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that: Also includes: forming an etching stop material layer to entirely cover the bit line structure and the gate structure; as well as An insulating material layer is formed on the substrate, covering the etching stop material layer and partially located between the bit line structure and the gate structure.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: Also includes: A planarization process is performed to remove the insulating material layer covering the top surface of the gate structure and the top surface of the bit line structure.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: When performing the planarization process, the etching stop material layer covering the top surface of the gate structure is removed simultaneously to form the etching stop layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: Forming the gate structure and the bit line structure also includes: forming a first conductor layer and a first cap layer stacked in sequence on the substrate, the first conductor layer and the first cap layer being located in the first region; forming a second conductor layer and a capping material layer stacked in sequence on the substrate, located in the second region, wherein the capping material layer and the first capping layer have the same thickness, and a top surface of the capping material layer is higher than a top surface of the first capping layer; and An etch-back process is performed to partially remove the insulating material layer and the capping material layer in the second region to form an insulating layer and a second capping layer, wherein a top surface of the second capping layer is lower than a top surface of the first capping layer.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The insulating layer includes a first plane located in the first region and a second plane located in the second region, wherein the first plane is higher than the second plane.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that: When performing the etch-back process, the etching stop material layer covering the top surface of the gate structure is removed simultaneously to form the etching stop layer.

18. The method for manufacturing a semiconductor device according to claim 11, characterized in that: Also includes: forming a bit line spacer on the sidewall of the bit line structure, between the bit line structure and the etching stop layer covering the bit line structure; as well as A gate spacer is formed on the sidewall of the gate structure, between the gate structure and the etching stop layer disposed on the sidewall of the gate structure.

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