A semiconductor device, a manufacturing method thereof, and a semiconductor system

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same, as well as a semiconductor system. The manufacturing method includes: providing an initial stacked structure comprising multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer, the step surface of each step exposing the surface of the gate sacrificial layer; forming a buffer layer covering the step surface and sidewalls of each step; wherein the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step; and doping the buffer layer such that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer; wherein the second sub-buffer layer has a greater etch selectivity to the doped first sub-buffer layer than the second sub-buffer layer has to the undoped first sub-buffer layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and a semiconductor system. Background Technology

[0002] In a three-dimensional memory, gate layers and interlayer insulating layers can be alternately stacked to form a stacked structure, which includes a core region and a step region. The core region can be used to form a channel structure, and the step region can be used to form a step structure. Furthermore, contact holes extending to the corresponding gate layer can be formed in the step region, and conductive material can be filled into the contact holes to form a contact structure (CT) for leading out electrical signals from the corresponding gate layer.

[0003] Currently, there is an urgent need to improve the manufacturing methods of semiconductor devices to enhance their reliability. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, as well as a semiconductor system.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising:

[0007] An initial stack-up structure is provided, the initial stack-up structure including multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer, the step surface of each step exposing the surface of the gate sacrificial layer;

[0008] A buffer layer is formed to cover the step surface and sidewalls of each step; wherein the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step;

[0009] The buffer layer is doped such that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer; wherein the second sub-buffer layer has a greater etching selectivity to the doped first sub-buffer layer than the second sub-buffer layer has a greater etching selectivity to the undoped first sub-buffer layer.

[0010] In some embodiments, the doping process on the buffer layer includes:

[0011] The buffer layer is subjected to ion implantation.

[0012] The buffer layer is then annealed.

[0013] In some embodiments, the ion implantation angle during the ion implantation process is substantially perpendicular to the surface of the first sub-buffer layer;

[0014] The ion implantation process performed on the buffer layer includes:

[0015] Ion implantation was performed on the first sub-buffer layer.

[0016] In some embodiments, after the buffer layer is doped, the manufacturing method further includes:

[0017] The second sub-buffer layer covering the sidewalls of each step is removed using a first wet etching process to expose the sidewalls of each step.

[0018] In some embodiments, a portion of the first sub-buffer layer is doped to form the doped first sub-buffer layer, and the undoped first sub-buffer layer is located between the gate sacrificial layer and the doped first sub-buffer layer.

[0019] After removing the second sub-buffer layer covering the sidewalls of each step using a first wet etching process to expose the sidewalls of each step, the manufacturing method further includes:

[0020] The gate sacrificial layer and the undoped first sub-buffer layer are removed using a second wet etching process to form a gap; wherein, in the same etching process, the etching rate of the gate sacrificial layer is greater than the etching rate of the doped first sub-buffer layer.

[0021] A conductive material is filled into the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

[0022] In some embodiments, the doped first sub-buffer layer is formed by doping all of the first sub-buffer layers.

[0023] After removing the second sub-buffer layer covering the sidewalls of each step using a first wet etching process to expose the sidewalls of each step, the manufacturing method further includes:

[0024] The gate sacrificial layer is removed using a second wet etching process to form a gap; wherein, in the same etching process, the etching rate of the gate sacrificial layer is greater than the etching rate of the doped first sub-buffer layer.

[0025] A conductive material is filled into the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

[0026] In some embodiments, the etching solution in the first wet etching process includes a phosphoric acid solution or a hydrofluoric acid solution;

[0027] The etching solution in the second wet etching process includes sulfuric acid solution or sulfurous acid solution.

[0028] In some embodiments, after filling the gap with conductive material to form a gate layer, the manufacturing method further includes:

[0029] A filling layer is formed covering the doped first sub-buffer layer and the sidewalls of each step;

[0030] A contact structure is formed that sequentially penetrates the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

[0031] In some embodiments, forming a contact structure that sequentially penetrates the fill layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer includes:

[0032] A contact hole is formed that penetrates the fill layer along the stacking direction and extends to the corresponding doped first sub-buffer layer; wherein the doped first sub-buffer layer serves as an etch stop layer;

[0033] Remove the doped first sub-buffer layer located at the bottom of the contact hole, so that the contact hole extends to the corresponding gate layer;

[0034] The contact hole is filled with conductive material to form a contact structure.

[0035] In some embodiments, the material of the buffer layer is the same as the material of the gate sacrificial layer.

[0036] In some embodiments, the doping element in the doping process includes at least one of the following: carbon and boron.

[0037] In a second aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising:

[0038] The stacked structure includes multiple steps, each step including a gate layer and an interlayer insulating layer, and adjacent steps are separated by the interlayer insulating layer;

[0039] A first sub-buffer layer is doped, covering at least a portion of the step surface of each step and exposing the sidewalls of each step; wherein the first sub-buffer layer is in contact with the gate layer of each step.

[0040] In some embodiments, the doped first sub-buffer layer protrudes from the sidewall of the corresponding step.

[0041] In some embodiments, the semiconductor device further includes:

[0042] A filling layer that covers the doped first sub-buffer layer and the sidewalls of each step;

[0043] The contact structure extends sequentially through the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

[0044] In some embodiments, the gate layer includes a portion of the gate layer that is in contact with the doped first sub-buffer layer and a portion of the gate layer that is not in contact with the doped first sub-buffer layer.

[0045] The thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the stacking direction is greater than or equal to the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the stacking direction.

[0046] In some embodiments, the material of the doped first sub-buffer layer includes silicon nitride doped with carbon and / or boron.

[0047] Thirdly, embodiments of this disclosure provide a semiconductor system, the semiconductor system comprising:

[0048] At least one semiconductor device as described in the above technical solution; and

[0049] A controller is coupled to the semiconductor device and configured to control the semiconductor device.

[0050] This disclosure provides a semiconductor device and its manufacturing method, as well as a semiconductor system. In this embodiment, the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewall of the step. The buffer layer is doped such that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer. Thus, the second sub-buffer layer has a higher etch selectivity to the doped first sub-buffer layer than to the undoped first sub-buffer layer. This increases the process window for removing the second sub-buffer layer and reduces damage to the doped first sub-buffer layer, thereby improving leakage and short circuits between adjacent word lines and ultimately enhancing the reliability of the semiconductor device. Attached Figure Description

[0051] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0052] Figures 2A to 2I A cross-sectional structural diagram of the semiconductor device manufacturing process provided in the embodiments of this disclosure;

[0053] Figure 3 A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0054] Figure 4 A block diagram of a semiconductor system provided in an embodiment of this disclosure;

[0055] Figure 5 A block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0056] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0057] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0058] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0063] In three-dimensional memory (e.g., NAND flash memory), gate layers and interlayer insulating layers can be alternately stacked to form a stacked structure, which includes a core region and a step region. The core region can be used to form a channel structure, and the step region can be used to form a step structure. In three-dimensional memory, each gate layer needs to be connected to a contact structure located in the step region, thereby connecting each word line (WL) to a metal terminal. In other words, by applying voltage to individual word lines (i.e., individual memory cells) through the contact structure, control of the three-dimensional memory can be achieved.

[0064] However, from a manufacturing process perspective, the different gate layers (i.e., word lines) are located at different heights, meaning the distance between different gate layers and the top film is different. Therefore, during the etching process to form contact holes, it's crucial to ensure that the lower word lines are reached while preventing the upper word lines from being penetrated. Consequently, the thickness (THK) of the word lines connected to the contact structure needs to be increased, thereby enlarging the contact hole forming window. This thicker portion of the word lines is typically referred to as the "big head."

[0065] In a specific example, a gate sacrificial layer (e.g., silicon nitride (SiN)) and an interlayer insulating layer (e.g., silicon oxide) can be alternately stacked to form an initial stacked structure. The initial stacked structure is then etched to form multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer. Next, a dielectric layer (e.g., topologically selective silicon nitride (TS SiN)) can be formed covering the step surface of each step. Subsequently, in a gate replacement process, both the gate sacrificial layer and the dielectric layer can be replaced with a gate layer, i.e., word lines are formed, thereby increasing the thickness of the portion of the word line connected to the contact structure (i.e., forming a "big head"), and thus increasing the process window for forming contact holes.

[0066] In the aforementioned technical solution, it is necessary to remove the dielectric layer covering the sidewalls of the step to avoid leakage and short circuits between different word lines. However, the above technical solution is difficult to precisely remove the dielectric layer covering the sidewalls of the step, which can easily lead to problems of insufficient etching or over-etching. On the one hand, if the dielectric layer covering the sidewalls of the step is not completely removed, i.e., the sidewall remove window is insufficient, insufficient etching after the gate replacement process may lead to leakage and short circuits between different word lines. On the other hand, if the dielectric layer covering the sidewalls of the step is completely removed (i.e., over-etching), the dielectric layer on the step surface may be damaged, i.e., film roughness. During the gate replacement process, for example, in the process of forming a tungsten layer using tungsten hexafluoride (WF6), over-etching may lead to the diffusion of fluorine, which in turn may cause short circuits between different word lines.

[0067] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, as well as a semiconductor system. In these embodiments, the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewall of the step. The buffer layer is doped such that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer. Thus, the second sub-buffer layer has a higher etch selectivity to the doped first sub-buffer layer than to the undoped first sub-buffer layer. This increases the process window for removing the second sub-buffer layer and reduces damage to the doped first sub-buffer layer, thereby improving leakage and short circuits between adjacent word lines and ultimately enhancing the reliability of the semiconductor device.

[0068] refer to Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 1 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising:

[0069] Step S101: Provide an initial stacked structure, the initial stacked structure including multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer, the step surface of each step exposing the surface of the gate sacrificial layer;

[0070] Step S102: Form a buffer layer covering the step surface and sidewalls of each step; wherein the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step.

[0071] Step S103: The buffer layer is doped so that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer; wherein the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer.

[0072] refer to Figures 2A to 2I , Figures 2A to 2I This is a cross-sectional structural diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of this disclosure. (In conjunction with...) Figure 1 as well as Figures 2A to 2I The present disclosure describes in detail the manufacturing method of the semiconductor device provided in the embodiments.

[0073] Here, the plane containing the gate sacrificial layer and the interlayer insulating layer is defined as the XY plane, and the stacking direction of the stacked structure is defined as the Z direction. Figures 2A to 2I All of these diagrams illustrate the cross-sectional structure of the XZ plane during the manufacturing process of semiconductor devices.

[0074] In this embodiment of the present disclosure, in step S101, an initial stacked structure 200 is provided. The initial stacked structure 200 includes multiple steps 206. Each step 206 includes a gate sacrificial layer 202 and an interlayer insulating layer 204. The step surface 208 of each step 206 exposes the surface of the gate sacrificial layer 202.

[0075] like Figure 2A As shown, the initial stacked structure 200 includes alternately stacked gate sacrificial layers 202 and interlayer insulating layers 204. Etching the initial stacked structure 200 can form multiple steps 206, each step 206 including a gate sacrificial layer 202 and an interlayer insulating layer 204. Each step 206 includes a step surface 208 and a sidewall 210. The step surface 208 is parallel to the XY plane, and the sidewall 210 is parallel to the YZ plane. The step surface 208 of each step 206 exposes the surface of the gate sacrificial layer 202, and the sidewall 210 of each step exposes both the gate sacrificial layer 202 and the sidewall of the interlayer insulating layer 204.

[0076] Figure 2A The diagram illustrates two steps, namely, a first step and a second step, with the first step located above the second step. The first step includes a first step surface and a first sidewall, and the second step includes a second step surface and a second sidewall. The first step surface and the second step surface have different heights along the Z direction, and there is a first sidewall between the first step surface and the second step surface. That is, the first step surface and the second step surface are located on both sides of the first sidewall along the X direction.

[0077] The embodiments disclosed herein do not impose any special limitation on the number of steps included in the initial stacked structure. Figure 2A The two steps are only shown and do not constitute a limitation on the scope of protection of this disclosure.

[0078] In some embodiments, the process for forming the gate sacrificial layer and the interlayer insulating layer may include, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof.

[0079] In some embodiments, the material of the gate sacrificial layer may include, but is not limited to, silicon nitride, and the material of the interlayer insulating layer may include, but is not limited to, silicon oxide.

[0080] In this embodiment of the present disclosure, in step S102, a buffer layer 212 is formed covering the step surface 208 and sidewall 210 of each step 206; wherein, the buffer layer 212 includes a first sub-buffer layer 214 covering the step surface 208 of the step 206 and a second sub-buffer layer 216 covering the sidewall 210 of the step 206.

[0081] like Figure 2B As shown, a first sub-buffer layer 214 (e.g., forming a step surface 208 covering step 206) is formed. Figure 2B (as shown in the dashed box) and the second sub-buffer layer 216 covering the sidewall 210 of the step 206 (as shown in the dashed box). Figure 2B (As shown in the dashed circle); wherein, the first sub-buffer layer 214 and the second sub-buffer layer 216 together form the buffer layer 212. The first sub-buffer layer 214 is parallel to the XY plane, and the second sub-buffer layer 216 is parallel to the YZ plane.

[0082] Here, the materials of the first and second sub-buffer layers are the same. In the same etching process, the etching rates for the first and second sub-buffer layers can be the same or different. For example, the material of the buffer layer may include a topology-selective material, such that the etching rates for the horizontal portion (i.e., the first sub-buffer layer) and the vertical portion (i.e., the second sub-buffer layer) of the buffer layer are different. For instance, the density of the second sub-buffer layer covering the sidewall of the step is less than the density of the first sub-buffer layer covering the step surface, and the topology-selective material forming the buffer layer has an anisotropic etching rate. Therefore, in the same etching process, the etching rate for the second sub-buffer layer can be greater than the etching rate for the first sub-buffer layer.

[0083] In this embodiment of the disclosure, the materials of the buffer layer 212 and the gate sacrificial layer 202 may be the same or different.

[0084] Here, the buffer layer and the gate sacrificial layer can be made of the same material. In the same etching process, the etching rate of the buffer layer and the etching rate of the gate sacrificial layer can be the same or different. For example, different processes can be used to form the buffer layer and the gate sacrificial layer. Thus, even if the materials of the buffer layer and the gate sacrificial layer are the same, the etching rates of the buffer layer and the gate sacrificial layer can be different. For example, a buffer layer formed using an ALD process has good step coverage, but the film quality of the buffer layer is generally poor. Thus, even if the materials of the buffer layer and the gate sacrificial layer are the same, in the same etching process, the etching rate of the buffer layer can be greater than the etching rate of the gate sacrificial layer.

[0085] In some embodiments, the process for forming the buffer layer may include, but is not limited to, ALD.

[0086] In this embodiment of the present disclosure, in step S103, the buffer layer 212 is doped, such that at least a portion of the first sub-buffer layer 214 forms a doped first sub-buffer layer 218, and the remaining first sub-buffer layer 214 forms an undoped first sub-buffer layer 220; wherein, the second sub-buffer layer 216 has a greater etching selectivity to the doped first sub-buffer layer 218 than the second sub-buffer layer 216 has a greater etching selectivity to the undoped first sub-buffer layer 220.

[0087] In this embodiment of the disclosure, the buffer layer 212 is doped, including:

[0088] Ion implantation is performed on buffer layer 212, including ion implantation on first sub-buffer layer 214;

[0089] The buffer layer 212 is annealed, for example, by rapid thermal annealing (RTA).

[0090] like Figure 2C As shown, the buffer layer 212 is doped, and the doping process includes ion implantation and annealing. More specifically, the first sub-buffer layer 214 covering the step surface 208 of the step 206 is ion implanted, and the buffer layer 212 is annealed. Figure 2C The arrow indicates the direction of ion implantation, which is basically perpendicular to the surface of the first sub-buffer layer 214.

[0091] Here, "the direction of ion implantation is basically perpendicular to the surface of the first sub-buffer layer" means that the angle between the direction of ion implantation and the XY plane is 90 degrees, or the difference between the angle between the direction of ion implantation and the XY plane and 90 degrees meets the process error requirements.

[0092] It should be noted that the orthographic projection of the second sub-buffer layer onto the XY plane falls within the orthographic projection range of the first sub-buffer layer onto the XY plane. Therefore, during ion implantation of the buffer layer in a direction substantially perpendicular to the XY plane, the second sub-buffer layer is obscured by the first sub-buffer layer. In other words, ion implantation of the buffer layer in a direction substantially perpendicular to the XY plane means that only the first sub-buffer layer will be ion implanted, and the second sub-buffer layer will not be ion implanted.

[0093] In this embodiment of the disclosure, the doping element in the doping process includes at least one of the following: carbon and boron. In other words, the implanted element in the ion implantation process includes carbon and / or boron.

[0094] like Figure 2DAs shown, the buffer layer 212 is annealed to promote bonding between the ion-implanted elements and the elements in the first sub-buffer layer 214, thereby achieving doping. In the same etching process, the etching rate of the undoped first sub-buffer layer 220 is greater than the etching rate of the doped first sub-buffer layer 218, and the etching rate of the second sub-buffer layer 216 is greater than the etching rate of the doped first sub-buffer layer 218.

[0095] Here, the etching selectivity of the second sub-buffer layer over the doped first sub-buffer layer is the ratio between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer in the same etching process; similarly, the etching selectivity of the second sub-buffer layer over the undoped first sub-buffer layer is the ratio between the etching rate of the second sub-buffer layer and the etching rate of the undoped first sub-buffer layer in the same etching process. Since the etching rate of the undoped first sub-buffer layer is greater than the etching rate of the doped first sub-buffer layer in the same etching process, the etching selectivity of the second sub-buffer layer over the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer over the undoped first sub-buffer layer.

[0096] In some embodiments, the etching rate for the undoped first sub-buffer layer and the etching rate for the second sub-buffer layer may be the same or different in the same etching process. For example, during the formation of the buffer layer, the density of the second sub-buffer layer covering the sidewall of the step is less than the density of the first sub-buffer layer covering the step surface. Therefore, in the same etching process, the etching rate for the second sub-buffer layer may be greater than the etching rate for the undoped first sub-buffer layer.

[0097] In some embodiments, such as Figure 2D As shown, the first sub-buffer layer 214 is divided along the Z-direction into a doped first sub-buffer layer 218 and an undoped first sub-buffer layer 220. A portion of the first sub-buffer layer 214 is doped to form the doped first sub-buffer layer 218, while the undoped first sub-buffer layer 220 is located between the gate sacrificial layer 202 and the doped first sub-buffer layer 218. In other words, the sum of the thicknesses of the doped first sub-buffer layer 218 and the undoped first sub-buffer layer 220 along the Z-direction is the same as the thickness of the first sub-buffer layer 214 along the Z-direction. It should be noted that after the doped first sub-buffer layer is partially doped to form the doped first sub-buffer layer, the doped first sub-buffer layer and the gate layer (i.e., the word line layer) make contact at the "larger end" after the gate replacement process.

[0098] In other embodiments, the entire first sub-buffer layer is doped to form a doped first sub-buffer layer, which is located above the gate sacrificial layer and in contact with it. In other words, the thickness of the doped first sub-buffer layer along the Z-direction is the same as that of the first sub-buffer layer along the Z-direction. It should be noted that after the gate replacement process is performed, the gate layer (i.e., the word line layer) has a uniform thickness along the Z-direction, meaning there is no "large end" in the gate layer. Thus, the doped first sub-buffer layer and the gate layer are in contact.

[0099] In this embodiment of the present disclosure, the thickness of the first sub-buffer layer along the Z direction and the concentration of doped elements in the first sub-buffer layer can be controlled by controlling the parameters of the ion implantation process and the annealing process, such as the ion implantation energy, ion implantation depth, ion implantation concentration, and the temperature and time of the annealing process. This increases the difference between the etching rate of the second sub-buffer layer and the etching rate of the first sub-buffer layer in the same etching process, that is, increases the etching selectivity of the second sub-buffer layer for the first sub-buffer layer.

[0100] In some embodiments, the higher the ion implantation energy and the greater the ion implantation depth, the greater the thickness of the doped first sub-buffer layer along the Z direction.

[0101] In some embodiments, the higher the ion implantation concentration, the greater the difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer, that is, the greater the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer.

[0102] In some embodiments, the selection of annealing temperature and time is related to the type of material and dopant element of the buffer layer. Generally, the longer the annealing time, the greater the doping depth of the first sub-buffer layer and the greater the thickness of the doped first sub-buffer layer along the Z direction.

[0103] In this embodiment of the disclosure, after step S103, the manufacturing method further includes:

[0104] Using a first wet etching process, the second sub-buffer layer 216 covering the sidewall 210 of each step 206 is removed to expose the sidewall 210 of each step 206.

[0105] like Figure 2EAs shown, in the same etching process, the etching rate of the undoped first sub-buffer layer 220 (or the second sub-buffer layer 216) is greater than the etching rate of the doped first sub-buffer layer 218. By using the first wet etching process to remove the second sub-buffer layer 216, the process window for removing the second sub-buffer layer 216 can be increased and the damage to the doped first sub-buffer layer 218 can be reduced. That is, while completely removing the second sub-buffer layer 216, damage to the doped first sub-buffer layer 218 can be avoided as much as possible. In this way, leakage and short circuit between adjacent word lines can be improved, thereby improving the reliability of the semiconductor device.

[0106] In this embodiment of the disclosure, the etching solution in the first wet etching process may include a phosphoric acid solution (H3PO4) or a hydrofluoric acid solution (HF).

[0107] Here, a phosphoric acid solution or a hydrofluoric acid solution can be used to remove the second sub-buffer layer covering the sidewall of the step. This embodiment of the present disclosure does not impose a specific limitation on the concentration of the etching solution in the first wet etching process; the concentration of the etching solution in the first wet etching process can be adjusted according to the concentration of the doping element in the first sub-buffer layer.

[0108] Still Figure 2E As shown, a portion of the first sub-buffer layer is doped to form a doped first sub-buffer layer 218, which protrudes from the sidewall 210 of the corresponding step 206. More specifically, the doped first sub-buffer layer can be divided along the X direction into a main body 218a and a protrusion 218b. The main body 218a contacts the undoped first sub-buffer layer 220, while the protrusion 218b does not contact the undoped first sub-buffer layer 220 and protrudes from the sidewall 210 of the corresponding step 206. In other words, the orthographic projection of the main body 218a in the XY plane coincides with the orthographic projection of the undoped first sub-buffer layer 220 in the XY plane, while the orthographic projection of the protrusion 218b in the XY plane is outside the range of the orthographic projection of the undoped first sub-buffer layer 220 in the XY plane.

[0109] It should be noted that, Figure 2E In the schematic cross-sectional view, the protrusion 218b has an arc-shaped outline. However, this embodiment does not impose any specific limitations on the outline shape of the protrusion. In the first wet etching process, if the etching rate of the second sub-buffer layer is much greater than the etching rate of the doped first sub-buffer layer, then the morphology of the doped first sub-buffer layer may not be significantly damaged during the etching process to remove the second sub-buffer layer. In this case, the protrusion of the doped first sub-buffer layer may have a rectangular outline in the schematic cross-sectional view.

[0110] In other embodiments, the entire first sub-buffer layer is doped to form a doped first sub-buffer layer, which protrudes from the sidewall of the corresponding step. More specifically, the doped first sub-buffer layer can be divided into a main body and a protrusion along the X direction. The main body contacts the gate sacrificial layer, while the protrusion does not contact the gate sacrificial layer and protrudes from the sidewall of the corresponding step.

[0111] In this embodiment of the disclosure, the undoped first sub-buffer layer 220 is located between the doped first sub-buffer layer 218 and the gate sacrificial layer 202; after removing the second sub-buffer layer 216 covering the sidewalls 210 of each step 206 using a first wet etching process to expose the sidewalls 210 of each step 206, the manufacturing method further includes:

[0112] The gate sacrificial layer 202 and the undoped first sub-buffer layer 220 are removed using a second wet etching process to form a gap 222; wherein, the etching rate of the gate sacrificial layer 202 is greater than the etching rate of the doped first sub-buffer layer 218 in the same etching process.

[0113] Conductive material is filled in the gap 222 to form a gate layer 224; wherein the gate layer 224 and the interlayer insulating layer 204 together form a stacked structure 226.

[0114] like Figure 2F As shown, the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 are removed using a second wet etching process to form a gap 222. Since the etching rate of the gate sacrificial layer 202 and the etching rate of the undoped first sub-buffer layer 220 are both greater than the etching rate of the doped first sub-buffer layer 218 in the same etching process, the wet etching process can increase the process window for removing the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 and reduce the damage to the doped first sub-buffer layer 218. That is, the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 are completely removed while the damage to the doped first sub-buffer layer 218 is avoided as much as possible.

[0115] Here, a "large head" is formed at one end of the gate layer along the X direction. The thickness of the "large head" along the Z direction is the sum of the thickness of the gate sacrificial layer along the Z direction and the thickness of the undoped first sub-buffer layer along the Z direction. In other words, the gate layer includes a portion of the gate layer in contact with the doped first sub-buffer layer and a portion of the gate layer not in contact with the doped first sub-buffer layer; the thickness H1 of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is greater than the thickness H2 of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0116] Still Figure 2FAs shown, a portion of the first sub-buffer layer is doped to form a doped first sub-buffer layer 218, which protrudes from the sidewall 210 of the corresponding step 206. More specifically, the main body 218a of the doped first sub-buffer layer contacts the "large head" of the gate layer 224, while the protrusion 218b of the doped first sub-buffer layer does not contact the "large head" of the gate layer 224 and protrudes from the sidewall 210 of the corresponding step 206.

[0117] In other embodiments, the entire first sub-buffer layer is doped to form a doped first sub-buffer layer, which protrudes from the sidewall of the corresponding step. More specifically, the main body of the doped first sub-buffer layer is in contact with the gate layer, while the protrusion of the doped first sub-buffer layer is not in contact with the gate layer and protrudes from the sidewall of the corresponding step. In this case, the gate layer does not have a "large head".

[0118] In this embodiment of the disclosure, the material of the buffer layer 212 is the same as the material of the gate sacrificial layer 202.

[0119] Here, the materials of the buffer layer and the gate sacrificial layer can be the same. Because the buffer layer and the gate sacrificial layer are made of the same material, the same etching solution can be used to remove both the gate sacrificial layer and the undoped first sub-buffer layer simultaneously, resulting in a simpler and lower-cost process. For example, nitrides can be used to form both the buffer layer and the gate sacrificial layer. For instance, both the materials of the buffer layer and the gate sacrificial layer can include silicon nitride.

[0120] Of course, other suitable materials can be selected so that, in the same etching process, the etching rate of the buffer layer is greater than the etching rate of the gate sacrificial layer. For example, silicon nitride can be used to form the gate sacrificial layer, and topologically selective silicon nitride can be used to form the buffer layer (i.e., the undoped first sub-buffer layer). The etching rate of the topologically selective silicon nitride material can be greater than the etching rate of silicon nitride. Since the etching rate of the undoped first sub-buffer layer is greater than the etching rate of the gate sacrificial layer, both the gate sacrificial layer and the undoped first sub-buffer layer can be removed more quickly.

[0121] In this embodiment of the disclosure, the etching solution in the second wet etching process may include a sulfuric acid solution or a sulfurous acid solution.

[0122] Here, a sulfuric acid solution (HSO), i.e., a sulfuric acid solution or a sulfurous acid solution, can be used to remove the gate sacrificial layer and the undoped first sub-buffer layer located between the gate sacrificial layer and the doped first sub-buffer layer. This disclosure embodiment does not specifically limit the concentration of the etching solution in the second wet etching process; the concentration of the etching solution in the second wet etching process can be specifically adjusted according to the dopant concentration of the first sub-buffer layer.

[0123] In this embodiment of the present disclosure, after all the first sub-buffer layers are doped, a doped first sub-buffer layer is formed, at which point the doped first sub-buffer layer and the gate sacrificial layer are in contact. After removing the second sub-buffer layer covering the sidewalls of each step using a first wet etching process to expose the sidewalls of each step, the manufacturing method further includes:

[0124] The gate sacrificial layer is removed using a second wet etching process to form an gap; wherein, in the same etching process, the etching rate of the gate sacrificial layer is greater than the etching rate of the doped first sub-buffer layer.

[0125] Conductive material is filled into the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

[0126] Here, the gate sacrificial layer is removed using a second wet etching process to form a gap. Since the etching rate of the gate sacrificial layer is greater than that of the doped first sub-buffer layer in the same etching process, the process window for removing the gate sacrificial layer can be increased and the damage to the doped first sub-buffer layer can be reduced during the wet etching process. That is, the gate sacrificial layer can be completely removed while avoiding damage to the doped first sub-buffer layer as much as possible.

[0127] Here, a "big head" is not formed at one end of the gate layer, and the thickness of the gate layer along the Z direction is the same as the thickness of the gate sacrificial layer along the Z direction. In other words, the gate layer includes a portion of the gate layer in contact with the doped first sub-buffer layer and a portion of the gate layer not in contact with the doped first sub-buffer layer; the thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is the same as the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0128] In this embodiment of the disclosure, after filling the gap 222 with conductive material to form the gate layer 224, the manufacturing method further includes:

[0129] A filling layer 228 is formed covering the first sub-buffer layer 218 and the sidewalls 210 of each step;

[0130] A contact structure 232 is formed that sequentially penetrates the fill layer 228 and the doped first sub-buffer layer 218 along the stacking direction and extends to the corresponding gate layer 224.

[0131] In this embodiment of the disclosure, a contact structure 232 is formed that sequentially penetrates the fill layer 228 and the doped first sub-buffer layer 218 along the stacking direction and extends to the corresponding gate layer 224, including:

[0132] A contact hole 230 is formed that penetrates the fill layer 228 along the stacking direction and extends to the corresponding doped first sub-buffer layer 218; wherein the doped first sub-buffer layer 218 serves as an etch stop layer (ESL).

[0133] Remove the doped first sub-buffer layer 218 located at the bottom of the contact hole 230 so that the contact hole 230 extends to the corresponding gate layer 224;

[0134] The contact hole 230 is filled with conductive material to form a contact structure 232.

[0135] like Figure 2G As shown, a fill layer 228 is formed covering the doped first sub-buffer layer 218 and the sidewalls 210 of each step 206. After the gate replacement process is performed, each step includes a step surface and a sidewall. The exposed surface of the gate layer 224 on the step surface is in contact with the doped first sub-buffer layer 218, and the exposed sidewalls of the gate layer 224 and the interlayer insulating layer 204 on the step sidewall are in direct contact with the fill layer 228.

[0136] In some embodiments, the process for forming the filler layer may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0137] In some embodiments, the material of the filler layer may include, but is not limited to, silicon oxide.

[0138] like Figure 2H As shown, the process of forming the contact hole 230 is divided into two stages: In the first stage, the contact hole 230 is formed by etching along the Z direction, penetrating the filling layer 228 and extending to the corresponding doped first sub-buffer layer 218; wherein, the doped first sub-buffer layer 218 can be used as an etching stop layer, so that the contact holes 230 corresponding to different gate layers 224 are all stopped in the doped first sub-buffer layer 218 above the corresponding gate layer 224.

[0139] Here, there is a high etch selectivity between the fill layer and the doped first sub-buffer layer, so the doped first sub-buffer layer can be used as an etch stop layer, which can better improve the leakage phenomenon between word lines caused by over-etching.

[0140] like Figure 2IAs shown, in the second stage, the doped first sub-buffer layer 218 located at the bottom of the contact hole 230 is removed, allowing the contact hole 230 to continue downward through the doped first sub-buffer layer 218 and extend to the corresponding gate layer 224. Thus, the contact hole 230 is formed by staged etching, and the doped first sub-buffer layer 218 is used as an etching stop layer. This ensures that the contact hole 230 extends to the lower gate layer 224 while preventing the upper gate layer 224 from being etched through, thereby simultaneously improving the problems of insufficient and over-etching.

[0141] Still Figure 2I As shown, conductive material can also be filled into the contact hole 230 to form a contact structure 232 extending along the Z direction to the corresponding gate layer 224.

[0142] In this embodiment, the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewall of the step. The buffer layer is doped so that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer. Thus, the second sub-buffer layer has a higher etch selectivity to the doped first sub-buffer layer than the second sub-buffer layer has to the undoped first sub-buffer layer. This maximizes the difference between the etch rate of the second sub-buffer layer and the etch rate of the doped first sub-buffer layer, thereby increasing the process window for removing the second sub-buffer layer and reducing damage to the doped first sub-buffer layer. This improves leakage and short circuits between adjacent word lines, thereby enhancing the reliability of the semiconductor device.

[0143] In a specific example, firstly, a gate sacrificial layer (e.g., silicon nitride) and an interlayer insulating layer (e.g., silicon oxide) can be alternately stacked to form an initial stack structure. The initial stack structure may include multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer. Here, the etching rate of the gate sacrificial layer can be defined as S1.

[0144] Next, a buffer layer (e.g., topologically selective silicon nitride) is formed covering the step surface and sidewalls of each step. The buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step. The first sub-buffer layer can be referred to as a flat SiN film on the steps, and the second sub-buffer layer can be referred to as a sidewall SiN on the steps. Here, the etching rate for the first sub-buffer layer can be defined as S2, and the etching rate for the second sub-buffer layer can be defined as S3; where S3 > S2.

[0145] It should be noted that the buffer layer can be formed using the ALD process. The etching rate of the buffer layer is greater than that of the gate sacrificial layer, i.e., S3 > S1 and S2 > S1. Here, the buffer layer formed using the ALD process has better step coverage, but the film quality of the buffer layer is generally lower and it is more easily etched away.

[0146] Related technical solutions use in-situ methods to perform surface treatment on the buffer layer. For example, plasma treatment (PT) can remove impurity elements in the topologically selective silicon nitride on the step surface, and can also make the topologically selective silicon nitride on the step surface more dense, thereby increasing the difference between the etching rate of the topologically selective silicon nitride on the step surface and the etching rate of the topologically selective silicon nitride on the step sidewall. However, this surface treatment method has several drawbacks. Firstly, while it achieves some directionality, it cannot create ion treatment that is perfectly perpendicular to the horizontal plane. This increases the density of topologically selective silicon nitride (TSH) on the step surface but also on the step sidewalls, failing to maximize the difference between the etching rates of TSH on the step surface and those on the step sidewalls. Secondly, because this method cannot create ion treatment that is perfectly perpendicular to the horizontal plane, the energy of the ion treatment is insufficient. This means that the TSH on both the bottom step surface and the step sidewalls are located in the weakest ion treatment region, resulting in a insufficient difference between the etching rates of TSH on the step surface and those on the step sidewalls. Consequently, the process of removing TSH from the step sidewalls may still suffer from under-etching or over-etching issues.

[0147] In this embodiment of the present disclosure, the buffer layer can then be doped, such that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer, and the remaining first sub-buffer layer forms an undoped first sub-buffer layer; wherein the undoped first sub-buffer layer is located between the doped first sub-buffer layer and the gate sacrificial layer. Here, the etching rate for the undoped first sub-buffer layer is the same as the etching rate for the first sub-buffer layer, which is still S2, and the etching rate for the doped first sub-buffer layer is defined as S4; wherein, S2 > S4. In summary, S3 > S2 > S1 > S4.

[0148] Next, the second sub-buffer layer is removed using a first wet etching process. Since the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer (i.e., S3 / S4) is greater than that of the second sub-buffer layer to the undoped first sub-buffer layer (i.e., S3 / S2), the second sub-buffer layer can be completely removed while minimizing damage to the doped first sub-buffer layer.

[0149] Here, taking advantage of the characteristic that the direction of ion implantation is basically perpendicular to the horizontal plane in ion implantation, the topologically selective silicon nitride of the first sub-buffer layer is subjected to ex-situ doping. This allows different doping elements (e.g., carbon and / or boron) to be implanted into the topologically selective silicon nitride of the first sub-buffer layer at higher energies. Then, through annealing, the doping elements are bonded to the topologically selective silicon nitride, which increases the wet etching selectivity of the second sub-buffer layer for the doped first sub-buffer layer. This allows for better selective etching to completely remove the second sub-buffer layer covering the sidewall of the step.

[0150] Here, ion implantation can achieve strong directionality. Anisotropic ion implantation can maximize the difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer, so as to achieve a greater etching selectivity.

[0151] Here, the doped first sub-buffer layer offers better resistance to etching solutions (e.g., H3PO4 and HF) compared to the undoped first and second sub-buffer layers. The second sub-buffer layer can be removed using anisotropic wet etching, while the doped first sub-buffer layer is well preserved. In other words, in this embodiment, the difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer in the same etching process is maximized to increase the process window for removing the second sub-buffer layer and reduce damage to the doped first sub-buffer layer.

[0152] Next, the gate sacrificial layer and the undoped first sub-buffer layer are removed using a second wet etching process. Due to the etching selectivity ratio of the gate sacrificial layer to the doped first sub-buffer layer (i.e., S1 / S4) and the etching selectivity ratio of the undoped first sub-buffer layer to the doped first sub-buffer layer (i.e., S2 / S4), the gate sacrificial layer and the undoped first sub-buffer layer can be removed quickly and cleanly.

[0153] refer to Figure 3 , Figure 3 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 3 As shown, this disclosure provides a semiconductor device, which includes:

[0154] The stacked structure 226 includes multiple steps 206, each step 206 includes a gate layer 224 and an interlayer insulating layer 204, and adjacent steps 206 are separated by the interlayer insulating layer 204.

[0155] A first sub-buffer layer 218 is doped, covering at least a portion of the step surface 208 of each step 206 and exposing the sidewall 210 of each step 206; wherein the first sub-buffer layer 218 is in contact with the gate layer 224 of each step 206.

[0156] Here, the step surface of each step is parallel to the XY plane, and the sidewall of the step is parallel to the YZ plane; wherein, the exposed gate layer surface of the step surface is in direct contact with the doped first sub-buffer layer, and the exposed sidewall of the step surface is in direct contact with the sidewall of the gate layer and the interlayer insulating layer and the filling layer.

[0157] In this embodiment of the disclosure, the doped first sub-buffer layer 218 protrudes from the sidewall 210 of the corresponding step 206.

[0158] Here, the doped first sub-buffer layer 218 can be divided into a main body 218a and a protrusion 218b along the X direction. The main body 218a is in contact with the gate layer 224, and the protrusion 218b is not in contact with the gate layer 224. The protrusion 218b protrudes from the sidewall 210 of the step 206.

[0159] In this embodiment of the disclosure, the semiconductor device further includes:

[0160] A filling layer 228 covers the doped first sub-buffer layer 218 and the sidewalls 210 of each step 206;

[0161] The contact structure 232 extends sequentially through the fill layer 228 and the doped first sub-buffer layer 218 along the stacking direction and extends to the corresponding gate layer 224.

[0162] like Figure 3 As shown, the contact interface between the protrusion 218b of the first sub-buffer layer and the filler layer 228 is arc-shaped. This embodiment does not impose any particular limitation on the shape of the contact interface between the protrusion 218b and the filler layer 228; the shape of the contact interface between the protrusion 218b and the filler layer 228 can also be a straight line.

[0163] Here, each gate layer needs to have its electrical signal led out through a contact structure; that is, each word line needs to have its electrical signal led out through a contact structure.

[0164] In this embodiment of the disclosure, the gate layer 224 includes a portion of the gate layer 224 that is in contact with the doped first sub-buffer layer 218 and a portion of the gate layer 224 that is not in contact with the doped first sub-buffer layer 218.

[0165] The thickness of the portion of the gate layer 224 that contacts the doped first sub-buffer layer 218 along the stacking direction is greater than or equal to the thickness of the portion of the gate layer 224 that does not contact the doped first sub-buffer layer 218 along the stacking direction.

[0166] In some embodiments, a portion of the first sub-buffer layer is doped to form a doped first sub-buffer layer, and an undoped first sub-buffer layer is located between the doped first sub-buffer layer and the gate sacrificial layer. After the gate replacement process is performed, the thickness H1 of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is greater than the thickness H2 of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0167] In other embodiments, all first sub-buffer layers are doped to form a doped first sub-buffer layer. The doped first sub-buffer layer is located above the gate sacrificial layer and is in contact with the gate sacrificial layer. After the gate replacement process is performed, the thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is the same as the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0168] In this embodiment of the disclosure, the material of the first sub-buffer layer 218 includes silicon nitride doped with carbon and / or boron.

[0169] refer to Figure 4 , Figure 4 A block diagram of a semiconductor system provided for embodiments of this disclosure. (See diagram below.) Figure 4 As shown, this disclosure provides a semiconductor system 300, which includes:

[0170] At least one semiconductor device 302 as described in the above technical solution; and

[0171] The controller 304 is coupled to the semiconductor device 302 and is configured to control the semiconductor device 302.

[0172] Here, the semiconductor device provided in the embodiments of this disclosure can be part of a three-dimensional memory, or the semiconductor device provided in the embodiments of this disclosure can also include peripheral circuits. Thus, the semiconductor device provided in the embodiments of this disclosure can also be a three-dimensional memory.

[0173] Here, the semiconductor system provided in the embodiments of this disclosure may include at least one semiconductor device and a controller coupled to the semiconductor device.

[0174] Here, the controller can be used to control the semiconductor device to perform erase, read or write operations, and to decode, parse or perform operations on the instructions issued or received by the semiconductor device.

[0175] In some embodiments, the semiconductor system may include, but is not limited to, solid-state drives and memory cards.

[0176] refer to Figure 5 , Figure 5 A block diagram of an electronic device provided in an embodiment of this disclosure. (As shown) Figure 5As shown, this embodiment of the disclosure provides an electronic device 306, which includes the semiconductor system 300 described above. Here, the electronic device may include a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device, or power bank, etc.

[0177] This disclosure provides a semiconductor device and its manufacturing method, as well as a semiconductor system. In this embodiment, the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewall of the step. The buffer layer is doped such that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer. Thus, the second sub-buffer layer has a higher etch selectivity to the doped first sub-buffer layer than to the undoped first sub-buffer layer. This increases the process window for removing the second sub-buffer layer and reduces damage to the doped first sub-buffer layer, thereby improving leakage and short circuits between adjacent word lines and ultimately enhancing the reliability of the semiconductor device.

[0178] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0179] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: An initial stack-up structure is provided, the initial stack-up structure including multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer, the step surface of each step exposing the surface of the gate sacrificial layer; A buffer layer is formed to cover the step surface and sidewalls of each step; wherein the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step; The buffer layer is doped such that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer; wherein the second sub-buffer layer has a greater etching selectivity to the doped first sub-buffer layer than the second sub-buffer layer has to the undoped first sub-buffer layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The doping process on the buffer layer includes: The buffer layer is subjected to ion implantation. The buffer layer is then annealed.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, In the ion implantation process, the angle of ion implantation is basically perpendicular to the surface of the first sub-buffer layer; The ion implantation process performed on the buffer layer includes: Ion implantation was performed on the first sub-buffer layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After the buffer layer is doped, the manufacturing method further includes: The second sub-buffer layer covering the sidewalls of each step is removed using a first wet etching process to expose the sidewalls of each step.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, A portion of the first sub-buffer layer is doped to form the doped first sub-buffer layer, and the undoped first sub-buffer layer is located between the gate sacrificial layer and the doped first sub-buffer layer. After removing the second sub-buffer layer covering the sidewalls of each step using a first wet etching process to expose the sidewalls of each step, the manufacturing method further includes: The gate sacrificial layer and the undoped first sub-buffer layer are removed using a second wet etching process to form a gap; wherein, in the same etching process, the etching rate of the gate sacrificial layer is greater than the etching rate of the doped first sub-buffer layer. A conductive material is filled into the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

6. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The doped first sub-buffer layer is formed by doping all of the first sub-buffer layers. After removing the second sub-buffer layer covering the sidewalls of each step using a first wet etching process to expose the sidewalls of each step, the manufacturing method further includes: The gate sacrificial layer is removed using a second wet etching process to form a gap; wherein, in the same etching process, the etching rate of the gate sacrificial layer is greater than the etching rate of the doped first sub-buffer layer. A conductive material is filled into the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

7. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that, The etching solution in the first wet etching process includes a phosphoric acid solution or a hydrofluoric acid solution; The etching solution in the second wet etching process includes sulfuric acid solution or sulfurous acid solution.

8. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that, After filling the gap with conductive material to form a gate layer, the manufacturing method further includes: A filling layer is formed covering the doped first sub-buffer layer and the sidewalls of each step; A contact structure is formed that sequentially penetrates the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The formation of the contact structure, which sequentially penetrates the fill layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer, includes: A contact hole is formed that penetrates the fill layer along the stacking direction and extends to the corresponding doped first sub-buffer layer; wherein the doped first sub-buffer layer serves as an etch stop layer; Remove the doped first sub-buffer layer located at the bottom of the contact hole, so that the contact hole extends to the corresponding gate layer; The contact hole is filled with conductive material to form a contact structure.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The material of the buffer layer is the same as the material of the gate sacrificial layer.

11. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The doping element in the doping process includes at least one of the following: carbon and boron.

12. A semiconductor device, characterized in that, The semiconductor device includes: The stacked structure includes multiple steps, each step including a gate layer and an interlayer insulating layer, and adjacent steps are separated by the interlayer insulating layer; A first sub-buffer layer is doped, covering at least a portion of the step surface of each step and exposing the sidewalls of each step; wherein the first sub-buffer layer is in contact with the gate layer of each step.

13. The semiconductor device according to claim 12, characterized in that, The doped first sub-buffer layer protrudes from the sidewall of the corresponding step.

14. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: A filling layer that covers the doped first sub-buffer layer and the sidewalls of each step; The contact structure extends sequentially through the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

15. The semiconductor device according to claim 12, characterized in that, The gate layer includes a portion of the gate layer that is in contact with the doped first sub-buffer layer and a portion of the gate layer that is not in contact with the doped first sub-buffer layer; The thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the stacking direction is greater than or equal to the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the stacking direction.

16. The semiconductor device according to claim 12, characterized in that, The material of the first sub-buffer layer includes silicon nitride doped with carbon and / or boron.

17. A semiconductor system, characterized in that, The semiconductor system includes: At least one semiconductor device as claimed in any one of claims 12 to 16; and A controller is coupled to the semiconductor device and configured to control the semiconductor device.

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