Memory chip, memory device and method of manufacturing memory device

Abstract

The invention relates to a memory chip, a memory device and a method of manufacturing the memory device. A memory chip includes a plurality of micro-pattern lines, a capping layer covering portions of the micro-pattern lines. A bond pad passes through the capping layer and is coupled to one of the micro-pattern lines. The bond pad includes a first pad portion coupled to the associated micro pattern line and a second pad portion coupled to the first pad portion and exposed to a top surface of the memory chip. An upper surface of the second pad portion has a convex shape.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to memory devices and methods of manufacturing the memory devices. Background Art

[0002] A nonvolatile memory device is a memory device that can retain stored data even when power is turned off. In recent years, due to the limitation of the integration of a two-dimensional nonvolatile memory device forming a single layer of memory cells on a substrate, a three-dimensional nonvolatile memory device in which memory cells are vertically stacked on a substrate has been proposed.

[0003] A three-dimensional nonvolatile memory device includes alternately stacked interlayer insulators and gates and a channel layer passing through the alternately stacked interlayer insulators and gates. Memory cells are stacked along the channel layer. In order to improve the reliability of the three-dimensional nonvolatile memory device, various structures and manufacturing methods are being developed. Summary of the invention

[0004] Various embodiments of the present disclosure are directed to a memory chip including a bonding pad coupled to a micro pattern and a method of manufacturing the memory chip.

[0005] As used herein, the term "micro pattern line" should be interpreted as referring to a layer of conductive material formed within or on the surface of a semiconductor material and carrying an electrical signal (voltage or current) between two or more electrical nodes. A "micro pattern line" should not be interpreted as necessarily being straight or having a specific cross-sectional shape. A "micro pattern line" is also not necessarily formed within or on a specific geometric plane; therefore, a micro pattern line can have both vertical and horizontal portions.

[0006] Embodiments of the present disclosure may provide a three-dimensional semiconductor memory device, which may include: a plurality of micro-pattern lines; a cover layer covering the upper portions of the plurality of micro-pattern lines; and at least one bonding pad, the at least one bonding pad passing through the cover layer to be coupled to any one of the micro-pattern lines. The bonding pad includes a first portion, which is referred to as a "first pad portion" electrically and mechanically coupled to the associated micro-pattern line. The bonding pad also includes a second portion, which is referred to herein as a "second pad portion" electrically coupled to the first pad portion and exposed to the exterior or outside of the device. The upper surface of the second pad portion has a convex shape.

[0007] Embodiments of the present disclosure may provide a semiconductor memory cell array, the semiconductor memory cell array comprising: a plurality of bit lines, the plurality of bit lines being located on the memory cell array; first bonding pads, the first bonding pads being respectively connected to the plurality of bit lines; metal lines; and second bonding pads, the second bonding pads being connected to the metal lines. The first bonding pads are bonded to the second bonding pads, and each of the first bonding pads has a pin structure.

[0008] A second embodiment of the present disclosure may provide a method for manufacturing a semiconductor memory cell array, which includes a plurality of bit lines on a substrate, the method comprising the following steps: forming a covering layer on the upper portion of the plurality of bit lines, and then forming a plurality of holes exposing the plurality of bit lines; forming a barrier metal layer and a metal seed layer along the upper surface of the covering layer and the side walls and bottom surfaces of the plurality of holes; forming a pad mask pattern on the metal seed layer including openings exposing pad areas overlapping the holes; and forming a bonding pad pattern filling the openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory chip according to an embodiment of the present disclosure.

[0010] Figure 2 is a perspective view showing a portion of a memory chip according to an embodiment of the present disclosure.

[0011] Figure 3A and Figure 3B It is schematically shown Figure 2 A plan view of an example of a memory chip.

[0012] Figure 4 is a cross-sectional view showing a portion of a memory chip according to an embodiment of the present disclosure.

[0013] Figure 5A and Figure 5B It is shown Figure 4 A perspective view of an example of a first bonding pad.

[0014] 6A to 6F is a horizontal cross-sectional view illustrating a method of manufacturing a memory chip according to an embodiment of the present disclosure.

[0015] Figure 7 is a block diagram illustrating a memory system including a memory chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The specific structural or functional descriptions of the embodiments of the present disclosure introduced in this specification or this application are only used to describe the embodiments of the present disclosure. The description should not be interpreted as being limited to the embodiments described in the specification or application.

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings to the extent that those skilled in the art to which the present disclosure pertains can easily practice the technical spirit of the present disclosure.

[0018] Figure 1 1 is a block diagram showing a semiconductor memory device 100 according to an embodiment of the present disclosure. For the sake of brevity, the semiconductor memory device 100 is hereinafter referred to as a memory device 100 .

[0019] The memory device 100 may include a memory cell array 110 and a logic circuit 120. The logic circuit 120 may include a row decoder (X-DEC) 121, a page buffer circuit 122, and a peripheral circuit (PERI circuit) 123.

[0020] The memory cell array 110 may include a plurality of memory blocks, each of which is named with an identifier "BLK". Not shown in the drawings is that each memory block BLK may include a plurality of cell strings. Each cell string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor all connected in series.

[0021] The memory cells of the memory cell array 110 may be volatile memory cells or nonvolatile memory cells. Hereinafter, the memory device 100 will be described as a vertical NAND flash memory device, but it should be understood that the technical idea of ​​the present disclosure is not limited thereto.

[0022] The memory cell array 110 may be coupled to the row decoder 121 through a plurality of row lines RL. The row lines RL may include Figure 1 At least one drain selection line not shown, Figure 1 The multiple word lines and Figure 1 The memory cell array 110 may be coupled to the page buffer circuit 122 through the bit lines BL.

[0023] The row decoder 121 may select any one of the memory blocks BLK in the memory cell array 110 in response to a row address X_A provided to the row decoder 121 through the peripheral circuit 123. The row decoder 121 may transmit an operating voltage X_V provided from the peripheral circuit 123 to a row line RL coupled to a memory block selected from among the memory blocks BLK included in the memory cell array 110.

[0024] The page buffer circuit 122 may include a plurality of page buffers PB respectively connected to the bit lines BL. The page buffer circuit 122 may receive a page buffer control signal PB_C from the peripheral circuit 123, and may transmit and receive a data signal DATA to and from the peripheral circuit 123. The page buffer circuit 122 may control the bit lines BL arranged on the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 122 may detect data stored in the memory cells of the memory cell array 110 by sensing the signals of the bit lines BL of the memory cell array 110 in response to the page buffer control signal PB_C, and may transmit the data signal DATA to the peripheral circuit 123 according to the detected data. The page buffer circuit 122 may apply a signal to the bit line BL based on the data signal DATA received from the peripheral circuit 123 in response to the page buffer control signal PB_C, so that data may be written to the memory cells of the memory cell array 110. The page buffer circuit 122 may write or read data to or from the memory cells connected to the activated word lines.

[0025] The peripheral circuit 123 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the semiconductor device 100, and may send a data signal DATA to and receive a data signal DATA from a device (e.g., a memory controller) outside the semiconductor device 100. The peripheral circuit 123 may output a signal for writing data to or reading data from the memory cell array 110, such as a row address X_A or a page buffer control signal PB_C, based on the command signal CMD, the address signal ADD, and the control signal CTRL. The peripheral circuit 123 may generate various voltages required by the semiconductor device 100, including an operating voltage X_V.

[0026] As used herein, the term "memory chip" should be interpreted as referring to a semiconductor substrate having substantially planar top and bottom surfaces, with one or more semiconductor materials between the top and bottom surfaces, and one or more electronic devices, transistors, resistors, etc. formed using well-known semiconductor manufacturing techniques.

[0027] Figure 2 is a perspective view showing a part of the physical structure of the memory device 100 according to an embodiment of the present disclosure. Figure 3A and Figure 3B is a schematic diagram showing an embedded Figure 1 A plan view of the physical layout of a memory chip MC of a memory device.

[0028] Reference Figure 2, the memory device 100 according to the embodiment of the present disclosure may include a memory chip MC and a logic chip LC bonded on the memory chip MC. The memory device 100 may have a peripheral over cell (POC) structure.

[0029] Reference Figure 3A , the memory chip MC may include a memory cell array 110 located on a first substrate 10 and a plurality of bit lines BL1 to BLn located on the memory cell array 110. As shown in the figure, each bit line BL1 to BLn may extend in a second direction SD. Several electrically and physically parallel bit lines BL1 to BLn whose lengths extend in the second direction SD are adjacent, but are laterally separated from each other by a distance extending in a first direction FD. As shown in the figure, FD and SD are orthogonal to each other. The bit lines BL1 to BLn, the first direction FD, and the second direction SD may all be located in the same geometric plane, which is parallel to and perpendicularly separated from a geometric plane of an upper surface of the first substrate 10 which is substantially planar. The first direction FD may correspond to an extension direction of a word line, and the second direction SD may correspond to an extension direction of a bit line. Extending to the shown Figure 3A A vertical direction VD in and extending from the plane of the first substrate 10 may vertically protrude from the upper surface of the first substrate 10 and may perpendicularly intersect the first direction FD and the second direction SD.

[0030] A plurality of first bonding pads PAD1 may be provided on the surface Smc of the memory chip MC facing the logic chip LC (see Figure 2 ). Each of the plurality of bit lines BL1 to BLn may be coupled to at least one first bonding pad PAD1. Although it is shown and described in the embodiments of the present disclosure that one bit line BL is coupled to one first bonding pad PAD1, a plurality of first bonding pads PAD1 may be commonly coupled to one bit line BL. Therefore, the first bonding pad PAD1 may overlap with a plurality of the plurality of bit lines BL1 to BLn. A lower portion of each of the first bonding pads PAD1 may be electrically and physically connected to a corresponding one of the lines BL of the plurality of bit lines BL1 to BLn.

[0031] As the integration density of semiconductor devices increases, the number of bit lines BL arranged in the same area of ​​a memory chip MC may increase. This may require a decrease in one or both of the width of a bit line and the spacing distance between adjacent bit lines.

[0032] Reference Figure 3B, the memory chip MC may include a memory cell array 110 located on a first substrate 10 and a plurality of bit lines BL1 to BLm (where m is a positive integer greater than n) also located on the memory cell array 110. Each of the plurality of bit lines BL1 to BLm may have the same constant width. Each bit line may be arranged to be spaced apart from adjacent bit lines by the same preset distance.

[0033] like Figure 3B As shown, the length of each of the plurality of bit lines BL1 to BLm may extend in the second direction SD. The bit lines BL1 to BLm may be separated from each other in the transverse direction by a spacing distance extending in the first direction FD. The bit lines in the plurality of bit lines BL1 to BLm may be arranged parallel to each other. As the number of the plurality of bit lines BL1 to BLm increases, the number of first bonding pads PAD1 corresponding to the plurality of bit lines BL1 to BLm also increases, and the first bonding pads PAD1 corresponding to the adjacent bit lines may be arranged diagonally between the first direction FD and the second direction SD to maintain physical separation from each other. In addition, one first bonding pad PAD1 may overlap with one or more bit lines. The lower portion of each of the first bonding pads PAD1 may be electrically and physically connected to a corresponding bit line among the plurality of bit lines BL1 to BLn.

[0034] Although it is shown and described in the embodiment of the present disclosure that the first bonding pads PAD1 are arranged in a diagonal manner, the bonding pads PAD1 adjacent to each other may be arranged in a zigzag direction.

[0035] Refer again Figure 2 , the logic chip LC may be bonded on the memory chip MC so that the second bonding pad PAD2 is coupled to the first bonding pad PAD1. The logic chip LC may include Figure 1 The logic circuit 120. That is, the logic chip LC may include a high voltage transistor region HVR and a low voltage transistor region LVR. The high voltage transistor region HVR is a region where high voltage transistors are arranged, and the low voltage transistor region LVR is a region where low voltage transistors are arranged.

[0036] Figure 4 is a cross-sectional view showing a portion of a memory device according to an embodiment of the present disclosure.

[0037] Reference Figure 4 , the memory chip MC may include a first substrate 10 . A memory cell array 110 may be located on the first substrate 10 .

[0038] The first substrate 10 may be formed as a single crystal silicon layer, SOI (Silicon on Insulator), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on an insulator, or a polysilicon layer formed on an insulator. According to an embodiment, the memory chip MC may include a line structure coupled to the memory cell array 110 by performing an additional line formation process after removing the first substrate 10.

[0039] The memory cell array 110 may include a plurality of row lines RL and a plurality of interlayer insulators 20 alternately stacked on a first substrate 10, and a plurality of channel structures CH passing through the row lines RL and the interlayer insulators 20 in a vertical direction VD. At least one layer from the bottom among the row lines RL may form a source select line SSL. At least one layer from the top may form a drain select line DSL. The row lines RL between the source select line SSL and the drain select line DSL may form a word line WL.

[0040] Each of the plurality of channel structures CH may include a channel layer 30 and a gate insulating layer 32. The channel layer 30 may be polycrystalline silicon or monocrystalline silicon, and may include p-type impurities such as boron (B). The shape of the gate insulating layer 32 may be similar to a hollow tube of a cylinder to surround the outer wall of the channel layer 30. The gate insulating layer 32 may include a tunnel insulator, a charge storage layer, and a blocking layer stacked sequentially from the outer wall of the channel layer 30. In some embodiments, the gate insulating layer 32 may have an oxide-nitride-oxide (ONO) stacked structure in which an oxide layer, a nitride layer, and an oxide layer are stacked sequentially. A source select transistor may be formed in a portion where a source select line SSL surrounds a plurality of channel structures CH. A memory cell may be formed in a portion where a word line WL surrounds a plurality of channel structures CH. A drain select transistor may be formed in a portion where a drain select line DSL surrounds a plurality of channel structures CH.

[0041] A bit line (eg, BL1) may be disposed on the channel structure CH. The bit line BL1 may extend in the second direction SD. Figure 4 Only one bit line BL1 is shown in FIG. 1 , but it should be understood that a plurality of bit lines BL1 to BLm are repeatedly arranged in the first direction FD (see FIG. 1 ). Figure 3B ),like Figure 4 As shown, the first direction FD extends to the Figure 4 within and extending from the geometric plane.

[0042] The bit line contact BLC may be disposed under the bit line BL1 to couple the bit line BL1 and the channel structure CH. A plurality of channel structures CH are arranged in a row extending in the second direction SD and may be commonly coupled to one bit line BL1.

[0043] Slits SLT may be provided in the alternately stacked row lines RL and interlayer insulators 20 so that the slits SLT may separate the row lines RL, the interlayer insulators 20, and the channel structures CH into memory block units or memory finger units as blocks smaller than memory blocks.

[0044] A cover layer 40 may be provided on the first substrate 10 to cover the channel structure CH, the bit line BL1, and the alternately stacked row lines RL and the interlayer insulator 20. A first buffer layer 60 may be formed on the cover layer 40, and an upper surface of the first buffer layer 60 may form a side of the memory chip MC facing the logic chip LC. The first bonding pad PAD1 may be located on one side of the memory chip MC. The first bonding pad PAD1 may be exposed to one side of the memory chip MC. The first bonding pad PAD1 may be located in the first buffer layer 60 and may extend into the cover layer 40 to be directly connected to the bit line BL1. Although Figure 4 Only one first bonding pad PAD1 is shown, but it should be understood that a plurality of first bonding pads PAD1 are repeatedly disposed in the first direction FD to be respectively coupled to corresponding bit lines. The first bonding pad PAD1 may have a pin structure. The first bonding pad PAD1 may have a T shape.

[0045] The logic chip LC may include a second substrate 12 and a plurality of transistors HVT and LVN located on the second substrate 12. The second substrate 12 may be formed of a single crystal silicon layer SOI, a silicon layer formed on a silicon germanium layer, a single crystal silicon layer formed on an insulator, or a polycrystalline silicon layer formed on an insulator. The second substrate 12 may be formed of the same material as the first substrate 10.

[0046] The transistors HVT and LVN may include a high voltage transistor HVT located on a high voltage transistor region HVR of the second substrate 12 and a low voltage transistor LVT located on a low voltage transistor region LVR of the second substrate 12. Figure 4 One high voltage transistor HVT and two low voltage transistors LVT are shown, but it should be understood that a plurality of high voltage transistors HVT and a plurality of low voltage transistors LVT may be provided on the second substrate 12 .

[0047] The metal line ML may be located on the second substrate 12 and may be coupled to the high voltage transistor HVT through the second contact C2. In addition, the metal line ML may be coupled to the second bonding pad PAD2 through the first contact C1. The first contact C1 may pass through the insulator 80 to be coupled to the second bonding pad PAD2.

[0048] An insulator 50 may be provided on the second substrate 12 to cover the transistors HVN and LVN and the metal line ML. The insulator 50 may be silicon oxide, for example, HDP oxide or TEOS oxide. An insulator 80 and a second buffer layer 70 may be formed above the insulator 50. The upper surface of the second buffer layer 70 may form a side of the logic chip LC facing the memory chip MC. The second bonding pad PAD2 may be provided on one side of the logic chip LC. In other words, the second bonding pad PAD2 may be located in the second buffer layer 70, and the upper surface of the second bonding pad PAD2 may be exposed to one side of the logic chip LC.

[0049] The first bonding pad PAD1 may correspond to the second bonding pad PAD2. The first bonding pad PAD1 and the second bonding pad PAD2 may be arranged to face each other. In order to connect the corresponding first bonding pad PAD1 and the second bonding pad PAD2 to each other, the logic chip LC may be bonded to the memory chip MC. The first bonding pad PAD1, the second bonding pad PAD2, and the first contact C1 may form an electrical path to connect the bit line BL1 of the memory chip MC and the metal line ML of the logic chip LC.

[0050] Figure 5A and Figure 5B It is shown Figure 4 A perspective view of an example of a first bonding pad.

[0051] Reference Figure 5A and Figure 5B The first bonding pad PAD1 may include a first pad portion P1 and a second pad portion P2. The first pad portion P1 is formed by Figure 4 The first pad portion P1 may have a substantially rectilinear shape, i.e., characterized by straight lines, such that its shape is reminiscent of a rectangular parallelepiped or a plate. The second pad portion P2 may be in contact with the bottom surface of the first pad portion P1 and face toward Figure 4 The bit line BL1 extends and Figure 4 The second pad portion P2 may also have a structure such as Figure 5A In an alternative embodiment, the second pad portion P2 may be cylindrical, such as Figure 5B The bottom surface P2BOT of the second pad portion P2 may be directly connected to Figure 4 of bit line BL1.

[0052] 6A to 6F It is shown that according to the above and in Figures 1 to 5B 0 is a vertical cross-sectional view of steps of a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure shown in FIG.

[0053] Reference Fig. 6A , the memory cell array 110 is formed on the first substrate 10. The memory cell array 110 may be Figure 4 The memory cell array 110 may include a structure in which a plurality of interlayer insulators and a plurality of conductive layers for word lines are alternately stacked. The structure may also include a plurality of channel structures passing through the stacked structure in a vertical direction VD, such as Fig. 6A shown.

[0054] Next, a first insulator 201, which may include an oxide layer, is formed on the memory cell array 110, and a micro pattern line 203 is formed to pass through at least a portion of the first insulator 201. The micro pattern line 203 is connected to the memory cell array 110. The plurality of micro pattern lines 203 may be a linear structure, that is, a thin, narrow, and elongated layer formed of a conductive material. The plurality of micro pattern lines 203 may be Figure 3A and Figure 3B The plurality of bit lines BL1 to BLn and BL1 to BLm are shown. The plurality of micro pattern lines 203 may extend along the second direction SD and be arranged along the first direction FD. The plurality of micro pattern lines 203 may each have a constant width and be arranged to be spaced apart from each other at regular intervals.

[0055] Next, the first insulator 201 is covered with a first cover layer 205, which is formed over the plurality of micro pattern lines 203. Then, a second cover layer 207 is covered over the first cover layer 205. The cover layer is preferably non-conductive. The first cover layer 205 may include a silicon nitride layer (SiN). The second cover layer 207 may include a silicon oxide layer (SiO2).

[0056] Reference Figure 6B After forming a photoresist pattern (not shown) on the second capping layer 207, an etching process using the photoresist pattern (not shown) is performed to form a hole H, through which each of the plurality of micro pattern lines 203 is exposed. Although one hole H is shown in the embodiment of the present disclosure, a plurality of holes may be formed to correspond to the plurality of micro pattern lines 203, respectively. The plurality of holes may be formed so as not to overlap each other. For example, the plurality of holes may be arranged diagonally between the first direction FD and the second direction SD.

[0057] In forming the hole H, a primary etching process may be performed to etch the second capping layer 207, thereby exposing the first capping layer 205. Thereafter, a secondary etching process may be performed to form the hole H and thereby expose the plurality of micro pattern lines 203.

[0058] Subsequently, the photoresist pattern is removed.

[0059] Reference Figure 6C, a barrier metal layer 209 may be formed on the upper surface of the second capping layer 207, the sidewalls and the bottom surface of the hole H. Thereafter, a metal seed layer 211 is formed on the barrier metal layer 209. The metal seed layer 211 may completely fill the inside of the hole H and may contain copper (Cu).

[0060] Reference Fig.6D , a pad mask pattern 213 is formed on the metal seed layer 211. The pad mask pattern 213 may include an opening OP through which a pad region overlapping the hole H is exposed. The pad mask pattern 213 may be formed as a photoresist pattern.

[0061] Subsequently, a bonding pad material 215 is formed in the opening OP of the pad mask pattern 213. The bonding pad material 215 may contain copper (Cu). For example, the bonding pad material 215 may be formed or deposited by selectively growing an exposed portion of the metal seed layer 211 inside the hole H. For example, the bonding pad material 215 may be formed by an electroplating method. The upper surface of the bonding pad material 215 may be convex.

[0062] According to an embodiment, the bonding pad material 215 may be formed by gap-filling a metal material in the opening OP.

[0063] Reference Fig. 6E , remove the pad mask pattern 213 (see Fig.6D ) to expose the metal seed layer 211. Subsequently, the exposed metal seed layer 211 and the barrier metal layer 209 are etched away in sequence, and the etching process is preferably a wet etching process. Therefore, the metal seed layer 211 and the barrier metal layer 209 can only remain under the bonding pad material 215.

[0064] Reference Fig. 6F , a buffer layer 217 may be formed on the entire structure including the bonding pad material 215, and a planarization process (CMP; chemical mechanical polishing) may be performed to expose an upper surface of the bonding pad material 215. The buffer layer 217 may include silicon carbon nitride (SiCN).

[0065] Since the barrier metal layer 209 is not exposed during the planarization process, a step can be prevented from occurring between the bonding pad material 215 and materials of the barrier metal layer 209 and the buffer layer 217. In addition, the plurality of micro pattern lines 203 can be directly coupled to the first bonding pad PAD1, thereby simplifying the process.

[0066] The first bonding pad PAD1 may be formed to include a barrier metal layer 209, a metal seed layer 211, and a bonding pad material 215. The first bonding pad PAD1 may be Figure 4The first bonding pad PAD1 may have a filling hole H (see Figure 6C ) and opening OP (see Fig.6D ). The first bonding pad PAD1 may have a pin structure. The first bonding pad PAD1 may have a T shape.

[0067] According to the above-described embodiment, the first bonding pad PAD1 may include a filling opening OP ( Fig.6D ) of the first pad portion (corresponding to Figure 5A and Figure 5B P1) and filling hole H( Figure 6C ) of the second pad portion (corresponding to Figure 5A and Figure 5B For example, the second pad portion P2 of the first bonding pad PAD1 overlaps one corresponding micro pattern line 203 to be physically and electrically coupled to the one corresponding micro pattern line 203, but does not overlap a micro pattern line adjacent to the corresponding micro pattern line 203. However, the first pad portion P1 of the first bonding pad PAD1 may overlap the corresponding micro pattern line 203 and the adjacent micro pattern line.

[0068] In addition, the first bonding pad PAD1 may include a barrier metal layer 209 , but the barrier metal layer 209 may be formed only on the bottom surface of the first bonding pad PAD1 . A side surface of the first bonding pad PAD1 may have a structure in which a metal seed layer 211 and a bonding pad material 215 are in contact with a buffer layer 217 .

[0069] Figure 7 is a block diagram illustrating a memory system including a semiconductor device according to an embodiment of the present disclosure.

[0070] Reference Figure 7 , the memory system 1000 may include a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 may include a plurality of semiconductor devices 100. The plurality of semiconductor devices 100 may be divided into a plurality of groups. Although it has been illustrated and described in the present embodiment that the host 1300 is included in the memory system 1000, the memory system 1000 may include only the controller 1200 and the memory device 1100, and the host 1300 may be located outside the memory system 1000.

[0071] exist Figure 7 , it is shown that a plurality of groups GR1 to GRn of the memory device 1100 communicate with the controller 1200 through the first channel CH1 to the nth channel CHn, respectively. Each memory device 100 may be a reference Figure 1 , Figure 2 and FIG. 5A to FIG. 5B A semiconductor device is described.

[0072] Each of the groups GR1 to GRn may communicate with the controller 1200 through one common channel. The controller 1200 may control the plurality of semiconductor devices 100 of the memory device 1100 through the plurality of channels CH1 to CHn.

[0073] The controller 1200 is connected between the host 1300 and the memory device 1100. The controller 1200 may access the memory device 1100 in response to a request from the host 1300. For example, the controller 1200 may control a read operation, a program operation, an erase operation, and a background operation of the memory device 1100 in response to a host command Host_CMD received from the host 1300. The host 1300 may send an address signal ADD and a data signal DATA to be programmed together with the host command Host_CMD during a program operation, and may send the address signal ADD together with the host command Host_CMD during a read operation. During a program operation, the controller 1200 sends a command corresponding to a program operation and a data signal DATA to be programmed to the memory device 1100. During a read operation, the controller 1200 sends a command corresponding to a read operation to the memory device 1100, receives a read data signal DATA from the memory device 1100, and sends the received data signal DATA to the host 1300. The controller 1200 may provide an interface between the memory device 1100 and the host 1300. The controller 1200 may execute firmware for controlling the memory device 1100.

[0074] The host 1300 may include a portable electronic device such as a computer, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a camera, a camcorder, or a mobile phone. The host 1300 may use a host command Host_CMD to make a request for a programming operation, a read operation, an erase operation, etc. of the memory system 1000. In order to perform a programming operation of the memory device 1100, the host 1300 may send a data signal DATA, an address signal ADD, and a host command Host_CMD corresponding to the programming operation to the controller 1200. In order to perform a read operation, the host may send an address signal ADD and a host command Host_CMD corresponding to the read operation to the controller 1200. Here, the address signal ADD may be a logical address of the data.

[0075] The controller 1200 and the memory device 1100 may be integrated into a single device. As an embodiment, the controller 1200 and the memory device 1100 may be integrated into a single device to form a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into a single device to form a memory card, such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a Compact Flash card (CF), a Smart Media Card (SM, SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC), an SD card (SD, Mini SD, Micro SD, SDHC), or a Universal Flash Storage (UFS).

[0076] In an embodiment, the memory system 1000 may be configured as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device capable of sending / receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, an RFID device, one of various components for forming a computing system, and the like.

[0077] In an embodiment, the memory device 1100 or the memory system 1000 may be installed in various types of packages. For example, the memory device 1100 or the memory system 1000 may be packaged in a package stack (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic lead chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system-level package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), a wafer-level processing stacked package (WSP), etc.

[0078] The foregoing description is intended for illustrative purposes only. The true scope of the invention is defined by the following claims.

[0079] CROSS-REFERENCE TO RELATED APPLICATIONS

[0080] This application claims the priority of Korean Patent Application No. 10-2023-0094811 filed in the Korean Intellectual Property Office on July 20, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory chip, comprising: Multiple micro pattern lines; a covering layer, the covering layer covering a portion of the micro-pattern line; as well as a bonding pad passing through the cover layer, the bonding pad being electrically coupled to a predetermined micro-pattern line; Wherein, the bonding pad comprises: a first pad portion electrically coupled to the predetermined micro-pattern line; and a second pad portion coupled to the first pad portion and exposed to a top surface of the memory chip, and Wherein an upper surface of the second pad portion has a convex shape.

2. The memory chip according to claim 1, wherein: The bonding pad comprises: a barrier metal layer on the sidewall and bottom surface of the first pad portion and on the bottom surface of the second pad portion; and A bonding pad material is disposed on the barrier metal layer.

3. The memory chip according to claim 2, wherein: The bond pad material includes copper.

4. The memory chip according to claim 2, wherein: The barrier metal layer is located only on the bottom surface of the bonding pad.

5. The memory chip according to claim 2, wherein: The first pad partially passes through the cover layer.

6. The memory chip according to claim 5, wherein: The covering layer comprises: a first covering layer disposed on upper portions of the plurality of micro pattern lines and comprising a silicon nitride layer; and The second covering layer is disposed on the first covering layer and includes a silicon oxide layer.

7. The memory chip according to claim 5, further comprising: a buffer layer, the buffer layer being disposed above the cover layer, Wherein one side of the second pad portion contacts the buffer layer.

8. The memory chip according to claim 7, wherein: The buffer layer is in contact with the bond pad material.

9. The memory chip according to claim 1, wherein: The second pad portion overlaps a micro-pattern line located adjacent to the predetermined micro-pattern line.

10. The memory chip according to claim 1, wherein: The bonding pad has a damascene structure.

11. The memory chip according to claim 1, wherein: The bonding pad has a pin structure.

12. A memory device, the memory device comprising: a memory cell array; a plurality of bit lines, the plurality of bit lines being located on the memory cell array; first bonding pads, the first bonding pads being respectively coupled to the plurality of bit lines; Metal wire; as well as a second bonding pad coupled to the metal line, wherein the first bonding pad is bonded to the second bonding pad, and Wherein, each of the first bonding pads has a pin structure.

13. The memory device according to claim 12, wherein: Each of the first bonding pads comprises: a first pad portion directly coupled to any one of the plurality of bit lines; and A second pad portion is coupled to the first pad portion.

14. The memory device according to claim 13, wherein: Each of the first bonding pads comprises: a barrier metal layer on the sidewall and bottom surface of the first pad portion and on the bottom surface of the second pad portion; and A bonding pad material is disposed on the barrier metal layer.

15. The memory device of claim 14, wherein: The barrier metal layer is located only on a bottom surface of each of the first bonding pads.

16. The memory device of claim 15, further comprising: a cover layer and a buffer layer, wherein the cover layer and the buffer layer are sequentially disposed on the upper portions of the plurality of bit lines, The first pad partially passes through the cover layer, and the second pad partially passes through the buffer layer.

17. The memory device of claim 16, wherein: The bond pad material is in contact with the buffer layer.

18. A method of manufacturing a memory device, the method comprising the steps of: forming a memory cell array and a plurality of conductive patterns on a substrate; forming a cover layer on upper portions of the plurality of conductive patterns, and then forming a plurality of holes exposing the plurality of conductive patterns; forming a barrier metal layer and a metal seed layer along an upper surface of the capping layer and sidewalls and bottom surfaces of the plurality of holes; forming a pad mask pattern including an opening exposing a pad region overlapping the hole on the metal seed layer; and A bonding pad pattern filling the opening is formed.

19. The method according to claim 18, further comprising the steps of: forming the bonding pad pattern, removing the pad mask pattern, and sequentially etching the exposed metal seed layer and barrier metal layer; as well as A buffer layer is formed to cover the bonding pad pattern, and then a planarization process is performed to expose an upper portion of the bonding pad pattern.

20. The method according to claim 18, wherein: The opening corresponds to any one of a plurality of bit lines and overlaps a bit line adjacent to a predetermined bit line.

21. The method according to claim 18, wherein: The metal seed layer and the bonding pad pattern include copper.

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