Semiconductor structure, forming method thereof and memory array

Abstract

The invention discloses a semiconductor structure, a forming method thereof and a memory array. The forming method comprises the following steps: providing a substrate; performing ion implantation on the substrate to form a well region and a doped region located on the well region; forming a first photoresist layer with a control gate pattern on the doped region; sequentially etching the doped region and the well region by taking the first photoresist layer as a mask, and forming a first opening in the substrate and a source / drain region positioned on the well region; forming a control gate layer in the first opening and on the source / drain region; the control gate layer on the source / drain region and part of the control gate layer in the first opening are removed through etching, a control gate and a second opening are formed in the substrate, and the top surface of the control gate is flush with the bottom of the source / drain region. A control gate is formed in a substrate, namely the control gate is an embedded gate, so that the length of a carrier channel is increased under the condition that the distance between a source and a drain in the horizontal direction is not changed or reduced, the withstand voltage of a source-drain junction is improved, the area of a storage unit is further reduced, and the performance of the memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a forming method thereof, and a storage array. Background Art

[0002] Flash memory includes NAND flash memory and NOR flash memory, and flash memory is a non-volatile memory, that is, data will not be lost even if power is off.

[0003] However, in order to reduce the size of the existing flash memory, on the one hand, the thickness of the charge tunneling layer and the charge trapping layer is reduced, so that the longitudinal thickness of the flash memory is reduced, but at the same time, there is a pressure limit on the control gate end, and the voltage difference between the source and the drain needs to be increased. The existing distance between the source and the drain does not meet the voltage difference between the source and the drain required by the current memory, resulting in reduced performance of the memory; on the other hand, by reducing the distance between the source and the drain, the lateral width of the flash memory is reduced, resulting in a reduction in the channel length between the source and the drain, and a reduction in the source-drain junction withstand voltage, which further leads to reduced performance of the memory. Summary of the invention

[0004] The technical problem solved by the present invention is how to improve the performance of the memory.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; performing ion implantation on the substrate to form a well region and a doped region located on the well region; forming a first photoresist layer having a control gate pattern on the doped region; using the first photoresist layer as a mask, sequentially etching the doped region and the well region to form a first opening in the substrate and a source / drain region located on the well region; forming a control gate layer in the first opening and on the source / drain region; etching and removing the control gate layer on the source / drain region and the control gate layer in a portion of the first opening to form a control gate and a second opening in the substrate, wherein the second opening is located on the top surface of the control gate, the top surface of the control gate is flush with the bottom of the source / drain region, and the source / drain region is located on the top surface of the control gate.

[0006] Optionally, the process for etching the doped region and the well region is: a dry etching process, the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

[0007] Optionally, the method for forming the semiconductor structure also includes: before the step of forming a control gate layer, forming a control gate dielectric layer on the surface of the first opening and the surface of the source / drain region; after the step of forming the control gate, etching away the control gate dielectric layer on the top surface of the source / drain region and the control gate dielectric layer on the side wall of the second opening to form a dielectric layer.

[0008] Optionally, the step of forming a control gate dielectric layer includes: forming a charge tunneling layer on the surface of the first opening and the surface of the source / drain region; forming a charge trapping layer on the surface of the charge tunneling layer; and forming a charge blocking layer on the surface of the charge trapping layer.

[0009] Optionally, after the step of forming the dielectric layer, it also includes: depositing an isolation layer on the side wall surface of the second opening and the top of the control gate; forming an interlayer dielectric layer on the isolation layer, wherein the interlayer dielectric layer covers the source / drain region and the control gate; forming a second photoresist layer having a contact hole pattern on the interlayer dielectric layer; using the second photoresist layer as a mask, sequentially etching the interlayer dielectric layer and the isolation layer until the surface of the source / drain region and the top surface of the control gate are exposed to form a contact hole.

[0010] Optionally, after the step of forming the contact hole, it also includes: forming a metal layer at the bottom of the contact hole; performing an annealing process to react the metal layer with the top surface of the source / drain region and the top surface of the control gate to form a metal silicide layer; and filling the contact hole with a conductive material to form a conductive plug.

[0011] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate; a well region located in the substrate; a doped region located in the substrate and on the surface of the well region; a first opening located in the doped region and in part of the well region; a source / drain region located in the doped region; a control gate located in the first opening; and a second opening located on the control gate and between adjacent source / drain regions.

[0012] Optionally, the semiconductor structure further includes: a dielectric layer located on the sidewall and bottom surface of the control gate, the dielectric layer including: a charge tunneling layer, a charge trapping layer located on the surface of the charge tunneling layer, and a charge blocking layer located on the surface of the charge trapping layer.

[0013] Optionally, the semiconductor structure further includes: an interlayer dielectric layer, the interlayer dielectric layer covers the source / drain region and the control gate; a contact hole located in the interlayer dielectric layer; and a metal silicide layer located on the bottom surface of the contact hole.

[0014] Correspondingly, the present invention further provides a memory array, comprising memory cells arranged in an array, wherein the memory cells are formed by the above-mentioned method for forming a semiconductor structure.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] The present invention forms a control gate in a substrate, that is, the control gate is a buried gate, and the bottom of the source / drain region is flush with the top surface of the control gate, so that the channel length distance between adjacent source / drain regions is increased from the distance in the horizontal direction to the sum of the lengths along the control gate surface in the substrate, so that when the distance between the source and drain in the horizontal direction remains unchanged or decreases, the carrier channel length becomes longer, the withstand voltage of the source-drain junction is improved, and the storage unit area is reduced, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0018] Figures 2 to 11 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention;

[0019] Fig.12 It is a schematic diagram of the structure of a memory array in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0021] refer to Figure 1 In the current flash memory, the control gate 201 and the control gate dielectric layer 202 are located on the substrate (not shown in the figure), and the source / drain structure 203 is located in the substrate, so that the channel length L1 is the distance between adjacent source / drain structures.

[0022] In order to reduce the size of the memory, on the one hand, it is necessary to reduce the thickness of the charge tunneling layer Tunnel Oxide and the charge trapping layer Charge Trap Layer (i.e., the control gate dielectric layer 202) so as to reduce the longitudinal thickness of the flash memory. However, because the control gate dielectric layer becomes thinner, the withstand voltage of the control gate and the source / drain structure will also become smaller, and the control gate cannot be subjected to high voltage, and the tunneling voltage of the charge tunneling layer tunnel oxide cannot be reached. Therefore, the CHE (Channel Hot Electron, Chinese for channel hot electrons) programming and erasing method needs to be adopted in this structure. The condition for forming hot carriers is that a certain voltage needs to be applied to the source and drain ends, and the withstand voltage of the source and drain junction is required to be higher than this voltage. Generally, the longer the channel length, the higher the withstand voltage. However, the current channel length does not meet the withstand voltage of the source and drain junction required by the current memory, resulting in reduced performance of the memory.

[0023] On the other hand, by reducing the distance between the source and the drain, the lateral width of the flash memory is reduced, resulting in a reduction in the channel length between the source and the drain, and a reduction in the source-drain junction withstand voltage, which further leads to a reduction in the performance of the memory.

[0024] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, as well as a memory array. By forming a buried control gate in a substrate, the contact area between the control gate and the substrate is increased, thereby increasing the channel length distance between adjacent source / drain regions, so that the carrier channel length becomes longer while the distance between the source and drain in the horizontal direction remains unchanged or decreases, thereby improving the withstand voltage of the source-drain junction, thereby reducing the memory cell area and improving the performance of the memory.

[0025] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Please refer to Figure 2 , providing a substrate 100.

[0027] In this embodiment, the substrate 100 is made of silicon.

[0028] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0029] Please refer to Figure 3 , forming a protection layer 103 on the doping region 1021 ; performing ion implantation on the substrate 100 to form a well region 101 and a doping region 1021 located on the well region 101 .

[0030] The material of the protection layer 103 is silicon oxide or silicon oxynitride.

[0031] The process for forming the protective layer 103 is: chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: deposition rate of 2000 angstroms per minute to 3000 angstroms per minute, and deposition time of 3 seconds to 10 seconds; deposition rate of 400 angstroms per minute to 600 angstroms per minute, and deposition time of 5 seconds to 10 seconds.

[0032] The protection layer 103 is used to protect the substrate 100 from being damaged during the subsequent ion implantation process.

[0033] Specifically, when the material of the protective layer 103 is silicon oxide, the thermal expansion coefficient is 0.5×10 -6 / ℃, is a material with good thermal stability and high temperature performance, so it can maintain structural stability in high temperature environment and ensure the normal operation of ion implantation; density is 2.2g / cm 3 Up to 2.6g / cm 3 Therefore, the silicon oxide is a material with high hardness and corrosion resistance. In the subsequent etching process of the silicon nitride layer, the silicon oxide layer can serve as an etching barrier layer to ensure that the substrate 100 is not etched and make the hardness of the protective layer 103 high. Since the working principle of ion implantation is to bombard the semiconductor material through a high-energy ion beam, the protective layer 103 has good mechanical strength and hardness to withstand the impact of the ion beam and ensure the stable operation of the equipment.

[0034] In this embodiment, the process parameters for implanting ions into the substrate 100 to form the well region 101 are: ion concentration range is 2.0E4 ions / cm 2 To 5.0E7 ions / cm 2 .

[0035] The doped region 1021 is used for subsequently forming the source / drain region 102 .

[0036] In some embodiments, the type of ions in the well region 101 is opposite to the type of ions in the doping region 1021 .

[0037] In one embodiment, the ion type in the well region 101 is P-type ion, and the ion type in the doping region 1021 is N-type ion.

[0038] In another embodiment, the ion type in the well region 101 is N-type ion, and the ion type in the doping region 1021 is P-type ion.

[0039] Please refer to Figure 4 , a first photoresist layer 104 having a control gate 107 pattern is formed on the protection layer 103 .

[0040] Please refer to Figure 5 , using the first photoresist layer 104 as a mask, the protection layer 103, the doped region 1021 and the well region 101 are etched in sequence to form a first opening 105 and a source / drain region 102 located on the well region 101 in the substrate 100; and a control gate dielectric layer is formed on the surface of the first opening 105 and the surface of the source / drain region 102.

[0041] The step of forming a control gate dielectric layer includes: forming a charge tunneling layer 1061 on the surface of the first opening 105 and the surface of the source / drain region 102; forming a charge trapping layer 1062 on the surface of the charge tunneling layer 1061; and forming a charge blocking layer 1063 on the surface of the charge trapping layer 1062.

[0042] In this embodiment, the control gate dielectric layer is an "ONO" structure, that is, a "sandwich structure" formed by silicon oxide, silicon nitride and silicon oxide.

[0043] In this embodiment, the process for etching the doped region 1021 and the well region 101 is: a dry etching process, and the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate 100 are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

[0044] Please refer to Figure 6 , a control gate layer 1071 is formed in the first opening 105 and on the source / drain region 102 .

[0045] The material of the control gate layer 1071 is single crystal silicon or polycrystalline silicon.

[0046] Please refer to Figure 7, the control gate layer 1071 on the source / drain region 102 and the control gate layer 1071 in a portion of the first opening 105 are removed by etching, and a control gate 107 and a second opening 108 are formed in the substrate 100 .

[0047] The second opening 108 is located on the top surface of the control gate 107 . The top surface of the control gate 107 is flush with the bottom of the source / drain region 102 . The source / drain region 102 is located on the top surface of the control gate 107 .

[0048] The second opening 108 is used for a second contact hole subsequently located on the top surface of the control gate 107 .

[0049] Please refer to Figure 8 , the control gate dielectric layer on the top surface of the source / drain region 102 and the control gate dielectric layer on the side wall of the second opening 108 are etched away to form a dielectric layer 106 ; an isolation layer 109 is deposited on the side wall surface of the second opening 108 and on the top of the control gate 107 to form a dielectric layer.

[0050] In this embodiment, the groove is in a "U" shape.

[0051] Of course, the present invention is not limited to this, and other channel shapes in which the channel length is greater than the horizontal distance between the source and the drain are within the protection scope of the present invention.

[0052] In the above scheme, since the control gate 107 is located in the substrate 100, the channel length distance L2 between adjacent source / drain regions 102 is increased from the distance in the horizontal direction to the sum of the lengths along the surface of the control gate 107 located in the substrate 100, thereby achieving a condition in which the distance between the source and the drain in the horizontal direction remains unchanged or decreases, and the carrier channel length becomes longer, thereby improving the withstand voltage of the source-drain junction, thereby reducing the storage unit area and improving the performance of the memory.

[0053] Specifically, the present invention is directed to an embedded non-volatile memory structure, and adopts a CHE (Channel Hot Electron) programming and erasing method. In the above scheme, by increasing the channel length, normal pressure is ensured at both ends of the source and drain, thereby realizing CHE programming and erasing.

[0054] Please refer to Fig. 9, forming an interlayer dielectric layer 110 on the isolation layer 109, the interlayer dielectric layer 110 covering the source / drain region 102 and the control gate 107; forming a second photoresist layer having a first contact hole 1101 pattern on the interlayer dielectric layer 110; using the second photoresist layer as a mask, sequentially etching the interlayer dielectric layer 110 and the isolation layer 109 until the top surface of the source / drain region 102 is exposed to form the first contact hole 1101.

[0055] The process of etching the interlayer dielectric layer 110 is dry etching, and the process parameters of the dry etching include: chamber pressure of 20mT to 100mT, source power of 500W to 2800W, bias power of 30W to 2800W, gas flow rate of 20sccm to 200sccm, and etching time of 8s to 20s.

[0056] After the step of forming the first contact hole 1101, it also includes: forming a first metal layer (not shown in the figure) at the bottom of the first contact hole 1101; performing an annealing process to react the first metal layer with the top surface of the source / drain region 102 to form a first metal silicide layer 1102.

[0057] In this embodiment, the method for forming the first metal layer is a chemical vapor deposition process, the material of the first metal layer is a nickel-platinum alloy, titanium or cobalt, and the thickness of the first metal layer ranges from 80 angstroms to 130 angstroms.

[0058] In this embodiment, the steps of performing annealing process treatment include: performing a first sub-annealing process treatment on the top surface of the first metal layer and a portion of the source / drain region 102 to cause the first metal layer and the top surface of a portion of the source / drain region 102 to react to form a high-resistance metal silicide layer (not shown in the figure); performing a second sub-annealing process treatment on the high-resistance metal silicide layer to cause a phase change reaction to occur in the high-resistance metal silicide layer to form a first metal silicide layer 1102.

[0059] In this embodiment, the first annealing process adopts a rapid thermal annealing furnace, and the process parameters of the first annealing process are: annealing temperature is 200° C. to 350° C., and annealing time is 15 seconds to 45 seconds.

[0060] In this embodiment, the second annealing process adopts a rapid thermal annealing furnace, and the process parameters of the second annealing process are: annealing temperature is 300° C. to 600° C., and time is 15 seconds to 45 seconds.

[0061] In this embodiment, after the first partial annealing process, the method further includes: removing the first metal layer that does not react with silicon by wet etching to prevent a circuit short circuit caused by bridging.

[0062] The temperature of the first sub-annealing process is lower than the temperature of the second sub-annealing process. In the first sub-annealing process, the annealing temperature is 200°C to 350°C. The first metal layer will only react with a portion of the top surface of the source / drain region 102 to form a high-resistance metal silicide layer. If the annealing temperature is outside the range of 200°C to 350°C, it will cause the first metal layer to react incompletely or over-react with a portion of the top surface of the source / drain region 102.

[0063] In the second annealing process, the annealing temperature is 300°C to 600°C, which converts the high-resistance metal silicide layer into a low-resistance metal silicide layer. If the annealing temperature is outside the range of 300°C to 600°C, the high-resistance metal silicide layer will not be completely converted into the low-resistance metal silicide layer.

[0064] In the above scheme, two annealing processes are used to form the first metal silicide layer 1102, avoiding the problem of short circuit caused by generating a low-resistance metal silicide layer through only one annealing process. Specifically, the process temperature under the one annealing process will be very high. In such a high temperature environment, silicon can diffuse along the grain boundaries of the first metal silicide layer 1102, causing excessive growth of the first metal silicide layer 1102 above the silicon oxide boundary, and subsequent wet etching cannot remove the first metal silicide layer 1102 on the oxide, causing a short circuit.

[0065] In this embodiment, the material of the first metal silicide layer 1102 is: NiSi containing Pt.

[0066] Please refer to Fig.10 , filling the first contact hole 1101 with conductive material to form a first conductive plug 1103 .

[0067] In this embodiment, the first conductive plug 1103 is formed by using a chemical vapor deposition process or a physical vapor deposition process.

[0068] In this embodiment, the material of the first conductive plug 1103 is copper, aluminum or tungsten.

[0069] Please refer to Fig.11 , Fig.11 is along Fig.10 A cross-sectional schematic diagram along the AA1 direction is shown in which a third photoresist layer (not shown in the figure) having a contact hole pattern is formed on the interlayer dielectric layer 110; using the third photoresist layer as a mask, the interlayer dielectric layer 110 and the isolation layer 109 are sequentially etched until the top surface of the control gate 107 is exposed to form a second contact hole (not shown in the figure).

[0070] After the step of forming the second contact hole, the step further includes: forming a second metal layer at the bottom of the second contact hole (not shown in the figure); performing an annealing process to react the second metal layer (not shown in the figure) with the top surface of the control gate 107 to form a second metal silicide layer 111; and filling the second contact hole (not shown in the figure) with a conductive material to form a second conductive plug 112.

[0071] In this embodiment, the method for forming the second metal silicide layer 111 and the second conductive plug 112 is the same as the method for forming the second metal silicide layer 111 and the second conductive plug 112 described above, and will not be repeated herein.

[0072] Please continue to refer to Fig.10 as well as Fig.11 The present invention also provides a semiconductor structure, comprising: a substrate 100; a well region 101 located in the substrate 100; a doped region 1021 located in the substrate 100 and located on the surface of the well region 101; a first opening 105 located in the doped region 1021 and in a portion of the well region 101; a source / drain region 102 located in the doped region 1021; a control gate 107 located in the first opening 105; and a second opening 108 located on the control gate 107 and between adjacent source / drain regions 102.

[0073] In this embodiment, the semiconductor structure also includes: a dielectric layer located on the sidewall and bottom surface of the control gate 107, and the dielectric layer includes: a charge tunneling layer 1061, a charge trapping layer 1062 located on the surface of the charge tunneling layer 1061, and a charge blocking layer 1063 located on the surface of the charge trapping layer 1062.

[0074] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 110, the interlayer dielectric layer 110 covers the source / drain region 102 and the control gate 107; a contact hole located in the interlayer dielectric layer 110; and a metal silicide layer located on the bottom surface of the contact hole.

[0075] Please refer to Fig.12 , Fig.12 3 is a schematic diagram of the structure of a memory array, wherein the memory array includes a plurality of memory cells 301 arranged in an array.

[0076] In this embodiment, the storage unit 301 is a transistor, the gates of the transistors in the same row are connected to the same word line (WL00 to WL02), the drains of the transistors in the same row are connected to the same bit line (BLD0 to BLD3), and the sources of the transistors in the same row are connected to the same bit line (BLS0 to BLS3).

[0077] In some embodiments, applying a high level value to any word line turns on the channel between the source and the drain, and applying a low level value to any word line turns off the channel between the source and the drain.

[0078] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Performing ion implantation on the substrate to form a well region and a doped region located on the well region; forming a first photoresist layer having a control gate pattern on the doped region; Using the first photoresist layer as a mask, sequentially etching the doped region and the well region to form a first opening and a source / drain region located on the well region in the substrate; forming a control gate layer in the first opening and on the source / drain region; The control gate layer on the source / drain region and the control gate layer in a portion of the first opening are etched away to form a control gate and a second opening in the substrate, wherein the second opening is located on the top surface of the control gate, the top surface of the control gate is flush with the bottom of the source / drain region, and the source / drain region is located on the top surface of the control gate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process for etching the doped region and the well region is: a dry etching process, the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

3. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before the step of forming the control gate layer, forming a control gate dielectric layer on the surface of the first opening and the surface of the source / drain region; After the step of forming the control gate, the control gate dielectric layer on the top surface of the source / drain region and the control gate dielectric layer on the side wall of the second opening are removed by etching to form a dielectric layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The step of forming a control gate dielectric layer comprises: forming a charge tunneling layer on a surface of the first opening and a surface of the source / drain region; forming a charge trapping layer on the surface of the charge tunneling layer; A charge blocking layer is formed on the surface of the charge trapping layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: After the step of forming the dielectric layer, the method further comprises: Depositing an isolation layer on the sidewall surface of the second opening and on the top of the control gate; forming an interlayer dielectric layer on the isolation layer, wherein the interlayer dielectric layer covers the source / drain region and the control gate; forming a second photoresist layer having a contact hole pattern on the interlayer dielectric layer; Using the second photoresist layer as a mask, the interlayer dielectric layer and the isolation layer are sequentially etched until the surface of the source / drain region and the top surface of the control gate are exposed to form a contact hole.

6. The method for forming a semiconductor structure according to claim 5, wherein: After the step of forming the contact hole, the method further comprises: forming a metal layer at the bottom of the contact hole; Performing an annealing process to react the metal layer with the top surface of the source / drain region and the top surface of the control gate to form a metal silicide layer; A conductive material is filled into the contact hole to form a conductive plug.

7. A semiconductor structure, characterized in that: include: substrate; A well region located in the substrate; a doped region, located in the substrate and on the surface of the well region; A first opening is located in the doped region and a portion of the well region; A source / drain region, located in the doped region; a control grid, located in the first opening; The second opening is located on the control gate and between adjacent source / drain regions.

8. The semiconductor structure according to claim 7, wherein: Also includes: A dielectric layer is located on the sidewall and bottom surface of the control gate, and the dielectric layer includes: a charge tunneling layer, a charge trapping layer located on the surface of the charge tunneling layer, and a charge blocking layer located on the surface of the charge trapping layer.

9. The semiconductor structure according to claim 7, wherein: Also includes: an interlayer dielectric layer, the interlayer dielectric layer covering the source / drain region and the control gate; A contact hole located in the interlayer dielectric layer; The metal silicide layer is located on the bottom surface of the contact hole.

10. A memory array, characterized in that: The invention comprises memory cells arranged in an array, wherein the memory cells are formed by the method for forming a semiconductor structure according to any one of claims 1 to 6.

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