Lateral double-diffused metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The embodiment of the invention provides a lateral double-diffused metal oxide semiconductor field effect transistor and a preparation method thereof, and the lateral double-diffused metal oxide semiconductor field effect transistor comprises the components of a semiconductor substrate which is provided with a body region and a drift region; the gate structure is arranged on the semiconductor substrate and covers partial surfaces of the body region and the drift region; the self-aligned silicide barrier layer is arranged on the semiconductor substrate and covers part of the surface of the drift region; the metal field plate is arranged on one side, deviating from the semiconductor substrate, of the self-aligned silicide barrier layer; the surface of the semiconductor substrate is further provided with dielectric layers located on the two sides of the metal field plate and the self-aligned silicide barrier layer. A diffusion barrier layer is arranged between the metal field plate and the dielectric layer so as to prevent metal materials of the metal field plate from diffusing into the dielectric layer. While the voltage endurance capability of the lateral double-diffused metal oxide semiconductor field effect transistor is improved, the diffusion of the metal material in the dielectric layer can be reduced to a certain extent.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of semiconductor technology, and in particular to a lateral double diffused metal oxide semiconductor field effect transistor and a preparation method thereof. Background Art

[0002] LDMOS (Lateral Diffused Metal Oxide Semiconductor) is a power device suitable for high voltage applications. It has the characteristics of fast operating frequency, good stability and low switching loss. It is one of the core devices of BCD (Bipolar-CMOS-DMOS) products.

[0003] In order to ensure that LDMOS has both good voltage resistance and low on-resistance, a polysilicon field plate is usually formed on the surface of the drift region of LDMOS to regulate the electric field on the surface of the drift region. However, the conductivity of the polysilicon field plate is weak, resulting in poor electric field regulation capability. Using a metal field plate with strong conductivity to replace the polysilicon field plate can improve the electric field regulation capability and thus improve the voltage resistance of LDMOS.

[0004] However, when a metal field plate is used instead of a polysilicon field plate in LDMOS, the metal material is easily diffused into the dielectric layer around the field plate, which affects the performance of the LDMOS. Summary of the invention

[0005] In view of this, multiple embodiments of this specification are directed to providing a lateral double diffused metal oxide semiconductor field effect transistor and a method for manufacturing the same, which can reduce the diffusion of metal materials in the dielectric layer to a certain extent.

[0006] An embodiment of the present specification provides a lateral double diffused metal oxide semiconductor field effect transistor, comprising: a semiconductor substrate, the semiconductor substrate being formed with a body region and a drift region; a gate structure, the gate structure being arranged on the semiconductor substrate and covering a portion of the surface of the body region and the drift region; a self-aligned silicide barrier layer, the self-aligned silicide barrier layer being arranged on the semiconductor substrate and covering a portion of the surface of the drift region; wherein the self-aligned silicide barrier layer also covers a side of the gate structure located in the drift region, and a portion of the surface adjacent to the side; a metal field plate, the metal field plate being arranged on a side of the self-aligned silicide barrier layer away from the semiconductor substrate; wherein a dielectric layer located on both sides of the metal field plate and the self-aligned silicide barrier layer is further arranged on the surface of the semiconductor substrate; a diffusion barrier layer is arranged between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

[0007] Optionally, the material of the metal field plate is one of the following: tungsten, copper, aluminum-copper alloy; wherein, when the material of the metal field plate is tungsten or aluminum-copper alloy, the material of the diffusion barrier layer is titanium and titanium nitride; or, when the material of the metal field plate is copper, the material of the diffusion barrier layer is tantalum and tantalum nitride.

[0008] Optionally, when the material of the metal field plate is tungsten, the thickness range of the diffusion barrier layer is: 260Å~330Å; wherein the ratio of the thickness of titanium to titanium nitride is 1:2; or, when the material of the metal field plate is aluminum-copper alloy, the thickness range of the diffusion barrier layer is: 280Å~350Å; wherein the ratio of the thickness of titanium to titanium nitride is 3:4; or, when the material of the metal field plate is copper, the thickness range of the diffusion barrier layer is: 380Å~410Å; wherein the ratio of the thickness of tantalum to tantalum nitride is 1:1.

[0009] Optionally, the lateral double diffused metal oxide semiconductor field effect transistor also includes a metallization layer; wherein the metallization layer is arranged on a side of the metal field plate away from the semiconductor substrate, and a surface of the metal field plate facing away from the semiconductor substrate is covered by a metal portion of the metallization layer.

[0010] Optionally, the metal portion of the metallization layer is made of the same material as that of the metal field plate.

[0011] Optionally, the semiconductor substrate is also formed with a plurality of heavily doped regions; the surfaces of the plurality of heavily doped regions are respectively provided with contact structures passing through the dielectric layer; wherein the contact structure includes a contact plug and a contact barrier layer arranged around the surface of the contact plug; the material of the contact barrier layer is the same as the material of the diffusion barrier layer, and the material of the contact plug is the same as the material of the metal field plate; or, the material of the contact plug is different from the material of the metal field plate and the metal part of the metallization layer.

[0012] An embodiment of the present specification provides a method for preparing a lateral double diffused metal oxide semiconductor field effect transistor, the method comprising: providing a substrate; the substrate comprising a semiconductor substrate, a gate structure, a self-aligned silicide blocking material layer and a dielectric material layer disposed on the surface of the semiconductor substrate; the self-aligned silicide blocking material layer is covered by the dielectric material layer; wherein the semiconductor substrate is formed with a body region and a drift region; the gate structure is disposed on the semiconductor substrate and covers a portion of the surface of the body region and the drift region; the self-aligned silicide blocking material layer covers a portion of the surface of the drift region, and the self-aligned silicide blocking material layer also Covering the side of the gate structure located in the drift region and a portion of the surface adjacent to the side; etching the dielectric material layer and the self-aligned silicide barrier material layer to form a self-aligned silicide barrier layer and a dielectric layer located on the surface of the semiconductor substrate, and a filling window located on the side of the self-aligned silicide barrier layer away from the semiconductor substrate; forming a diffusion barrier layer and a metal field plate in the filling window; wherein the dielectric layer is located on both sides of the metal field plate and the self-aligned silicide barrier layer; and the diffusion barrier layer is at least partially located between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

[0013] Optionally, the semiconductor substrate is also formed with a plurality of heavily doped regions; contact structures passing through the dielectric layer are respectively formed on the surfaces of the plurality of heavily doped regions; the step of forming a diffusion barrier layer and a metal field plate in the filling window comprises: setting the diffusion barrier layer on the side and bottom of the filling window; the diffusion barrier layer forms a field plate window; filling and forming a metal field plate in the field plate window; the method further comprises: forming a metal material layer on the surface of the metal field plate, the dielectric layer and the plurality of contact structures facing away from the semiconductor substrate; wherein the metal material layer and the metal field plate are made of the same material, and the process of forming the metal material layer and the process of forming the metal field plate belong to the same process step.

[0014] Optionally, the method also includes: for the metal material layer, using photolithography and etching processes to form a metallization layer; the metallization layer includes a metal part formed after the metal material layer is etched, and a metal insulation part; wherein the surface of the metal field plate and the contact structure facing away from the semiconductor substrate is covered by the metal part of the metallization layer.

[0015] An embodiment of the present specification provides a method for preparing a lateral double diffused metal oxide semiconductor field effect transistor, the method comprising: providing a semiconductor substrate; the semiconductor substrate comprising a semiconductor substrate, a gate structure, a self-aligned silicide barrier material layer disposed on the surface of the semiconductor substrate, an intermediate dielectric material layer, and a plurality of contact structures passing through the intermediate dielectric material layer; the self-aligned silicide barrier material layer is covered by the intermediate dielectric material layer; wherein the semiconductor substrate is formed with a body region, a drift region, and a plurality of heavily doped regions corresponding to the plurality of contact structures; the gate structure is disposed on the semiconductor substrate and covers a portion of the surface of the body region and the drift region; the self-aligned silicide barrier material layer covers a portion of the surface of the drift region, and the self-aligned silicide barrier layer also covers the side of the gate structure located in the drift region, and a portion of the surface adjacent to the side; the plurality of contact structures are respectively located on the surfaces of the corresponding heavily doped regions; an intermetallic insulating material layer, a hard mask layer, and a photoresist are stacked on the surfaces of the intermediate dielectric material layer and the contact structure. layer; forming a plurality of openings for defining the shape of the metallization layer in the metal-intermediate insulating material layer by photolithography and etching processes; wherein the metal-intermediate insulating material is etched to form the metal-intermediate insulating portion of the metallization layer; etching the intermediate dielectric material layer and the self-aligned silicide barrier material layer in the opening corresponding to the self-aligned silicide barrier material layer to form the self-aligned silicide barrier layer and the dielectric layer located on the surface of the semiconductor substrate, and a filling window located on the side of the self-aligned silicide barrier layer away from the semiconductor substrate; depositing a diffusion barrier layer on the side and bottom of the filling window; the diffusion barrier layer forms a field plate window; filling the field plate window and the plurality of openings with the same metal material to form a metal field plate, and a metallization layer composed of the metal-intermediate insulating portion and the metallization layer filled in the plurality of openings; wherein the dielectric layer is located on both sides of the metal field plate and the self-aligned silicide barrier layer; the diffusion barrier layer is at least partially located between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

[0016] The unexpected effect of the multiple embodiments provided in this specification is that the field plate structure formed by setting a metal field plate and a diffusion barrier layer can utilize the strong electric field suppression ability of the metal field plate to improve the voltage resistance of LDMOS. At the same time, due to the diffusion barrier layer between the metal field plate and the dielectric layer of LDMOS to block the metal material, the diffusion of the metal material in the dielectric layer can be reduced to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of an LDMOS provided in this specification.

[0018] Figure 2 A schematic diagram of an LDMOS provided for one embodiment of the present specification.

[0019] Figure 3 A schematic diagram of a method for preparing an LDMOS provided in one embodiment of this specification.

[0020] Figure 4 A schematic diagram of a substrate provided for one embodiment of the present specification.

[0021] Figure 5 A schematic diagram of etching a dielectric material layer and a self-aligned silicide blocking material layer is provided for one embodiment of the present specification.

[0022] Figure 6 and Figure 7 A schematic diagram of forming a diffusion barrier layer and a metal field plate in a filling window according to an embodiment of the present specification.

[0023] Figure 8 A schematic diagram of forming a metallization layer is provided for one embodiment of the present specification.

[0024] Fig. 9 A schematic diagram of fabricating a contact structure on the surface of a heavily doped region is provided for one embodiment of the present specification.

[0025] Fig.10 A schematic diagram of forming a filling window is provided for one embodiment of the present specification.

[0026] Fig.11 A schematic diagram of forming a diffusion barrier layer in a filling window according to an embodiment of the present disclosure is provided.

[0027] Fig.12 A schematic diagram of forming a metal field plate and a metal material layer is provided for one embodiment of the present specification.

[0028] Fig.13 A schematic diagram of forming a metallization layer by manufacturing a metal material layer according to an embodiment of the present specification.

[0029] Fig.14 A schematic diagram of a method for preparing an LDMOS according to another embodiment of the present specification.

[0030] Fig.15 A schematic diagram of a semiconductor substrate provided according to another embodiment of the present disclosure.

[0031] Fig.16 A schematic diagram of stacking an intermetallic insulating material layer, a hard mask layer, and a photoresist layer on the surface of an intermediate dielectric material layer and a contact structure is provided for another embodiment of the present specification.

[0032] Fig.17A schematic diagram of forming a plurality of openings in an intermetallic insulating material layer according to another embodiment of the present disclosure is provided.

[0033] Fig.18 and Fig.19 A schematic diagram of opening a filling window in an opening corresponding to a position of a self-aligned silicide blocking material layer is provided as another embodiment of the present specification.

[0034] Fig. 20 A schematic diagram of forming a diffusion barrier layer according to another embodiment of the present disclosure.

[0035] Fig.21 A schematic diagram of forming a metal field plate and a metallization layer is provided for another embodiment of the present specification.

[0036] Description of reference numerals: 10a, N-channel LDMOS; 11a, N-type drift region; 12a, field plate; 13a, adjacent dielectric layer; 14a, adjacent salicide barrier layer; 10, LDMOS; 11, semiconductor substrate; 111, body region; 112, drift region; 113, heavily doped region; 114, P-type well region; 115, deep P-type well region; 116, P-type epitaxial region; 12, salicide barrier layer; 13, metal field plate; 14, diffusion barrier layer; 15, dielectric layer; 16, metallization layer; 161. Metal part; 162. Intermetallic insulating part; 17. Contact structure; 171. Contact barrier layer; 172. Contact plug; 18. Gate structure; 21. Substrate; 22. Self-aligned silicide barrier material layer; 23. Dielectric material layer; 24. Filling window; 25. Contact window; 26. Field plate window; 27. Metal material layer; 31. Semiconductor substrate; 32. Intermetallic insulating material layer; 33. Hard mask layer; 34. Photoresist layer; 35. Opening; 36. Intermediate dielectric material layer. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of this specification will be described clearly and completely below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, rather than all the embodiments.

[0038] In this specification, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0039] Unless otherwise stated, all technical and scientific terms used in this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above" and "the" used in this specification embodiment and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0040] In the description of this specification, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this specification, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0041] In the description of this specification, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of simplified description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present application.

[0042] In the description of this specification, unless otherwise clearly defined, the terms "install", "connect", "connect", "fix", "set", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0043] See also Figure 1 . Figure 1 Schematic diagram of the structure of an N-channel LDMOS 10a provided in this specification. Figure 1 As shown in FIG. 1 , a field plate 12a formed of polysilicon is provided on the side of the surface of the N-type drift region 11a of the LDMOS 10a away from the substrate to regulate the electric field on the surface of the N-type drift region 11a and improve the voltage resistance of the LDMOS.

[0044] In order to enhance the ability of the field plate 12a to regulate the surface electric field of the N-type drift region 11a and further improve the voltage resistance of the LDMOS 10a, a metal field plate formed of a metal material can be used instead of a polysilicon field plate. This is mainly because the metal field plate has better conductivity and stronger electric field regulation ability. However, Figure 1 As shown in FIG. 1 , an adjacent dielectric layer (Interlayer Dielectric, ILD) 13a and an adjacent self-aligned silicide barrier layer (Self-Aligned Block, SAB) 14a adjacent to the field plate are also provided in the LDMOS 10a. When a metal field plate made of a metal material is used instead of a polysilicon field plate, the metal material of the field plate 12a may easily diffuse into the adjacent dielectric layer 13a, thereby affecting the performance of the LDMOS 10a.

[0045] Therefore, it is necessary to provide an LDMOS and a method for manufacturing the same, which can reduce the diffusion of the metal material of the metal field plate in the dielectric layer while using the metal field plate, thereby improving the performance of the LDMOS.

[0046] See also Figure 2 An embodiment of the present specification provides an LDMOS 10 . The LDMOS 10 is an N-channel LDMOS, and includes a semiconductor substrate 11 , a gate structure 18 , a salicide barrier layer 12 , a dielectric layer 15 , and a metal field plate 13 .

[0047] The semiconductor substrate 11 can serve as the basic structure of the LDMOS 10, not only for providing mechanical support, but also for affecting the electrical properties of the device, such as threshold voltage and carrier mobility, by doping ions. Specifically, the semiconductor substrate 11 can be made of silicon (Si), or can be made of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), etc., as required.

[0048] The semiconductor substrate 11 may be formed with a body region 111 (Bulk) and a drift region 112 (Drift). The body region 111, as the main part of the semiconductor substrate 11, may be used to control the body voltage, thereby affecting the working state of the LDMOS 10. The body region 111 may be a well region formed by ion doping in the semiconductor substrate 11. Depending on the type of LDMOS, the body region 111 may have different conductivity types. For example, for Figure 2In the N-channel LDMOS shown, the body region 111 is a P-type region of the semiconductor substrate 11, and may specifically include a P-type well region 114 (P-Well, PW), a deep P-well region 115 (Deep P-Well, DPW), and a P-type epitaxial region 116 (P-Type Epitaxial Layer, P-EPI). For a P-channel LDMOS, the body region is an N-type region of the semiconductor substrate. The drift region 112 is a lightly doped region in the semiconductor substrate 11, which is used to provide sufficient withstand voltage for the LDMOS 10. For an N-channel LDMOS 10, the drift region 112 is an N-type region. For a P-channel LDMOS, the drift region is a P-type region.

[0049] In addition to the body region 111 and the drift region 112, a plurality of heavily doped regions 113 including a source, a drain, a body contact region, etc. may be formed in the semiconductor substrate 11. The plurality of heavily doped regions 113 may include a P-type heavily doped region and an N-type heavily doped region according to different doped ion types. The source and the body contact region are located on one side of the body region 111 and are in contact with the body region 111. The source and the body contact region have different doping types. The body contact region may have the same doping type as the body region 111, but the doping concentration is higher than that of the body region 111. For example, for an N-channel LDMOS 10, the body contact region may be a P-type heavily doped region. The drain is located on the side of the drift region 112 away from the source and is in contact with the drift region 112. The drift region 112 may be located between the source and the drain. The drain may have the same doping type as the drift region 112, but the doping concentration is higher than that of the drift region 112. For example, for an N-channel LDMOS 10 , the drain may be an N-type heavily doped region.

[0050] On the side of the P-type epitaxial region 116 away from the drift region 112, the semiconductor substrate 11 is further formed with an N-type isolation well region for isolation, and an N-type heavily doped region in contact with the N-type isolation well region and close to the surface of the semiconductor substrate 11. In addition to the source, drain and body contact regions, the multiple heavily doped regions 113 may also include the N-type heavily doped region.

[0051] A gate structure 18 covering both the body region 111 and a portion of the drift region 112 is disposed on the surface of the semiconductor substrate 11, and a self-aligned silicide barrier layer 12 covering a portion of the drift region 112. Specifically, the self-aligned silicide barrier layer 12 may also cover the side of the gate structure 18 located in the drift region 112, and a portion of the surface of the gate structure 18 adjacent to the side and away from the semiconductor substrate 11, that is, Figure 2As shown in , the self-aligned silicide barrier layer 12 covers the drift region 112 and the portion of the gate structure 18 near the drift region 112 at the same time. Among them, the gate structure 18 can be composed of a gate material and a gate oxide layer. As a gate electrode, the gate material can be polysilicon or a metal (such as aluminum Al). The gate material can be isolated from the substrate by the gate oxide layer. The gate oxide layer can specifically be silicon dioxide SiO2. In some possible embodiments, the gate structure 18 can also include a work function adjustment layer. When a voltage is applied to the gate structure 18, carriers can be attracted or repelled, thereby controlling the flow of carriers between the source and the drain. The self-aligned silicide barrier layer 12 can be used as a dielectric layer between the field plate and the drift region 112, and together with the field plate, it plays a role in regulating the surface electric field of the drift region 112, and can define the formation position and shape of the field plate. Specifically, the material of the self-aligned silicide barrier layer 12 can be silicide, for example, silicon dioxide, silicon nitride, etc.

[0052] The metal field plate 13 is disposed on the side of the self-aligned silicide barrier layer 12 away from the semiconductor substrate 11. The metal field plate 13 is connected to the same potential as the source and the body region 111. When a high voltage is applied to the drain, the metal field plate 13 can regulate the electric field distribution in the drift region 112 at the same potential as the source, so that the voltage resistance of the LDMOS 10 is improved. Specifically, the projection of the metal field plate 13 on the surface of the semiconductor substrate 11 can be within the drift region 112 and located in the area formed by the self-aligned silicide barrier layer 12 covering the drift region 112. In some possible embodiments, the projection of the metal field plate 13 on the surface of the semiconductor substrate 11 can also overlap with the area formed by the self-aligned silicide barrier layer 12 covering the drift region 112.

[0053] A dielectric layer 15 (Inter-Layer Dielectric, ILD) is also provided on the surface of the semiconductor substrate 11. The dielectric layer 15 can be used to achieve electrical isolation between different metal layers of the LDMOS 10. Specifically, the dielectric layer 15 can be located on both sides of the metal field plate 13 and the self-aligned silicide barrier layer 12, that is, the stacked structure formed by the self-aligned silicide barrier layer 12 and the metal field plate 13 can pass through the dielectric layer 15.

[0054] A diffusion barrier layer 14 is provided between the metal field plate 13 and the dielectric layer 15 to prevent the metal material of the metal field plate 13 from diffusing into the dielectric layer 15. The unexpected effect of this embodiment is that, by providing the field plate structure formed by the metal field plate 13 and the diffusion barrier layer 14, while utilizing the strong electric field suppression capability of the metal field plate 13 to improve the withstand voltage capability of the LDMOS 10, the diffusion barrier layer 14 between the metal field plate 13 and the dielectric layer 15 of the LDMOS 10 blocks the metal material, thereby reducing the diffusion of the metal material in the dielectric layer 15 and preventing the performance of the LDMOS 10 from being affected.

[0055] In this embodiment, a diffusion barrier layer 14 may also be provided between the metal field plate 13 and the salicide barrier layer 12 to make the surface of the metal field plate 13 more tightly wrapped, further reducing the phenomenon of metal material diffusing outward. It should be noted that, in some possible embodiments, the diffusion barrier layer 14 only needs to be provided between the metal field plate 13 and the dielectric layer 15 to achieve the effect of reducing the diffusion of metal materials in the dielectric layer 15.

[0056] Furthermore, since polysilicon is usually used in the related art to form Figure 1 The field plate shown in the figure has a height relative to the semiconductor substrate of the portion close to the gate structure 18, which is higher than the height relative to the semiconductor substrate of the portion far from the gate structure 18. Therefore, multiple polysilicon deposition and etching processes are required in the manufacturing process, and the process steps are relatively complicated, and the process stability is poor. In this embodiment, the polysilicon deposition and etching processes are avoided by using the metal field plate 13, which not only simplifies the process steps, but also increases the stability of the process.

[0057] In this embodiment, the material of the metal field plate 13 is one of the following: tungsten, copper, and aluminum-copper alloy; wherein, when the material of the metal field plate 13 is tungsten or aluminum-copper alloy, the material of the diffusion barrier layer 14 is titanium and titanium nitride; or, when the material of the metal field plate 13 is copper, the material of the diffusion barrier layer 14 is tantalum and tantalum nitride.

[0058] Since the metal field plates 13 made of different materials have different outward diffusion rates of the metal materials, the material of the diffusion barrier layer 14 needs to be determined according to the material of the metal field plate 13. Specifically, for example, the diffusion rates of tungsten and aluminum-copper alloys are usually low, so titanium and titanium nitride are selected as the corresponding materials of the diffusion barrier layer 14. The diffusion rate of copper is high, so tantalum and tantalum nitride, which have better diffusion barrier effects, need to be selected as the corresponding materials of the diffusion barrier layer 14.

[0059] In this embodiment, when the material of the metal field plate 13 is tungsten, the thickness of the diffusion barrier layer 14 ranges from 260Å to 330Å, wherein the ratio of the thickness of titanium to titanium nitride is 1:2; or, when the material of the metal field plate 13 is an aluminum-copper alloy, the thickness of the diffusion barrier layer 14 ranges from 280Å to 350Å, wherein the ratio of the thickness of titanium to titanium nitride is 3:4; or, when the material of the metal field plate 13 is copper, the thickness of the diffusion barrier layer 14 ranges from 380Å to 410Å, wherein the ratio of the thickness of tantalum to tantalum nitride is 1:1. In this way, for the combination of metal field plates 13 and diffusion barrier layers 14 of different materials, diffusion barrier layers 14 of different thicknesses are respectively set, taking into account both the conductivity of the metal field plate 13 and the anti-diffusion capability of the diffusion barrier layer 14.

[0060] In this embodiment, the lateral double diffused metal oxide semiconductor field effect transistor also includes a metallization layer 16; wherein the metallization layer 16 is arranged on the side of the metal field plate 13 away from the semiconductor substrate 11, and the surface of the metal field plate 13 facing away from the semiconductor substrate 11 is covered by the metal part 161 of the metallization layer 16.

[0061] The metallization layer 16 can be used to achieve electrical connection with an external circuit. Specifically, the metallization layer 16 can include a metal portion 161 and a metal-to-metal insulating portion 162. By covering the metal portion 161 of the metallization layer 16 on the surface of the metal field plate 13 facing away from the semiconductor substrate 11, a conductive path between the metal field plate 13 and the metallization layer 16 is achieved, so that there is no need to additionally set up a contact structure 17, thereby simplifying the process steps. In addition, since the contact area between the metal field plate 13 and the metal portion 161 of the metallization layer 16 is increased, the conductive performance is improved, and the electric field suppression capability of the metal field plate 13 can be improved, and the withstand voltage performance of the LDMOS 10 can be further improved.

[0062] In this embodiment, the metal portion 161 of the metallization layer 16 is made of the same material as the metal field plate 13 .

[0063] In the case where the metal portion 161 of the metallization layer 16 and the metal field plate 13 are made of the same material, the process of forming the metal field plate 13 and the metal portion 161 can be implemented in the same process step. For example, the metal field plate 13 and the metal portion 161 of the metallization layer 16 are directly formed in the same deposition process step. In this way, the process steps can be simplified, and since the same material as the metal portion 161 of the metallization layer 16 is used, the conductivity between the metal field plate 13 and the metallization layer 16 is improved, thereby improving the electric field suppression capability of the metal field plate 13.

[0064] In this embodiment, contact structures 17 passing through the dielectric layer 15 are respectively arranged on the surfaces of multiple heavily doped regions 113 of the semiconductor substrate 11; wherein the contact structure 17 includes a contact plug 172 and a contact barrier layer 171 arranged around the surface of the contact plug 172; the material of the contact barrier layer 171 is the same as the material of the diffusion barrier layer 14, and the material of the contact plug 172 is the same as the material of the metal field plate 13; or, the material of the contact plug 172 is different from the material of the metal field plate 13 and the metal part 161 of the metallization layer 16.

[0065] In this embodiment, contact structures 17 may be led out from the surfaces of the plurality of heavily doped regions 113 and penetrate the dielectric layer 15 to be connected to the metal portion 161 in the metallization layer 16 to achieve electrical connection with an external circuit.

[0066] When the material of the contact barrier layer 171 is the same as that of the diffusion barrier layer 14, and the material of the contact plug 172 is the same as that of the metal field plate 13, the contact structure 17 and the field plate structure composed of the metal field plate 13 and the contact barrier layer 171 can be formed in the same process step. In this way, the process steps can be simplified and the process cost can be reduced.

[0067] Since the material of the contact plug 172 is usually metal tungsten, and tungsten has poor conductivity, when the material of the contact plug 172 is different from the material of the metal field plate 13 and the metal portion 161 of the metallization layer 16, aluminum, copper, etc. can be used as the material of the metal field plate 13 and the metal portion 161 of the metallization layer 16, which has better conductivity and improves the electric field suppression capability of the metal field plate 13 on the surface of the drift region 112, so that the voltage resistance of the LDMOS 10 is better.

[0068] It should be noted that, in order to explain this embodiment in detail, Figure 2 The N-channel LDMOS 10 provided is only an example, and other types of LDMOS 10, such as P-channel LDMOS 10, are also applicable to this embodiment.

[0069] See also Figure 3-Figure 13 An embodiment of the present specification provides a method for preparing a lateral double diffused metal oxide semiconductor field effect transistor, and the preparation method may include the following steps.

[0070] S110: providing a substrate.

[0071] In some embodiments, Figure 4As shown, the base 21 includes a semiconductor substrate 11, a self-aligned silicide blocking material layer 22, a dielectric material layer 23 and a gate structure 18 arranged on the surface of the semiconductor substrate 11; the self-aligned silicide blocking material layer 22 is covered by the dielectric material layer 23; wherein the semiconductor substrate 11 is formed with a body region 111 and a drift region 112; the gate structure 18 is arranged on the semiconductor substrate 11 and covers a portion of the surface of the body region 111 and the drift region 112; the self-aligned silicide blocking material layer 22 covers a portion of the surface of the drift region 112, and the self-aligned silicide blocking material layer 22 also covers the side of the gate structure 18 located in the drift region 112, and a portion of the surface adjacent to the side.

[0072] S120: etching the dielectric material layer and the salicide barrier material layer to form a salicide barrier layer and a dielectric layer located on the surface of the semiconductor substrate, and a filling window located on a side of the salicide barrier layer away from the semiconductor substrate.

[0073] In some embodiments, Figure 5 As shown, the semiconductor substrate 11 is also formed with a plurality of heavily doped regions 113. Corresponding to the positions of the plurality of heavily doped regions 113 and the self-aligned silicide blocking material layer 22, a filling window 24 located on the side of the self-aligned silicide blocking layer 12 away from the semiconductor substrate 11 and a contact window 25 located on the surface of each heavily doped region 113 are opened by using a photolithography and etching process. The contact window 25 penetrates the dielectric material layer 23. The dielectric material layer 23 is etched to form a dielectric layer 15. The self-aligned silicide blocking material layer 22 is etched to form a self-aligned silicide blocking layer 12. In some embodiments, the self-aligned silicide blocking layer 12 formed after etching can be simultaneously located on a portion of the surface of the drift region 112 and a portion of the surface of the gate structure 18, so that after a metal field plate is formed on the self-aligned silicide blocking layer 12, the electric field distribution of the drift region 112 is more uniform.

[0074] S130: forming a diffusion barrier layer and a metal field plate in the filling window; wherein the dielectric layer is located on both sides of the metal field plate and the self-aligned silicide barrier layer; the diffusion barrier layer is at least partially located between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

[0075] In some embodiments, contact structures passing through the dielectric layer are respectively formed on the surfaces of multiple heavily doped regions; the steps of forming a diffusion barrier layer and a metal field plate in the filling window include: setting a diffusion barrier layer on the side and bottom of the filling window; forming a field plate window with the diffusion barrier layer; and filling the field plate window to form a metal field plate.

[0076] Specifically, Figure 6 and Figure 7As shown, a certain thickness of Ti and TiN is deposited by PECVD (Plasma-Enhanced Chemical Vapor Deposition) process as a diffusion barrier layer 14. Then, metal tungsten is deposited in the field plate window 26 formed by the diffusion barrier layer 14, and the excess metal tungsten is removed by CMP (Chemical Mechanical Polishing) process, so that the diffusion barrier layer 14 and the metal field plate 13 are filled in the filling window 24 to form a field plate structure.

[0077] In some embodiments, in the same PECVD process step as described above, Ti and TiN may be deposited in each contact window 25, and metal tungsten may be deposited on Ti and TiN, and excess metal tungsten may be removed to form a contact structure 17 in each contact window 25. In this way, the contact structure 17 and the field plate structure may be fabricated using the same process step, thereby simplifying the process flow.

[0078] Then, if Figure 8 As shown, a metallization layer 16 may be formed on the surfaces of the metal field plate 13 , the dielectric layer 15 and the contact structure 17 .

[0079] In some embodiments, the preparation method also includes: forming a metal material layer on the surface of the metal field plate, the dielectric layer and the multiple contact structures facing away from the semiconductor substrate; wherein the metal material layer and the metal field plate are made of the same material, and the process of forming the metal material layer and forming the metal field plate belongs to the same process step.

[0080] In some embodiments, the material of the contact structure and the metal field plate may be different. Fig. 9 As shown, the contact structure 17 penetrating the dielectric material layer 23 can be fabricated on the surface of the heavily doped region 113 of the substrate 21 to form an intermediate dielectric material layer 36, and then the intermediate dielectric material layer 36 and the self-aligned silicide material layer 22 are etched to form Fig.10 The filling window 24 shown in FIG. Then, as Fig.11 As shown in FIG. 1 , a certain thickness of Ti and TiN is deposited in the filling window 24 to serve as the diffusion barrier layer 14. The field plate window 26 formed for the diffusion barrier layer 14 is as shown in FIG. Fig.12 As shown, an aluminum-copper alloy can also be deposited by a CVD (chemical vapor deposition) process to form an integrally formed metal field plate 13 and a metal material layer 27 for making the metallization layer 16. In this way, the metal field plate 13 and the metal material layer 27 are made by the same process step, and there is no need to make the metal material layer 27 separately, thereby simplifying the process steps.

[0081] In some embodiments, Fig.13As shown, the preparation method further includes: for the metal material layer 27, using photolithography and etching processes to form a metallization layer 16; the metallization layer 16 includes a metal portion 161 formed after the metal material layer 27 is etched, and a metal-to-metal insulating portion 162; wherein, the surface of the metal field plate 13 and the contact structure 17 facing away from the semiconductor substrate 11 is covered by the metal portion 161 of the metallization layer 16. In this way, the contact surface between the metal field plate 13 and the metal portion 161 in the metallization layer 16 can be made larger, and the conductivity is better, thereby improving the electric field suppression capability of the metal field plate 13.

[0082] See also Figure 14-Figure 21 Another embodiment of the present specification provides a method for preparing a lateral double diffused metal oxide semiconductor field effect transistor, and the preparation method may include the following steps: S210: providing a semiconductor substrate.

[0083] In some embodiments, Fig.15 As shown, the semiconductor base 31 includes a semiconductor substrate 11, a gate structure 18, a self-aligned silicide blocking material layer 22 arranged on the surface of the semiconductor substrate 11, an intermediate dielectric material layer 36, and a plurality of contact structures 17 passing through the intermediate dielectric material layer 36; the self-aligned silicide blocking material layer 22 is covered by the intermediate dielectric material layer 36; wherein the semiconductor substrate 11 is formed with a body region 111, a drift region 112, and a plurality of heavily doped regions 113 corresponding to the plurality of contact structures 17; the gate structure 18 is arranged on the semiconductor substrate 11, and covers a portion of the surface of the body region 111 and the drift region 112; the self-aligned silicide blocking material layer 22 covers a portion of the surface of the drift region 112, and the self-aligned silicide blocking material layer 22 also covers the side of the gate structure 18 located in the drift region 112, and a portion of the surface adjacent to the side; and the plurality of contact structures 17 are respectively located on the corresponding surfaces of the heavily doped regions 113.

[0084] S220: stacking an intermetallic insulating material layer, a hard mask layer, and a photoresist layer on the surface of the intermediate dielectric material layer and the contact structure.

[0085] In some embodiments, Fig.16 As shown, the intermetallic insulating material layer 32, the hard mask layer 33 and the photoresist layer 34 are stacked in sequence on the surface of the intermediate dielectric material layer 36 and the contact structure 17. Among them, the intermetallic insulating material layer 32 is used to make the metallization layer, and the hard mask layer 33 is used to ensure the accuracy and reliability of the pattern transfer during the photolithography process. The photoresist layer 34 has a plurality of etching openings after development, which serve as a position reference for subsequent etching.

[0086] S230: forming a plurality of openings for defining the shape of the metallization layer in the metal inter-insulating material layer through photolithography and etching processes; wherein the metal inter-insulating material is etched to form a metal inter-insulating portion of the metallization layer.

[0087] In some embodiments, Fig.17 As shown, after the etching process, a plurality of openings 35 may be formed in the metal-intermediate insulating material layer 32, and the positions of the openings 35 correspond to the positions of the etching openings of the photoresist layer 34. The metal-intermediate insulating material remaining after etching forms the metal-intermediate insulating portion 162 of the metallization layer.

[0088] S240: Etching the intermediate dielectric material layer and the self-aligned silicide blocking material layer in the opening corresponding to the self-aligned silicide blocking material layer to form a self-aligned silicide blocking layer and a dielectric layer located on the surface of the semiconductor substrate, and a filling window located on the side of the self-aligned silicide blocking layer away from the semiconductor substrate.

[0089] In some embodiments, Figure 18-19 As shown, a filling window 24 can be opened in the opening 35 at a corresponding position of the self-aligned silicide blocking material layer 22 by photolithography and etching processes.

[0090] S250: depositing a diffusion barrier layer on the side and bottom of the filling window; the diffusion barrier layer forms a field plate window.

[0091] In some embodiments, the material used to deposit and form the diffusion barrier layer 14 may be Ta or TaN. Fig. 20 As shown, the field plate window 26 formed by the diffusion barrier layer 14 and the opening 35 at the corresponding position of the salicide barrier material layer 22 can form a combined window together.

[0092] S260: Filling the field plate window and the multiple openings with the same metal material to form a metal field plate and a metallization layer consisting of an intermetallic insulating portion and the metal material filled in the multiple openings; wherein the dielectric layer is located on both sides of the metal field plate and the self-aligned silicide barrier layer; and the diffusion barrier layer is at least partially located between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

[0093] In some embodiments, Fig.21 As shown, a copper thin seed layer deposition, copper electroplating and CMP process can be performed on the merged window formed by the field plate window 26 and the opening 35 at the corresponding position of the self-aligned silicide blocking material layer 22, as well as other openings 35, so that a field plate structure composed of Ta and TaN and a copper metal field plate 13 is formed in the filling window 24, and the copper metal filled in the multiple openings 35 is used as a metal part 161 and an inter-metal insulating part 162 to form a metallization layer 16.

[0094] An unexpected effect of this embodiment is that the diffusion barrier layer 14 located between the metal field plate 13 and the dielectric layer 15 forms a barrier for the metal material, thereby reducing the diffusion of the metal material in the dielectric layer 15 .

[0095] Furthermore, the metal field plate 13 and the metal portion 161 in the metallization layer 16 are manufactured in the same process step, which can also simplify the process steps and save process costs.

[0096] It should be understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this specification, rather than to limit the scope of the present invention.

[0097] It can be understood that in the various embodiments in this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0098] It can be understood that the various embodiments described in this specification can be implemented individually or in combination, and the embodiments of this specification are not limited to this.

[0099] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0100] The above is only a specific embodiment of this specification, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A lateral double diffused metal oxide semiconductor field effect transistor, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate is formed with a body region and a drift region; A gate structure, wherein the gate structure is disposed on the semiconductor substrate and covers a portion of the surface of the body region and the drift region; A salicide blocking layer, which is disposed on the semiconductor substrate and covers a portion of the surface of the drift region; wherein the salicide blocking layer also covers a side surface of the gate structure located in the drift region and a portion of the surface adjacent to the side surface; A metal field plate, the metal field plate being disposed on a side of the salicide barrier layer facing away from the semiconductor substrate; The surface of the semiconductor substrate is also provided with dielectric layers located on both sides of the metal field plate and the self-aligned silicide barrier layer; a diffusion barrier layer is provided between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

2. The lateral double diffused metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The material of the metal field plate is one of the following: tungsten, copper, aluminum-copper alloy; wherein, when the material of the metal field plate is tungsten or aluminum-copper alloy, the material of the diffusion barrier layer is titanium and titanium nitride; or, when the material of the metal field plate is copper, the material of the diffusion barrier layer is tantalum and tantalum nitride.

3. The lateral double diffused metal oxide semiconductor field effect transistor according to claim 2, characterized in that: When the material of the metal field plate is tungsten, the thickness of the diffusion barrier layer ranges from 260Å to 330Å; wherein the ratio of the thickness of titanium to that of titanium nitride is 1:2; or, When the material of the metal field plate is aluminum-copper alloy, the thickness of the diffusion barrier layer ranges from 280Å to 350Å; wherein the ratio of the thickness of titanium to that of titanium nitride is 3:4; or, When the material of the metal field plate is copper, the thickness of the diffusion barrier layer ranges from 380Å to 410Å; wherein the ratio of the thickness of tantalum to tantalum nitride is 1:

1.

4. The lateral double diffused metal oxide semiconductor field effect transistor according to any one of claims 1 to 3, characterized in that: The lateral double diffused metal oxide semiconductor field effect transistor also includes a metallization layer; wherein the metallization layer is arranged on a side of the metal field plate away from the semiconductor substrate, and a surface of the metal field plate facing away from the semiconductor substrate is covered by a metal portion of the metallization layer.

5. The lateral double diffused metal oxide semiconductor field effect transistor according to claim 4, characterized in that: The metal part of the metallization layer is made of the same material as the metal field plate.

6. The lateral double diffused metal oxide semiconductor field effect transistor according to claim 5, characterized in that: The semiconductor substrate is also formed with a plurality of heavily doped regions; the surfaces of the plurality of heavily doped regions are respectively provided with contact structures passing through the dielectric layer; wherein the contact structure comprises a contact plug and a contact barrier layer arranged around the surface of the contact plug; the material of the contact barrier layer is the same as the material of the diffusion barrier layer, and the material of the contact plug is the same as the material of the metal field plate; or, the material of the contact plug is different from the material of the metal field plate and the metal part of the metallization layer.

7. A method for preparing a lateral double diffused metal oxide semiconductor field effect transistor, characterized in that: The method comprises: A substrate is provided; the substrate comprises a semiconductor substrate, a gate structure, a self-aligned silicide blocking material layer and a dielectric material layer arranged on the surface of the semiconductor substrate; the self-aligned silicide blocking material layer is covered by the dielectric material layer; wherein the semiconductor substrate is formed with a body region and a drift region; the gate structure is arranged on the semiconductor substrate and covers a portion of the surface of the body region and the drift region; the self-aligned silicide blocking material layer covers a portion of the surface of the drift region, and the self-aligned silicide blocking material layer also covers a side surface of the gate structure located in the drift region, and a portion of the surface adjacent to the side surface; Etching the dielectric material layer and the salicide barrier material layer to form a salicide barrier layer and a dielectric layer located on the surface of the semiconductor substrate, and a filling window located on a side of the salicide barrier layer away from the semiconductor substrate; A diffusion barrier layer and a metal field plate are formed in the filling window; wherein the dielectric layer is located on both sides of the metal field plate and the self-aligned silicide barrier layer; and the diffusion barrier layer is at least partially located between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

8. The method according to claim 7, characterized in that The semiconductor substrate is also formed with a plurality of heavily doped regions; the surfaces of the plurality of heavily doped regions are respectively formed with contact structures penetrating the dielectric layer; the step of forming a diffusion barrier layer and a metal field plate in the filling window comprises: arranging the diffusion barrier layer on the side and bottom of the filling window; the diffusion barrier layer forms a field plate window; and filling and forming a metal field plate in the field plate window; The method further comprises: A metal material layer is formed on the surface of the metal field plate, the dielectric layer and the multiple contact structures facing away from the semiconductor substrate; wherein the metal material layer and the metal field plate are made of the same material, and the process of forming the metal material layer and the metal field plate belongs to the same process step.

9. The method according to claim 8, characterized in that The method further comprises: A metallization layer is formed by photolithography and etching processes for the metal material layer; the metallization layer includes a metal portion formed after the metal material layer is etched, and an inter-metal insulating portion; wherein the surface of the metal field plate and the contact structure facing away from the semiconductor substrate is covered by the metal portion of the metallization layer.

10. A method for preparing a lateral double diffused metal oxide semiconductor field effect transistor, characterized in that: The method comprises: A semiconductor substrate is provided; the semiconductor substrate comprises a semiconductor substrate, a gate structure, a self-aligned silicide blocking material layer arranged on the surface of the semiconductor substrate, an intermediate dielectric material layer, and a plurality of contact structures passing through the intermediate dielectric material layer; the self-aligned silicide blocking material layer is covered by the intermediate dielectric material layer; wherein the semiconductor substrate is formed with a body region, a drift region, and a plurality of heavily doped regions corresponding to the plurality of contact structures; the gate structure is arranged on the semiconductor substrate and covers a portion of the surface of the body region and the drift region; the self-aligned silicide blocking material layer covers a portion of the surface of the drift region, and the self-aligned silicide blocking material layer also covers a side surface of the gate structure located in the drift region, and a portion of the surface adjacent to the side surface; the plurality of contact structures are respectively located on the surface of the corresponding heavily doped regions; A metal-to-metal insulating material layer, a hard mask layer and a photoresist layer are stacked on the surfaces of the intermediate dielectric material layer and the contact structure; By means of photolithography and etching processes, a plurality of openings for defining the shape of the metallization layer are formed in the metallization insulating material layer; wherein the metallization insulating portion of the metallization layer is formed after the metallization insulating material is etched; Etching the intermediate dielectric material layer and the self-aligned silicide barrier material layer in the opening corresponding to the self-aligned silicide barrier material layer to form a self-aligned silicide barrier layer and a dielectric layer located on the surface of the semiconductor substrate, and a filling window located on a side of the self-aligned silicide barrier layer away from the semiconductor substrate; Depositing a diffusion barrier layer on the side and bottom of the filling window; the diffusion barrier layer forms a field plate window; The same metal material is filled in the field plate window and the multiple openings to form a metal field plate and a metallization layer composed of the metal inter-insulating portion and the metal material filled in the multiple openings; wherein the dielectric layer is located on both sides of the metal field plate and the self-aligned silicide barrier layer; and the diffusion barrier layer is at least partially located between the metal field plate and the dielectric layer to prevent the metal material of the metal field plate from diffusing into the dielectric layer.

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