Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a first initial gate material layer on a substrate surface using a first low-pressure chemical vapor deposition process, wherein the material of the first initial gate material layer is polycrystalline silicon; forming a second initial gate material layer on the surface of the first initial gate material layer using a second low-pressure chemical vapor deposition process, wherein the material of the second initial gate material layer is polycrystalline silicon, and the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, wherein a gate material layer comprises the first initial gate material layer and the second initial gate material layer; implanting dopant ions into the gate material layer using an ion implantation process, wherein the first initial gate material layer has a first doping concentration and the second initial gate material layer has a second doping concentration; and annealing the gate material layer to reduce defects in the gate material layer and to make the first doping concentration greater than the second doping concentration, thereby helping to suppress the polycrystalline depletion effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] The continuous reduction in transistor manufacturing costs and the continuous improvement in transistor performance are two major trends in the development of integrated circuit manufacturing processes. Reducing the transistor's geometry is the most effective way to lower manufacturing costs and improve performance. However, this presents a significant challenge to proportionally shrinking the gate size.

[0003] The depletion of charge carriers at or near the interface between the gate oxide and the polysilicon gate (polysilicon depletion effect) has severely impacted the performance of Complementary Metal Oxide Semiconductor (CMOS) devices. The polysilicon depletion effect leads to a substantial increase in the gate dielectric thickness, thereby negatively affecting device performance. The impact of the polysilicon depletion effect becomes increasingly significant as the gate oxide thickness gradually decreases.

[0004] Therefore, the performance of polysilicon gates produced by existing technologies urgently needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; and a gate layer located on a portion of the surface of the substrate, the gate layer comprising a first gate material layer and a second gate material layer located on the surface of the first gate material layer, wherein the materials of the first gate material layer and the second gate material layer are both polycrystalline silicon, the grain size of the first gate material layer is smaller than the grain size of the second gate material layer, the first gate material layer has a first doping concentration, the second gate material layer has a second doping concentration, and the first doping concentration is greater than the second doping concentration.

[0007] Optionally, the gate layer further includes: a third gate material layer located on the surface of the substrate, wherein the first gate material layer is located on the surface of the third gate material layer, the material of the third gate material layer is polycrystalline silicon, and the grain size of the third gate material layer is smaller than the grain size of the first gate material layer, and the third gate material layer has a third doping concentration, which is greater than the first doping concentration.

[0008] Optionally, it may also include a gate oxide layer located between the substrate surface and the gate layer.

[0009] Accordingly, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first initial gate material layer on the surface of the substrate using a first low-pressure chemical vapor deposition process, wherein the material of the first initial gate material layer is polycrystalline silicon; forming a second initial gate material layer on the surface of the first initial gate material layer using a second low-pressure chemical vapor deposition process, wherein the material of the second initial gate material layer is polycrystalline silicon, and the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, wherein a gate material layer includes the first initial gate material layer and the second initial gate material layer; implanting dopant ions into the gate material layer using an ion implantation process, wherein the first initial gate material layer has a first doping concentration and the second initial gate material layer has a second doping concentration; annealing the gate material layer to reduce defects in the gate material layer and to make the first doping concentration greater than the second doping concentration; patterning the gate material layer to form a gate layer, wherein the gate layer includes the first gate material layer and the second gate material layer, wherein the first initial gate material layer is used to form the first gate material layer and the second initial gate material layer is used to form the second gate material layer.

[0010] Optionally, the first low-pressure chemical vapor deposition process has a first process temperature; the second low-pressure chemical vapor deposition process has a second process temperature, which is higher than the first process temperature.

[0011] Optionally, the first process temperature range is 610°C to 620°C; the second process temperature range is 615°C to 625°C.

[0012] Optionally, before forming the first initial gate material layer, the method further includes: using a third low-pressure chemical vapor deposition process to form a third initial gate material layer on the substrate surface, wherein the material of the third initial gate material layer is amorphous silicon, and the gate material layer further includes the third initial gate material layer, with the first initial gate material layer formed on the surface of the third initial gate material layer; the ion implantation process further gives the third initial gate material layer a third doping concentration; the annealing process further transforms the material of the third initial gate material layer from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer, and makes the third doping concentration greater than the first doping concentration; the gate layer further includes a third gate material layer, with the third initial gate material layer forming the third gate material layer.

[0013] Optionally, the third low-pressure chemical vapor deposition process has a third process temperature, which is lower than the first process temperature.

[0014] Optionally, the temperature range of the third process temperature is 500°C to 610°C.

[0015] Optionally, the process parameters of the ion implantation process include: the ions include N-type or P-type conductive ions.

[0016] Optionally, a gate oxide material layer is formed on the substrate surface before forming the first initial gate material layer; the gate oxide material layer under the gate layer is used as the gate oxide layer.

[0017] Accordingly, the technical solution of the present invention also provides another method for forming a semiconductor structure, comprising: providing a substrate; forming a first initial gate material layer on the surface of the substrate using a first low-pressure chemical vapor deposition process and a first in-situ doping process, wherein the material of the first initial gate material layer is polycrystalline silicon and the first initial gate material layer has a first doping concentration; forming a second initial gate material layer on the surface of the first initial gate material layer using a second low-pressure chemical vapor deposition process and a second in-situ doping process, wherein the material of the second initial gate material layer is polycrystalline silicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer and the second initial gate material layer has a second doping concentration, wherein a gate material layer includes the first initial gate material layer and the second initial gate material layer; annealing the gate material layer to reduce defects in the gate material layer and to make the first doping concentration greater than the second doping concentration; patterning the gate material layer to form a gate layer, wherein the gate layer includes the first gate material layer and the second gate material layer, wherein the first initial gate material layer is used to form the first gate material layer and the second initial gate material layer is used to form the second gate material layer.

[0018] Optionally, the first low-pressure chemical vapor deposition process has a first process temperature; the second low-pressure chemical vapor deposition process has a second process temperature, which is higher than the first process temperature.

[0019] Optionally, the first process temperature range is 610°C to 620°C; the second process temperature range is 615°C to 625°C.

[0020] Optionally, before forming the first initial gate material layer, the method further includes: forming a third initial gate material layer on the substrate surface using a third low-pressure chemical vapor deposition process and a third in-situ doping process; the material of the third initial gate material layer is amorphous silicon; the gate material layer further includes the third initial gate material layer; the third initial gate material layer has a third doping concentration; and the first initial gate material layer is formed on the surface of the third initial gate material layer. The annealing process further transforms the material of the third initial gate material layer from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer, and makes the third doping concentration greater than the first doping concentration. The gate layer further includes the third gate material layer, and the third gate material layer is formed from the third initial gate material layer.

[0021] Optionally, the third low-pressure chemical vapor deposition process has a third process temperature, which is lower than the first process temperature.

[0022] Optionally, the temperature range of the third process temperature is 500°C to 610°C.

[0023] Optionally, a gate oxide material layer is formed on the substrate surface before forming the first initial gate material layer; the gate oxide layer is formed by the gate oxide material layer under the gate layer.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] In the semiconductor structure formation method provided by the present invention, the formed gate material layer includes a first initial gate material layer and a second initial gate material layer. The grain size of the first initial gate material layer is smaller than that of the second initial gate material layer. The gate material layer is patterned to form a gate layer, so that in the final formed gate layer, the first doping concentration of the first gate material layer is greater than the second doping concentration of the second gate layer. Since the first gate material layer is closer to the gate oxide layer than the second gate layer, it is beneficial to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0026] Furthermore, a third initial gate material layer is formed on the surface of the substrate. The material of the third initial gate material layer is amorphous silicon. The annealing process also changes the material of the third initial gate material layer from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer. This results in the third doping concentration of the third gate material layer being greater than the first doping concentration of the first gate material layer. Since the third gate material layer is closer to the gate oxide layer than the first gate material layer, it is more beneficial to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0027] In the semiconductor structure provided by the present invention, the grain size of the first gate material layer is smaller than that of the second gate material layer, and the first doping concentration of the first gate material layer is greater than that of the second doping concentration of the second gate material layer. Since the first gate material layer is closer to the gate oxide layer than the second gate material layer, it is beneficial to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0028] Furthermore, the grain size of the third gate material layer is smaller than that of the first gate material layer, and the third doping concentration of the third gate material layer is greater than that of the first doping concentration of the first gate material layer. Since the third gate material layer is closer to the gate oxide layer than the first gate material layer, it is more conducive to suppressing the polycrystalline depletion effect without changing the total content of doped ions in the gate layer. Attached Figure Description

[0029] Figure 1 This is a flowchart of the steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 2 to 8 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0031] Figure 9 This is a graph showing the relationship between process temperature and grain size in low-pressure chemical vapor deposition (LPCVD).

[0032] Figure 10 This is a flowchart of the steps of a method for forming a semiconductor structure according to another embodiment of the present invention;

[0033] Figures 11 to 16 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0034] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0035] As described in the background section, the performance of polysilicon gates produced by existing technologies urgently needs to be improved.

[0036] Specifically, in MOS devices using polysilicon gates, the voltage applied to the gate attracts minority carriers to the interface between the dielectric and the channel, forming an inversion carrier distribution. This leads to carrier accumulation near the interface to maintain charge neutrality, inevitably depleting the charge of the nearby semiconductor. When the semiconductor's charge is completely depleted, it essentially becomes an insulator, effectively increasing the effective thickness of the gate dielectric. Although the depletion layer thickness is only a few angstroms of SiO2, its impact becomes significant when the gate dielectric thickness decreases to tens of angstroms, making the polysilicon depletion effect undeniable.

[0037] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure in which the formed gate material layer includes a first initial gate material layer and a second initial gate material layer. The grain size of the first initial gate material layer is smaller than that of the second initial gate material layer. The gate material layer is patterned to form a gate layer, thereby ensuring that the first doping concentration of the first gate material layer in the final gate layer is greater than the second doping concentration of the second gate layer. Since the first gate material layer is closer to the gate oxide layer than the second gate layer, it is beneficial to suppress the polycrystalline depletion effect without changing the total dopant ion content within the gate layer.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figure 1 This is a flowchart of the steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 1 The method for forming the semiconductor structure includes the following steps:

[0041] Step S101: Provide a substrate;

[0042] Step S103: A first initial gate material layer is formed on the surface of the substrate using a first low-pressure chemical vapor deposition process. The material of the first initial gate material layer is polycrystalline silicon.

[0043] Step S104: Using a second low-pressure chemical vapor deposition process, a second initial gate material layer is formed on the surface of the first initial gate material layer. The material of the second initial gate material layer is polycrystalline silicon, and the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer. The gate material layer includes the first initial gate material layer and the second initial gate material layer.

[0044] Step S105: Doped ions are implanted into the gate material layer using an ion implantation process. The first initial gate material layer has a first doping concentration, and the second initial gate material layer has a second doping concentration.

[0045] Step S106: Anneal the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration.

[0046] Step S107: Pattern the gate material layer to form a gate layer. The gate layer includes a first gate material layer and a second gate material layer. The first gate material layer is formed with the first initial gate material layer, and the second gate material layer is formed with the second initial gate material layer.

[0047] In this embodiment, before performing step S103, that is, before forming the first initial gate material layer, the following steps are also included:

[0048] Step S102: A third initial gate material layer is formed on the substrate surface using a third low-pressure chemical vapor deposition process. The material of the third initial gate material layer is amorphous silicon. The gate material layer also includes the third initial gate material layer. The first initial gate material layer is formed on the surface of the third initial gate material layer.

[0049] In another embodiment, step S102 may be omitted.

[0050] The following will be described in detail with reference to the accompanying drawings.

[0051] Figures 2 to 8 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0052] Please refer to step S101 for execution. Figure 2 Substrate 200 is provided.

[0053] In this embodiment, a gate oxide material layer 201 is formed on the surface of the substrate 200 before the first initial gate material layer is formed. The gate oxide material layer 201 is used to form the gate oxide layer.

[0054] In this embodiment, the substrate 200 is made of silicon.

[0055] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0056] In this embodiment, before performing step S103, that is, before forming the first initial gate material layer, step S102 is also performed. For details, please refer to [link / reference needed]. Figure 3 .

[0057] Please refer to Figure 3 A third initial gate material layer 202 is formed on the surface of the substrate 200 using a third low-pressure chemical vapor deposition process. The material of the third initial gate material layer 202 is amorphous silicon.

[0058] Specifically, the third initial gate material layer 202 is formed on the surface of the gate oxide material layer 201.

[0059] In this embodiment, the third low-pressure chemical vapor deposition process has a third process temperature.

[0060] In this embodiment, the temperature range of the third process temperature is 500°C to 610°C.

[0061] It should be noted that the first, second, and third low-pressure chemical vapor deposition processes described in this article are all LPCVD (Low Pressure Chemical Vapor Deposition) processes.

[0062] Here, we will combine Figure 9 The process temperature and the final polycrystalline silicon grain size of the low-pressure chemical vapor deposition process are explained.

[0063] Figure 9 This is a graph showing the relationship between process temperature and grain size in low-pressure chemical vapor deposition.

[0064] Depend on Figure 9 It is known that within the third process temperature range, i.e., 500℃ to 610℃, the material of the third initial gate material layer 202 is amorphous silicon. Subsequently, through annealing, the material of the third initial gate material layer 202 will change from amorphous silicon to polycrystalline silicon. Furthermore, the higher the third process temperature, the smaller the grain size of the final polycrystalline silicon. The grain size of the final third gate material layer can be adjusted by controlling the third process temperature.

[0065] Please refer to step S103 for execution. Figure 4 A first initial gate material layer 203 is formed on the surface of the substrate 200 using a first low-pressure chemical vapor deposition process. The material of the first initial gate material layer 203 is polycrystalline silicon.

[0066] More specifically, the first initial gate material layer 203 is formed on the surface of the third initial gate material layer 202.

[0067] The first initial gate material layer 203 is used to form the first gate material layer.

[0068] In this embodiment, the first low-pressure chemical vapor deposition process has a first process temperature, and the third process temperature is lower than the first process temperature.

[0069] In this embodiment, the first process temperature range is 610°C to 620°C.

[0070] Continue to refer to Figure 9 It is known that within the first process temperature range, i.e. 610°C to 620°C, the material of the first initial gate material layer 202 formed is polycrystalline silicon. The grain size of the final first gate material layer can be adjusted by controlling the first process temperature.

[0071] Please refer to step S104 for execution. Figure 4 A second low-pressure chemical vapor deposition process is used to form a second initial gate material layer 204 on the surface of the first initial gate material layer 203. The material of the second initial gate material layer 204 is polycrystalline silicon, and the grain size of the second initial gate material layer 204 is larger than the grain size of the first initial gate material layer 203. The gate material layer includes the first initial gate material layer 203 and the second initial gate material layer 204.

[0072] The second initial gate material layer 204 is used to form the second gate material layer.

[0073] In this embodiment, the gate material layer further includes the third initial gate material layer 202. In another embodiment, the gate material layer includes the first initial gate material layer and the second initial gate material layer, but does not include the third initial gate material layer.

[0074] In this embodiment, the second low-pressure chemical vapor deposition process has a second process temperature, which is higher than the first process temperature.

[0075] In this embodiment, the temperature range of the second process temperature is 615°C to 625°C.

[0076] Continue to refer to Figure 9 It can be seen that within the second process temperature range, i.e., 615℃ to 625℃, the material of the second initial gate material layer 204 formed is polycrystalline silicon, and the higher the second process temperature, the larger the grain size of the final polycrystalline silicon. The grain size of the final formed second gate material layer can be adjusted by controlling the second process temperature.

[0077] Here, by controlling the second process temperature to be greater than the first process temperature, the grain size of the second initial gate material layer 204 can be made greater than the grain size of the first initial gate material layer 203, thereby making the grain size of the second gate material layer greater than the grain size of the first gate material layer.

[0078] Please refer to step S105 for execution. Figure 6 Doped ions are implanted into the gate material layer using an ion implantation process. The first initial gate material layer 203 has a first doping concentration, and the second initial gate material layer 204 has a second doping concentration.

[0079] In this embodiment, the ion implantation process also gives the third initial gate material layer 202 a third doping concentration.

[0080] The process parameters for the ion implantation process include: the dopant ions include N-type or P-type conductive ions. In this embodiment, the dopant ion is a P-type conductive ion, specifically, the dopant ion is boron.

[0081] Please refer to step S106 for execution. Figure 7 Annealing is performed on the gate material layer to reduce defects in the gate material layer and to make the first doping concentration greater than the second doping concentration.

[0082] It should be noted that, since the grain size of the first initial gate material layer 203 is smaller than that of the second initial gate material layer 204, doped ions tend to accumulate at the grain boundaries. Therefore, the purpose of making the first doping concentration greater than the second doping concentration can be achieved.

[0083] In this embodiment, the annealing process further transforms the material of the third initial gate material layer 202 from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer 202 smaller than the grain size of the first initial gate material layer 203, and makes the third doping concentration greater than the first doping concentration.

[0084] It should be noted that the grain size of the obtained third initial gate material layer 202 is smaller than that of the first initial gate material layer 203. Since doped ions tend to accumulate at the grain boundaries, the purpose of making the third doping concentration greater than the first doping concentration can be achieved.

[0085] To execute S107, please refer to [link / reference]. Figure 8 The gate material layer is patterned to form a gate layer, which includes a first gate material layer 206 and a second gate material layer 207. The first gate material layer 206 is formed with the first initial gate material layer 203, and the second gate material layer 207 is formed with the second initial gate material layer 204.

[0086] Thus, the first gate material layer 206 is formed from the first initial gate material layer 203, and the first gate material layer 206 also has the first doping concentration. The second gate material layer 207 is formed from the second initial gate material layer 203, and the second gate material layer 207 also has the second doping concentration. Since the first doping concentration is greater than the second doping concentration, the first gate material layer 206 is closer to the gate oxide layer than the second gate material layer 207. This helps to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0087] In this embodiment, the gate layer further includes a third gate material layer 205, which is formed by the third initial gate material layer 202.

[0088] Here, the third gate material layer 205 is formed from the third initial gate material layer 202. The third gate material layer 205 also has the third doping concentration. Since the third doping concentration is greater than the first doping concentration, the third gate material layer 205 is closer to the gate oxide layer 208 than the first gate material layer 206. This further helps to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0089] In this embodiment, the method of patterning the gate material layer to form the gate layer includes: forming a patterned photoresist layer on a portion of the surface of the gate material layer; using the photoresist layer as a mask, etching the gate material layer until the surface of the substrate 200 is exposed to form the gate layer.

[0090] In this embodiment, a gate oxide layer 208 is also formed using the gate oxide material layer 201 under the gate layer.

[0091] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 8 The system includes: a substrate 200; and a gate layer located on a portion of the surface of the substrate 200, the gate layer including a first gate material layer 206 and a second gate material layer 207 located on the surface of the first gate material layer 206, both the first gate material layer 206 and the second gate material layer 207 being polycrystalline silicon, the grain size of the first gate material layer 206 being smaller than the grain size of the second gate material layer 207, the first gate material layer 206 having a first doping concentration, and the second gate material layer 207 having a second doping concentration, the first doping concentration being greater than the second doping concentration.

[0092] Here, the grain size of the first gate material layer 206 is smaller than the grain size of the second gate material layer 207, and the first doping concentration of the first gate material layer 206 is greater than the second doping concentration of the second gate material layer 207. Since the first gate material layer 206 is closer to the gate oxide layer than the second gate material layer 207, it is beneficial to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0093] In this embodiment, the gate layer further includes: a third gate material layer 205 located on the surface of the substrate 200, the first gate material layer 206 located on the surface of the third gate material layer 205, the material of the third gate material layer 205 being polycrystalline silicon, and the grain size of the third gate material layer 205 being smaller than the grain size of the first gate material layer 206, the third gate material layer 205 having a third doping concentration, the third doping concentration being greater than the first doping concentration.

[0094] Here, the grain size of the third gate material layer 205 is smaller than that of the first gate material layer 206, and the third doping concentration of the third gate material layer 205 is greater than that of the first doping concentration of the first gate material layer 206. Since the third gate material layer 205 is closer to the gate oxide layer 208 than the first gate material layer 206, it is more conducive to suppressing the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0095] In this embodiment, the semiconductor structure further includes a gate oxide layer 208 located between the surface of the substrate 200 and the gate layer.

[0096] Specifically, the gate oxide layer 208 is located between the surface of the substrate 200 and the third gate material layer 205.

[0097] Figure 10 This is a flowchart of the steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0098] The main difference between this embodiment and the previous embodiment is that the doping method of the doped ions in the gate material layer is different.

[0099] Figure 10 This is a flowchart of the steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0100] Please refer to Figure 10 The method for forming the semiconductor structure includes the following steps:

[0101] Step S301, provide a substrate;

[0102] Step S303: A first initial gate material layer is formed on the substrate surface using a first low-pressure chemical vapor deposition process and a first in-situ doping process. The material of the first initial gate material layer is polycrystalline silicon, and the first initial gate material layer has a first doping concentration.

[0103] Step S304: Using a second low-pressure chemical vapor deposition process and a second in-situ doping process, a second initial gate material layer is formed on the surface of the first initial gate material layer. The material of the second initial gate material layer is polycrystalline silicon. The grain size of the second initial gate material layer is larger than that of the first initial gate material layer, and the second initial gate material layer has a second doping concentration. The gate material layer includes the first initial gate material layer and the second initial gate material layer.

[0104] Step S305: Anneal the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration;

[0105] Step S306: Pattern the gate material layer to form a gate layer. The gate layer includes a first gate material layer and a second gate material layer. The first gate material layer is formed with the first initial gate material layer, and the second gate material layer is formed with the second initial gate material layer.

[0106] In this embodiment, before performing step S303, that is, before forming the first initial gate material layer, the following steps are also included:

[0107] Step S302: A third initial gate material layer is formed on the substrate surface using a third low-pressure chemical vapor deposition process and a third in-situ doping process. The material of the third initial gate material layer is amorphous silicon. The gate material layer also includes the third initial gate material layer. The third initial gate material layer has a third doping concentration. The first initial gate material layer is formed on the surface of the third initial gate material layer.

[0108] In another embodiment, step S302 may be omitted.

[0109] The following will be described in detail with reference to the accompanying drawings.

[0110] Figures 11 to 16 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to another embodiment of the present invention.

[0111] Please refer to step S301 for execution. Figure 11 Substrate 400 is provided.

[0112] In this embodiment, a gate oxide material layer 401 is formed on the surface of the substrate 400 before the first initial gate material layer is formed. The gate oxide material layer 401 is used to form the gate oxide layer.

[0113] In this embodiment, before executing step S303, that is, before forming the first initial gate material layer, step S302 is also executed. For details, please refer to [link / reference needed]. Figure 12 .

[0114] Please refer to Figure 12 A third initial gate material layer 402 is formed on the surface of the substrate 400 using a third low-pressure chemical vapor deposition process and a third in-situ doping process. The material of the third initial gate material layer 402 is amorphous silicon, and the third initial gate material layer 402 has a third doping concentration.

[0115] Specifically, the third initial gate material layer 402 is formed on the surface of the gate oxide material layer 401.

[0116] In this embodiment, the third low-pressure chemical vapor deposition process has a third process temperature.

[0117] In this embodiment, the temperature range of the third process temperature is 500°C to 610°C.

[0118] Please refer to step S303 for execution. Figure 13 A first initial gate material layer 403 is formed on the surface of the substrate 400 using a first low-pressure chemical vapor deposition process and a first in-situ doping process. The material of the first initial gate material layer 403 is polycrystalline silicon, and the first initial gate material layer 403 has a first doping concentration.

[0119] Specifically, the first initial gate material layer 403 is formed on the surface of the third initial gate material layer 402.

[0120] In this embodiment, the first low-pressure chemical vapor deposition process has a first process temperature, and the third process temperature is lower than the first process temperature.

[0121] In this embodiment, the first process temperature range is 610°C to 620°C.

[0122] Please refer to step S104 for execution. Figure 14 A second initial gate material layer 404 is formed on the surface of the first initial gate material layer 403 using a second low-pressure chemical vapor deposition process and a second in-situ doping process. The material of the second initial gate material layer 404 is polycrystalline silicon. The grain size of the second initial gate material layer 404 is larger than the grain size of the first initial gate material layer 403, and the second initial gate material layer 404 has a second doping concentration. The gate material layer includes the first initial gate material layer 403 and the second initial gate material layer 404.

[0123] In this embodiment, the second low-pressure chemical vapor deposition process has a second process temperature, which is higher than the first process temperature.

[0124] In this embodiment, the temperature range of the second process temperature is 615°C to 625°C.

[0125] In this embodiment, the gate material layer further includes the third initial gate material layer 402.

[0126] Please refer to step S305 for execution. Figure 15 Annealing is performed on the gate material layer to reduce defects in the gate material layer and to make the first doping concentration greater than the second doping concentration.

[0127] The annealing process also transforms the material of the third initial gate material layer 402 from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer 402 smaller than the grain size of the first initial gate material layer 403, and makes the third doping concentration greater than the first doping concentration.

[0128] Please refer to step S306 for execution. Figure 16 The gate material layer is patterned to form a gate layer, which includes a first gate material layer 406 and a second gate material layer 407. The first gate material layer 406 is formed with the first initial gate material layer 403, and the second gate material layer 407 is formed with the second initial gate material layer 404.

[0129] Thus, the first gate material layer 406 is formed from the first initial gate material layer 403, and the first gate material layer 406 also has the first doping concentration. The second gate material layer 407 is formed from the second initial gate material layer 403, and the second gate material layer 407 also has the second doping concentration. Since the first doping concentration is greater than the second doping concentration, the first gate material layer 406 is closer to the gate oxide layer than the second gate material layer 407. This helps to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0130] In this embodiment, the gate layer further includes a third gate material layer 405, which is formed by the third initial gate material layer 402.

[0131] Here, the third gate material layer 405 is formed from the third initial gate material layer 402. The third gate material layer 405 also has the third doping concentration. Since the third doping concentration is greater than the first doping concentration, the third gate material layer 405 is closer to the gate oxide layer 408 than the first gate material layer 406. This further helps to suppress the polycrystalline depletion effect without changing the total content of doped ions in the gate layer.

[0132] In this embodiment, a gate oxide layer 408 is also formed by the gate oxide material layer 401 under the gate layer.

[0133] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A gate layer located on a portion of the substrate surface, the gate layer comprising a first gate material layer and a second gate material layer located on the surface of the first gate material layer, both the first gate material layer and the second gate material layer being made of polycrystalline silicon, the grain size of the first gate material layer being smaller than the grain size of the second gate material layer, the first gate material layer having a first doping concentration, the second gate material layer having a second doping concentration, and the first doping concentration being greater than the second doping concentration; The gate layer further includes a third gate material layer located on the surface of the substrate, wherein the first gate material layer is located on the surface of the third gate material layer, the material of the third gate material layer is polycrystalline silicon, and the grain size of the third gate material layer is smaller than the grain size of the first gate material layer, and the third gate material layer has a third doping concentration, which is greater than the first doping concentration.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The gate oxide layer located between the substrate surface and the gate layer.

3. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A third initial gate material layer is formed on the surface of the substrate using a third low-pressure chemical vapor deposition process. The material of the third initial gate material layer is amorphous silicon. A first initial gate material layer is formed on the surface of the third initial gate material layer using a first low-pressure chemical vapor deposition process. The material of the first initial gate material layer is polycrystalline silicon. A second low-pressure chemical vapor deposition process is used to form a second initial gate material layer on the surface of the first initial gate material layer. The material of the second initial gate material layer is polycrystalline silicon. The grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer. The gate material layer includes the first initial gate material layer, the second initial gate material layer and the third initial gate material layer. Doped ions are implanted into the gate material layer using an ion implantation process. The first initial gate material layer has a first doping concentration, the second initial gate material layer has a second doping concentration, and the ion implantation process also gives the third initial gate material layer a third doping concentration. The gate material layer is annealed to reduce defects in the gate material layer and to make the first doping concentration greater than the second doping concentration. The annealing process also changes the material of the third initial gate material layer from amorphous silicon to polycrystalline silicon and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer, and makes the third doping concentration greater than the first doping concentration. The gate material layer is patterned to form a gate layer, which includes a first gate material layer, a second gate material layer and a third gate material layer. The first gate material layer is formed with the first initial gate material layer, the second gate material layer is formed with the second initial gate material layer, and the third gate material layer is formed with the third initial gate material layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first low-pressure chemical vapor deposition process has a first process temperature; The second low-pressure chemical vapor deposition process has a second process temperature, which is higher than the first process temperature.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The first process temperature range is 610°C to 620°C; the second process temperature range is 615°C to 625°C.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The third low-pressure chemical vapor deposition process has a third process temperature, which is lower than the first process temperature.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The temperature range of the third process temperature is 500°C to 610°C.

8. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process parameters of the ion implantation process include: the ions include N-type or P-type conductive ions.

9. The method for forming a semiconductor structure as described in claim 3, characterized in that, Before forming the first initial gate material layer, a gate oxide material layer is also formed on the surface of the substrate; the gate oxide material layer under the gate layer is used as the gate oxide layer.

10. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A third initial gate material layer is formed on the substrate surface using a third low-pressure chemical vapor deposition process and a third in-situ doping process. The material of the third initial gate material layer is amorphous silicon. A first initial gate material layer is formed on the surface of the third initial gate material layer using a first low-pressure chemical vapor deposition process and a first in-situ doping process. The material of the first initial gate material layer is polycrystalline silicon, and the first initial gate material layer has a first doping concentration. A second initial gate material layer is formed on the surface of the first initial gate material layer using a second low-pressure chemical vapor deposition process and a second in-situ doping process. The material of the second initial gate material layer is polycrystalline silicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, and the second initial gate material layer has a second doping concentration. The gate material layer includes the first initial gate material layer, the second initial gate material layer, and the third initial gate material layer, and the third initial gate material layer has a third doping concentration. The gate material layer is annealed to reduce defects in the gate material layer and to make the first doping concentration greater than the second doping concentration. The annealing process also changes the material of the third initial gate material layer from amorphous silicon to polycrystalline silicon and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer, and makes the third doping concentration greater than the first doping concentration. The gate material layer is patterned to form a gate layer, which includes a first gate material layer, a second gate material layer and a third gate material layer. The first gate material layer is formed with the first initial gate material layer, the second gate material layer is formed with the second initial gate material layer, and the third gate material layer is formed with the third initial gate material layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first low-pressure chemical vapor deposition process has a first process temperature; The second low-pressure chemical vapor deposition process has a second process temperature, which is higher than the first process temperature.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first process temperature range is 610°C to 620°C; the second process temperature range is 615°C to 625°C.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The third low-pressure chemical vapor deposition process has a third process temperature, which is lower than the first process temperature.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The temperature range of the third process temperature is 500°C to 610°C.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before forming the first initial gate material layer, a gate oxide material layer is also formed on the surface of the substrate; the gate oxide layer is formed by the gate oxide material layer under the gate layer.

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