A low-resistance superjunction structure eliminating the gate-source lateral alternating structure and a manufacturing method thereof

Abstract

The present invention discloses a low-resistance superjunction structure that eliminates the lateral alternating gate-source structure and a manufacturing method thereof, comprising a plurality of MOS cells connected in parallel, wherein a single MOS cell comprises a drain, an upper metal source, a gate, a semiconductor epitaxial layer, a substrate layer, a P-well layer, and an N-well layer; a groove is formed by etching between adjacent MOS cells, an oxide layer is deposited at the bottom of the groove, and a side metal source is arranged on the surface of the oxide layer; the top of the side metal source contacts a dielectric layer; the dielectric layer is a laterally continuous dielectric layer, the gate is arranged inside the dielectric layer, adjacent gates are isolated by the dielectric layer, and a gate-source alternating structure is not formed, and an upper metal source is arranged on the upper surface of the dielectric layer. The present invention increases the injection depth of the heavily doped P-well layer through the groove, and buries the source ohmic contact in the vertical direction of the epitaxial layer, thereby eliminating the lateral alternating gate-source structure in the device and greatly reducing the cell size.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a low-resistance super junction structure eliminating a gate-source lateral alternating structure and a manufacturing method thereof. Background Art

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles, photovoltaic inverters, charging piles and other fields. With the gradual development of SiC MOSFET devices, the voltage requirements of the devices at the application end are gradually increasing. For SiC MOSFET, higher voltage resistance means thicker epitaxial layer, and the increase of epitaxial layer means a sharp increase in the on-resistance of the device. For devices with the same on-resistance, the epitaxial thickness and device area of ​​high-voltage devices will be much higher than those of low-voltage devices. The superjunction structure solves the above problems due to its special structure.

[0003] However, the manufacture of super junction structures usually requires very deep P+ implantation to improve voltage resistance and reduce on-resistance. The implantation depth of P+ ions is limited by the implantation capability of the implantation machine. Currently, implantation machines in the industry can usually only achieve an implantation depth of 2~3μm. If you want to manufacture a heavily doped P well layer with a thickness of more than 5μm, it is actually impossible. Even with more advanced implantation machines, silicon carbide substrates cannot withstand such a high concentration of impurity ions, resulting in material damage. Limited by process manufacturing, super junction structures are greatly limited in actual device production and cannot be widely used. Summary of the invention

[0004] The purpose of the present invention is to provide a low-resistance super junction structure that eliminates the gate-source lateral alternating structure and a method for manufacturing the same, which not only solves the problem in the prior art that P+ injection is limited by the injection capacity of the implanter, improves the feasibility of the process, but also further reduces the cell size, reduces the specific on-resistance, and improves the device performance and power density.

[0005] The technical solution adopted by the present invention is:

[0006] The present invention also provides a low-resistance superjunction structure that eliminates the gate-source lateral alternating structure, comprising a plurality of MOS cells connected in parallel, characterized in that a single MOS cell comprises a drain, a substrate layer, a diffusion layer, a dielectric layer, a gate, and an upper metal source electrode in order from bottom to top, wherein the diffusion layer is located on the surface of the substrate layer and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer comprises a lightly doped P-well layer and a heavily doped P-well layer, wherein the heavily doped P-well layer extends to the bottom of the diffusion layer and contacts the substrate layer;

[0007] A groove is etched in the middle of the heavily doped P-well layer between adjacent MOS cells, the bottom of the groove may or may not extend to the substrate layer, an oxide layer is deposited at the bottom of the groove, a side metal source is provided on the surface of the oxide layer and the top of the groove, the top of the side metal source is in contact with the dielectric layer, and the side metal source is in lead-out contact with the upper metal source near the main junction of the device; the side surface of the side metal source is in ohmic contact with the N-well layer, the lightly doped P-well layer and the heavily doped P-well layer;

[0008] The dielectric layer is a laterally continuous dielectric layer, the gate is arranged inside the dielectric layer, adjacent gates are isolated by the dielectric layer, and no gate-source alternating structure is formed, and an upper metal source is arranged on the upper surface of the dielectric layer.

[0009] Furthermore, the substrate layer is arranged on the drain surface, the heavily doped P-well layer and the diffusion layer are arranged on the substrate layer surface, and the heavily doped P-well layer is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P-well layers on both sides of the single MOS cell, the lightly doped P-well layer is arranged on the surfaces of the diffusion layer and the heavily doped P-well layer, and is respectively connected to the diffusion layer and the heavily doped P-well layer, the N-well layer is located on the surface of the lightly doped P-well layer, and is connected to the lightly doped P-well layer, and the gate is isolated and connected to the upper surface of the N-well layer, the surface of the lightly doped P-well layer and the diffusion layer through a dielectric layer.

[0010] Furthermore, the N-well layer includes a lightly doped N-well layer and a heavily doped N-well layer, the heavily doped N-well layer is located on the upper layer of the lightly doped N-well layer; the lightly doped N-well layer is located on the surface of the lightly doped P-well layer, the side of the side metal source is in ohmic contact with the lightly doped N-well layer, the heavily doped N-well layer, the lightly doped P-well layer and the heavily doped P-well layer, and the gate is connected to the upper surface of the heavily doped N-well layer, the lightly doped P-well layer and the surface of the diffusion layer through isolation of a dielectric layer.

[0011] In a single MOS cell, the lightly doped P-well layer is also arranged on both sides of the single MOS cell, located on the surface of the diffusion layer and the heavily doped P-well layer, and the N-well layer is arranged on both sides of the single MOS cell, located on the surface of the lightly doped P-well layer. The N-well layer and the diffusion layer are isolated by the lightly doped P-well layer.

[0012] The gate is connected to the upper surface of the N-well layer located on both sides of the cell, the surface of the lightly doped P-well layer inside the N-well layer, and the surface of the middle diffusion layer through dielectric layer isolation.

[0013] Furthermore, the height of the oxide layer filled in the trench is lower than the bottom cross-sectional height of the lightly doped P-well layer, so that the side metal source can contact the heavily doped P-well layer.

[0014] More preferably, the groove is perpendicular to the substrate layer.

[0015] When the low-resistance super junction structure is in a blocking state, the oxide layer bears pressure together with the device. This will not cause the device's withstand voltage characteristics to decrease. During the device manufacturing process, the provision of the oxide layer can greatly reduce the requirements for ion implanters during the super junction structure manufacturing process. The present invention designs the source ohmic contact in the vertical direction within the epitaxial layer, which can greatly reduce the cell size occupied by the source contact.

[0016] The present invention also provides a method for manufacturing the low-resistance super junction structure, the method comprising the following steps:

[0017] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0018] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0019] S3. Between adjacent MOS cells, a groove is formed by etching the reserved heavily doped P-well layer. The depth and width of the groove can be set according to the specific device design.

[0020] S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer that meets the specifications;

[0021] S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer, and then depositing metal into the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench;

[0022] S6. Complete the remaining parts of the device according to the normal process.

[0023] In the step S6, the gate electrode, the dielectric layer and the upper metal source electrode are generally manufactured according to normal processes.

[0024] In the step S5, the oxide layer may be deposited using an oxide layer deposition device.

[0025] Furthermore, in step S3, by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench, it is determined whether the substrate epitaxial layer trench etching process is qualified, and:

[0026]

[0027] In the formula, C Indicates the yield rate of the trenches etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d 0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched groove, g Indicates the existence rate of cracks in the inner surface of the groove;

[0028] whenC When ≥80%, it means that the process of trench etching the surface of the substrate epitaxial layer meets the requirements of good products.

[0029] Furthermore, in step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating.

[0030]

[0031] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where h The larger the value, the worse the uprightness of the groove; m It indicates the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u Indicates the maximum inward inclination angle of the groove side wall after heating.

[0032] The beneficial effects of the present invention are:

[0033] The present invention solves for the first time the problem of the difficulty of the super junction device manufacturing process. By increasing the groove etching, the injection port of the implanter can penetrate deep into the groove, so that when the maximum injection depth of the implanter remains unchanged, the injection depth of the heavily doped P-well layer is increased through the groove, making it possible to manufacture a heavily doped P-well layer with an injection depth greater than the maximum injection depth of the implanter. This greatly reduces the requirements of the super junction device for the implanter, significantly reduces the difficulty of manufacturing super junction devices, lowers the threshold for manufacturing super junction devices, and lays a solid foundation for the industrial application of super junction devices.

[0034] Furthermore, the present invention utilizes the trench to perform impurity injection and then fills the trench with oxide, which can reduce the difficulty of deep trench filling in the industrial manufacturing process without losing the withstand voltage characteristics of the device.

[0035] The present invention designs the source ohmic contact to be buried in the vertical direction within the epitaxial layer, and the adjacent N-well layer, lightly doped P-well layer and heavily doped P-well layer can directly contact the side metal source, so that adjacent MOS cells do not need to be isolated by a heavily doped P-well layer, thereby greatly reducing the lateral cell size occupied by the source contact.

[0036] Furthermore, since the lateral metal source is buried in the U groove, the present invention eliminates the isolation layer between the gate and source in the horizontal direction, and the device cell size can be reduced by more than 50% compared with the prior art. The lateral alternating gate-source structure in the device is eliminated, and any concerns about the process, materials and electrical characteristics caused by the gate-source lateral isolation dielectric layer are completely eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1It is a cross-sectional schematic diagram of the low-resistance super junction structure eliminating the gate-source lateral alternating structure of the present invention in Example 1.

[0038] In the figure: 1, drain; 2, upper metal source; 3, dielectric layer; 4, gate; 5, side metal source; 6, oxide layer; 61, trench; 7, lightly doped P well layer; 8, heavily doped P well layer; 9, diffusion layer; 10, lightly doped N well layer; 11, heavily doped N well layer; 12, substrate layer. DETAILED DESCRIPTION

[0039] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments, but the protection scope of the present invention is not limited thereto. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0040] Example 1

[0041] This embodiment provides a low-resistance super junction structure that eliminates the gate-source lateral alternating structure. The structural schematic diagram is shown in FIG. Figure 1 As shown, it includes several MOS cells connected in parallel, characterized in that a single MOS cell includes a drain 1, a substrate layer 12, a diffusion layer 9, a dielectric layer 3, a gate 4, and an upper metal source 2 from bottom to top, the diffusion layer 9 is located on the surface of the substrate layer 12, and is formed with a P well layer and an N well layer by ion implantation; the P well layer includes a lightly doped P well layer 7 and a heavily doped P well layer 8, wherein the heavily doped P well layer 8 extends to the bottom of the diffusion layer 9 and contacts with the substrate layer 12.

[0042] Between adjacent MOS cells, in the middle of the heavily doped P-well layer 8, a groove 61 is etched and formed, the bottom of the groove 61 may or may not extend to the substrate layer 12, and in this embodiment, it is chosen not to extend to the substrate layer, an oxide layer 6 is deposited at the bottom of the groove 61, and a side metal source 5 is provided on the surface of the oxide layer 6 and the top of the groove 61, the top of the side metal source 5 is in contact with the dielectric layer 3, and the side metal source 5 is in lead-out contact with the upper metal source 2 near the main junction of the device; the side surface of the side metal source 5 is in ohmic contact with the N-well layer, the lightly doped P-well layer 7 and the heavily doped P-well layer 8;

[0043] The dielectric layer 3 is a laterally continuous dielectric layer. The gate 4 is disposed inside the dielectric layer 3 . Adjacent gates 4 are isolated by the dielectric layer 3 , and no gate-source alternating structure is formed. An upper metal source 2 is disposed on the upper surface of the dielectric layer 3 .

[0044] Further, the substrate layer 12 is arranged on the surface of the drain 1, the heavily doped P well layer 8 and the diffusion layer 9 are arranged on the surface of the substrate layer 12, and the heavily doped P well layer 8 is respectively arranged on both sides of a single MOS cell, the diffusion layer 9 is located in the middle of the heavily doped P well layer 8 located on both sides of the single MOS cell, the lightly doped P well layer 7 is arranged on the surface of the diffusion layer 9 and the heavily doped P well layer 8, and is respectively connected to the diffusion layer 9 and the heavily doped P well layer 8, the N well layer is located on the surface of the lightly doped P well layer 7, Figure 1 In the embodiment, the N well layer includes a lightly doped N well layer 10 and a heavily doped N well layer 11, wherein the heavily doped N well layer 11 is located on the upper layer of the lightly doped N well layer 10; the lightly doped N well layer 10 is located on the surface of the lightly doped P well layer 7; the side surface of the side metal source 5 is in ohmic contact with the lightly doped N well layer 10 and the heavily doped N well layer 11, the lightly doped P well layer 7 and the heavily doped P well layer 8, and the gate 4 is isolated and connected with the upper surface of the heavily doped N well layer 11, the lightly doped P well layer 7 and the surface of the diffusion layer 9 through the dielectric layer 3;

[0045] In a single MOS cell, the lightly doped P-well layer 7 is also arranged on both sides of the single MOS cell, located on the surface of the diffusion layer 9 and the heavily doped P-well layer 8. The lightly doped N-well layer 10 and the heavily doped N-well layer 11 are both arranged on both sides of the single MOS cell. The lightly doped N-well layer 10 and the heavily doped N-well layer 11 are isolated from the diffusion layer 9 by the lightly doped P-well layer 7.

[0046] The gate 4 is isolated and connected to the upper surface of the heavily doped N-well layer 11 on both sides of the cell, the surface of the lightly doped P-well layer 7 inside the heavily doped N-well layer 11 , and the surface of the middle diffusion layer 9 through the dielectric layer 3 .

[0047] Furthermore, the height of the oxide layer 6 filled in the trench 61 is lower than the bottom cross-sectional height of the lightly-doped P-well layer 7 , so that the side metal source 5 can contact the heavily-doped P-well layer 8 .

[0048] More preferably, the groove 61 is perpendicular to the substrate layer 12 .

[0049] Because a side metal source is provided in the trench, no lateral isolation is required between the gate and the source.

[0050] When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device.

[0051] The low-resistance super junction structure eliminating the gate-source lateral alternating structure is prepared by the following method:

[0052] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0053] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0054] S3. Between adjacent MOS cells, a groove is formed by etching in the middle of the reserved heavily doped P-well layer. The depth and width of the groove can be set according to the specific device design.

[0055] In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating, and:

[0056]

[0057] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where h The larger the value, the worse the uprightness of the groove; m It indicates the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u Indicates the maximum inward inclination angle of the groove side wall after heating.

[0058] The ratio of the cross-sectional width at the bottom of the trench to the cross-sectional width at the top of the semiconductor substrate layer is m= 1.5, the maximum inclination angle of the groove side wall after heating is u =4.2 (degrees), then:

[0059]

[0060] From the above calculation, we can know that the vertical coefficient of the inner wall of the trench etched by the semiconductor substrate layer is h =1.8.

[0061] The average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench are inspected to determine whether the substrate epitaxial layer trench etching process is qualified.

[0062]

[0063] In the formula, C Indicates the yield rate of the trenches etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d 0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched groove, g Indicates the existence rate of cracks in the inner surface of the groove;

[0064] when C When ≥80%, it means that the process of trench etching the surface of the substrate epitaxial layer meets the requirements of good products.

[0065] Among them, the average width of the trench etched in the substrate epitaxial layer is d =3.4 (micrometers), the target width of the etched groove isd 0 = 2 (micrometers), the existence rate of cracks in the inner surface of the groove is g =35% (the existence rate of cracks = the number of substrate epitaxial layers with more than 10 cracks in the groove ÷ the number of sampled substrate epitaxial layers), then:

[0066]

[0067] From the above calculations, it can be known that the process of trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0068] S4. Perform multiple injections at multiple angles to obtain a heavily doped P-well layer that meets the specifications. Multiple injections at multiple angles can be performed by rotating the wafer and tilting it.

[0069] S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer, and then depositing metal in the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench. In this embodiment, the top of the side metal source electrode can contact the dielectric layer; the oxide layer can be deposited using an oxide layer deposition device.

[0070] S6. The gate, dielectric layer and upper metal source are fabricated according to normal processes. In the planar structure, the side metal source 5 and the upper metal source 2 are brought into contact near the main junction of the device; Figure 1 Not drawn in.

[0071] In this embodiment, a side metal source is designed, and the source ohmic contact is designed in the vertical direction within the epitaxial layer. The adjacent N-well layer, lightly doped P-well layer and heavily doped P-well layer can directly contact the side metal source, so that adjacent MOS cells do not need to be isolated by a heavily doped P-well layer. The design structure is more compact and the lateral cell size occupied by the source contact is greatly reduced.

[0072] In addition, this embodiment further eliminates the gate-source lateral alternating structure, eliminates at least one isolation layer between the source and the gate, and the lateral cell length of the source metal opening, so that the cell size is further reduced, which can be reduced from the conventional 6 microns to 3 microns, and the size is reduced by more than 50%. And it makes the process simpler. Conventional gate-source lateral isolation requires sufficient thickness of the lateral dielectric layer to prevent breakdown, and requires stable polysilicon etching without sharp corners and wavy bends, otherwise it will cause the gate source to be easily broken down, so the etching process is strict, and the quality requirements of the isolation material (such as silicon oxide) are also relatively strict. Since the isolation problem needs to be considered during the design, the size of the lateral isolation layer must be reserved, and the size of the device cell must be increased. After the present invention is changed to a new structure, all the above concerns disappear. The process requirements of this embodiment are lower and the manufacturing is simpler.

Claims

1. A low-resistance superjunction structure eliminating the gate-source lateral alternating structure, comprising a plurality of MOS cells connected in parallel, characterized in that A single MOS cell includes, from bottom to top, a drain, a substrate layer, a diffusion layer, a dielectric layer, a gate, and an upper metal source, wherein the diffusion layer is located on the surface of the substrate layer and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer includes a lightly doped P-well layer and a heavily doped P-well layer, wherein the heavily doped P-well layer extends to the bottom of the diffusion layer and contacts the substrate layer; A groove is etched in the middle of the heavily doped P-well layer between adjacent MOS cells, the bottom of the groove may or may not extend to the substrate layer, an oxide layer is deposited at the bottom of the groove, a side metal source is provided on the surface of the oxide layer and the top of the groove, the top of the side metal source is in contact with the dielectric layer, and the side metal source is in lead-out contact with the upper metal source near the main junction of the device; the side surface of the side metal source is in ohmic contact with the N-well layer, the lightly doped P-well layer and the heavily doped P-well layer; The dielectric layer is a laterally continuous dielectric layer, the gate is arranged inside the dielectric layer, adjacent gates are isolated by the dielectric layer, and no gate-source alternating structure is formed, and an upper metal source is arranged on the upper surface of the dielectric layer.

2. The low-resistance superjunction structure eliminating the gate-source lateral alternating structure according to claim 1, characterized in that The substrate layer is arranged on the drain surface, the heavily doped P-well layer and the diffusion layer are arranged on the substrate layer surface, and the heavily doped P-well layer is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P-well layers on both sides of the single MOS cell, the lightly doped P-well layer is arranged on the surfaces of the diffusion layer and the heavily doped P-well layer, and is respectively connected to the diffusion layer and the heavily doped P-well layer, the N-well layer is located on the surface of the lightly doped P-well layer, and is connected to the lightly doped P-well layer, and the gate is isolated and connected to the upper surface of the N-well layer, the surfaces of the lightly doped P-well layer and the diffusion layer through a dielectric layer.

3. The low-resistance superjunction structure eliminating the gate-source lateral alternating structure as claimed in claim 2, characterized in that The N-well layer includes a lightly doped N-well layer and a heavily doped N-well layer, wherein the heavily doped N-well layer is located on the upper layer of the lightly doped N-well layer; the lightly doped N-well layer is located on the surface of the lightly doped P-well layer, the side surface of the side metal source is in ohmic contact with the lightly doped N-well layer, the heavily doped N-well layer, the lightly doped P-well layer and the heavily doped P-well layer, and the gate is isolated and connected to the upper surface of the heavily doped N-well layer, the lightly doped P-well layer and the surface of the diffusion layer through a dielectric layer.

4. The low-resistance superjunction structure eliminating the gate-source lateral alternating structure according to claim 1, characterized in that The height of the oxide layer filled in the trench is lower than the bottom cross-sectional height of the lightly doped P-well layer, so that the side metal source is in contact with the heavily doped P-well layer.

5. The low-resistance superjunction structure eliminating the gate-source lateral alternating structure according to claim 1, characterized in that When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device.

6. The low-resistance superjunction structure eliminating the gate-source lateral alternating structure according to claim 1, characterized in that The trench is perpendicular to the substrate layer.

7. The method for manufacturing a low-resistance super junction structure eliminating a gate-source lateral alternating structure according to any one of claims 1 to 6, characterized in that The method comprises the following steps: S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them; S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation; S3, between adjacent MOS cells, a trench is formed by etching the reserved heavily doped P-well layer; S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer that meets the specifications; S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer, and then depositing metal into the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench; S6. Complete the remaining parts of the device according to the normal process.

8. The method according to claim 7, characterized in that In step S3, the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench are inspected to determine whether the substrate epitaxial layer trench etching process is qualified, as follows: In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench; When C≥80%, it means that the process of trench etching the surface of the substrate epitaxial layer meets the requirements of good products.

9. The method according to claim 8, characterized in that In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating. In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where h The larger the value, the worse the uprightness of the groove; m It indicates the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u Indicates the maximum inward inclination angle of the groove side wall after heating.

Images