Electrostatic protection device with low trigger voltage and high failure current and manufacturing method thereof

Abstract

The invention provides a symmetric bidirectional silicon controlled rectifier electrostatic protection device with low trigger voltage and high failure current and a manufacturing method thereof. The symmetric bidirectional silicon controlled rectifier electrostatic protection device comprises a P-type substrate, an N-type deep trap, an N-type trap, a P-type trap and the like, a first N well and a second P + injection region, the first N well and a third P + injection region, and a cross gate directly connected with a cathode and an anode through highly doped P + injection jointly determine the trigger voltage of the device, and the cross gate generates a downward electric field to attract electrons in the N wells to a breakdown surface of the cross gate, so that the concentration of one side of the breakdown surface is increased, and the trigger voltage is reduced; the first P + injection region, the first N + injection region and the second grid electrode are connected together to serve as an anode of the device; the first grid electrode, the third N + injection region and the fourth P + injection region are connected together to serve as a cathode of the device; the device effectively protects a chip I / O signal port for transmitting positive and negative levels under the condition that the trigger voltage of the device is reduced. The device has the characteristics of low trigger voltage and high failure current, and can be applied to bidirectional ESD protection of an I / O port.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection, and in particular to a low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device and a manufacturing method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the size of devices has been continuously reduced. The failure of integrated circuit chips and electronic products caused by electrostatic discharge (ESD) has become more and more serious. According to relevant statistics, the damage caused by ESD in the field of microelectronics is as high as about 10 billion US dollars per year. This data shows the necessity of ESD protection measures for integrated circuit chips and electronic products.

[0003] Compared with other ESD devices, traditional thyristor devices (Silicon Controlled Rectifier, SCR) have advantages such as strong current discharge capability per unit area and small parasitic capacitance. However, traditional thyristor devices have disadvantages such as too high trigger voltage and too low holding voltage after the device is triggered. Too high trigger voltage will cause the protection device to fail to protect the core circuit in time, and too low holding voltage will cause the device to latch, resulting in the ESD protection device being unable to play its normal role and unable to ensure the integrity of the I / O port transmission signal.

[0004] Symmetrical bidirectional thyristor devices are improved on the basis of traditional thyristors. They have a symmetrical structural layout and the same working principle as traditional unidirectional thyristors. Symmetrical bidirectional thyristors can discharge ESD current from two directions. Figure 1 , its equivalent circuit diagram is shown in Figure 2. When an ESD pulse is applied to the anode of the bidirectional SCR, the N-type deep well and the second P-well form a reverse biased PN junction. When the ESD pulse voltage is higher than the reverse biased PN junction avalanche breakdown voltage, the device will generate an avalanche breakdown current, and the avalanche breakdown current flows through the second P-well parasitic resistor Rp2. When the voltage across Rp2 is higher than the forward conduction voltage of the longitudinal NPN transistor, the longitudinal NPN transistor is turned on. After the longitudinal NPN transistor is turned on, it provides a base current to the lateral PNP transistor, causing the lateral PNP transistor to turn on. The two transistors provide base currents to each other to promote each other and form a positive feedback link. When the two transistors are fully turned on, they form an SCR path to discharge the ESD current. The bidirectional SCR has a symmetrical structure. When an ESD pulse is applied to the cathode, the N-type deep well and the first P-well form a reverse biased PN junction avalanche breakdown, causing the PNP transistor and the NPN transistor to be turned on successively to discharge static electricity. However, traditional SCRs have the disadvantages of high trigger voltage and low holding voltage. A high trigger voltage will cause the device to fail to meet the design window requirements, and a low holding voltage is prone to latch-up effect. Therefore, it is necessary to lower the trigger voltage to ensure that the device can promptly turn on the protection core circuit when the ESD current arrives, and at the same time increase the holding voltage of the bidirectional thyristor to avoid the latch-up effect. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device and a manufacturing method thereof, and is applied to the ESD protection design of an I / O port with an operating voltage of 0 to 5.5V.

[0006] The invention provides a symmetrical bidirectional thyristor electrostatic protection device with simple structure, low trigger voltage and high failure current, and a manufacturing method thereof.

[0007] To achieve the above object, the technical solution of the embodiment of the present invention is implemented as follows:

[0008] The present invention provides a low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device, comprising a P-type substrate; an N-type deep well is arranged in the P-type substrate; a first P-well, a first N-well and a second P-well are arranged from left to right above the N-type deep well; a first P+ injection area and a first N+ injection area are arranged in the first P-well; a second N+ injection area is arranged in the first N-well; a third N+ injection area and a fourth P+ injection area are arranged in the second P-well; a second P+ injection area is arranged between the first P-well and the first N-well; a third P+ injection area is arranged between the first N-well and the second P-well; the three electrodes of the first P+ injection area, the first N+ injection area and the second gate are connected together as the anode of the device, and the three electrodes of the first gate, the third N+ injection area and the fourth P+ injection area are connected together as the cathode of the device.

[0009] Preferably, a first field oxygen isolation region is provided between the left side of the first P+ injection region and the left edge of the P-type substrate; a second field oxygen isolation region is provided on the right side of the first P+ injection region and the left side of the first N+ injection region; a third field oxygen isolation region is provided on the right side of the first N+ injection region and the left side of the second P+ injection region; a first gate is provided on the right side of the second P+ injection region and the left side of the second N+ injection region; a second gate is provided on the right side of the second N+ injection region and the left side of the third P+ injection region; a fourth field oxygen isolation region is provided on the right side of the third P+ injection region and the left side of the third N+ injection region; a fifth field oxygen isolation region is provided on the right side of the third N+ injection region and the left side of the fourth P+ injection region; and a sixth field oxygen isolation region is provided between the right side of the fourth P+ injection region and the right edge of the P-type substrate.

[0010] Preferably, the first field oxygen isolation region, the second field oxygen isolation region and the third field oxygen isolation region are located on the surface of the first P well; the first gate and the second gate are located on the surface of the first N well; the fourth field oxygen isolation region, the fifth field oxygen isolation region and the sixth field oxygen isolation region are located on the surface of the second P well.

[0011] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region, the first N well, and the second P well constitute a PNP-type transistor, and the first N well, the second P well, and the third N+ injection region constitute an NPN-type transistor, and a forward SCR path is formed when the parasitic PNP and the parasitic NPN are turned on. When a high-voltage ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the fourth P+ injection region, the first N well, and the first P well constitute a PNP-type transistor, and the first N well, the first P well, and the first N+ injection region constitute an NPN-type transistor, and a reverse SCR path is formed when the parasitic PNP and the parasitic NPN are turned on.

[0012] Preferably, when a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, and the ESD current flows along the first P+ injection area into the first N well, the second P well, and the third N+ injection area. When the ESD current increases to a certain value, the reverse PN junction formed by the third P+ injection area and the first N well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second P well. When the voltage drop on the equivalent resistance reaches 0.7V, the longitudinal NPN transistor is turned on and the base current is provided to the lateral PNP transistor to promote its conduction, forming a positive feedback effect. At this time, the forward SCR path is successfully opened. When the high-voltage ESD pulse reaches the cathode of the device, the anode of the device is connected to a low potential, and the ESD current flows along the fourth P+ injection area into the first N well, the first P well, and the first N+ injection area. When the ESD current increases to a certain value, the reverse PN junction composed of the second P+ injection area and the first N well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the first P well. When the voltage drop on the equivalent resistance reaches 0.7V, the longitudinal NPN transistor is turned on and the base current is provided to the lateral PNP transistor to promote its conduction, forming a positive feedback effect. At this time, the reverse SCR path is successfully opened.

[0013] The present invention provides a method for manufacturing a symmetrical bidirectional thyristor electrostatic protection device with low trigger voltage and high failure current, the method comprising:

[0014] Step 1: forming an N-type deep well in a P-type substrate;

[0015] Step 2: generating a first P well, a first N well, and a second P well above the N-type deep well;

[0016] Step 3: sequentially generating a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a first gate, a second gate, a fourth field oxygen isolation region, a fifth field oxygen isolation region, and a sixth field oxygen isolation region from left to right in the P-type substrate;

[0017] Step 4: forming a first P+ injection region and a first N+ injection region in the first P well from left to right, forming a second N+ injection region in the first N well from left to right, and forming a second P+ injection region between the contact surface of the first P well and the first N well, forming a third N+ injection region and a fourth P+ injection region in the second P well from left to right, and forming a third P+ injection region between the contact surface of the first N well and the second P well; and the left side of the first field oxygen isolation region contacts the left edge of the P-type substrate, the right side of the first field oxygen isolation region contacts the left side of the first P+ injection region, the right side of the first P+ injection region contacts the left side of the second field oxygen isolation region, the right side of the second field oxygen isolation region contacts the left side of the first N+ injection region, and the right side of the first N+ injection region contacts the third field oxygen isolation region. region; the right side of the third field oxygen isolation region contacts the left side of the second P+ injection region, the right side of the second P+ injection region contacts the left side of the first gate, the right side of the first gate contacts the left side of the second N+ injection region, the right side of the second N+ injection region contacts the left side of the second gate, the right side of the second gate contacts the left side of the third P+ injection region, the right side of the third P+ injection region contacts the left side of the fourth field oxygen isolation region, the right side of the fourth field oxygen isolation region contacts the left side of the third N+ injection region, the right side of the third N+ injection region contacts the left side of the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region contacts the left side of the fourth P+ injection region, the right side of the fourth P+ injection region contacts the left side of the sixth field oxygen isolation region, and the right side of the sixth field oxygen isolation region contacts the right edge of the P-type substrate;

[0018] Step 5: performing annealing treatment on the first P+ injection region, the first N+ injection region, the second P+ injection region, the second N+ injection region, the third P+ injection region, the third N+ injection region, and the fourth P+ injection region to eliminate the migration of impurities in the injection region;

[0019] Step six: connect the first P+ injection region, the first N+ injection region, and the second gate together as the anode of the device, and connect the first gate, the third N+ injection region, and the fourth P+ injection region together as the cathode of the device.

[0020] Preferably, the method further comprises:

[0021] A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

[0022] The present invention provides a low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device and a manufacturing method thereof, and the beneficial effects thereof are:

[0023] 1. The present invention can reduce the trigger voltage and increase the holding voltage by optimizing the device process level and the gate electric field without increasing the device layout area. When the anode applies ESD current, the first deep N well can form an additional vertical parasitic NPN conductive path, which passes through the first P+ injection area, the first P well, the first N well, the first deep N well, the second P well, and the third N+ injection area, and shunts with the main path first P+ injection area, the first P well, the first N well, the second P well, and the third N+ injection area to increase the reverse holding voltage. The first N well and the third P+ injection area constitute the reverse PN junction breakdown voltage. At the same time, because the second gate is connected to the anode, a downward electric field will be generated, thereby increasing the concentration of electrons on the reverse PN junction side. This structural design can effectively reduce the forward device trigger voltage. When the cathode applies ESD current, the first deep N well can form an additional vertical parasitic NPN conductive path, which passes through the fourth P+ injection area, the second P well, the first N well, the first P well, the first deep N well, the first N+ injection area, and the main path fourth P+ injection area, the second P well, the first N well, the first P well, the first N+ injection area, to shunt and increase the forward holding voltage. The first N well and the second P+ injection area form a reverse PN junction breakdown voltage. At the same time, because the first gate is connected to the anode, a downward electric field will be generated, thereby increasing the concentration of electrons on one side of the reverse PN junction. This structural design can effectively reduce the reverse device trigger voltage.

[0024] 2. The first gate and the second gate of the present invention have adjustable sizes to increase the distance between the anode and cathode of the device, which can extend the effective length of the discharge current path of the ESD current and thus increase its equivalent resistance, thereby improving the holding voltage of the device. The N-type deep well can completely isolate the main structure of the thyristor from the P-type substrate, effectively improving the device's anti-leakage capability.

[0025] 3. The size S2 of the first P+ injection area and the fourth P+ injection area in the first P-well and the second P-well of the present invention is adjustable. When S2 is increased, the parasitic PNP tube gain is increased, the positive feedback link is strengthened, and the failure current is improved. Therefore, the failure current of the device will increase with the increase of size S2. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a cross-sectional view of a currently known bidirectional SCR electrostatic protection device;

[0027] Figure 2 It is the equivalent circuit diagram of the currently known bidirectional SCR electrostatic protection device;

[0028] Figure 3 A cross-sectional view of a symmetrical bidirectional thyristor electrostatic protection device with low trigger voltage and high failure current provided by the present invention;

[0029] Figure 4 The equivalent circuit diagram of the low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device provided by the present invention;

[0030] Figure 5 This is a simulation diagram of the total current density distribution of the low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device provided by the present invention. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0033] like Figure 3 As shown, a low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device comprises a P-type substrate 101; an N-type deep well 201 is provided in the P-type substrate 101; a first P-well 401, a first N-well 301, and a second P-well 402 are provided above the N-type deep well 201 from left to right; a first P+ injection region 501 and a first N+ injection region 502 are provided in the first P-well 401; a second N+ injection region 504 is provided in the first N-well 301; a third N+ injection region 506, a first N+ injection region 507, a first N+ injection region 508 are provided in the second P-well 402 Four P+ injection regions 507; a second P+ injection region 503 is provided between the first P well 401 and the first N well 301; a third P+ injection region 505 is provided between the first N well 301 and the second P well 402; the three electrodes of the first P+ injection region 501, the first N+ injection region 502, and the second gate 702 are connected together as the anode of the device, and the three electrodes of the first gate 701, the third N+ injection region 506, and the fourth P+ injection region 507 are connected together as the cathode of the device.

[0034] In one embodiment, a first field oxygen isolation region 601 is provided between the left side of the first P+ injection region 501 and the left edge of the P-type substrate 101; a second field oxygen isolation region 602 is provided on the right side of the first P+ injection region 501 and the left side of the first N+ injection region 502; a third field oxygen isolation region 603 is provided on the right side of the first N+ injection region 502 and the left side of the second P+ injection region 503; a first gate 701 is provided on the right side of the second P+ injection region 503 and the left side of the second N+ injection region 504; a second gate 702 is provided on the right side of the second N+ injection region 504 and the left side of the third P+ injection region 505; a fourth field oxygen isolation region 604 is provided on the right side of the third P+ injection region 505 and the left side of the third N+ injection region 506; a fifth field oxygen isolation region 605 is provided on the right side of the third N+ injection region 506 and the left side of the fourth P+ injection region 507; a sixth field oxygen isolation region 606 is provided between the right side of the fourth P+ injection region 507 and the right edge of the P-type substrate 101.

[0035] In one embodiment, the first field oxygen isolation region 601, the second field oxygen isolation region 602 and the third field oxygen isolation region 603 are located on the surface of the first P well 401; the first gate 701 and the second gate 702 are located on the surface of the first N well 301; the fourth field oxygen isolation region 604, the fifth field oxygen isolation region 605 and the sixth field oxygen isolation region 606 are located on the surface of the second P well 402.

[0036] In one embodiment, if Figure 3 As shown, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region 501, the first N well 301, and the second P well 402 constitute a PNP type transistor, the first N well 301, the second P well 402, and the third N+ injection region 506 constitute an NPN type transistor, and when the parasitic PNP and the parasitic NPN are turned on, a forward SCR path is formed. When the ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the fourth P+ injection region 507, the first N well 301, and the first P well 401 constitute a PNP type transistor, the first N well 301, the first P well 401, and the first N+ injection region 502 constitute an NPN type transistor, and when the parasitic PNP and the parasitic NPN are turned on, a reverse SCR path is formed.

[0037] When the high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, and the ESD current flows along the first P+ injection area 501 into the first N well 301, the second P well 402, and the third N+ injection area 506. When the ESD current increases to a certain value, the reverse PN junction composed of the third P+ injection area 505 and the first N well 301 undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second P well 402. The equivalent circuit diagram shows Figure 4 It can be seen that when the voltage drop on the equivalent resistor reaches 0.7V, the longitudinal NPN transistor is turned on and the base current is provided to the lateral PNP transistor to promote its conduction, forming a positive feedback effect. At this time, the forward SCR path is successfully turned on. When the ESD pulse reaches the cathode of the device, the anode of the device is connected to a low potential, and the ESD current flows along the fourth P+ injection area 507 into the first N well 301, the first P well 401, and the first N+ injection area 502. When the ESD current increases to a certain value, the reverse PN junction composed of the second P+ injection area 503 and the first N well 301 undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistor of the first P well 401. The equivalent circuit diagram shows Figure 4 It can be seen that when the voltage drop on the equivalent resistor reaches 0.7V, the vertical NPN transistor is turned on and provides base current to the lateral PNP transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the reverse SCR path is successfully opened.

[0038] Compared with the traditional bidirectional symmetrical thyristor electrostatic protection device, the device changes the path of the traditional symmetrical bidirectional thyristor device. The reverse biased PN junction composed of the second P+ injection area 503 and the first N well 301, the third P+ injection area 505 and the first N well 301 enables the device to have a lower trigger voltage. At the same time, the device has an additional discharge path, which is simulated by the total current density distribution of the device. Figure 5 It can be seen that the current density distribution below the second P+ injection area 503 and the third P+ injection area 505 is the most dense, indicating that this path is the main discharge path. At the same time, the current is also relatively dense in the N-type deep well 201, indicating that this discharge path is a secondary discharge path. This discharge path can guide the current to flow deep into the device, and can effectively improve the device's holding voltage and failure current.

[0039] The first gate 701 and the second gate 702 can increase the distance between the anode and cathode of the device, and can effectively improve the holding voltage of the device. The N-type deep well 201 can completely isolate the main structure of the thyristor from the P-type substrate 101, and effectively improve the anti-leakage capability of the device.

[0040] The size S2 of the first P+ injection region 501 and the fourth P+ injection region 507 in the first P-well 401 and the second P-well 402 is adjustable. When S2 is increased, the parasitic PNP tube gain is increased, the positive feedback link is strengthened, and the failure current is improved. Therefore, the failure current of the device will increase with the increase of the size S2.

[0041] The embodiment of the present invention also provides a method for manufacturing a low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device, comprising the following steps:

[0042] Step 1: forming an N-type deep well 201 in a P-type substrate 101;

[0043] Step 2: Generate a first P well 401, a first N well 301, and a second P well 402 above the N-type deep well 201;

[0044] Step 3: Generate a first field oxygen isolation region 601, a second field oxygen isolation region 602, a third field oxygen isolation region 603, a first gate 701, a second gate 702, a fourth field oxygen isolation region 604, a fifth field oxygen isolation region 605, and a sixth field oxygen isolation region 606 in the P-type substrate 101 from left to right;

[0045] Step 4: A first P+ injection region 501 and a first N+ injection region 502 are sequentially formed from left to right in the first P well 401, a second N+ injection region 504 is sequentially formed from left to right in the first N well 301, and a second P+ injection region 503 is formed between the contact surface of the first P well 401 and the first N well 301, a third N+ injection region 506 and a fourth P+ injection region 507 are sequentially formed from left to right in the second P well 402, and a third N+ injection region 507 and a fourth P+ injection region 508 are sequentially formed between the first N well 301 and the second P well 402. A third P+ injection region 505 is formed between the contact surfaces of the well 402; and the left side of the first field oxygen isolation region 601 contacts the left edge of the P-type substrate 101, the right side of the first field oxygen isolation region 601 contacts the left side of the first P+ injection region 501, the right side of the first P+ injection region 501 contacts the left side of the second field oxygen isolation region 602, the right side of the second field oxygen isolation region 602 contacts the left side of the first N+ injection region 502, the right side of the first N+ injection region 502 contacts the third field oxygen isolation region The third field oxygen isolation region 603 contacts the left side of the second P+ injection region 503 on the right side, the second P+ injection region 503 contacts the left side of the first gate 701 on the right side, the first gate 701 contacts the left side of the second N+ injection region 504 on the right side, the second N+ injection region 504 contacts the left side of the second gate 702 on the right side, the second gate 702 contacts the left side of the third P+ injection region 505 on the right side, the third P+ injection region 505 contacts the left side of the fourth field oxygen isolation region 604 on the right side, the fourth field oxygen isolation region 604 contacts the left side of the third N+ injection region 506 on the right side, the third N+ injection region 506 contacts the left side of the fifth field oxygen isolation region 605 on the right side, the fifth field oxygen isolation region 605 contacts the left side of the fourth P+ injection region 507 on the right side, the fourth P+ injection region 507 contacts the left side of the sixth field oxygen isolation region 606 on the right side, and the sixth field oxygen isolation region 606 contacts the right edge of the P-type substrate 101 on the right side;

[0046] Step 5: performing annealing treatment on the first P+ injection region 501, the first N+ injection region 502, the second P+ injection region 503, the second N+ injection region 504, the third P+ injection region 505, the third N+ injection region 506, and the fourth P+ injection region 507 to eliminate the migration of impurities in the injection region;

[0047] Step six: Connect the first P+ injection region 501, the first N+ injection region 502, and the second gate 702 together as the anode of the device, and connect the first gate 701, the third N+ injection region 506, and the fourth P+ injection region 507 together as the cathode of the device.

[0048] Optionally, the method further comprises:

[0049] A silicon dioxide film is grown on the P-type substrate 101, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

[0050] The manufacturing method of the low trigger voltage and high failure current symmetrical bidirectional thyristor electrostatic protection device of the present invention is simple in process and easy to operate. The manufactured symmetrical bidirectional thyristor electrostatic protection device structure has a reverse avalanche breakdown surface with a lower breakdown voltage, which can effectively reduce the trigger voltage of the device. At the same time, the design enables the device to have an additional ESD current discharge path, which can effectively increase the device holding voltage. The device can be applied to the ESD protection design of I / O ports of 0 to 5.5V, and can effectively protect the internal chip from the risk of latch-up. The example device of the present invention adopts a 0.25μm BCDMOS process.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A low trigger voltage and high failure current electrostatic protection device, characterized in that: It comprises a P-type substrate; an N-type deep well is provided in the P-type substrate; A first P well, a first N well, and a second P well are arranged above the N-type deep well from left to right; a first P+ injection region and a first N+ injection region are arranged in the first P well; A second N+ implantation region is provided in the first N well; A third N+ injection region and a fourth P+ injection region are provided in the second P-well; a second P+ injection region is provided between the first P-well and the first N-well; a third P+ injection region is provided between the first N-well and the second P-well; the first P+ injection region, the first N+ injection region and the second gate are connected together as the anode of the device, and the first gate, the third N+ injection region and the fourth P+ injection region are connected together as the cathode of the device.

2. The low trigger voltage and high failure current electrostatic protection device according to claim 1, characterized in that: A first field oxygen isolation region is provided between the left side of the first P+ injection region and the left edge of the P-type substrate; a second field oxygen isolation region is provided on the right side of the first P+ injection region and the left side of the first N+ injection region; a third field oxygen isolation region is provided on the right side of the first N+ injection region and the left side of the second P+ injection region; a first gate is provided on the right side of the second P+ injection region and the left side of the second N+ injection region; a second gate is provided on the right side of the second N+ injection region and the left side of the third P+ injection region; a fourth field oxygen isolation region is provided on the right side of the third P+ injection region and the left side of the third N+ injection region; a fifth field oxygen isolation region is provided on the right side of the third N+ injection region and the left side of the fourth P+ injection region; a sixth field oxygen isolation region is provided between the right side of the fourth P+ injection region and the right edge of the P-type substrate.

3. The low trigger voltage and high failure current electrostatic protection device according to claim 2, characterized in that: The first field oxygen isolation region, the second field oxygen isolation region and the third field oxygen isolation region are located on the surface of the first P well; the first gate and the second gate are located on the surface of the first N well; the fourth field oxygen isolation region, the fifth field oxygen isolation region and the sixth field oxygen isolation region are located on the surface of the second P well.

4. The low trigger voltage and high failure current electrostatic protection device according to claim 2, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region, the first N well, and the second P well constitute a PNP type transistor, and the first N well, the second P well, and the third N+ injection region constitute an NPN type transistor. When the parasitic PNP and the parasitic NPN are turned on, a forward SCR path is formed; when the ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the fourth P+ injection region, the first N well, and the first P well constitute a PNP type transistor, and the first N well, the first P well, and the first N+ injection region constitute an NPN type transistor. When the parasitic PNP and the parasitic NPN are turned on, a reverse SCR path is formed.

5. The low trigger voltage and high failure current electrostatic protection device according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, and the ESD current flows along the first P+ injection area into the first N well, the second P well, and the third N+ injection area. When the ESD current increases to a certain value, the reverse PN junction composed of the third P+ injection area and the first N well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second P well. When the voltage drop on the equivalent resistance reaches 0.7V, the vertical NPN transistor is turned on and the base current is provided to the lateral PNP transistor to promote its conduction, forming a positive feedback effect. At this time, the forward SCR path is successfully opened. When the ESD pulse reaches the cathode of the device, the anode of the device is connected to a low potential, and the ESD current flows along the fourth P+ injection area into the first N well, the first P well, and the first N+ injection area. When the ESD current increases to a certain value, the reverse PN junction composed of the second P+ injection area and the first N well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the first P well. When the voltage drop on the equivalent resistance reaches 0.7V, the longitudinal NPN transistor is turned on and the base current is provided to the lateral PNP transistor to promote its conduction, forming a positive feedback effect. At this time, the reverse SCR path is successfully opened.

6. A method for manufacturing a low trigger voltage and high failure current electrostatic protection device, characterized in that: The method comprises: Step 1: forming an N-type deep well in a P-type substrate; Step 2: generating a first P well, a first N well, and a second P well above the N-type deep well; Step 3: sequentially generating a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a first gate, a second gate, a fourth field oxygen isolation region, a fifth field oxygen isolation region, and a sixth field oxygen isolation region from left to right in the P-type substrate; Step 4: forming a first P+ injection region and a first N+ injection region in the first P well from left to right, forming a second N+ injection region in the first N well from left to right, and forming a second P+ injection region between the contact surface of the first P well and the first N well, forming a third N+ injection region and a fourth P+ injection region in the second P well from left to right, and forming a third P+ injection region between the contact surface of the first N well and the second P well; and the left side of the first field oxygen isolation region contacts the left edge of the P-type substrate, the right side of the first field oxygen isolation region contacts the left side of the first P+ injection region, the right side of the first P+ injection region contacts the left side of the second field oxygen isolation region, the right side of the second field oxygen isolation region contacts the left side of the first N+ injection region, and the right side of the first N+ injection region contacts the third field oxygen isolation region. region; the right side of the third field oxygen isolation region contacts the left side of the second P+ injection region, the right side of the second P+ injection region contacts the left side of the first gate, the right side of the first gate contacts the left side of the second N+ injection region, the right side of the second N+ injection region contacts the left side of the second gate, the right side of the second gate contacts the left side of the third P+ injection region, the right side of the third P+ injection region contacts the left side of the fourth field oxygen isolation region, the right side of the fourth field oxygen isolation region contacts the left side of the third N+ injection region, the right side of the third N+ injection region contacts the left side of the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region contacts the left side of the fourth P+ injection region, the right side of the fourth P+ injection region contacts the left side of the sixth field oxygen isolation region, and the right side of the sixth field oxygen isolation region contacts the right edge of the P-type substrate; Step 5: performing annealing treatment on the first P+ injection region, the first N+ injection region, the second P+ injection region, the second N+ injection region, the third P+ injection region, the third N+ injection region, and the fourth P+ injection region to eliminate the migration of impurities in the injection region; Step six: connect the first P+ injection region, the first N+ injection region, and the second gate together as the anode of the device, and connect the first gate, the third N+ injection region, and the fourth P+ injection region together as the cathode of the device.

7. The method for manufacturing a low trigger voltage and high failure current electrostatic protection device according to claim 6, characterized in that: The method also includes: A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

Images