NMOS (N-channel metal oxide semiconductor) triggered stackable unidirectional silicon controlled electrostatic protection device and manufacturing method thereof
By introducing NMOS trigger structure and DTSCR stack structure into ESD protection devices, the problems of high trigger voltage and latch-up effect of existing devices are solved, lower trigger voltage and higher sustaining voltage are achieved, and the ESD of the device is significantly improved. Protective properties.
Patent Information
- Application Number
- CN202411502813.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-01-21
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
When faced with ESD pulses, the trigger voltage is high, making it difficult to effectively protect the core circuit, and it is easy to have a latch effect.
Using NMOS triggered one -way one -way silicon static protective device, by introducing the NMOS trigger structure and the DTSCR stacking structure, the trigger voltage of the device is reduced, and the width and stacking structure of the oxygen isolation area are adjusted to increase the maintenance voltage and anti -resistance of the device. 闩 Lock ability.
It effectively reduces the trigger voltage of the device, making it easier to turn on, while improving the maintenance voltage and anti-latch capabilities, significantly improving the ESD protection performance of the device.
Smart Images
Figure CN119342901A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electrostatic protection, and in particular to an NMOS-triggered stackable unidirectional thyristor electrostatic protection device and a manufacturing method thereof. Background Art
[0002] With the advancement of semiconductor manufacturing technology, the failure of integrated circuit chips and electronic products caused by ESD has become more serious. ESD protection for electronic products and integrated circuit chips has become one of the main problems faced by product engineers. The ESD design window is an issue that product engineers need to focus on when designing ESD protection, including the trigger voltage V t1 , trigger current I t1 , Maintaining voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 , on-resistance R on The trigger voltage of the ESD protection device must be lower than the maximum withstand voltage of the protected port of the core circuit, i.e., the drain-source breakdown voltage. Usually, the trigger voltage is 10% to 20% lower than the maximum withstand voltage. The maintenance voltage of the ESD protection device must be 1.1 to 1.2 times higher than the normal working voltage of the core circuit to protect the core circuit from latching up due to the ESD protection device always being turned on. The failure current I t2 It is one of the important parameters to measure the robustness of ESD protection devices. It indicates the maximum current that the ESD protection device can withstand. If the core circuit is to be effectively protected, the failure current I t2 When the ESD protection device is on, the clamping voltage must be less than the maximum withstand voltage of the protected port; the on-resistance R on It is the resistance characteristic of the device after entering the holding point, which is related to the holding voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 According to Ohm's law, the on-resistance R on Expressed as failure voltage V t2 , Maintaining voltage V h Difference and fault current I t2 , Maintaining current I h The ratio of the difference; the human body model HBM regards the equivalent resistance of the human body as 1.5kΩ, and the HBM protection level is 1500 times I t2 .
[0003] The failure modes caused by ESD include hard failure, soft failure, and potential failure. The causes of these failures can be divided into electrical failure and thermal failure. Thermal failure refers to the current of several amperes to tens of amperes generated locally on the chip when the ESD pulse comes. It lasts for a short time but generates a lot of heat, causing the local metal connection to melt or causing hot spots on the chip, resulting in secondary breakdown. Electrical failure refers to the electric field strength formed by the voltage applied to the gate oxide layer being greater than the dielectric strength, causing surface breakdown or dielectric breakdown. As the threat posed by ESD to chips becomes more and more serious, research on its physical mechanism is receiving more and more attention.
[0004] Compared with other ESD devices, traditional unidirectional thyristor devices have a dual conductance modulation mechanism, high discharge efficiency per unit area, small unit parasitic capacitance, and the best robustness.
[0005] The cross-section diagram of the traditional unidirectional thyristor electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of the unidirectional SCR, the first N-well and the first P-well form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current will be generated inside the device. The current flows through the first P-well and flows to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the first P-well is equivalent to the base voltage drop of the transistor NPN. When this voltage is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After this transistor is turned on, it provides base current for the horizontal PNP transistor. After the horizontal PNP transistor is also turned on, it further provides base current for the vertical NPN transistor, forming a positive feedback mechanism to fully open the SCR path. Therefore, even if there is no avalanche current afterwards, the large current can be discharged due to the conduction of the transistor. Summary of the invention
[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing an NMOS-triggered stackable unidirectional thyristor electrostatic protection device and the manufacturing method thereof and is applied to the design of an ESD protection network with an operating voltage of 0 to 5.5V.
[0007] The technical solution of the present invention to solve the above problems is:
[0008] In a first aspect, an embodiment of the present invention provides an NMOS-triggered stackable unidirectional thyristor electrostatic protection device, comprising a P-type substrate; a first P-well, a first N-well, a second P-well, a second N-well, and a third P-well are sequentially arranged on the P-type substrate from left to right;
[0009] The first P well is provided with the first N+ injection, the first gate, and the second N+ injection from left to right in sequence; the first N well is provided with the third N+ injection and the first P+ injection from left to right in sequence; the second P well is provided with the second P+ injection, the fourth N+ injection, and the third P+ injection from left to right in sequence; the second N well is provided with the fifth N+ injection, the fourth P+ injection, and the sixth N+ injection from left to right in sequence; the third P well is provided with the fifth P+ injection, the seventh N+ injection, and the sixth P+ injection from left to right in sequence;
[0010] The first gate is between the first N+ injection and the second N+ injection;
[0011] The three electrodes of the second N+ injection in the first P well, the third N+ injection in the first N well and the first P+ injection are all connected together and serve as the anode of the device; the four electrodes of the first gate injection in the first P well, the sixth N+ injection in the second N well, the seventh N+ injection and the sixth P+ injection in the third P well are all connected together and serve as the cathode of the device; the first N+ injection in the first P well and the second P+ injection in the second P well are connected together through a metal wire without connecting to a potential; the four electrodes of the fourth N+ injection and the third P+ injection in the second P well, the fifth N+ injection and the fourth P+ injection in the second N well, and the fifth P+ injection in the third P well are connected together through a metal wire without connecting to a potential.
[0012] Preferably, there are thirteen field oxygen isolation zones; the first field oxygen isolation zone is to the left of the first N+ injection, the second field oxygen isolation zone is between the second N+ injection and the third N+ injection, the third field oxygen isolation zone is between the third N+ injection and the first P+ injection, the fourth field oxygen isolation zone is between the first P+ injection and the second P+ injection, the fifth field oxygen isolation zone is between the second P+ injection and the fourth N+ injection, the sixth field oxygen isolation zone is between the fourth N+ injection and the third P+ injection, the seventh field oxygen isolation zone is between the third P+ injection and the fifth N+ injection, the eighth field oxygen isolation zone is between the fifth N+ injection and the fourth P+ injection, the ninth field oxygen isolation zone is between the fourth P+ injection and the sixth N+ injection, the tenth field oxygen isolation zone is between the sixth N+ injection and the fifth P+ injection, the eleventh field oxygen isolation zone is between the fifth P+ injection and the seventh N+ injection, the twelfth field oxygen isolation zone is between the seventh N+ injection and the sixth P+ injection, and the thirteenth field oxygen isolation zone is to the right of the sixth P+ injection.
[0013] Preferably, the first field oxygen isolation region is located on the surface of the first P well, the second field oxygen isolation region bridges the surface at the junction of the first P well and the first N well, the third field oxygen isolation region is located on the surface of the first N well, the fourth field oxygen isolation region bridges the surface at the junction of the first N well and the second P well, the fifth field oxygen isolation region is located on the surface of the second P well, the sixth field oxygen isolation region is located on the surface of the second P well, the seventh field oxygen isolation region bridges the surface at the junction of the second P well and the second N well, the eighth field oxygen isolation region is located on the surface of the second N well, the ninth field oxygen isolation region is located on the surface of the second N well, the tenth field oxygen isolation region bridges the surface at the junction of the third P well and the second N well, the eleventh field oxygen isolation region is located on the surface of the third P well, the twelfth field oxygen isolation region is located on the surface of the third P well, and the thirteenth field oxygen isolation region is located on the surface of the third P well.
[0014] Preferably, when the cathode of the device is connected to a low potential and an ESD pulse reaches the anode of the device, the breakdown surface is between the first P well and the second N+ injection; the first N+ injection, the first gate, and the second N+ injection constitute an NMOS; the first P well and the first N+ injection, the first gate, and the second N+ injection in the first P well, the third N+ injection and the first P+ injection in the first N well and the second P well, the second P+ injection, the fourth N+ injection, and the third P+ injection in the second P well and the second P well, a total of three wells and eight electrodes together constitute the NMOS trigger structure of the device; the fifth N+ injection, the fourth P+ injection, and the sixth N+ injection in the second N well and the second N well, the fifth P+ injection, the seventh N+ injection, and the sixth P+ injection in the third P well and the fifth P well, a total of two wells and six injections together constitute the DTSCR stack structure of the device; when an avalanche breakdown occurs in the trigger structure, a trigger current is provided to the stack structure.
[0015] Preferably, when the cathode of the device is connected to a low potential, when an ESD pulse reaches the anode of the device, the first N+ injection, the first P well, and the second N+ injection constitute a parasitic transistor NPN1, the first P+ injection, the third N+ injection / first N well, the second P well / the second P+ injection / the third P+ injection constitute a parasitic transistor PNP1, the third N+ injection / first N well, the second P well / the second P+ injection / the third P+ injection, and the fourth N+ injection constitute a parasitic transistor NPN2, the parasitic transistors NPN1, PNP1, and NPN2 constitute an NMOS trigger structure, the fourth P+ injection, the fifth N+ injection / the sixth N+ injection / the second N well, the third P well / the fifth P+ injection The fifth N+ injection / sixth N+ injection / second N-well, third P-well / fifth P+ injection / sixth P+, seventh N+ injection constitute parasitic transistor NPN3, parasitic transistors PNP1 and NPN2 constitute a trigger structure SCR, parasitic transistors PNP2 and NPN3 constitute a stacked structure SCR; when the second N+ injection and the first P-well undergo avalanche breakdown, there is a current path from the second N+ injection / first P-well / first P-type substrate / third P-well / sixth P+ injection, when the voltage drop of RP4 reaches 0.7V, the parasitic transistor NPN1 of the NMOS is turned on, providing a trigger current to the device. At this time, the trigger main current path of the device changes from the original second N+ injection / first P well / first P-type substrate / third P well / sixth P+ to second N+ injection / first P well / first N+ injection / metal wire / second P+ injection / second P well / third P+ injection / metal wire / fifth N+ injection / second N well / sixth N+ injection; when the trigger current flows through RP2 and the voltage drop on RP2 reaches 0.7V, parasitic NPN2 turns on, the parasitic transistor NPN2 on the right turns on and provides base current to the parasitic transistor PNP1 on the left, thereby promoting its conduction. When the parasitic transistors PNP1 and NPN2 are turned on, a forward SCR path is formed, forming Positive feedback effect, at this time the SCR of the trigger structure is turned on; the stacked structure is equivalent to a well resistor RN2 when the SCR is not turned on. The same as the SCR turning-on principle of the trigger structure, when the voltage drop on RP3 reaches 0.7V, the parasitic NPN3 is turned on, the parasitic transistor NPN3 on the right is turned on and provides base current to the parasitic transistor PNP2 on the left to promote its conduction. When the parasitic transistor PNP2 and the parasitic transistor NPN3 are turned on, a forward SCR path is formed, forming a positive feedback effect, and the SCR of the stacked structure is turned on; when the SCR of the trigger structure and the stacked structure are both turned on, the device is fully turned on, and the maintenance voltage is equivalent to the clamping voltage of the two series SCRs.
[0016] Preferably, the width S1 of the fourth field oxygen isolation region is adjustable. When S1 increases, the distance between the anode and cathode increases, and the sustaining voltage increases.
[0017] Preferably, the number of stacked structures is adjustable. The number of stacked structures in the abstract figure is one. If the number of stacked structures is increased, the holding voltage of the device can be increased exponentially, further improving the anti-latch capability of the device.
[0018] In a second aspect, an embodiment of the present invention provides a method for manufacturing an NMOS-triggered stackable unidirectional thyristor electrostatic protection device, comprising the following steps:
[0019] Step 1: Generate a first P-well, a first N-well, a second P-well / a second N-well, and a third P-well from left to right on a P-type substrate;
[0020] Step 2: Generate a first N+ injection, a first gate, and a second N+ injection from left to right on the first P well; generate a third N+ injection and a first P+ injection from left to right on the first N well; generate a second P+ injection, a fourth N+ injection, and a third P+ injection from left to right on the second P well; generate a fifth N+ injection, a fourth P+ injection, and a sixth N+ injection from left to right on the second N well; generate a fifth P+ injection, a seventh N+ injection, and a sixth P+ injection from left to right on the third P well;
[0021] Step three: Generate a first field oxygen isolation region on the left side of the first N+ injection on the first P well, generate a second field oxygen isolation region between the second N+ injection and the third N+ injection, generate a third field oxygen isolation region between the third N+ injection and the first P+ injection, generate a fourth field oxygen isolation region between the first P+ injection and the second P+ injection, generate a fifth field oxygen isolation region between the second P+ injection and the fourth N+ injection, generate a sixth field oxygen isolation region between the fourth N+ injection and the third P+ injection, generate a seventh field oxygen isolation region between the third P+ injection and the fifth N+ injection, generate an eighth field oxygen isolation region between the fifth N+ injection and the fourth P+ injection, generate a ninth field oxygen isolation region between the fourth P+ injection and the sixth N+ injection, generate a tenth field oxygen isolation region between the sixth N+ injection and the fifth P+ injection, generate an eleventh field oxygen isolation region between the fifth P+ injection and the seventh N+ injection, generate a twelfth field oxygen isolation region between the seventh N+ injection and the sixth P+ injection, and generate a thirteenth field oxygen isolation region on the right side of the sixth P+ injection.
[0022] Step 4: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas;
[0023] Step 5: Connect the three electrodes of the second N+ injection in the first P well, the third N+ injection in the first N well and the first P+ injection together and use them as the anode of the device; connect the four electrodes of the first gate injection in the first P well, the sixth N+ injection in the second N well, the seventh N+ injection and the sixth P+ injection in the third P well together and use them as the cathode of the device; connect the first N+ injection in the first P well and the second P+ injection in the second P well through a metal wire without connecting them to a potential; connect the five electrodes of the fourth N+ injection and the third P+ injection in the second P well, the fifth N+ injection and the fourth P+ injection in the second N well, and the fifth P+ injection in the third P well through a metal wire without connecting them to a potential.
[0024] Preferably, before forming the N-well and the P-well in the P-type substrate, the method further comprises:
[0025] A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is reached to remove the silicon nitride layer.
[0026] The beneficial effects of the present invention are:
[0027] 1. The present invention adjusts the breakdown surface and introduces an NMOS trigger structure based on the traditional unidirectional thyristor electrostatic protection device to change the breakdown surface of the traditional SCR from the well breakdown of the first N well and the first P well to the second N+ injection and the first P well junction breakdown, thereby effectively reducing the trigger voltage of the device and making the device easier to turn on.
[0028] 2. In order to better exert the performance of the unidirectional thyristor, the present invention stacks a DTSCR stacking structure on the right side of the NMOS trigger structure. When an ESD pulse reaches the anode of the device, the first N+ injection, the first P well, and the second N+ injection constitute a parasitic transistor NPN1, the first P+ injection, the third N+ injection / first N well, the second P well / the second P+ injection / the third P+ injection constitute a parasitic transistor PNP1, the third N+ injection / first N well, the second P well / the second P+ injection / the third P+ injection, and the fourth N+ injection constitute a parasitic transistor NPN2, and the parasitic transistors NPN1, PNP1, and NPN2 constitute an NMOS trigger structure, and the fourth P+ injection, the fifth N+ injection / the third N+ injection / the first N well, the second P well / the second P+ injection / the third P+ injection, and the fourth N+ injection constitute a parasitic transistor NPN2. The sixth N+ injection / second N-well, third P-well / fifth P+ injection / sixth P+ injection constitute a parasitic transistor PNP2, the fifth N+ injection / sixth N+ injection / second N-well, third P-well / fifth P+ injection / sixth P+, seventh N+ injection constitute a parasitic transistor NPN3, parasitic transistors PNP1 and NPN2 constitute a trigger structure SCR, parasitic transistors PNP2 and NPN3 constitute a stacked structure SCR; when the second N+ injection and the first P-well undergo avalanche breakdown, there is a current path from the second N+ injection / first P-well / first P-type substrate / third P-well / sixth P+ injection, when the voltage drop of RP4 reaches 0.7V, the parasitic transistor NPN1 of the NMOS is turned on, giving The device provides a trigger current. At this time, the main trigger current path of the device changes from the original second N+ injection / first P well / first P-type substrate / third P well / sixth P+ to second N+ injection / first P well / first N+ injection / metal wire / second P+ injection / second P well / third P+ injection / metal wire / fifth N+ injection / second N well / sixth N+ injection; when the trigger current flows through RP2 and the voltage drop on RP2 reaches 0.7V, the parasitic NPN2 is turned on, the parasitic transistor NPN2 on the right is turned on and provides base current to the parasitic transistor PNP1 on the left to promote its conduction. When the parasitic transistor PNP1 and the parasitic transistor NPN2 are turned on, a forward SCR path is formed to form a positive feedback. effect, at this time the SCR of the trigger structure is turned on; the stacked structure is equivalent to a well resistor RN2 when the SCR is not turned on. The same as the SCR turning-on principle of the trigger structure, when the voltage drop on RP3 reaches 0.7V, the parasitic NPN3 is turned on, the parasitic transistor NPN3 on the right is turned on and provides base current to the parasitic transistor PNP2 on the left to promote its conduction. When the parasitic transistors PNP2 and NPN3 are turned on, a forward SCR path is formed, forming a positive feedback effect, and the SCR of the stacked structure is turned on; when the SCR of the trigger structure and the stacked structure are both turned on, the device is fully turned on, and the holding voltage is equivalent to the clamping voltage of the two series SCRs, which can greatly improve the holding voltage of the device.
[0029] 3. The width S1 of the fourth field oxygen isolation region of the present invention is adjustable. When S1 increases, the distance between the anode and cathode increases, and the sustaining voltage increases.
[0030] 4. The number of stacking structures described in the present invention is adjustable. The number of stacking structures in the abstract figure is one. If the number of stacking structures is increased, the holding voltage of the device can be increased exponentially, further improving the anti-latch capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.
[0032] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.
[0033] Figure 3 It is a cross-sectional view of an embodiment of the present invention.
[0034] Figure 4 2 is an equivalent circuit diagram of an embodiment of the present invention.
[0035] Figure 5 A total current density distribution simulation diagram of an NMOS-triggered stackable unidirectional thyristor electrostatic protection device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0036] The ESD protection design of the analog switch chip applied to the present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0037] like Figure 3As shown, an NMOS-triggered stackable unidirectional thyristor electrostatic protection device includes a P-type substrate 101; the P-type substrate 101 is provided with a first P well 201, a first N well 301, a second P well 202, a second N well 302, and a third P well 203 from left to right; the first P well 201 is provided with a first N+ injection 501, a first gate 601, and a second N+ injection 502 from left to right; the first N well 301 is provided with a third N well 203 from left to right + injection 503, first P+ injection 701; the second P well 202 is provided with a second P+ injection 702, a fourth N+ injection 504, and a third P+ injection 703 from left to right; the second N well 302 is provided with a fifth N+ injection 505, a fourth P+ injection 704, and a sixth N+ injection 506 from left to right; the third P well 203 is provided with a fifth P+ injection 705, a seventh N+ injection 507, and a sixth P+ injection 706 from left to right; the first The gate 601 is between the first N+ injection 501 and the second N+ injection 502; the three electrodes of the second N+ injection 502 in the first P well 201, the third N+ injection 503 in the first N well 301 and the first P+ injection 701 are all connected together and serve as the anode of the device; the four electrodes of the first gate 601 injection in the first P well 201, the sixth N+ injection 506 in the second N well 302, the seventh N+ injection 507 and the sixth P+ injection 706 in the third P well 203 are all connected together and serve as the cathode of the device; the first N+ injection 501 in the first P well 201 and the second P+ injection 702 in the second P well 202 are connected together through a metal wire and are not connected to a potential; the four electrodes of the fourth N+ injection 504 and the third P+ injection 703 in the second P well 202, the fifth N+ injection 505 and the fourth P+ injection 704 in the second N well 502, and the fifth P+ injection 705 in the third P well 203 are connected together through a metal wire and are not connected to a potential. Its equivalent circuit diagram is shown in Figure 4 .
[0038] In one embodiment, the NMOS-triggered stackable unidirectional thyristor electrostatic protection device has thirteen field oxygen isolation regions; the first field oxygen isolation region 401 is on the left side of the first N+ injection 501, the second field oxygen isolation region 402 is between the second N+ injection 502 and the third N+ injection 503, the third field oxygen isolation region 403 is between the third N+ injection 503 and the first P+ injection 701, the fourth field oxygen isolation region 404 is between the first P+ injection 701 and the second P+ injection 702, the fifth field oxygen isolation region 405 is between the second P+ injection 702 and the fourth N+ injection 504, and the sixth field oxygen isolation region 406 is between the fourth N+ injection 504 and the third P+ injection 706. 03, the seventh field oxygen isolation zone 407 is between the third P+ injection 703 and the fifth N+ injection 505, the eighth field oxygen isolation zone 408 is between the fifth N+ injection 505 and the fourth P+ injection 704, the ninth field oxygen isolation zone 409 is between the fourth P+ injection 704 and the sixth N+ injection 506, the tenth field oxygen isolation zone 410 is between the sixth N+ injection 506 and the fifth P+ injection 705, the eleventh field oxygen isolation zone 411 is between the fifth P+ injection 705 and the seventh N+ injection 507, the twelfth field oxygen isolation zone 412 is between the seventh N+ injection 507 and the sixth P+ injection 706, and the thirteenth field oxygen isolation zone 413 is to the right of the sixth P+ injection 706.
[0039] In one embodiment, the first field oxygen isolation region 401 is located on the surface of the first P well 201, the second field oxygen isolation region 402 is connected across the surface at the junction of the first P well 201 and the first N well 301, the third field oxygen isolation region 403 is located on the surface of the first N well 301, the fourth field oxygen isolation region 404 is connected across the surface at the junction of the first N well 301 and the second P well 202, the fifth field oxygen isolation region 405 is located on the surface of the second P well 202, the sixth field oxygen isolation region 406 is located on the surface of the second P well 202, and the seventh field oxygen isolation region 408 is connected to the surface of the second P well 202. 407 bridges the surface at the junction of the second P well 202 and the second N well 302, the eighth field oxygen isolation region 408 is located on the surface of the second N well 302, the ninth field oxygen isolation region 409 is located on the surface of the second N well 302, the tenth field oxygen isolation region 410 bridges the surface at the junction of the third P well 203 and the second N well 302, the eleventh field oxygen isolation region 411 is located on the surface of the third P well 203, the twelfth field oxygen isolation region 412 is located on the surface of the third P well 203, and the thirteenth field oxygen isolation region 413 is located on the surface of the third P well 203.
[0040] In one embodiment, the cathode of the device is connected to a low potential. When an ESD pulse reaches the anode of the device, the breakdown plane is between the first P well 201 and the second N+ injection 502; the first N+ injection 501, the first gate 601, and the second N+ injection 502 constitute an NMOS; the first P well 201 and the first N+ injection 501, the first gate 601, and the second N+ 502 injection in the first P well 201, the first N well 301 and the third N+ injection 503 in the first N well 301, the first P+ injection 701, the second P well 202 and the second P+ injection 503 in the second P well 202 Injection 702, the fourth N+ injection 504, and the third P+ injection 703, a total of three wells and eight electrodes together constitute the NMOS trigger structure of the device; the second N well 302 and the fifth N+ injection 505, the fourth P+ injection 704, the sixth N+ injection 506 in the second N well 302, the third P well 203 and the fifth P+ injection 705, the seventh N+ 507 injection, and the sixth P+ injection 706 in the fifth P well 205, a total of two wells and six injections together constitute the DTSCR stack structure of the device; when the trigger structure undergoes avalanche breakdown, a trigger current is provided to the stack structure.
[0041] Please refer to Figures 4 to 5When an ESD pulse reaches the anode of the device, the first N+ injection 501, the first P well 201, and the second N+ injection 502 constitute a parasitic transistor NPN1, the first P+ injection 701, the third N+ injection 503 / the first N well 301, the second P well 202 / the second P+ injection 702 / the third P+ injection 703 constitute a parasitic transistor PNP1, the third N+ injection 503 / the first N well 301, the second P well 201 / the second P+ injection 702 / the third P+ injection 703, and the fourth N+ injection 504 constitute a parasitic transistor NPN2, and the parasitic transistors NPN1, PNP1, and NPN2 constitute an NMOS trigger structure. The fourth P+ injection 704, the fifth N+ injection 505 / the sixth N+ injection 506 / the second N well 302, the third P well 203 / the fifth P+ injection 705 / the sixth P+ injection 706 constitute a parasitic transistor PNP2, the fifth N+ injection 505 / the sixth N+ injection 506 / the second N well 302, the third P well 703 / the fifth P+ injection 705 / the sixth P+ 706, the seventh N+ injection 707 constitute a parasitic transistor NPN3, the parasitic transistors PNP1 and NPN2 constitute a trigger structure SCR, and the parasitic transistors PNP2 and NPN3 constitute a stacked structure SCR; when the second N+ injection 502 and the first P well 201 occur During avalanche breakdown, there is a current path from the second N+ injection 502 / first P well 201 / first P type substrate 101 / third P well 203 / sixth P+ injection 706. When the voltage drop of RP4 reaches 0.7V, the parasitic transistor NPN1 of the NMOS turns on and provides a trigger current to the device. At this time, the main trigger current path of the device changes from the original second N+ injection 502 / first P well 201 / first P type substrate 101 / third P well 203 / sixth P+ injection 706 to the second N+ injection 502 / first P well 201 / first N+ injection 501 / metal line / second P+ injection 702 / second P well 202 / third P + injection 703 / metal line / fifth N+ injection 505 / second N well 302 / sixth N+ injection 506; when the trigger current flows through RP2 and the voltage drop on RP2 reaches 0.7V, the parasitic NPN2 is turned on, the parasitic transistor NPN2 on the right is turned on and provides base current to the parasitic transistor PNP1 on the left to promote its conduction. When the parasitic transistors PNP1 and NPN2 are turned on, a positive SCR path is formed to form a positive feedback effect. At this time, the SCR of the trigger structure is turned on; the stacked structure is equivalent to a well resistor RN2 when the SCR is not turned on. The voltage drop on RP3 reaches 0.When the voltage is 7V, the parasitic NPN3 is turned on, the parasitic transistor NPN3 on the right is turned on and provides base current to the parasitic transistor PNP2 on the left to promote its conduction. When the parasitic transistors PNP2 and NPN3 are turned on, a positive SCR path is formed, forming a positive feedback effect. At this time, the SCR of the stacked structure is turned on; when the trigger structure and the SCR of the stacked structure are both turned on, the device is fully turned on, and the maintenance voltage is equivalent to the clamping voltage of the two series SCRs.
[0042] 2. This device can control the ESD design window requirements in different application scenarios by controlling the width S1 of the fourth field oxygen isolation region. When S1 increases, the distance between the cathode and cathode increases, and the sustaining voltage increases. The sustaining voltage can be controlled by controlling the number of stacked structures DTSCR. The number of stacked structures is adjustable, such as Figure 3 The stacking number is one. If the stacking number is increased, the holding voltage of the device can be increased exponentially, further improving the anti-latch capability of the device.
[0043] The embodiment of the present invention further provides a method for manufacturing an NMOS-triggered stackable unidirectional thyristor electrostatic protection device, comprising the following steps:
[0044] Step 1: Generate a first P well 201, a first N well 301, a second P well 202, a second N well 302, and a third P well 203 from left to right on a P-type substrate 101;
[0045] Step 2: Generate a first N+ injection 501, a first gate 601, and a second N+ injection 502 from left to right on the first P well 201; generate a third N+ injection 503 and a first P+ injection 701 from left to right on the first N well 301; generate a second P+ injection 702, a fourth N+ injection 504, and a third P+ injection 703 from left to right on the second P well 202; generate a fifth N+ injection 505, a fourth P+ injection 704, and a sixth N+ injection 506 from left to right on the second N well 502; generate a fifth P+ injection 705, a seventh N+ injection 507, and a sixth P+ injection 706 from left to right on the third P well 203;
[0046] Step 3: Generate a first field oxygen isolation region 401 on the left side of the first N+ injection 501 on the first P well 201, generate a second field oxygen isolation region 402 between the second N+ injection 502 and the third N+ injection 503, generate a third field oxygen isolation region 403 between the third N+ injection 503 and the first P+ injection 701, generate a fourth field oxygen isolation region 404 between the first P+ injection 701 and the second P+ injection 702, generate a fifth field oxygen isolation region 405 between the second P+ injection 702 and the fourth N+ injection 504, generate a sixth field oxygen isolation region 406 between the fourth N+ injection 504 and the third P+ injection 703, and generate a sixth field oxygen isolation region 407 between the third P+ injection 703 and the first P+ injection 701. A seventh field oxygen isolation zone 407 is generated between the five N+ injections 505, an eighth field oxygen isolation zone 408 is generated between the fifth N+ injection 505 and the fourth P+ injection 704, a ninth field oxygen isolation zone 409 is generated between the fourth P+ injection 704 and the sixth N+ injection 506, a tenth field oxygen isolation zone 410 is generated between the sixth N+ injection 506 and the fifth P+ injection 705, an eleventh field oxygen isolation zone 411 is generated between the fifth P+ injection 705 and the seventh N+ injection 507, a twelfth field oxygen isolation zone 412 is generated between the seventh N+ injection 507 and the sixth P+ injection 706, and a thirteenth field oxygen isolation zone 413 is generated to the right of the sixth P+ injection 706.
[0047] Step 4: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;
[0048] Step 5: Connect the three electrodes of the second N+ injection 502 in the first P well 201, the third N+ injection 503 in the first N well 301 and the first P+ injection 701 together and use them as the anode of the device; connect the four electrodes of the first gate injection 601 in the first P well 201, the sixth N+ injection 506 in the second N well 302, the seventh N+ injection 507 and the sixth P+ injection 706 in the third P well 203 together and use them as the cathode of the device; connect the first N+ injection 501 in the first P well 201 and the second P+ injection 702 in the second P well 202 through a metal wire without connecting them to a potential; connect the five electrodes of the fourth N+ injection 504 and the third P+ injection 703 in the second P well 202, the fifth N+ injection 505 and the fourth P+ injection 704 in the second N well 502, and the fifth P+ injection 705 in the third P well 203 through a metal wire without connecting them to a potential.
[0049] The manufacturing method of a stackable unidirectional thyristor electrostatic protection device triggered by NMOS of the present invention is simple in process and easy to operate. The trigger structure selected by the present invention utilizes the characteristic that the parasitic NPN trigger voltage of the NMOS tube is lower than the avalanche breakdown voltage of N+ and PW to reduce the trigger voltage; and the stacking structure behind the trigger structure can control the maintenance voltage by controlling the number of stacking structures. Although the traditional stacking structure increases the maintenance voltage by stacking, the triggering voltage also increases exponentially, which is not suitable for I / O port protection under low operating voltage; the device proposed by the present invention adds a stacking device, the triggering voltage of the device is basically maintained unchanged, and the maintenance voltage can be increased, which can effectively avoid the latch effect and improve the protection performance of the device. This device can be used in the ESD protection design of I / O ports of 0 to 5.5V. The example device of the present invention adopts a 0.18μm CMOS process.
[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. An NMOS-triggered stackable unidirectional thyristor electrostatic protection device, characterized in that: including a P-type substrate; The P-type substrate is provided with a first P-well, a first N-well, a second P-well, a second N-well, and a third P-well in sequence from left to right; The first P well is provided with the first N+ injection, the first gate, and the second N+ injection from left to right in sequence; the first N well is provided with the third N+ injection and the first P+ injection from left to right in sequence; the second P well is provided with the second P+ injection, the fourth N+ injection, and the third P+ injection from left to right in sequence; the second N well is provided with the fifth N+ injection, the fourth P+ injection, and the sixth N+ injection from left to right in sequence; The third P well is provided with a fifth P+ injection, a seventh N+ injection, and a sixth P+ injection from left to right in sequence; The first gate is between the first N+ injection and the second N+ injection; The three electrodes of the second N+ injection in the first P well, the third N+ injection in the first N well and the first P+ injection are all connected together and serve as the anode of the device; The four electrodes of the first gate injection in the first P well, the sixth N+ injection in the second N well, the seventh N+ injection and the sixth P+ injection in the third P well are all connected together and serve as the cathode of the device; The first N+ injection in the first P well and the second P+ injection in the second P well are connected together through a metal wire without connecting potential; The five electrodes, the fourth N+ injection and the third P+ injection in the second P well, the fifth N+ injection and the fourth P+ injection in the second N well, and the fifth P+ injection in the third P well, are connected together by metal wires without being connected to any potential.
2. The NMOS-triggered stackable unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: There are thirteen field oxygen isolation regions; the first field oxygen isolation region is to the left of the first N+ injection, the second field oxygen isolation region is between the second N+ injection and the third N+ injection, the third field oxygen isolation region is between the third N+ injection and the first P+ injection, the fourth field oxygen isolation region is between the first P+ injection and the second P+ injection, the fifth field oxygen isolation region is between the second P+ injection and the fourth N+ injection, the sixth field oxygen isolation region is between the fourth N+ injection and the third P+ injection, the seventh field oxygen isolation region is between the third P+ injection and the fifth N+ injection, the eighth field oxygen isolation region is between the fifth N+ injection and the fourth P+ injection, the ninth field oxygen isolation region is between the fourth P+ injection and the sixth N+ injection, the tenth field oxygen isolation region is between the sixth N+ injection and the fifth P+ injection, the eleventh field oxygen isolation region is between the fifth P+ injection and the seventh N+ injection, the twelfth field oxygen isolation region is between the seventh N+ injection and the sixth P+ injection, and the thirteenth field oxygen isolation region is to the right of the sixth P+ injection.
3. The field oxygen isolation region according to claim 2, characterized in that: The first field oxygen isolation region is located on the surface of the first P well, the second field oxygen isolation region is connected across the surface at the junction of the first P well and the first N well, the third field oxygen isolation region is located on the surface of the first N well, the fourth field oxygen isolation region is connected across the surface at the junction of the first N well and the second P well, the fifth field oxygen isolation region is located on the surface of the second P well, the sixth field oxygen isolation region is located on the surface of the second P well, the seventh field oxygen isolation region is connected across the surface at the junction of the second P well and the second N well, the eighth field oxygen isolation region is located on the surface of the second N well, the ninth field oxygen isolation region is located on the surface of the second N well, the tenth field oxygen isolation region is connected across the surface at the junction of the third P well and the second N well, the eleventh field oxygen isolation region is located on the surface of the third P well, the twelfth field oxygen isolation region is located on the surface of the third P well, and the thirteenth field oxygen isolation region is located on the surface of the third P well.
4. The NMOS-triggered stackable unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The cathode of the device is connected to a low potential. When an ESD pulse reaches the anode of the device, the breakdown surface is between the first P well and the second N+ injection. The first N+ injection, the first gate, and the second N+ injection constitute an NMOS. The first P well and the first N+ injection, the first gate, and the second N+ injection in the first P well, the first N well and the third N+ injection and the first P+ injection in the first N well, the second P well and the second P+ injection, the fourth N+ injection, and the third P+ injection in the second P well, a total of three wells and eight electrodes together constitute the NMOS trigger structure of the device; The second N well and the fifth N+ injection, the fourth P+ injection, the sixth N+ injection in the second N well, the fifth P+ injection, the seventh N+ injection, the sixth P+ injection in the third P well and the fifth P well, a total of two wells and six injections together constitute the DTSCR stacking structure of the device; When avalanche breakdown occurs in the trigger structure, a trigger current is provided to the stack structure.
5. The NMOS-triggered stackable unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The cathode of the device is connected to a low potential. When an ESD pulse reaches the anode of the device, the first N+ injection, the first P well, and the second N+ injection constitute a parasitic transistor NPN1. The first P+ injection, the third N+ injection / first N well, the second P well / the second P+ injection / the third P+ injection constitute a parasitic transistor PNP1. The third N+ injection / first N well, the second P well / the second P+ injection / the third P+ injection, and the fourth N+ injection constitute a parasitic transistor NPN2. The parasitic transistors NPN1, PNP1, and NPN2 constitute an NMOS trigger structure. The fourth P+ injection, the fifth N+ injection / the sixth N+ injection / the second N well, the third P well / the fifth P+ injection / the third N+ injection / the fourth N+ injection constitute a parasitic transistor NPN2. The sixth P+ injection constitutes a parasitic transistor PNP2, the fifth N+ injection / sixth N+ injection / second N-well, third P-well / fifth P+ injection / sixth P+, seventh N+ injection constitutes a parasitic transistor NPN3, parasitic transistors PNP1 and NPN2 constitute a trigger structure SCR, parasitic transistors PNP2 and NPN3 constitute a stacked structure SCR; when the second N+ injection and the first P-well undergo avalanche breakdown, there is a current path from the second N+ injection / first P-well / first P-type substrate / third P-well / sixth P+ injection, when the voltage drop of RP4 reaches 0.7V, the parasitic transistor NPN1 of the NMOS is turned on, providing a trigger current to the device, At this time, the trigger main current path of the device changes from the original second N+ injection / first P well / first P-type substrate / third P well / sixth P+ to second N+ injection / first P well / first N+ injection / metal wire / second P+ injection / second P well / third P+ injection / metal wire / fifth N+ injection / second N well / sixth N+ injection; when the trigger current flows through RP2 and the voltage drop on RP2 reaches 0.7V, parasitic NPN2 turns on, the parasitic transistor NPN2 on the right turns on and provides base current to the parasitic transistor PNP1 on the left, thereby promoting its conduction. When the parasitic transistors PNP1 and NPN2 are turned on, a forward SCR path is formed to form a positive Feedback effect, at this time, the SCR of the trigger structure is turned on; the stacked structure is equivalent to a well resistor RN2 when the SCR is not turned on. The same as the SCR turning-on principle of the trigger structure, when the voltage drop on RP3 reaches 0.7V, the parasitic NPN3 is turned on, and the parasitic transistor NPN3 on the right is turned on and provides base current to the parasitic transistor PNP2 on the left to promote its conduction. When the parasitic transistor PNP2 and the parasitic transistor NPN3 are turned on, a forward SCR path is formed, forming a positive feedback effect, and the SCR of the stacked structure is turned on; when the SCR of the trigger structure and the stacked structure are both turned on, the device is fully turned on, and the maintenance voltage is equivalent to the clamping voltage of the two series SCRs.
6. The NMOS-triggered stackable unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The width S1 of the fourth field oxygen isolation region is adjustable. When S1 increases, the distance between the anode and cathode increases, and the sustaining voltage increases.
7. The NMOS-triggered stackable unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The number of stacking structures is adjustable. The number of stacking structures in the abstract figure is one. If the number of stacking structures is increased, the holding voltage of the device can be increased exponentially, further improving the anti-latch capability of the device.
8. A method for manufacturing an NMOS-triggered stackable unidirectional thyristor electrostatic protection device according to any one of claims 1 to 7, comprising the following steps: Step 1: Generate a first P well, a first N well, a second P well, a second N well, and a third P well from left to right on a P-type substrate; Step 2: Generate a first N+ injection, a first gate, and a second N+ injection from left to right on the first P well; generate a third N+ injection and a first P+ injection from left to right on the first N well; generate a second P+ injection, a fourth N+ injection, and a third P+ injection from left to right on the second P well; generate a fifth N+ injection, a fourth P+ injection, and a sixth N+ injection from left to right on the second N well; generate a fifth P+ injection, a seventh N+ injection, and a sixth P+ injection from left to right on the third P well; Step 3: generating a first field oxygen isolation region on the left side of the first N+ injection on the first P well, generating a second field oxygen isolation region between the second N+ injection and the third N+ injection, generating a third field oxygen isolation region between the third N+ injection and the first P+ injection, generating a fourth field oxygen isolation region between the first P+ injection and the second P+ injection, generating a fifth field oxygen isolation region between the second P+ injection and the fourth N+ injection, generating a sixth field oxygen isolation region between the fourth N+ injection and the third P+ injection, generating a seventh field oxygen isolation region between the third P+ injection and the fifth N+ injection, generating an eighth field oxygen isolation region between the fifth N+ injection and the fourth P+ injection, generating a ninth field oxygen isolation region between the fourth P+ injection and the sixth N+ injection, generating a tenth field oxygen isolation region between the sixth N+ injection and the fifth P+ injection, generating an eleventh field oxygen isolation region between the fifth P+ injection and the seventh N+ injection, generating a twelfth field oxygen isolation region between the seventh N+ injection and the sixth P+ injection, and generating a thirteenth field oxygen isolation region on the right side of the sixth P+ injection; Step 4: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas; Step 5: Connect the second N+ injection in the first P well, the third N+ injection in the first N well and the first P+ injection electrodes together to make the anode of the device; Connect the first gate injection in the first P well, the sixth N+ injection in the second N well, the seventh N+ injection and the sixth P+ injection in the third P well together to serve as the cathode of the device; Connecting the first N+ injection in the first P well and the second P+ injection in the second P well together through a metal wire without connecting the potential; The five electrodes of the fourth N+ injection and the third P+ injection in the second P well, the fifth N+ injection and the fourth P+ injection in the second N well, and the fifth P+ injection in the third P well are connected together through metal wires without connecting any potential.
9. The method for manufacturing a NMOS-triggered stackable unidirectional thyristor electrostatic protection device according to claim 8, characterized in that: The following steps are also included before step one: growing a layer of silicon dioxide film on a P-type substrate, and then depositing a layer of silicon nitride; spin coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and the isolation shallow groove to remove the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical polishing until the silicon nitride layer is formed to remove the nitride.