Nested one-way silicon controlled electrostatic protection device with MOSFET and manufacturing method of nested one-way silicon controlled electrostatic protection device
By introducing the third P+ injection and MOS structure into the traditional unidirectional silicon controlled electrostatic protection device, the breakdown surface is adjusted and an additional ESD current discharge path is formed, which solves the problem of the positive feedback mechanism of traditional devices under ESD pulses and achieves It has the characteristics of high maintaining voltage and high failure current, and enhances the protection capability of the device.
Patent Information
- Application Number
- CN202411503098.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-01-21
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Traditional unidirectional thyristor electrostatic protection devices are prone to positive feedback mechanisms under ESD pulses, resulting in an increase in on-resistance, a decrease in maintaining voltage, insufficient failure current, and difficult to achieve a high protection level.
By introducing the third P+ injection across the first N-well and the first P-well, the breakdown surface is adjusted, the trigger voltage of the device is reduced, and two MOS structures are introduced based on the traditional unidirectional thyristor. , forming an additional ESD current discharge path to suppress the positive feedback effect of the SCR path.
It effectively reduces the trigger voltage of the device, increases the holding voltage and failure current, enhances the robustness of the device, avoids the latch-up effect, and achieves a high protection level.
Smart Images
Figure CN119342902A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of electrostatic protection, and in particular to a nested unidirectional thyristor electrostatic protection device with MOSFET and a manufacturing method thereof. Background Art
[0002] With the advancement of semiconductor manufacturing technology, the failure of integrated circuit chips and electronic products caused by ESD has become more serious. ESD protection for electronic products and integrated circuit chips has become one of the main problems faced by product engineers. The ESD design window is an issue that product engineers need to focus on when designing ESD protection, including the trigger voltage V t1 , trigger current I t1 , Maintain voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 , on-resistance R on The trigger voltage of the ESD protection device must be lower than the maximum withstand voltage of the protected port of the core circuit, i.e., the drain-source breakdown voltage. Usually, the trigger voltage is 10% to 20% lower than the maximum withstand voltage. The maintenance voltage of the ESD protection device must be 1.1 to 1.2 times higher than the normal working voltage of the core circuit to protect the core circuit from latching up due to the ESD protection device always being turned on. The failure current I t2 It is one of the important parameters to measure the robustness of ESD protection devices. It indicates the maximum current that the ESD protection device can withstand. If the core circuit is to be effectively protected, the failure current I t2 When the ESD protection device is on, the clamping voltage must be less than the maximum withstand voltage of the protected port; the on-resistance R on It is the resistance characteristic of the device after entering the holding point, which is related to the holding voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 According to Ohm's law, the on-resistance R on Expressed as failure voltage V t2 , Maintain voltage V h Difference and fault current I t2 , Maintaining current I h The ratio of the difference; the human body model HBM regards the equivalent resistance of the human body as 1.5kΩ, and the HBM protection level is 1500 times I t2 .
[0003] The failure modes caused by ESD include hard failure, soft failure, and potential failure. The causes of these failures can be divided into electrical failure and thermal failure. Thermal failure refers to the current of several amperes to tens of amperes generated locally on the chip when the ESD pulse comes. It lasts for a short time but generates a lot of heat, causing the local metal connection to melt or causing hot spots on the chip, resulting in secondary breakdown. Electrical failure refers to the electric field strength formed by the voltage applied to the gate oxide layer being greater than the dielectric strength, causing surface breakdown or dielectric breakdown. As the threat posed by ESD to chips becomes more and more serious, research on its physical mechanism is receiving more and more attention.
[0004] Compared with other ESD devices, traditional unidirectional thyristor devices have a dual conductance modulation mechanism, high discharge efficiency per unit area, small unit parasitic capacitance, and the best robustness.
[0005] The cross-section diagram of the traditional unidirectional thyristor electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of the unidirectional SCR, the first N-well and the first P-well form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current will be generated inside the device. The current flows through the first P-well and flows to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the first P-well is equivalent to the base voltage drop of the transistor NPN. When this voltage is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After this transistor is turned on, it provides base current for the horizontal PNP transistor. After the horizontal PNP transistor is also turned on, it further provides base current for the vertical NPN transistor, forming a positive feedback mechanism to fully open the SCR path. Therefore, even if there is no avalanche current afterwards, the large current can be discharged due to the conduction of the transistor. Summary of the invention
[0006] In order to solve the above technical problems, the present invention provides a nested unidirectional thyristor electrostatic protection device with MOSFET and a manufacturing method thereof, and is applied to the design of an ESD protection network with an operating voltage of 0 to 5.5V.
[0007] The technical solution of the present invention to solve the above problems is:
[0008] In a first aspect, an embodiment of the present invention provides a nested unidirectional thyristor electrostatic protection device with MOSFET, including a P-type substrate; an N-type deep well is provided in the P-type substrate; a first N+ injection, a first P+ injection, a second P+ injection and a first gate are provided on the first N-well; a third P+ injection is provided between the first N-well and the first P-well; a second N+ injection, a second gate, a third N+ injection and a fourth P+ injection are provided in the first P-well; a fourth N+ injection is provided in the second N-well; the first gate is between the second P+ injection and the third P+ injection, and the second gate is between the second N+ injection and the third N+ injection;
[0009] The five electrodes of the first N+ injection, the first P+ injection, the second P+ injection, the first gate and the fourth N+ injection in the second N-well are connected together and serve as the anode of the device; the second gate, the third N+ injection and the fourth P+ injection in the first P-well are connected together and serve as the cathode of the device.
[0010] Preferably, there are five field oxygen isolation regions; the first field oxygen isolation region is between the first N+ injection and the first P+ injection region, the second field oxygen isolation region is between the first P+ injection and the second P+ injection, the third field oxygen is between the third P+ injection and the second N+ injection, the fourth field oxygen is between the third N+ injection and the fourth P+ injection, and the fifth field oxygen is between the fourth P+ injection and the fourth N+ injection.
[0011] Preferably, the first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region and the fourth field oxygen isolation region are located on the surface of the first P-well; and the fifth field oxygen isolation region is located on the surface between the first P-well and the second N-well.
[0012] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well and the third P+ injection; at this time, the first N+ injection, the first P+ injection, the first N well, the third P+ injection, the first P well, the third N+ injection, the fourth P+ injection and the first N+ injection, the second P+ injection, the first N well, the third P+ injection, the first P well, the third N+ injection, and the fourth P+ injection form a path for dissipating the ESD current.
[0013] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well and the third P+ injection; at this time, the first N+ injection, the first P+ injection, the first N well, the third P+ injection, the first P well, the third N+ injection, the fourth P+ injection and the first N+ injection, the second P+ injection, the first N well, the third P+ injection, the first P well, the third N+ injection, and the fourth P+ injection form a path for dissipating the ESD current.
[0014] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the third P+ injection / first N-well junction is broken down, the ESD current in the first N-well will converge to the first N+ injection region because the floating N+ region is heavily doped.
[0015] Preferably, the width S1 of the third P+ implant is adjustable, and when S1 increases, the sustain voltage increases.
[0016] In a second aspect, an embodiment of the present invention provides a method for manufacturing a nested unidirectional thyristor electrostatic protection device with a MOSFET, comprising the following steps:
[0017] Step 1: forming an N-type deep well in a P-type substrate;
[0018] Step 2: generating a first N-well, a first P-well and a second N-well in the first N-type deep well;
[0019] Step 3: Generate a first N+ injection, a first P+ injection, a second P+ injection and a first gate from left to right on the first N well; generate a third P+ injection between the first N well and the first P well; generate a second N+ injection, a second gate, a third N+ injection and a fourth P+ injection from left to right in the first P well; generate a fourth N+ injection in the second N well;
[0020] Step 4: forming a first field oxygen isolation region between the first N+ implantation and the first P+ implantation on the first N well, generating a second field oxygen between the first P+ implantation and the second P+ implantation on the first N well, generating a third field oxygen between the third P+ implantation between the first N well and the first P well and the second N+ implantation on the first P well, generating a fourth field oxygen between the third N+ implantation and the fourth P+ implantation on the first P well, and generating a fifth field oxygen between the fourth P+ implantation on the first P well and the fourth N+ implantation on the second N well;
[0021] Step 5: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas;
[0022] Step six: Connect the first N+ injection, the first P+ injection, the second P+ injection, the first gate and the fourth N+ injection together as the anode of the device, and connect the second gate, the third N+ injection and the fourth P+ injection together as the cathode of the device.
[0023] Preferably, before forming the N-type deep well in the P-type substrate, the method further comprises:
[0024] A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is reached to remove the silicon nitride layer.
[0025] The beneficial effects of the present invention are:
[0026] 1. The present invention adjusts the breakdown surface and, based on the traditional unidirectional thyristor electrostatic protection device, introduces a third P+ injection bridged between the first N-well and the first P-well, thereby changing the breakdown surface from the well breakdown of the first N-well and the first P-well to the junction breakdown of the first N-well and the third P+ injection, thereby effectively reducing the trigger voltage of the device and making the device easier to turn on.
[0027] 2. In order to better exert the performance of the unidirectional thyristor, the present invention introduces two MOS structures. The first N+ injection, the second P+ injection, the third P+ injection and the first gate in the first N well constitute a PMOS tube, and the second gate, the third N+ injection and the fourth P+ injection in the first P well constitute an NMOS tube. The P+ region is embedded between the N+ in the N well and the drain P+ region of the PMOS and connected to the anode. On the basis of the traditional low-trigger unidirectional thyristor electrostatic protection device, an additional ESD current discharge path is provided, which can effectively suppress the positive feedback effect of the SCR discharge path. The thyristor rectifier electrostatic release device of the present invention has the characteristics of high holding voltage and high failure current, and can achieve a high protection level while effectively avoiding the latch effect.
[0028] 3. The width S1 of the third P+ implantation in the present invention is adjustable. When S1 increases, the sustaining voltage increases. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.
[0030] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.
[0031] Figure 3 It is a cross-sectional view of an embodiment of the present invention.
[0032] Figure 4 2 is an equivalent circuit diagram of an embodiment of the present invention.
[0033] Figure 5 A total current density distribution simulation diagram of a nested unidirectional thyristor electrostatic protection device with MOSFET provided in one embodiment of the present invention. DETAILED DESCRIPTION
[0034] The ESD protection design of the analog switch chip applied to the present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0035] like Figure 3 As shown, a nested unidirectional thyristor electrostatic protection device with MOSFET includes a P-type substrate 101; an N-type deep well 301 is provided in the substrate; a first N-well 401, a first P-well 402 and a second N-well 403 are provided on the N-type deep well; a first N+ injection 501, a first P+ injection 502, a second P+ injection 503 and a first gate 701 are provided on the first N-well 401 from left to right; a third P+ injection 504 is provided between the first N-well and the first P-well and bridged between the two wells; a second N+ injection 505, a second gate 702, a third N+ injection 506 and a fourth P+ injection 507 are provided in the first P-well from left to right; a fourth N+ injection 508 is generated in the second N-well 403; the first gate 701 is provided in the first between the second P+ injection 503 and the third P+ injection 504, and the second gate 702 is between the second N+ injection 505 and the third N+ injection 506; the five electrodes of the first N+ injection 501, the first P+ injection 502, the second P+ injection 503, the first gate 701 and the fourth N+ injection 508 in the second N well 403 in the first N well 401 are connected together and used as the anode of the device, and the second gate 702, the third N+ injection 506 and the fourth P+ injection 507 in the first P well 402 are connected together and used as the cathode of the device; in this way, an additional ESD current discharge path is provided on the basis of the traditional low-trigger unidirectional thyristor electrostatic protection device, which can effectively suppress the positive feedback effect of the SCR discharge path, thereby improving the holding voltage.
[0036] In one embodiment, the nested unidirectional thyristor electrostatic protection device with MOSFET has five field oxygen isolation regions; there are five field oxygen isolation regions; the first field oxygen isolation region 601 is between the first N+ injection 501 and the first P+ injection region 502, the second field oxygen isolation region 602 is between the first P+ injection 502 and the second P+ injection 503, the third field oxygen 603 is between the third P+ injection 504 and the second N+ injection 505, the fourth field oxygen 604 is between the third N+ injection 506 and the fourth P+ injection 507, and the fifth field oxygen is between the fourth P+ injection 508 and the fourth N+ injection 509.
[0037] In one embodiment, the first field oxygen isolation region 601 and the second field oxygen isolation region 602 are located on the surface of the first N-well 401; the third field oxygen isolation region 603 and the fourth field oxygen isolation region 604 are located on the surface of the first P-well 402; and the fifth field oxygen isolation region 605 is located on the surface between the first N-well 401 and the first P-well 402.
[0038] In one embodiment, if Figures 4 to 5 As shown, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well 401 and the third P+ injection 504; at this time, the first N+ injection 501, the first P+ injection 502, the first N well 401, the third P+ injection 504, the first P well 402, the third N+ injection 506, the fourth P+ injection 507 and the first N+ injection 501, the second P+ injection 503, the first N well 401, the third P+ injection 503, the first P well 402, the third N+ injection 506, and the fourth P+ injection 503 form a path for discharging ESD current.
[0039] When the ESD pulse reaches the anode of the device and the cathode of the device is grounded, the first P+ injection 502, the first N-well 401 / the first deep N-well 301, the first P-well 402 and the second P+ injection 502, the first N-well 401 and the first P-well 402 constitute two parallel longitudinal parasitic transistors PNP, and the first N-well 401 / the first deep N-well 301, the first P-well 402 and the third N+ injection 506 constitute a lateral parasitic transistor NPN. When the voltage drop thereof reaches 0.7V, the right lateral parasitic transistor NPN is turned on and provides base current to the two parallel longitudinal parasitic transistors PNP on the left, thereby promoting their conduction. When the longitudinal parasitic transistor PNP and the lateral parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well 401 and the third P+ injection 504.
[0040] When the ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the third P+ injection 504 / first N well 401 junction is broken down, because the first N+ injection region 501 is heavily doped, the ESD current in the first N well 401 will converge to the first N+ injection region 501; in addition, when the ESD pulse reaches the anode of the device, the first N+ injection region 501 / first N well 401 / N-type deep well 301 / second N well 403 / fourth N+ injection region 508 forms a reverse-biased PN junction with the P-type substrate 101, which helps to reduce device leakage.
[0041] The device can be adjusted by controlling the width S1 of the third P+ implant according to the requirements of the ESD design window in different application scenarios. When S1 increases, the sustaining voltage increases.
[0042] The embodiment of the present invention also provides a method for manufacturing a nested unidirectional thyristor electrostatic protection device with MOSFET, comprising the following steps:
[0043] Step 1: forming an N-type deep well 301 in the P-type substrate 101;
[0044] Step 2: Generating a first N-well 401, a first P-well 402 and a second N-well 402 in the first N-type deep well 301;
[0045] Step 3: Generate a first N+ injection 501, a first P+ injection 502, a second P+ injection 503 and a first gate 701 from left to right on the first N well 401; generate a third P+ injection 504 between the first N well 401 and the first P well 402; generate a second N+ injection 505, a second gate 702, a third N+ injection 504 and a fourth P+ injection 507 from left to right in the first P well 402; generate a fourth N+ injection 508 in the second N well 402;
[0046] Step 4: forming a first field oxygen isolation region 601 between the first N+ implant 501 and the first P+ implant 502 on the first N well 401, generating a second field oxygen 602 between the first P+ implant 502 and the second P+ implant 503 on the first N well 401, generating a third field oxygen 603 between the third P+ implant 504 on the first N well 401 and the second N+ implant 505 on the first P well 402, generating a fourth field oxygen 604 between the third N+ implant 506 and the fourth P+ implant 507 on the first P well 402, and generating a fifth field oxygen 605 between the fourth P+ implant 507 on the first P well 402 and the fourth N+ implant 508 on the second N well 403;
[0047] Step 5: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas;
[0048] Step 6: Connect the first N+ injection 501, the first P+ injection 502, the second P+ injection 503, the first gate 701 and the fourth N+ injection 508 together as the anode of the device, and connect the second gate 702, the third N+ injection, and the fourth P+ injection 507 together as the cathode of the device;
[0049] The manufacturing method of the nested unidirectional thyristor electrostatic protection device with MOSFET of the present invention is simple in process and easy to operate. In order to better exert the performance of the unidirectional thyristor, the present invention adds an ESD current discharge path on the basis of the traditional low-trigger unidirectional thyristor electrostatic protection device, which can effectively suppress the positive feedback effect of the SCR discharge path. The thyristor rectifier electrostatic release device of the present invention has the characteristics of high holding voltage and high failure current, which can achieve a high protection level while effectively avoiding the latch effect. This device can be used in the ESD protection design of I / O ports of 0 to 5.5V. The example device of the present invention adopts a 0.25μm BCDMOS process.
[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A nested unidirectional thyristor electrostatic protection device with MOSFET, characterized in that: including a P-type substrate; An N-type deep well is provided in the substrate; The N-type deep well is provided with a first N-well and a first P-well; The N-type deep well is provided with a first N-well, a first P-well and a second N-well from left to right in sequence; the first N-well is provided with a first N+ injection, a first P+ injection, a second P+ injection and a first gate from left to right in sequence; and a third P+ injection is provided between the first N-well and the first P-well; The first P well is provided with a second N+ injection, a second gate, a third N+ injection and a fourth P+ injection from left to right; the second N well is provided with a fourth N+ injection; The first gate is between the second P+ injection and the third P+ injection, and the second gate is between the second N+ injection and the third N+ injection; The four electrodes of the first N+ injection, the first P+ injection, the second P+ injection, and the first gate in the first N well and the fourth N+ injection in the second N well are connected together and serve as the anode of the device; the three electrodes of the second gate, the third N+ injection and the fourth P+ injection in the first P well are connected together and serve as the cathode of the device.
2. The nested unidirectional thyristor electrostatic protection device with MOSFET according to claim 1, characterized in that: There are five field oxygen isolation regions; the first field oxygen isolation region is between the first N+ injection and the first P+ injection region, the second field oxygen isolation region is between the first P+ injection and the second P+ injection, the third field oxygen is between the third P+ injection and the second N+ injection, the fourth field oxygen is between the third N+ injection and the fourth P+ injection, and the fifth field oxygen is between the fourth P+ injection and the fourth N+ injection.
3. The field oxygen isolation region according to claim 2, characterized in that: The first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the second field oxygen isolation region and the third field oxygen isolation region are located on the surface of the first P-well; and the fifth field oxygen isolation region is located on the surface between the first P-well and the N-well.
4. The nested unidirectional thyristor electrostatic protection device with MOSFET according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N-well and the third P+ injection; at this time, the first N+ injection, the first P+ injection, the first N-well, the third P+ injection, the first P-well, the third N+ injection, the fourth P+ injection and the first N+ injection, the second P+ injection, the first N-well, the third P+ injection, the first P-well, the third N+ injection, and the fourth P+ injection form a path for dissipating the ESD current.
5. The nested unidirectional thyristor electrostatic protection device with MOSFET according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N well and the first P well and the second P+ injection, the first N well and the first P well constitute two parasitic transistors PNP, and the first N well, the first P well and the third N+ injection constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left to promote its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N well and the third P+ injection.
6. The nested unidirectional thyristor electrostatic protection device with MOSFET according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the third P+ injection / first N-well junction is broken down, the ESD current in the first N-well will converge to the first N+ injection region because the floating N+ region is heavily doped.
7. The nested unidirectional thyristor electrostatic protection device with MOSFET according to claim 1, characterized in that: The width S1 of the third P+ implant is adjustable, and when S1 increases, the sustain voltage increases.
8. A method for manufacturing a nested unidirectional thyristor electrostatic protection device with MOSFET according to any one of claim 1, comprising the following steps: Step 1: forming an N-type deep well in a P-type substrate; Step 2: generating a first N-well, a first P-well and a second N-well in the N-type deep well; Step 3: Generate a first N+ injection, a first P+ injection, a second P+ injection and a first gate on the first N well from left to right; generating a third P+ implant between the first N-well and the first P-well; A second N+ injection, a second gate, a third N+ injection, and a fourth P+ injection are sequentially generated in the first P well from left to right; generating a fourth N+ implant in the second N well; Step 4: forming a first field oxygen isolation region between the first N+ implantation and the first P+ implantation on the first N well, generating a second field oxygen between the first P+ implantation and the second P+ implantation on the first N well, generating a third field oxygen between the third P+ implantation between the first N well and the first P well and the second N+ implantation on the first P well, generating a fourth field oxygen between the third N+ implantation and the fourth P+ implantation on the first P well, and generating a fifth field oxygen between the fourth P+ implantation on the first P well and the fourth N+ implantation on the second N well; Step 5: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas; Step six: Connect the first N+ injection, the first P+ injection, the second P+ injection, the first gate and the fourth N+ injection together as the anode of the device, and connect the second gate, the third N+ injection and the fourth P+ injection together as the cathode of the device.
9. The method for manufacturing a nested unidirectional thyristor electrostatic protection device with MOSFET according to claim, characterized in that: The following steps are also included before step one: growing a layer of silicon dioxide film on a P-type substrate, and then depositing a layer of silicon nitride; spin coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and the isolation shallow groove to remove the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical polishing until the silicon nitride layer is formed to remove the silicon nitride layer.