One-way silicon controlled electrostatic protection device with NMOS shunt and manufacturing method of one-way silicon controlled electrostatic protection device
By introducing NMOS diversion and GDPMOS structures in one -way silicon static protective devices, regulating the breakdown surface and suppressing positive feedback effects, solving the problem of damaging the traditional device under the ESD pulse, and achieving higher maintenance voltage and failure The current enhances the ESD protection capacity of the device.
Patent Information
- Application Number
- CN202411503193.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-01-21
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Traditional unidirectional thyristor electrostatic protection devices are prone to thermal failure and electrical failure under ESD pulses, leading to chip damage, and maintaining voltage and failure current is difficult to meet the high requirements of ESD protection design.
Design a one -way silicon static protective device with NMOS diversion. By introducing the third P+injection area between the first N trap and the first P+, the cutting surface is adjusted, and the breakdown surface is introduced, and GDPMOS is introduced in the device With the NMOS structure, the surface path deletes current and parasitic PNP diversion, and the positive feedback effect of the SCR path inhibits the SCR path.
It effectively reduces the trigger voltage of the device, increases the holding voltage and failure current, enhances the robustness and ESD protection capabilities of the device, and reduces the occurrence of latch-up effects.
Smart Images
Figure CN119342904A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of electrostatic protection, and in particular to a unidirectional thyristor electrostatic protection device with NMOS shunt and a manufacturing method thereof. Background Art
[0002] With the advancement of semiconductor manufacturing technology, the failure of integrated circuit chips and electronic products caused by ESD has become more serious. ESD protection for electronic products and integrated circuit chips has become one of the main problems faced by product engineers. The ESD design window is an issue that product engineers need to focus on when designing ESD protection, including the trigger voltage V t1 , trigger current I t1 , Maintain voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 , on-resistance R on The trigger voltage of the ESD protection device must be lower than the maximum withstand voltage of the protected port of the core circuit, i.e., the drain-source breakdown voltage. Usually, the trigger voltage is 10% to 20% lower than the maximum withstand voltage. The maintenance voltage of the ESD protection device must be 1.1 to 1.2 times higher than the normal working voltage of the core circuit to protect the core circuit from latching up due to the ESD protection device always being turned on. The failure current I t2 It is one of the important parameters to measure the robustness of ESD protection devices. It indicates the maximum current that the ESD protection device can withstand. If the core circuit is to be effectively protected, the failure current I t2 When the ESD protection device is on, the clamping voltage must be less than the maximum withstand voltage of the protected port; the on-resistance R on It is the resistance characteristic of the device after entering the holding point, which is related to the holding voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 According to Ohm's law, the on-resistance R on Expressed as failure voltage V t2 , Maintaining voltage V h Difference and fault current I t2 , Maintaining current I h The ratio of the difference; the human body model HBM regards the equivalent resistance of the human body as 1.5kΩ, and the HBM protection level is 1500 times I t2 .
[0003] The failure modes caused by ESD include hard failure, soft failure, and potential failure. The causes of these failures can be divided into electrical failure and thermal failure. Thermal failure refers to the current of several amperes to tens of amperes generated locally on the chip when the ESD pulse comes. It lasts for a short time but generates a lot of heat, causing the local metal connection to melt or causing hot spots on the chip, resulting in secondary breakdown. Electrical failure refers to the electric field strength formed by the voltage applied to the gate oxide layer being greater than the dielectric strength, causing surface breakdown or dielectric breakdown. As the threat posed by ESD to chips becomes more and more serious, research on its physical mechanism is receiving more and more attention.
[0004] Compared with other ESD devices, traditional unidirectional thyristor devices have a dual conductance modulation mechanism, high discharge efficiency per unit area, small unit parasitic capacitance, and the best robustness.
[0005] The cross-section diagram of the traditional unidirectional thyristor electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of the unidirectional SCR, the first N-well and the first P-well form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current will be generated inside the device. The current flows through the first P-well and flows to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the first P-well is equivalent to the base voltage drop of the transistor NPN. When this voltage is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After this transistor is turned on, it provides base current for the horizontal PNP transistor. After the horizontal PNP transistor is also turned on, it further provides base current for the vertical NPN transistor, forming a positive feedback mechanism to fully open the SCR path. Therefore, even if there is no avalanche current afterwards, the large current can be discharged due to the conduction of the transistor. Summary of the invention
[0006] In order to solve the above technical problems, the present invention provides a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS and a manufacturing method thereof, and is applied to the design of an ESD protection network with an operating voltage of 0 to 5.5V.
[0007] The technical solution of the present invention to solve the above problems is:
[0008] In a first aspect, an embodiment of the present invention provides a unidirectional thyristor electrostatic protection device with NMOS shunt, including a P-type substrate; a first N-well and a first P-well, a second N-well and a second P-well are provided in the P-type substrate; a first N+ injection, a first P+ injection, a first gate, and a second P+ injection are generated on the first N-well from left to right; a third P+ injection area spanning the two wells is generated between the first N-well and the first P-well; a second N+ injection, a second gate, and a third N+ injection area spanning the two wells are generated on the first P-well from left to right; a fourth P+ injection and a fourth N+ injection are generated on the second N-well from left to right; a fifth P+ injection is generated on the second P-well from left to right;
[0009] The first N+ injection, the first P+ injection, and the first gate are connected together and serve as the anode of the device, the second P+ injection, the third P+ injection, the second N+ injection, and the second gate are connected together without connecting a potential, the third N+ injection, the fourth P+ injection, the fourth N+ injection, and the fifth P+ injection are connected together and serve as the cathode of the device.
[0010] Preferably, there are eight field oxygen isolation regions; the first field oxygen isolation region is to the left of the first N+ injection, the second field oxygen isolation region is between the first N+ injection and the first P+ injection, the third field oxygen is between the second P+ injection and the third P+ injection, the fourth field oxygen is between the third P+ injection and the second N+ injection, the fifth field oxygen is between the third N+ injection and the fourth P+ injection, the sixth field oxygen is between the fourth P+ injection and the fourth N+ injection, the seventh field oxygen is between the fourth N+ injection and the fifth P+ injection, and the eighth field oxygen is to the right of the fifth P+ injection.
[0011] Preferably, the first field oxygen isolation region, the second field oxygen isolation region, and the third field oxygen isolation region are located on the surface of the first N-well; the fourth field oxygen isolation region is located on the surface of the first P-well; the fifth field oxygen isolation region and the sixth field oxygen isolation region are located on the surface of the second N-well; the seventh field oxygen isolation region is located at the junction of the first P-well surface and the second N-well surface; and the eighth field oxygen isolation region is located on the surface of the second P-well.
[0012] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well and the third P+ injection; at this time, the GDPMOS composed of the first P+ injection, the first gate, and the second P+ injection, and the NMOS surface path composed of the second N+ injection, the second gate and the third N+ injection.
[0013] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well and the first P-well constitute a parasitic transistor PNP, and the first N-well, the first P-well and the third N+ injection constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left to promote its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well and the third P+ injection.
[0014] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the third P+ injection / first N-well junction is broken down, the ESD current in the first N-well will enter the first P-well through the third P+ injection region and flow out from the third N+ injection region. On the one hand, the second N-well, the first P-well and the fourth P+ injection region form a parasitic PNP to shunt the SCR path. On the other hand, the GDPMOS formed by the first P+ injection, the first gate and the second P+ injection, and the NMOS formed by the second N+ injection, the second gate and the third N+ injection constitute a surface path discharge current. For the entire SCR path, the device is easier to turn on due to the current discharge of the surface path and the parasitic PNP shunt.
[0015] Preferably, the width of the third P+ implant is adjustable, and when the width increases, the trigger voltage decreases and the sustain voltage increases.
[0016] Preferably, the width of the second gate is adjustable, which represents the channel width of the NMOS. Increasing its width can effectively suppress the current saturation effect, while improving the current discharge capability of the NMOS, thereby further increasing the failure current and reducing the on-resistance. As the width of the second gate increases, the NMOS shunt capability and the base width of the parasitic NPN transistor increase, reducing the current gain coefficient β, thereby increasing the holding voltage.
[0017] In a second aspect, an embodiment of the present invention provides a method for manufacturing a unidirectional thyristor electrostatic protection device with NMOS shunt, comprising the following steps:
[0018] Step 1: generating a first N-well and a first P-well, a second N-well and a second P-well in a P-type substrate;
[0019] Step 2: Generate a first N+ injection, a first P+ injection, a first gate, and a second P+ injection on the first N well from left to right; generate a third P+ injection area between the first N well and the first P well to bridge the two wells; generate a second N+ injection, a second gate, and a third N+ injection area between the first P well and the second N well to bridge the two wells on the first P well from left to right; generate a fourth P+ injection and a fourth N+ injection on the second N well from left to right; generate a fifth P+ injection on the second P well from left to right;
[0020] Step 3: forming a first field oxygen isolation region on the right side of the first N+ implantation on the first N well, generating a second field oxygen between the first N+ implantation and the first P+ implantation on the first N well, generating a third field oxygen between the second P+ implantation and the third P+ implantation on the first N well, generating a fourth field oxygen between the third P+ implantation and the second N+ implantation on the first P well, generating a fifth field oxygen between the third N+ implantation and the fourth P+ implantation on the second N well, generating a sixth field oxygen between the fourth P+ implantation and the fourth N+ implantation on the second N well, generating a seventh field oxygen between the fifth P+ implantation and the fourth N+ implantation on the second P well, and generating an eighth field oxygen on the right side of the fifth P+ implantation on the second P well;
[0021] Step 4: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas;
[0022] Step 5: Connect the first N+ injection, the first P+ injection, and the first gate together and use them as the anode of the device, connect the second P+ injection, the third P+ injection, the second N+ injection, and the second gate together without connecting any potential, connect the third N+ injection, the fourth P+ injection, the fourth N+ injection, and the fifth P+ injection together and use them as the cathode of the device.
[0023] Preferably, before performing step 1, the method further comprises:
[0024] A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is reached to remove the silicon nitride layer.
[0025] The beneficial effects of the present invention are:
[0026] 1. The present invention adjusts the breakdown surface and, based on the traditional unidirectional thyristor electrostatic protection device, introduces a third P+ injection bridged between the first N-well and the first P-well, thereby changing the breakdown surface from the well breakdown of the first N-well and the first P-well to the junction breakdown of the first N-well and the third P+ injection, thereby effectively reducing the trigger voltage of the device and making the device easier to turn on.
[0027] 2. In order to better exert the performance of the unidirectional thyristor, the present invention introduces a GDPMOS structure and an NMOS structure. The first P+ injection, the first gate, and the second P+ injection in the first N well constitute a GDPMOS. The second N+ injection, the second gate, and the third N+ injection in the first P well together constitute an NMOS. The GDPMOS and the NMOS constitute a surface path discharge current. When the ESD current enters the first P well through the third P+ injection region connected across, it flows out from the third N+ injection region. On the one hand, the potential of the second N+ injection region is increased to accelerate the opening of the surface NMOS. On the other hand, the second N well, the first P well, and the fourth P+ injection region are connected to the first P well. The parasitic PNP formed by the injection area shunts the SCR path, which helps to increase the holding voltage of the device; the first P+ injection, the first gate, and the second P+ injection in the first N well constitute GDPMOS. When the GDPMOS is turned on, a part of the current will return to the cathode through the GDPMOS, the metal wire between the third P+ injection and the second N+ injection, the second N+ injection, the second gate, the NMOS formed by the third N+ injection, the first P well, and the third N+ injection, forming a GDPMOS-NMOS path. The formation of this path will weaken the positive feedback effect of the SCR path, thereby suppressing the latch effect, and thus can increase the holding voltage of the device.
[0028] 3. The width of the third P+ implantation described in the present invention is adjustable. When the width increases, the trigger voltage decreases and the sustaining voltage increases.
[0029] 4. The width of the second gate of the present invention is adjustable, which represents the channel width of NMOS. Increasing its width can effectively suppress the current saturation effect and improve the current discharge capability of NMOS, thereby further increasing the failure current and reducing the on-resistance. As the width of the second gate increases, the shunt capability of NMOS and the base width of the parasitic NPN transistor increase, reducing the current gain coefficient β, thereby increasing the holding voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.
[0031] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.
[0032] Figure 3 It is a cross-sectional view of an embodiment of the present invention.
[0033] Figure 4 2 is an equivalent circuit diagram of an embodiment of the present invention.
[0034] Figure 5 A total current density distribution simulation diagram of a unidirectional thyristor electrostatic protection device with NMOS shunt provided in one embodiment of the present invention. DETAILED DESCRIPTION
[0035] The ESD protection design of the analog switch chip applied to the present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0036] like Figure 3 As shown, a unidirectional thyristor electrostatic protection device with NMOS shunt includes a P-type substrate 101; a first N well 201, a first P well 203, a second N well 202, and a second P well 204 are provided in the substrate; a first N+ injection 301, a first P+ injection 302, a first gate 501, and a second P+ injection 303 are provided on the first N well 201 from left to right; a third P+ injection 304 is provided between the first N well 201 and the first P well 203 and connected across the two wells; A third N+ injection 306 is provided between the P well 203 and the second N well 202, which is connected across the two wells; a fourth P+ injection 307 and a fourth N+ injection 308 are provided on the second N well 202 from left to right; a fifth P+ injection 307 is provided on the second P well 204 from left to right; the first gate 501 is between the first P+ injection 302 and the second P+ injection 303, and the second gate 502 is between the second N+ injection 305 and the third N+ injection 306; the first N well 201 The four electrodes of the first N+ injection 301, the first P+ injection 302, the first gate 501, and the second N+ injection 303 are all connected together and serve as the anode of the device; the third N+ injection 306 bridged between the first P well 203 and the second N well 202 and the fourth P+ injection 307, the fourth N+ injection 308, and the fifth P+ injection 307 on the second P well 204 are connected together and serve as the cathode of the device; the second P+ injection 303 in the first N well 201 and the third P+ injection 304 bridged between the first N well 201 and the first P well 203 and the second N+ injection 305 in the first P well 203 and the second gate 502 are connected together through metal wires without connecting potential; in this way, after the SCR path is turned on, a GDPMOS-NMOS path will appear on the surface of the device, and part of the current of the SCR path will be discharged through this path, which will suppress the positive feedback effect in the original SCR path, thereby increasing the holding voltage.
[0037] In one embodiment, the unidirectional thyristor electrostatic protection device with NMOS shunt has eight field oxygen isolation regions; the first field oxygen isolation region is on the right side of the first N+ injection 301 on the first N well 201, the second field oxygen isolation region is between the first N+ injection 301 and the first P+ injection 302 on the first N well 201, the third field oxygen isolation region is between the second P+ injection 303 and the third P+ injection 304 on the first N well 201, and the fourth field oxygen isolation region is on the third P+ injection 304 on the first P well 203. 04 and the second N+ injection 305, the fifth field oxygen isolation zone is between the third N+ injection 306 and the fourth P+ injection 307 on the second N well 202, the sixth field oxygen isolation zone is between the fourth P+ injection 307 and the fourth N+ injection 308 on the second N well 202, the seventh field oxygen isolation zone is between the fourth N+ injection 308 on the second N well 202 and the fifth P+ injection 309 on the second P well 204, and the eighth field oxygen isolation zone is to the right of the fifth P+ injection 309 on the second P well 204.
[0038] In one embodiment, the first field oxygen isolation region, the second field oxygen isolation region, and the third field oxygen isolation region are located on the surface of the first N-well 201; the fourth field oxygen isolation region is located on the surface of the first P-well 203; the fifth field oxygen isolation region and the sixth field oxygen isolation region are located on the surface of the second N-well 202; the seventh field oxygen isolation region is located at the junction of the first P-well 203 surface and the second N-well 202 surface; and the eighth field oxygen isolation region is located on the surface of the second P-well 204.
[0039] In one embodiment, if Figures 4 to 5 As shown, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well 201 and the third P+ injection 304; at this time, the first P+ injection 302, the first gate 501, and the second P+ 303 injection constitute a GDPMOS, and the second N+ injection 305, the second gate 502 and the third N+ injection 306 constitute an NMOS. When the GDPMOS is turned on, it will form a GDPMOS-NMOS path with the NMOS. On the one hand, the conduction of the GDPMOS can increase the surface discharge current, and on the other hand, the conduction of the GDPMOS can speed up the speed at which the current flows to the first P well 203, thereby increasing the failure current.
[0040] When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection 302, the first N-well 201 and the first P-well 203 constitute a parasitic transistor PNP, and the first N-well 201, the first P-well 203 and the third N+ 306 injection constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well 201 and the third P+ injection 304.
[0041] When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the third P+ injection 304 / first N-well 201 junction is broken down, the ESD current in the first N-well 201 will enter the first P-well 203 through the third P+ injection region 304 and flow out from the third N+ injection region 306. On the one hand, the second N-well 202, the first P-well 203 and the fourth P+ injection region 307 form a parasitic PNP to shunt the SCR path. On the other hand, the GDPMOS formed by the first P+ injection 302, the first gate 501 and the second P+ injection 303, and the NMOS formed by the second N+ injection 305, the second gate 502 and the third N+ injection 306 constitute a surface path discharge current. For the entire SCR path, the device is easier to turn on due to the current discharge of the surface path and the parasitic PNP shunt.
[0042] This device can be designed according to the requirements of the ESD window in different application scenarios by controlling the width of the third P+ injection 304. When the width increases, the trigger voltage decreases and the holding voltage increases. The width of the second gate 502 is adjustable, which represents the channel width of the NMOS. Increasing its width can effectively suppress the current saturation effect and improve the current discharge capability of the NMOS, thereby further increasing the failure current and reducing the on-resistance. As the width of the second gate 502 increases, its NMOS shunting capability and the base width of the parasitic NPN transistor are increased, reducing the current gain coefficient β, thereby increasing the holding voltage.
[0043] The embodiment of the present invention provides a method for manufacturing a unidirectional thyristor electrostatic protection device with NMOS shunt, comprising the following steps:
[0044] Step 1: generating a first N-well 201 and a first P-well 203 , a second N-well 202 and a second P-well 204 in a P-type substrate 101 ;
[0045] Step 2: Generate a first N+ injection 301, a first P+ injection 302, a first gate 501, and a second P+ injection 303 on the first N well 201 from left to right; generate a third P+ injection region 304 between the first N well 201 and the first P well 203 to bridge the two wells; generate a second N+ injection 305, a second gate 502, and a third N+ injection region 306 between the first P well 203 and the second N well 202 to bridge the two wells on the first P well 203 from left to right; generate a fourth P+ injection 307 and a fourth N+ injection 308 on the second N well 202 from left to right; generate a fifth P+ injection 309 on the second P well 204 from left to right;
[0046] Step 3: forming a first field oxygen isolation region 401 on the right side of the first N+ implant 301 on the first N well 201, generating a second field oxygen 402 between the first N+ implant 301 and the first P+ implant 302 on the first N well 201, generating a third field oxygen 403 between the second P+ implant 303 and the third P+ implant 304 on the first N well 201, generating a fourth field oxygen 404 between the third P+ implant 304 and the second N+ implant 305 on the first P well 203, generating a fifth field oxygen 405 between the third N+ implant 306 and the fourth P+ implant 307 on the second N well 202, generating a sixth field oxygen 406 between the fourth P+ implant 307 and the fourth N+ implant 308 on the second N well 202, generating a seventh field oxygen 407 between the fifth P+ implant 309 and the fourth N+ implant 308 on the second P well 204, and generating an eighth field oxygen 408 on the right side of the fifth P+ implant 309 on the second P well 204;
[0047] Step 4: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas;
[0048] Step five: Connect the first N+ injection 301, the first P+ injection 302, and the first gate 501 together and use them as the anode of the device, connect the second P+ injection 303, the third P+ injection 304, the second N+ injection 305, and the second gate 502 together without connecting any potential, connect the third N+ injection 306, the fourth P+ injection 307, the fourth N+ injection 308, and the fifth P+ injection 309 together and use them as the cathode of the device.
[0049] The manufacturing method of the unidirectional thyristor electrostatic protection device with NMOS shunt of the present invention is simple and easy to operate. In order to better exert the performance of the unidirectional thyristor, the GDPMOS and NMOS structures introduced in the present invention generate a new surface path that weakens the positive feedback effect of the SCR path, thereby suppressing the latch effect, which can effectively improve the protection performance and failure level of the device. The device can be used in the ESD protection design of the I / O port of 0-5.5V. The example device of the present invention adopts a 0.25μm BCDMOS process.
[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A unidirectional thyristor electrostatic protection device with NMOS shunt, characterized in that: including a P-type substrate; The P-type substrate is provided with a first N-well and a first P-well; The P-type substrate is provided with a first N-well and a first P-well, a second N-well and a second P-well from left to right in sequence; the first N-well is then provided with a first N+ injection, a first P+ injection, a first gate, and a second P+ injection from left to right in sequence; and a third P+ injection is provided between the first N-well and the first P-well; The first P well is provided with a second N+ injection and a second gate from left to right in sequence; a third N+ injection is provided between the first P well and the second N well; the second N well is provided with a fourth P+ injection and a fourth N+ injection from left to right in sequence; The second P well is provided with a fifth P+ injection from left to right; The three electrodes of the first N+ injection, the first P+ injection and the first gate in the first N well are connected together and serve as the anode of the device; The third N+ injection electrode bridged between the first P well and the second N well is connected to the fourth P+ injection electrode in the second N well, and the fourth N+ injection electrode is connected to the fifth P+ injection electrode in the second P well and serves as the cathode of the device; The first gate in the first N-well, the second P+ implant connected between the first N-well and the first P-well, and the second gate in the first shallow P-well are connected together through a metal wire and are not connected to a potential; The fourth N+ injection in the first P well, the fifth N+ injection and the third gate are connected together through a metal wire and are not connected to a potential.
2. The unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 1, characterized in that: There are eight field oxygen isolation regions; the first field oxygen isolation region is to the left of the first N+ injection, the second field oxygen isolation region is between the first N+ injection and the first P+ injection, the third field oxygen is between the second P+ injection and the third P+ injection, the fourth field oxygen is between the third P+ injection and the second N+ injection, the fifth field oxygen is between the third N+ injection and the fourth P+ injection, the sixth field oxygen is between the fourth P+ injection and the fourth N+ injection, the seventh field oxygen is between the fourth N+ injection and the fifth P+ injection, and the eighth field oxygen is to the right of the fifth P+ injection.
3. The unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 2, characterized in that: The first field oxygen isolation region, the second field oxygen isolation region, and the third field oxygen isolation region are located on the surface of the first N-well; the fourth field oxygen isolation region is located on the surface of the first P-well; the fifth field oxygen isolation region and the sixth field oxygen isolation region are located on the surface of the second N-well; the seventh field oxygen isolation region is located at the junction of the second N-well surface and the second P-well surface; and the eighth field oxygen isolation region is located on the surface of the second P-well.
4. The unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well and the third P+ injection; at this time, the first P+ injection, the first gate, and the second P+ injection constitute a GDPMOS, and the second N+ injection, the second gate, and the third N+ injection constitute an NMOS. When the GDPMOS is turned on, it will form a GDPMOS-NMOS surface path with the NMOS to discharge current.
5. The unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well and the first P-well constitute a parasitic transistor PNP, and the first N-well, the first P-well and the third N+ injection constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well and the third P+ injection.
6. The unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is grounded, after the third P+ injection / first N-well junction is broken down, the ESD current in the first N-well will enter the first P-well through the bridged third P+ injection region and flow out from the third N+ injection region. On the one hand, the second N-well, the first P-well and the fourth P+ injection region form a parasitic PNP to shunt the SCR path. On the other hand, the GDPMOS formed by the first P+ injection, the first gate and the second P+ injection, and the NMOS formed by the second N+ injection, the second gate and the third N+ injection constitute a surface path discharge current. For the entire SCR path, the device is easier to turn on due to the current discharge of the surface path and the parasitic PNP shunt.
7. The unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 1, characterized in that: The width of the third P+ implant is adjustable. When the width increases, the trigger voltage decreases and the sustain voltage increases.
8. The unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 1, characterized in that: The width of the second gate is adjustable, which represents the channel width of the NMOS. Increasing its width can effectively suppress the current saturation effect and improve the current discharge capability of the NMOS, thereby further increasing the failure current and reducing the on-resistance. As the width of the second gate increases, the NMOS shunt capability and the base width of the parasitic NPN transistor increase, reducing the current gain coefficient β, thereby increasing the holding voltage.
9. A method for manufacturing a unidirectional thyristor electrostatic protection device with NMOS shunt according to any one of claims 1 to 8, comprising the following steps: Step 1: generating a first N-well and a first P-well, a second N-well and a second P-well in a P-type substrate; Step 2: Generate a first N+ injection, a first P+ injection, a first gate, and a second P+ injection on the first N well from left to right; generate a third P+ injection region between the first N well and the first P well to bridge the two wells; A second N+ implant, a second gate, and a third N+ implant region between the first P well and the second N well are sequentially generated from left to right on the first P well; Generating a fourth P+ implant and a fourth N+ implant in sequence from left to right on the second N well; Generating a fifth P+ implant from left to right on the second P well; Step 3: forming a first field oxygen isolation region on the right side of the first N+ implantation on the first N well, generating a second field oxygen between the first N+ implantation and the first P+ implantation on the first N well, generating a third field oxygen between the second P+ implantation and the third P+ implantation on the first N well, generating a fourth field oxygen between the third P+ implantation and the second N+ implantation on the first P well, generating a fifth field oxygen between the third N+ implantation and the fourth P+ implantation on the second N well, generating a sixth field oxygen between the fourth P+ implantation and the fourth N+ implantation on the second N well, generating a seventh field oxygen between the fifth P+ implantation on the second P well and the fourth N+ implantation on the second N well, and generating an eighth field oxygen on the right side of the fifth P+ implantation on the second P well; Step 4: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas; Step 5: Connect the first N+ injection, the first P+ injection, and the first gate together and use them as the anode of the device, connect the second P+ injection, the third P+ injection, the second N+ injection, and the second gate together without connecting any potential, connect the third N+ injection, the fourth P+ injection, the fourth N+ injection, and the fifth P+ injection together and use them as the cathode of the device.
10. The method for manufacturing a unidirectional thyristor electrostatic protection device with NMOS shunt according to claim 9, characterized in that: The following steps are also included before step one: growing a layer of silicon dioxide film on a P-type substrate, and then depositing a layer of silicon nitride; spin coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and the isolation shallow groove to remove the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical polishing until the silicon nitride layer is formed to remove the silicon nitride layer.