Back structure of TBC battery and preparation method thereof, TBC battery and preparation method thereof

Abstract

The present invention discloses a back structure of a TBC cell and a preparation method thereof, a TBC cell and a preparation method thereof, and belongs to the technical field of solar cells. The back structure of the TBC cell provided by the present invention includes a first doped polysilicon layer provided with a high-concentration doping area and a low-concentration doping area, which ensures good contact between the metal electrode and the polysilicon, and at the same time, the cell has a low contact resistance and a high conversion efficiency of the cell. The back structure of the TBC cell or the preparation method of the TBC cell provided by the present invention, on the basis of ensuring that the thickness of the first doped polysilicon layer is not reduced, reduces the adverse effect of laser patterning on subsequent wet etching of polysilicon by setting a low-concentration doping area, ensures the effect of wet etching of polysilicon, and further reduces the difficulty of the preparation process on the basis of ensuring the performance of the cell, and improves the cell manufacturing yield.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a back structure of a TBC cell and a preparation method thereof, a TBC cell and a preparation method thereof. Background Art

[0002] TOPCon cells, due to their unique structure, achieve selective carrier transmission, thereby reducing recombination, increasing the cell's open voltage and fill factor, and improving the cell conversion efficiency. The back contact of a BC cell means that both the emitter electrode and the base electrode are located on the back. On the one hand, the back contact cell structure transfers the emitter electrode to the back of the cell, thereby reducing or eliminating the shading loss of the front grid line and improving the cell efficiency; while the TBC (TOPCon+BC) cell structure uses the TOPCon structure for both polarities (P-type / N-type) in the back structure of the cell, achieving high current while meeting high open voltage and fill factor, thereby greatly improving the cell efficiency.

[0003] In industrialization, TBC cells usually prepare P-type doped polysilicon first, and then prepare N-type doped polysilicon. Before preparing N-type doped polysilicon, the P-type doped polysilicon layer needs to be removed. Therefore, the removal of P-type doped polysilicon is one of the keys to the preparation of TBC cells. Currently, the methods for removing the P-type doped polysilicon layer mainly include mask combined with wet etching or laser combined with wet etching, among which the more commonly used method is laser combined with wet etching.

[0004] The removal of the P-type doped polysilicon layer of the TBC battery is mainly affected by the doping concentration of the polysilicon. In particular, laser treatment will increase the surface concentration of the P-type doped polysilicon layer, making it difficult to etch the polysilicon layer. The existing method of reducing the doping concentration to solve the problem will increase the contact resistance, which is not conducive to improving the efficiency of the battery. Alternatively, new laser equipment such as femtosecond lasers can be used, but this will increase the equipment cost and is not conducive to reducing manufacturing costs.

[0005] For another example, in the patent application with publication number CN118610280 A, the etching difficulty of the P-type doped polysilicon layer is reduced by reducing the thickness of the P-type doped polysilicon layer. However, this solution will, on the one hand, cause the contact resistivity between the metal electrode and the polysilicon layer to increase, and on the other hand, will make it easier for the metal slurry to burn through the polysilicon, thereby destroying the structure, reducing the battery efficiency, and causing the battery yield to be low. Summary of the invention

[0006] 1. Problem to be solved

[0007] One of the objects of the present invention is to provide a back structure of a TBC cell and a TBC cell having the back structure, wherein the metal electrode of the back structure has good contact with the polysilicon layer;

[0008] At the same time, the present invention also provides a preparation process for a TBC battery. On the basis of not reducing the thickness of the polysilicon layer, a low-concentration doping area is set on the outer surface of the polysilicon layer so that the metal electrode of its back structure has good contact with the polysilicon layer, while reducing the difficulty of etching the polysilicon layer and improving the yield of the battery.

[0009] 2. Technical solution

[0010] In order to solve the above problems, the technical solution adopted by the present invention is as follows:

[0011] According to the purpose of the present invention, the first aspect of the present invention provides a back structure of a TBC battery, the back structure comprising a first emitter region, an isolation region, and a second emitter region located on the back of a base silicon wafer.

[0012] The first emitter region includes a first tunneling oxide layer, a first doped polysilicon layer, a passivation layer and a first metal electrode stacked on the back of the base silicon wafer, and the first metal electrode passes through the passivation layer and contacts the first doped polysilicon layer;

[0013] The second emitter region includes a second tunneling oxide layer, a second doped polysilicon layer, a passivation layer and a second metal electrode stacked on the back of the base silicon wafer, and the second metal electrode passes through the passivation layer and contacts the second doped polysilicon layer;

[0014] The isolation region is disposed between the first emission region and the second emission region;

[0015] Wherein, the first doped polysilicon layer includes a high-concentration doping region and a low-concentration doping region;

[0016] In the direction toward the base silicon wafer, the doping concentration of the low-concentration doping region increases from N1 to N2 in thickness, and the highest doping concentration N2 of the low-concentration doping region does not exceed the doping concentration of the high-concentration doping region;

[0017] The high-concentration doping region is located on a side close to the back side of the base silicon wafer, and the first metal electrode passes through the low-concentration doping region and contacts the high-concentration doping region.

[0018] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the doping concentrations at different positions of the high-concentration doping region are substantially the same.

[0019] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the first doped polysilicon layer is a P-type doped polysilicon layer, and the second doped polysilicon layer is an N-type doped polysilicon layer.

[0020] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the doping concentration N1 of the low-concentration doping area is 1E19atom / cm 3 ~4E19atom / cm 3 (atom / cm 3 Indicates that 1 times 10 to the 19th power of atoms are doped per cubic centimeter), the doping concentration N2 of the low-concentration doping area is 5E19atom / cm 3 ~1E20tom / cm 3 .

[0021] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, N2 / N1≥1.25, preferably 1.25≤N2 / N1≤10.

[0022] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the doping concentration of the high-concentration doping area is substantially close to the doping concentration N2, which is 5E19atom / cm 3 ~1E20tom / cm 3 .

[0023] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the thickness of the first doped polysilicon layer is D1, the thickness of the low-concentration doping area is D2, the thickness of the high-concentration doping area is D1-D2 (the difference between D1 and D2), and satisfies 2<D1 / D2<10, preferably satisfies 3<D1 / D2<7.

[0024] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the thickness of the first doped polysilicon layer is D1, and satisfies 50nm≤D1≤400nm.

[0025] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the thickness of the low-concentration doping region is D2, and satisfies 10nm<D2<150nm.

[0026] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the thickness of the second doped polysilicon layer is 30 nm to 300 nm.

[0027] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the doping concentration of the second doped polysilicon layer is 1E20atom / cm 3 ~1E21tom / cm 3 .

[0028] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the thickness of the first tunneling oxide layer is 0.5~2.5nm.

[0029] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the thickness of the second tunneling oxide layer is 0.5-2.5 nm.

[0030] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the thickness of the passivation layer is 40-80 nm.

[0031] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the thickness of the passivation layer of the first emission region is less than the thickness of the passivation layer of the second emission region.

[0032] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the thickness of the passivation layer of the first emission region is 60-80 nm, and the thickness of the passivation layer of the second emission region is 65-85 nm.

[0033] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the depth of the isolation region is 0.05-3 μm.

[0034] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the grain size of the low-concentration doping region is smaller than the grain size of the high-concentration doping region.

[0035] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the crystallization rate of the low-concentration doping region is lower than the crystallization rate of the high-concentration doping region.

[0036] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the crystallization rate of the low-concentration doping area is lower than 80%, and the crystallization rate of the high-concentration doping area is greater than 80%.

[0037] According to the back structure of the TBC battery of any embodiment of the first aspect of the present invention, the passivation layer includes any one or both of oxide and silicide.

[0038] According to the back structure of the TBC cell of any embodiment of the first aspect of the present invention, the passivation layer comprises one or more combinations of aluminum oxide, silicon nitride, silicon oxide and silicon oxynitride.

[0039] According to the purpose of the present invention, the second aspect of the present invention provides a method for preparing the back structure of a TBC battery as described in any embodiment of the first aspect of the present invention, comprising:

[0040] Step S1: polishing the surface of the base silicon wafer;

[0041] Step S2: firstly depositing a tunnel oxide layer and then depositing a polysilicon layer on the surface treated in step S1;

[0042] The polysilicon layer deposition includes a first stage and a second stage; the deposition temperature of the first stage is greater than the deposition temperature of the second stage;

[0043] and / or, the deposition pressure in the first stage is less than the deposition pressure in the second stage;

[0044] Step S3: performing doping by thermal diffusion to form a first doped polysilicon layer with a doped oxide layer;

[0045] Step S4: removing the doped oxide layer in a specific area by laser or etching to expose the polysilicon layer;

[0046] Step S5: removing the polysilicon layer exposed in step S4 by alkaline polishing;

[0047] Step S6: depositing a tunneling oxide layer and a polysilicon layer on the surface of the specific area processed in step S5;

[0048] Step S7: performing doping by thermal diffusion to form a second doped polysilicon layer with a doped oxide layer in the specific area;

[0049] Step S8: removing the doped oxide in the first doped polysilicon layer region and the doped oxide in the second doped polysilicon layer region by using laser or etching;

[0050] Step S9: removing the second doped polysilicon on the area where the first doped polysilicon layer is located on the back side of the base silicon wafer, and forming a groove between the area where the first doped polysilicon layer is located and the area where the second doped polysilicon layer is located;

[0051] Step S10: depositing a passivation layer on the back side of the base silicon wafer;

[0052] Step S11: Printing and sintering the back side of the base silicon wafer to form a first metal electrode and a second metal electrode.

[0053] According to the method for preparing the back structure of a TBC cell of any embodiment of the second aspect of the present invention, in step S2, the surface deposition of the polysilicon layer includes stage one and stage two;

[0054] The deposition temperature of the first stage is 580-600°C;

[0055] The deposition temperature of the second stage is 550-580°C;

[0056] According to the method for preparing the back structure of a TBC cell of any embodiment of the second aspect of the present invention, in step S2, the surface deposition of the polysilicon layer includes stage one and stage two;

[0057] The deposition pressure in the first stage is 150-250 mTorr (indicating the pressure in micrometers of mercury);

[0058] The deposition pressure in the second stage is 200-400 mTorr.

[0059] According to the method for preparing the back structure of a TBC cell of any embodiment of the second aspect of the present invention, in step S2, the surface deposition of the polysilicon layer includes stage one and stage two;

[0060] The deposition temperature of the first stage is 580-600°C;

[0061] The deposition temperature of the second stage is 550-580°C;

[0062] at the same time,

[0063] The deposition pressure in the first stage is 150-250 mTorr;

[0064] The deposition pressure in the second stage is 200-400 mTorr.

[0065] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S2, during the deposition process of the stage 1, the deposition temperature is kept constant;

[0066] During the deposition process of the second stage, the deposition temperature is gradually reduced from 580° C. to 550° C.;

[0067] Preferably, during the deposition process of the second stage, the deposition temperature is uniformly reduced from 580° C. to 550° C.

[0068] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S2, during the deposition process of the stage 1, the deposition pressure is kept constant;

[0069] During the deposition process of the second stage, the deposition pressure is constant or gradually increases;

[0070] Preferably, during the deposition process of the second stage, the deposition pressure is constant and greater than the pressure of the first stage.

[0071] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S2, the deposition temperature of the stage 1 is 580-600° C.;

[0072] The deposition temperature of the second stage is 550-580°C;

[0073] Meanwhile, during the deposition process of the stage 1, the deposition temperature is kept constant;

[0074] During the deposition process of the second stage, the deposition temperature is gradually reduced from 580° C. to 550° C.;

[0075] Preferably, during the deposition process of the second stage, the deposition temperature is uniformly reduced from 580° C. to 550° C.

[0076] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S2, the deposition pressure of the stage 1 is 150-250 mTorr;

[0077] The deposition pressure in the second stage is 200-400 mTorr.

[0078] at the same time,

[0079] During the deposition process of the first stage, the deposition pressure is kept constant;

[0080] During the deposition process of the second stage, the deposition pressure is constant or gradually increases;

[0081] Preferably, during the deposition process of the second stage, the deposition pressure is constant and greater than the pressure of the first stage.

[0082] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S1, the surface of the base silicon wafer is polished to form a texture, and the depth of the texture is greater than 20μm, preferably 20~30μm.

[0083] According to the method for preparing the back structure of a TBC battery according to any embodiment of the second aspect of the present invention, in step S2, the deposition temperature of the tunneling oxide layer is 590-650°C.

[0084] According to the method for preparing the back structure of a TBC battery according to any embodiment of the second aspect of the present invention, in step S2, the thickness of the tunneling oxide layer is 0.5~2.5nm.

[0085] According to the method for preparing the back structure of a TBC battery according to any embodiment of the second aspect of the present invention, in step S2, the thickness of the polysilicon layer is 50-400 nm.

[0086] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S2, the deposition thickness of the second stage is 10-150 nm;

[0087] The deposition thickness in the first stage is the thickness of the polysilicon layer minus the deposition thickness in the second stage.

[0088] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S2, the thickness of the polysilicon layer is D1, the deposition thickness of the stage two is D2, the deposition thickness of the stage one is D1-D2, and 2<D1 / D2<10 is satisfied, preferably 3<D1 / D2<7 is satisfied.

[0089] According to the method for preparing the back structure of a TBC battery in any embodiment of the second aspect of the present invention, in step S3, the diffusion is boron diffusion, the doped oxide layer is a borosilicate glass layer (hereinafter referred to as BSG), and the thickness of the doped oxide layer is 40~60nm.

[0090] According to the method for preparing the back structure of a TBC battery in any embodiment of the second aspect of the present invention, in step S3, the surface concentration of the polysilicon layer is less than 4E19, preferably 1 E19atom / cm 3 ~4E19atom / cm 3 .

[0091] According to the method for preparing the back structure of a TBC battery in any embodiment of the second aspect of the present invention, in step S3, the concentration of the polysilicon layer formed in the first stage is 5E19atom / cm 3 ~1E20tom / cm 3 ;

[0092] The surface concentration N1 of the polysilicon layer formed in the second stage is less than 4E19, preferably 1 E19atom / cm 3 ~4E19atom / cm 3

[0093] In the direction toward the base silicon wafer, the doping concentration of the low-concentration doped region increases from N1 to N2 in thickness, and the doping concentration N2 of the polysilicon layer formed in the second stage does not exceed the concentration of the polysilicon layer formed in the first stage;

[0094] Preferably, the doping concentration N2 of the polysilicon layer formed in the second stage is close to or equal to the concentration of the polysilicon layer formed in the first stage;

[0095] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S5, the polysilicon layer exposed in step S4 is removed by alkali polishing to form a polished morphology, while the area where BSG is not removed is retained, thereby forming a height difference (GAP), and the GAP range is 0.1~0.3μm, wherein the remaining thickness of BSG in the unremoved area is 10~30nm.

[0096] According to the method for preparing the back structure of a TBC battery according to any embodiment of the second aspect of the present invention, in step S6, the deposition temperature of the tunneling oxide layer is 590-650°C.

[0097] According to the method for preparing the back structure of a TBC battery according to any embodiment of the second aspect of the present invention, in step S6, the deposition thickness of the tunneling oxide layer is 0.5~2.5nm.

[0098] According to the method for preparing the back structure of a TBC battery according to any embodiment of the second aspect of the present invention, in step S6, the deposition temperature of the polysilicon layer is 590-630°C.

[0099] According to the method for preparing the back structure of a TBC battery according to any embodiment of the second aspect of the present invention, in step S6, the deposition thickness of the polysilicon layer is 30-300 nm.

[0100] According to the method for preparing the back structure of a TBC battery in any embodiment of the second aspect of the present invention, in step S7, the diffusion is phosphorus diffusion, the doped oxide layer is a phosphosilicate glass layer (hereinafter referred to as PSG), and the thickness of the doped oxide layer is 40-60 nm.

[0101] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S9, the position of the groove substantially corresponds to the position of the isolation area.

[0102] According to the method for preparing the back structure of a TBC battery of any embodiment of the second aspect of the present invention, in step S10, the thickness of the passivation layer is 40-80 nm.

[0103] According to the purpose of the present invention, the third aspect of the present invention provides a TBC battery, the battery comprising:

[0104] A base silicon wafer, wherein the base silicon wafer comprises a back side and a front side;

[0105] A back structure disposed on the back of the base silicon wafer, the back structure being the back structure of the TBC battery of any embodiment of the first aspect, or the back structure of the TBC battery prepared by the method of any embodiment of the second aspect;

[0106] A passivation layer is arranged on the front side of the base silicon wafer.

[0107] According to the TBC battery of any embodiment of the third aspect of the present invention, the thickness of the passivation layer is 50-100 nm.

[0108] According to the TBC battery of any embodiment of the third aspect of the present invention, the passivation layer includes any one or both of oxide and silicide.

[0109] According to the TBC cell of any embodiment of the third aspect of the present invention, the third passivation layer includes one or more combinations of aluminum oxide, silicon nitride, silicon oxide and silicon oxynitride.

[0110] According to the TBC battery of any embodiment of the third aspect of the present invention, the thickness of the third passivation layer is 50-100 nm.

[0111] According to the purpose of the present invention, the fourth aspect of the present invention provides a method for preparing a TBC battery as described in any embodiment of the third aspect of the present invention, comprising:

[0112] Step A1: polishing the surface of the base silicon wafer;

[0113] Step A2: firstly depositing a tunnel oxide layer and then depositing a polysilicon layer on the surface treated in step A1;

[0114] The polysilicon layer deposition includes a first stage and a second stage; the deposition temperature of the first stage is greater than the deposition temperature of the second stage;

[0115] and / or, the deposition pressure in the first stage is less than the deposition pressure in the second stage;

[0116] Step A3: performing doping by thermal diffusion to form a first doped polysilicon layer with a doped oxide layer;

[0117] Step A4: removing the doped oxide layer in a specific area by laser or etching to expose the polysilicon layer;

[0118] Step A5: removing the polysilicon layer exposed in step A4 by alkaline polishing;

[0119] Step A6: depositing a tunneling oxide layer and a polysilicon layer on the surface of the specific area treated in step A5;

[0120] Step A7: performing doping by thermal diffusion to form a second doped polysilicon layer with a doped oxide layer in the specific region;

[0121] Step A8: removing the doped oxide in the first doped polysilicon layer region and the doped oxide in the second doped polysilicon layer region by using laser or etching;

[0122] Step A9: etching and texturing the front side of the base silicon wafer;

[0123] Removing the second doped polysilicon on the area where the first doped polysilicon layer is located on the back side of the base silicon wafer, and forming a groove between the area where the first doped polysilicon layer is located and the area where the second doped polysilicon layer is located;

[0124] Step A10: depositing a passivation layer on the front and back sides of the base silicon wafer;

[0125] Step A11: Printing and sintering to form a first metal electrode and a second metal electrode on the back side of the base silicon wafer.

[0126] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the surface deposition of the polysilicon layer includes stage one and stage two;

[0127] The deposition temperature of the first stage is 580-600°C;

[0128] The deposition temperature of the second stage is 550-580°C;

[0129] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the surface deposition of the polysilicon layer includes stage one and stage two;

[0130] The deposition pressure in the first stage is 150-250 mTorr;

[0131] The deposition pressure in the second stage is 200-400 mTorr.

[0132] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the surface deposition of the polysilicon layer includes stage one and stage two;

[0133] The deposition temperature of the first stage is 580-600°C;

[0134] The deposition temperature of the second stage is 550-580°C;

[0135] at the same time,

[0136] The deposition pressure in the first stage is 150-250 mTorr;

[0137] The deposition pressure in the second stage is 200-400 mTorr.

[0138] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, during the deposition process of the stage 1, the deposition temperature is kept constant;

[0139] During the deposition process of the second stage, the deposition temperature is gradually reduced from 580° C. to 550° C.;

[0140] Preferably, during the deposition process of the second stage, the deposition temperature is uniformly reduced from 580° C. to 550° C.

[0141] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, during the deposition process of the stage 1, the deposition pressure is kept constant;

[0142] During the deposition process of the second stage, the deposition pressure is constant or gradually increases;

[0143] Preferably, during the deposition process of the second stage, the deposition pressure is constant and greater than the pressure of the first stage.

[0144] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the deposition temperature of the stage 1 is 580-600° C.;

[0145] The deposition temperature of the second stage is 550-580°C;

[0146] Meanwhile, during the deposition process of the stage 1, the deposition temperature is kept constant;

[0147] During the deposition process of the second stage, the deposition temperature is gradually reduced from 580° C. to 550° C.;

[0148] Preferably, during the deposition process of the second stage, the deposition temperature is uniformly reduced from 580° C. to 550° C.

[0149] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the deposition pressure of the stage 1 is 150-250 mTorr;

[0150] The deposition pressure in the second stage is 200-400 mTorr.

[0151] at the same time,

[0152] During the deposition process of the first stage, the deposition pressure is kept constant;

[0153] During the deposition process of the second stage, the deposition pressure is constant or gradually increases;

[0154] Preferably, during the deposition process of the second stage, the deposition pressure is constant and greater than the pressure of the first stage.

[0155] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A1, the surface of the base silicon wafer is polished to form a texture, and the depth of the texture is greater than 20μm, preferably 20~30μm.

[0156] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the deposition temperature of the tunneling oxide layer is 590-650°C.

[0157] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the thickness of the tunneling oxide layer is 0.5~2.5nm.

[0158] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the thickness of the polysilicon layer is 50-400 nm.

[0159] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the deposition thickness of the stage 2 is 10 nm to 150 nm;

[0160] The deposition thickness in the first stage is the thickness of the polysilicon layer minus the deposition thickness in the second stage.

[0161] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A2, the thickness of the polysilicon layer is D1, the deposition thickness of the stage two is D2, the deposition thickness of the stage one is D1-D2, and 2<D1 / D2<10 is satisfied, preferably 3<D1 / D2<7 is satisfied.

[0162] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A3, the diffusion is boron diffusion, the doped oxide layer is a borosilicate glass layer (hereinafter referred to as BSG), and the thickness of the doped oxide layer is 40~60nm.

[0163] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A3, the surface concentration of the polysilicon layer is less than 4E19, preferably 1 E19atom / cm 3 ~4E19atom / cm 3 .

[0164] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A3, the concentration of the polysilicon layer formed in the first stage is 5E19atom / cm 3 ~1E20tom / cm 3 ;

[0165] The surface concentration N1 of the polysilicon layer formed in the second stage is less than 4E19, preferably 1 E19atom / cm 3 ~4E19atom / cm 3

[0166] In the direction toward the base silicon wafer, the doping concentration of the low-concentration doped region increases from N1 to N2 in thickness, and the doping concentration N2 of the polysilicon layer formed in the second stage does not exceed the concentration of the polysilicon layer formed in the first stage;

[0167] Preferably, the doping concentration N2 of the polysilicon layer formed in the second stage is close to or equal to the concentration of the polysilicon layer formed in the first stage;

[0168] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A5, the polysilicon layer exposed in step A4 is removed by alkaline polishing to form a polished morphology, while the area where BSG is not removed is retained, thereby forming a height difference (GAP), and the GAP range is 0.1~0.3μm, wherein the remaining thickness of BSG in the unremoved area is 10~30nm.

[0169] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A6, the deposition temperature of the tunneling oxide layer is 590-650°C.

[0170] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A6, the deposition thickness of the tunneling oxide layer is 0.5~2.5nm.

[0171] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A6, the deposition temperature of the polysilicon layer is 590° C. to 630° C.

[0172] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A6, the deposition thickness of the polysilicon layer is 30 to 300 nm.

[0173] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A7, the diffusion is phosphorus diffusion, the doped oxide layer is a phosphosilicate glass layer (hereinafter referred to as PSG), and the thickness of the doped oxide layer is 40-60 nm.

[0174] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A9, the position of the groove substantially corresponds to the position of the isolation region.

[0175] According to the method for preparing a TBC battery of any embodiment of the fourth aspect of the present invention, in step A10, the thickness of the passivation layer is 40-80 nm.

[0176] Beneficial Effects

[0177] (1) The back structure of the TBC cell or the TBC cell with a back structure provided by the present invention has a first doped polysilicon layer provided with a high-concentration doping region and a low-concentration doping region, which ensures good contact between the metal electrode and the polysilicon. At the same time, the cell has a low contact resistance and a high conversion efficiency.

[0178] (2) The removal of the first doped polysilicon layer of the TBC cell is mainly affected by the doping concentration of the polysilicon, especially after laser treatment, which will affect the polysilicon layer, making the subsequent wet etching of the polysilicon difficult. To solve this problem, one of the treatment methods is to reduce the doping concentration of the first doped polysilicon layer. This method increases the contact resistance between the metal electrode and the polysilicon, which is not conducive to the efficiency of the cell; the second treatment method is to reduce the thickness of the first doped polysilicon layer. This method will also increase the contact resistance between the metal electrode and the polysilicon, and also increase the risk of the metal slurry burning through the polysilicon, thereby destroying the structure and reducing the yield and efficiency of the cell; the third treatment method is to use new laser equipment, such as femtosecond lasers, but this will increase the equipment cost and is not conducive to reducing manufacturing costs.

[0179] In this context, the back structure of the TBC battery or the preparation method of the TBC battery provided by the present invention, while ensuring that the thickness of the first doped polysilicon layer is not reduced, reduces the adverse effects of laser patterning on the subsequent wet etching of polysilicon by setting a low-concentration doping area, thereby ensuring the effect of wet etching of polysilicon, and further reducing the difficulty of the preparation process and improving the battery manufacturing yield while ensuring the battery performance.

[0180] (3) The back structure of the TBC battery or the method for preparing the TBC battery provided by the present invention requires that the low doping concentration N1 of the low doping area is 1 E19atom / cm 3 ~4E19atom / cm 3At the same time, the maximum doping concentration N2 of the low-concentration doping area is required not to exceed the doping concentration of the high-concentration doping area, and the maximum doping concentration N2 of the low-concentration doping area is required to be 5E19atom / cm 3 ~1E20tom / cm 3

[0181] It can further ensure that the adverse effects of laser patterning on subsequent wet etching of polysilicon are reduced, and the effect of wet etching of polysilicon is ensured, thereby reducing the difficulty of the preparation process and improving the battery manufacturing yield on the basis of ensuring battery performance.

[0182] (4) On the basis of the aforementioned requirements for the doping concentrations of the low-concentration doping region and the high-concentration doping region, it is further required that the ratio of the thickness of the low-concentration doping region (D2) to the thickness of the first doped polysilicon layer (D1) satisfies 2<D1 / D2<7. Based on this, it is possible to reduce the adverse effects of laser patterning on the subsequent wet etching of polysilicon and ensure the effect of wet etching of polysilicon, while avoiding the adverse effects of causing the contact resistance between the metal electrode and the polysilicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0183] Figure 1 A schematic diagram of the TBC battery and its back structure of Comparative Example 1 (prior art);

[0184] Figure 2 Schematic diagram of the back structure of the TBC battery (B-TBC-1) provided in Example 1 of the present invention;

[0185] Figure 3 yes Figure 2 A magnified schematic diagram of a local area C in the back structure of the TBC battery;

[0186] Figure 4 A schematic diagram of the structure of a TBC battery having B-TBC-1 provided by an embodiment of the present invention;

[0187] Figure 5 A doping curve diagram of the first doped polysilicon layer (ie, P-type polysilicon) provided in Embodiment 1 of the present invention;

[0188] Figure 6 Embodiment 1 of the present invention and comparative examples 1 and 2 provide a doping curve diagram of a first doped polysilicon layer (i.e., P-type polysilicon);

[0189] In the figure: 1. Base silicon wafer;

[0190] 100. front side of base silicon wafer; 110. third passivation layer;

[0191] 200, back side of base silicon wafer; 210, first emitter region; 211, first tunneling oxide layer; 212, first doped polysilicon layer; 212a, high concentration doping region; 212b, low concentration doping region; 213, first metal electrode; 214, first passivation layer; 220, second emitter region; 221, second tunneling oxide layer; 222, second doped polysilicon layer; 223, second metal electrode; 224, second passivation layer; 230, isolation region;

[0192] A, thickness direction of the first doped polysilicon layer;

[0193] C. Local area;

[0194] D1, thickness of the first doped polysilicon layer;

[0195] D2, thickness of low-concentration doped region;

[0196] D1-D2, thickness of high concentration doping area;

[0197] N1, doping concentration at the starting point of the low-concentration doping region;

[0198] N2, the doping concentration at the starting point of the high-concentration doping area (also the highest doping concentration in the low-concentration doping area)

[0199] ∠A: The angle between the line connecting the starting point of the low doping concentration area and the starting point of the high doping concentration and the horizontal line of the high doping concentration starting concentration. DETAILED DESCRIPTION

[0200] The present disclosure may be more easily understood by reference to the following description in conjunction with the accompanying drawings and examples, all of which constitute a part of the present disclosure. It should be understood that the present disclosure is not limited to the specific products, methods, conditions or parameters described and / or shown herein. Further, the terms used herein are only used for the purpose of describing specific embodiments by way of example and are not intended to be limiting unless otherwise stated.

[0201] It should also be understood that, for the sake of clarity, certain features of the present disclosure may be described herein in the context of separate embodiments, but may also be provided in combination with each other in a single embodiment. That is, unless clearly incompatible or specifically not included, each separate embodiment is considered to be combinable with any other embodiment, and the combination is considered to represent another different embodiment. Conversely, for the sake of simplicity, the various features of the present disclosure described in the context of a single embodiment may also be provided individually or in any sub-combination. Finally, although a particular embodiment may be described as part of a series of steps or part of a more general structure, each step or sub-structure itself may also be considered to be an independent embodiment.

[0202] Unless otherwise indicated, it should be understood that each individual element in a list and each combination of individual elements in the list will be interpreted as a different embodiment. For example, a list of embodiments expressed as "A, B, or C" should be interpreted to include embodiments "A", "B", "C", "A or B", "A or C", "B or C", or "A, B, or C".

[0203] In the present disclosure, the singular forms of the articles "a", "an", and "the" also include the corresponding plural references, and references to a specific value include at least that specific value unless the context clearly indicates otherwise. Thus, for example, reference to "a substance" is a reference to at least one of that substance and its equivalents.

[0204] The terms including ordinal numbers such as "first" and "second" can be used to explain various components or fluids, but these components and fluids are not limited by these terms. Therefore, without departing from the teachings of the present disclosure, these terms are only used to distinguish the component / fluid from another component / fluid.

[0205] When items are described by using conjunction terms such as “… and / or…”, the description should be understood to include any one of the associated listed items and all combinations of one or more thereof; for example, A and / or B should be interpreted as an embodiment including “A” but not including “B”, an embodiment including “B” but not including “A”, and an embodiment including “A” and “B”.

[0206] Throughout the specification of this application document, when a certain part is described as “including” a certain constituent element, unless otherwise clearly described to the contrary, it does not mean that other constituent elements are excluded but that other constituent elements may also be included.

[0207] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs; the terms used herein and / or include any and all combinations of one or more of the listed items. In order to make the technical solutions and advantages of the present invention clear, the technical solutions in the embodiments of the present invention will be fully described below.

[0208] Example 1

[0209] like Figure 2 , 3 As shown, in this embodiment, a back structure of a TBC battery (B-TBC-1) is provided. For the convenience of description, only the parts related to the embodiment of the present invention are shown. Figure 2~3 shown.

[0210] The back structure of the TBC battery provided by the embodiment of the present invention includes:

[0211] A base silicon wafer 1, a first emitter region 210 and a second emitter region 220 are arranged on the back side 200 of the base silicon wafer, and an isolation region 230 with a depth of 0.05-3 μm and a width of 10-100 μm is arranged between the first emitter region 210 and the second emitter region 220.

[0212] like Figure 2 As shown, the first emitter region 210 includes a first tunneling oxide layer 211, a first doped polysilicon layer 212, a first passivation layer 214, and a first metal electrode 213 that passes through the first passivation layer 214 and contacts the first doped polysilicon layer 212, wherein the first doped polysilicon layer 212 includes a high-concentration doping region 212a stacked on the first tunneling oxide layer 211 and a low-concentration doping region 212b stacked on the high-concentration doping region 212a, and the first metal electrode 213 passes through the low-concentration doping region 212b and contacts the high-concentration doping region 212a, but does not contact the first tunneling oxide layer 211.

[0213] The second emitter region 220 includes a second tunneling oxide layer 221 stacked on the back side 200 of the base silicon wafer, a second doped polysilicon layer 222 , a second passivation layer 224 , and a second metal electrode 223 passing through the second passivation layer 224 and contacting the second doped polysilicon layer 222 .

[0214] For the first tunneling oxide layer 211 and the second tunneling oxide layer 221, their formation is currently mainly thermal oxidation (including dry oxygen oxidation, wet oxygen oxidation), chemical vapor deposition (CVD) (including plasma chemical vapor deposition (PECVD) method, low pressure chemical vapor deposition (LPCVD) method, room temperature wet oxidation method, etc., preferably low pressure chemical vapor deposition (LPCVD) method. In some embodiments of the present invention, the thickness of the first tunneling oxide layer 211 is 0.5~2.5nm, and the thickness of the second tunneling oxide layer 221 is 0.5~2.5nm. With respect to the back structure B-TBC-1 of the specific TBC battery provided in this specific embodiment, the depth of the isolation region 230 is 2.5μm and the width is 40μm, the thickness of the first tunneling oxide layer 211 is 1.8 nm, and the thickness of the second tunneling oxide layer 221 is 1.5 nm.

[0215] The first doped polysilicon layer 212 and the second doped polysilicon layer 222 are respectively a "doped polysilicon layer" containing a first doping element and a "doped polysilicon layer" containing a second doping element, and the first doping element is different from the second doping element; there are several methods for forming the "doped polysilicon layer": for example, the doped polycrystalline layer is directly deposited by the LPCVD method, and this method can complete the deposition and doping of the polysilicon layer at one time; or the intrinsic polysilicon layer can be first deposited by the PECVD or LPCVD method, and then ion implantation, diffusion and other processes are used for doping, and the various doping methods have little difference in process effects. In some embodiments of the present invention, the first doped polysilicon layer 212 is P-type doped, and its thickness D1 is 50-400 nm. On this basis, the thickness D2 of the low-concentration doped region 212 b is 10 nm < D2 < 150 nm, and the thickness of the high-concentration doped region 212 a is D1-D2; in terms of concentration, the doping concentration of the high-concentration doped region 212 a is 5E19 atom / cm 3 ~1E20tom / cm 3 ;like Figure 3 In the direction A (towards the base silicon wafer), the doping concentration of the low-concentration doped region increases from N1 to N2 in thickness. The doping concentration N1 of the low-concentration doped region is 1 E19atom / cm 3 The maximum doping concentration N2 of the low-concentration doping region does not exceed the doping concentration of the high-concentration doping region. Preferably, the maximum doping concentration N2 of the low-concentration doping region is the same as the doping concentration of the high-concentration doping region 212a, which is 5 E19atom / cm 3 ~1E20tom / cm 3 In some embodiments of the present invention, the second doped polysilicon layer 222 is N-type doped, and its thickness D3 is 30-300 nm. On this basis, the doping concentration of the second doped polysilicon layer 222 is 1E20 atom / cm 3 ~1E21tom / cm 3 In some preferred embodiments of the present invention, 2<D1 / D2<7 is satisfied. In some preferred embodiments of the present invention, the requirement of N2 / N1≥1.25 is satisfied. In some preferred embodiments of the present invention, the requirement of 1.25≤N2 / N1≤10 is satisfied. Reference Figure 5 As shown, for the back structure B-TBC-1 of the specific TBC battery provided in this specific embodiment, the first doped polysilicon layer 212 is P-type doped, and its thickness D1 is 350nm, the thickness D2 of the low-concentration doping region 212b is 100nm, and the thickness of the high-concentration doping region 212a is D1-D2; in terms of concentration, the doping concentration of the high-concentration doping region 212a is 6 E19 atom / cm 3 ,and Figure 5 ∠A is the angle between the line connecting the starting point of the low doping concentration area and the starting point of the high doping concentration and the horizontal line of the high doping concentration starting concentration; Figure 3 In the direction A (towards the base silicon wafer), the doping concentration of the low-concentration doped region 212 b increases from N1 to N2 in thickness, and the doping concentration N1 of the low-concentration doped region 212 b is 2 E19 atom / cm 3 The maximum doping concentration N2 of the low-concentration doping region 212b is the same as the doping concentration of the high-concentration doping region 212a. The second doped polysilicon layer 222 is N-type doped, with a thickness D3 of 200nm and a doping concentration of 6E20tom / cm 3 ;

[0216] The first passivation layer 214 and the second passivation layer 224 include an oxide layer (such as a silicon oxide layer, an aluminum oxide layer (AlO x layer), nitride layer (such as silicon nitride (SiN x ) layer), a nitride oxide layer (such as a silicon nitride oxide layer), or one or more combinations thereof.

[0217] As some examples of the present invention, for example, the first passivation layer 214 and / or the second passivation layer 224 may be an oxide layer of a single material (such as a silicon oxide layer, an aluminum oxide layer (AlO x layer)), can be a nitride layer of a single material (such as silicon nitride (SiN x ) layer), a nitride oxide layer of a single material (such as a silicon nitride oxide layer), or an oxide layer (such as a silicon oxide layer, an aluminum oxide layer (AlO x layer) and nitride layers (such as silicon nitride (SiN x ) layer). It can be understood that the specific structure of the first passivation layer 214 and / or the second passivation layer 224 includes but is not limited to the several methods listed above, and the first passivation layer 214 and / or the second passivation layer 224 can be set accordingly according to actual use needs, which is not specifically limited here. Among them, the silicon oxide layer can be prepared by chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), or atomic layer deposition (ALD), which is prepared according to actual use needs, and is not specifically limited here; the nitride layer (such as silicon nitride (SiN x ) layer) can be prepared by chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) and magnetron sputtering technology, and it is prepared according to actual use needs. If conditions permit, chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) are preferably used for SiN xPreparation of the film; the aluminum oxide layer can be prepared by atomic layer deposition (ALD), plasma-assisted ALD, pyrolysis deposition, delocalized PECVD, molecular beam epitaxy, deposition of Al plus oxidation, etc., which is prepared according to the actual use needs and is not specifically limited here. Silicon nitride and aluminum oxide will produce a large amount of hydrogen at the same time as the thin film is deposited, which can form a good hydrogen passivation. In some embodiments of the present invention, the thickness of the first passivation layer 214 is 60~80nm, the thickness of the second passivation layer 224 is 65~85nm, and the thickness of the first passivation layer 214 is less than the thickness of the second passivation layer 224. For the back structure B-TBC-1 of the specific TBC battery provided in this specific embodiment, the thickness of the first passivation layer 214 is 70 nm, and the thickness of the second passivation layer 224 is 75 nm.

[0218] Further, for the back structure B-TBC-1 of the specific TBC cell provided in this specific embodiment, the isolation region 230 has a depth of 2.5 μm and a width of 40 μm. The resistivity of the selected base silicon wafer 1 is 6 ohm·cm, and it is an N-type single crystal silicon wafer with a thickness of 145 μm.

[0219] However, it should be noted that the base silicon wafer 1 with a resistance of more than 10 ohmcm can meet the battery performance requirements of the present invention, and no limitation or requirement is made here, and the final battery performance of various resistivities is not much different.

[0220] Example 2

[0221] This embodiment provides a method for preparing the back structure of a TBC battery as described in Embodiment 1, which specifically includes the steps of:

[0222] Step S1: polishing the surface of the base silicon wafer;

[0223] In some embodiments of the present invention, the silicon wafer can be polished with alkaline solution to remove the damaged layer and form a flat planar structure having a texture, wherein the texture includes any one, two or three of a pyramid, an inverted pyramid or a tower base structure; in terms of the size of the texture, its depth is greater than 20 μm, and preferably the depth is 25-30 μm; however, it should be noted that, in addition to using alkaline solution, the operation of this step can actually be performed in any existing manner, and the various methods have little difference in process effects.

[0224] Further, with regard to the back structure B-TBC-1 of the specific TBC battery provided in Example 1, in this embodiment, KOH (potassium hydroxide) alkaline liquid is used to react with the base silicon wafer 1 to remove the surface damage layer while forming a flat planar structure, which has a texture texture of a tower base structure, and its depth is 25-30μm in terms of the size of the tower base.

[0225] Step S2: firstly depositing a tunnel oxide layer and then depositing a polysilicon layer on the surface treated in step S1;

[0226] The polysilicon layer deposition includes a first stage and a second stage; the deposition temperature of the first stage is greater than the deposition temperature of the second stage; and / or the deposition pressure of the first stage is less than the deposition pressure of the second stage;

[0227] In some embodiments of the present invention, a tunneling oxide layer (SiO2) and a polysilicon layer (P-Poly) are deposited on the back side 200 of the base silicon wafer 1 after polishing by LPCVD equipment, wherein the thickness of the tunneling oxide layer is 0.5-2.5 nm, the deposition temperature is 590-650° C., the thickness of the polysilicon layer is 50-400 nm, the deposition temperature is 550° C.-600° C., and the pressure is 150-400 mTorr;

[0228] On this basis, in some embodiments of the present invention, the surface deposition of the polysilicon layer includes stage one and stage two; the deposition temperature of stage one is 580-600°C; the deposition temperature of stage two is 550-580°C; and the deposition pressure of stage one and stage two is any constant pressure from 150-220 mTorr. In some preferred embodiments, during the deposition process of stage two, the deposition temperature is uniformly reduced from 580°C to 550°C.

[0229] In some other embodiments of the present invention, the surface deposition of the polysilicon layer includes stage one and stage two; the deposition pressure of stage one is 150-220 mTorr; the deposition pressure of stage two is 220-300 mTorr; and the deposition temperature of stage one and stage two is any constant temperature from 550°C to 600°C. In some preferred embodiments, during the deposition process of stage two, the deposition pressure is increased uniformly from 220 mTorr to 300 mTorr.

[0230] In some other embodiments of the present invention, the surface deposition of the polysilicon layer includes a first stage and a second stage;

[0231] The deposition temperature of stage 1 is 580-600 °C. At the same time, the deposition pressure of stage 1 is any constant pressure from 150-220 mTorr.

[0232] The deposition temperature of stage 2 is 550-580 °C; meanwhile, the deposition pressure of stage 2 is 220-300 mTorr.

[0233] Among them, in some preferred embodiments, during the deposition process of stage 2, the deposition temperature is uniformly reduced from 580°C to 550°C.

[0234] In another preferred embodiment, during the deposition process of stage 2, the deposition pressure is increased uniformly from 220 mTorr to 300 mTorr.

[0235] Among them, in other preferred embodiments, during the deposition process of stage two, the deposition temperature is uniformly reduced from 580° C. to 550° C.; at the same time, during the deposition process of stage two, the deposition pressure is uniformly increased from 220 mTorr to 300 mTorr.

[0236] Further, with respect to the back structure B-TBC-1 of the specific TBC battery provided in Example 1, the surface deposition of the polysilicon layer in this embodiment includes stage one and stage two; the deposition temperature of stage one is 595°C, and the deposition thickness is the thickness of the high-concentration doping region 212a of B-TBC-1 provided in the aforementioned Example 1; the deposition temperature of stage two is 550~580°C, and the deposition thickness is the thickness of the low-concentration doping region 212b of B-TBC-1 provided in the aforementioned Example 1. During the deposition process of stage two, the deposition temperature is uniformly reduced from 580°C to 550°C; and the pressure of stage one and stage two is a constant pressure of 250 mTorr.

[0237] Step S3: performing doping by thermal diffusion to form a first doped polysilicon layer with a doped oxide layer;

[0238] In some other embodiments of the present invention, thermal diffusion is used to form a P-type doped region with a certain BSG thickness, wherein the diffusion source is BCl3 (boron trichloride), the BSG thickness is 40-60nm, and after diffusion, the doping concentration of the polysilicon layer in stage 1 is 5E19atom / cm 3 ~1E20tom / cm 3 ;like Figure 3 In the direction A (towards the base silicon wafer), the doping concentration of the polysilicon layer in the second stage increases from N1 to N2 in thickness, and the doping concentration N1 is 1 E19atom / cm 3 ~4E19atom / cm 3 The doping concentration N2 does not exceed the doping concentration of the polysilicon layer in stage 1. Preferably, the doping concentration N2 is 4.5 E19atom / cm 3 ~1E20tom / cm 3 .

[0239] Further, with respect to the back structure B-TBC-1 of the specific TBC battery provided in Example 1, in this embodiment, thermal diffusion is used for doping to form a P-type doping region with a BSG thickness of 50 nm, wherein the diffusion source is BCl3. After diffusion, the thickness and doping concentration of the polysilicon layer in the first stage are the same as the doping concentration of the high-concentration doping region 212a of B-TBC-1 provided in the aforementioned Example 1; Figure 3 In the direction A shown (towards the base silicon wafer), the thickness of the polysilicon layer in stage two is the same as the thickness of the low-concentration doping region 212b of the B-TBC-1 provided in the aforementioned embodiment 1, and the doping concentration of the polysilicon layer in stage two increases from N1 to N2 in thickness, and the doping concentration N1 is the same as the doping concentration N1 of the low-concentration doping region 212b of the B-TBC-1 provided in the aforementioned embodiment 1, and the doping concentration N2 is the same as the doping concentration of the high-concentration doping region 212a of the B-TBC-1 provided in the aforementioned embodiment 1.

[0240] Step S4: using laser or etching slurry to remove BSG in a specific area according to a specific pattern to expose the polysilicon layer;

[0241] Step S5: removing the polysilicon layer exposed in step S4 by alkaline polishing;

[0242] In some other embodiments of the present invention, the polysilicon layer exposed in step S4 is removed by alkali polishing to form a polished morphology, while the area where BSG is not removed is retained, thereby forming a height difference (GAP), the GAP range is 0.1-0.3μm, and the remaining thickness of BSG in the unremoved area is 10-30nm.

[0243] Further, with respect to the back structure B-TBC-1 of the specific TBC cell provided in Example 1, the average height difference (GAP) formed in this example is 0.15 μm, wherein the average remaining thickness of the BSG in the unremoved area is 20 nm.

[0244] Step S6: depositing a tunneling oxide layer and a polysilicon layer on the surface of the specific area after being processed in step S5;

[0245] In some other embodiments of the present invention, a tunneling oxide layer (SiO2) and a polysilicon layer are deposited on the back side 200 of the base silicon wafer after the treatment in step S5 by using an LPCVD device, wherein the tunneling oxide layer has a thickness of 0.5-2.5 nm and a deposition temperature of 590-650° C., and the polysilicon layer has a thickness of 30-300 nm and a deposition temperature of 590° C.-630° C.;

[0246] Further, with respect to the back structure B-TBC-1 of the specific TBC cell provided in Example 1, the deposition temperature of the tunneling oxide layer and the polysilicon layer deposited by the LPCVD equipment on the back side 200 of the base silicon wafer after the treatment in step S5 is 610°C.

[0247] Step S7: performing doping by thermal diffusion to form a second doped polysilicon layer with a doped oxide layer in the specific region;

[0248] In some other embodiments of the present invention, the base silicon wafer 1 after the treatment in step S6 is placed in a diffusion furnace to achieve N-type doping, the diffusion source is POCl3 (phosphorus oxychloride), and after diffusion, a doped oxide layer with a thickness of 40-60nm is formed, and a thickness of 30nm~300nm and a doping concentration of 1E20atom / cm 3 ~1E21tom / cm 3 The second doped polysilicon layer.

[0249] Further, with regard to the back structure B-TBC-1 of the specific TBC battery provided in Example 1, the base silicon wafer 1 processed in step S6 is placed in a diffusion furnace to achieve N-type doping. The diffusion source is POCl3. After diffusion, a doped oxide layer with a thickness of 55 nm is formed. The thickness and doping concentration are the same as the thickness and doping concentration of the second doped polysilicon layer 222 of the B-TBC-1 provided in the aforementioned Example 1.

[0250] Step S8: using laser or etching slurry to remove PSG in the first doped polysilicon layer and the second doped polysilicon layer according to a specific pattern;

[0251] Step S9: using chain acid etching to remove the second doped polysilicon on the area where the first doped polysilicon layer 212 is located on the back surface, and forming a groove between the area where the first doped polysilicon layer 212 is located and the area where the second doped polysilicon layer 22 is located;

[0252] In some other embodiments of the present invention, the back side 200 of the base silicon wafer is removed by chain acid etching, and the second doped polysilicon layer 222 of the first emitter region 210 is also removed synchronously, and grooves are formed in the first emitter region 210 and the second emitter region 220;

[0253] Step S10: depositing a passivation layer on the back side of the base silicon wafer;

[0254] Finally, with respect to the back structure B-TBC-1 of the specific TBC battery provided in Example 1, an isolation region 230 is formed at the groove;

[0255] In some other embodiments of the present invention, ALD or PECVD equipment is used to form a first passivation layer 214 with a thickness of 40-80 nm and a second passivation layer 224 with a thickness of 40-80 nm on the surface of the polysilicon layer on both sides of the groove on the back side 200 of the base silicon wafer.

[0256] Step S11: Printing and sintering on the back side 200 of the base silicon wafer to form a first metal electrode 213 and a second metal electrode 223 located in the first emitter region 210 and the second emitter region 220 respectively.

[0257] Comparative Example 1

[0258] This comparative example provides a back structure of a TBC battery (B-TBC-D1), and the back structure of the TBC battery is basically the same as the back structure of the TBC battery (B-TBC-1) in Example 1, with the only difference that the first doped polysilicon layer 212 is no longer divided into a high-concentration doping area 212a and a low-concentration doping area 212b, and the doping concentration of the first doped polysilicon layer 212 over its thickness D1 is the same as the doping concentration of the high-concentration doping area 212a in Example 1.

[0259] The preparation method of the back structure (B-TBC-D1) of the TBC battery in this comparative example is basically the same as that in Example 2, except for the deposition of the polysilicon layer in step S2;

[0260] The deposition conditions (temperature, pressure) of the polysilicon layer in this comparative example are the same as those in stage 1 of step S2 of Example 2, until the thickness reaches D1 of the back structure (B-TBC-1) of the TBC battery of Example 1.

[0261] Comparative Example 2

[0262] This comparative example provides a back structure of a TBC battery (B-TBC-D2), which is basically the same as the back structure of the TBC battery in Example 1 (B-TBC-1), except that the first doped polysilicon layer 212 is no longer divided into a high-concentration doping area 212a and a low-concentration doping area 212b, and the doping concentration of the entire first doped polysilicon layer 212 over its thickness D1 is the same as the doping concentration N1 of the low-concentration doping area 212b.

[0263] The preparation method of the back structure (B-TBC-D1) of the TBC battery in this comparative example is basically the same as that in Example 2, except for the deposition of the polysilicon layer in step S2;

[0264] The deposition pressure of the polysilicon layer in this comparative example is the same as that in stage 2 of step S2 of Example 2, and the temperature is kept constant at 550° C. until the thickness reaches D1 of the back structure (B-TBC-1) of the TBC battery in Example 1.

[0265] refer to Figure 6 As shown, the doping curves of the first doped polysilicon layer (ie, P-type polysilicon) of Example 1 and Comparative Examples 1 and 2 of the present invention are respectively shown.

[0266] Comparative Example 3

[0267] This comparative example provides a back structure of a TBC cell (B-TBC-D3). The back structure of the TBC cell is basically the same as the back structure of the TBC cell (B-TBC-1) in Example 1, except that the first doped polysilicon layer 212 is no longer divided into a high-concentration doped region 212a and a low-concentration doped region 212b, and the doping concentration of the entire first doped polysilicon layer 212 over its thickness is higher than the doping concentration of the high-concentration doped region 212a, which is 7E19atom / cm 3 At the same time, the thickness of the first doped polysilicon layer 212 is no longer D1, but the same as the thickness of the high-concentration doped region 212a (D1-D2).

[0268] The preparation method of the back structure (B-TBC-D1) of the TBC battery in this comparative example is basically the same as that in Example 2, except for the deposition of the polysilicon layer in step S2;

[0269] The polysilicon layer deposition conditions (temperature, pressure) in this comparative example were explored to be the optimal values ​​of temperature 595° C. and pressure 230 mTorr until the thickness reached the corresponding thickness.

[0270] Comparative Example 4

[0271] This comparative example provides a back structure of a TBC cell (B-TBC-D4), which is basically the same as the back structure of the TBC cell (B-TBC-1) in Example 1, except that the doping concentration of the low-concentration doped region 212b of the first doped polysilicon layer 212 does not change over its thickness, but is basically the same concentration of 3E19atom / cm 3 .

[0272] Example 3

[0273] This embodiment provides a back structure of a TBC battery (B-TBC-3), which is basically the same as the back structure of the TBC battery in Example 1 (B-TBC-1), except that the thickness ratio of the first doped polysilicon layer 212 and its low-concentration doped region 212b is D1 / D2=1.5.

[0274] Example 4

[0275] This embodiment provides a back structure of a TBC battery (B-TBC-4), which is basically the same as the back structure of the TBC battery in Example 1 (B-TBC-1), except that the thickness ratio of the first doped polysilicon layer 212 and its low-concentration doped region 212b is D1 / D2=12.

[0276] Example 5

[0277] The present embodiment provides a back structure of a TBC battery (B-TBC-5), and the back structure of the TBC battery is basically the same as the back structure of the TBC battery in Example 1 (B-TBC-1), and the only difference is the ratio of the doping concentrations N1 and N2 of the low-concentration doping region 212b of the first doped polysilicon layer 212. In the present embodiment, N2 / N1=1 (the requirement of N2 / N1≥1.25 is no longer met).

[0278] Example 6

[0279] This embodiment also provides a TBC battery. For the sake of convenience, only the parts related to the embodiment of the present invention are shown. Figure 2~Figure 4 shown.

[0280] The TBC cell comprises: a base silicon wafer 100;

[0281] A backside structure as described in Embodiment 1 disposed on the backside 200 of the base silicon wafer;

[0282] A third passivation layer 110 with a thickness of 50-100 nm is provided on the front side 100 of the base silicon wafer, and at the same time satisfies the reflectivity of less than 2%; further, with respect to the specific TBC battery (TBC-1) provided in this embodiment, the thickness of the third passivation layer 110 is 75 nm. In principle, the composition and structure of the third passivation layer 110 may be the same as or different from the first passivation layer 214 (or the second passivation layer 224), and corresponding adjustments may be made as needed. Specifically in this embodiment, the composition and structure of the third passivation layer 110 are exactly the same as those of the first passivation layer 214 (or the second passivation layer 224). Regarding the preparation of the TBC battery in this embodiment:

[0283] The preparation method of the TBC battery specifically comprises the steps of:

[0284] A1~A8, A11 are the same as steps S1~S8, S11 in Example 2.

[0285] A9, using chain acid etching to remove the plating on the front side 100 of the base silicon wafer, and then placing it in a groove type texturing tank to complete texturing, so that the front side 100 of the base silicon wafer forms a pyramid-shaped texturing surface, and in addition, it has the same function as S9 in Example 2;

[0286] A10, depositing a first passivation layer 214 and a second passivation layer 224 on the back side of the base silicon wafer 1, and depositing a third passivation layer 100 on the front side of the base silicon wafer 1;

[0287] A third passivation layer 110 is formed on the front surface of the base silicon wafer 100 by means of ALD and PECVD. In addition, the third passivation layer 110 has the same function as step S10 in embodiment 2.

[0288] Based on the back structure of the TBC battery described in this embodiment and in the above-mentioned embodiment 1, a TBC battery (TBC-1) was prepared in this embodiment:

[0289] In addition, based on the back structures of the TBC batteries of Comparative Examples 1 to 4 and Examples 3 to 5, the following TBC batteries were prepared in this Example:

[0290] With Figure 1 As shown, a TBC battery (TBC-D1) having a back structure of the TBC battery of Comparative Example 1;

[0291] A TBC battery (TBC-D2) having a backside structure of the TBC battery of Comparative Example 2;

[0292] A TBC battery (TBC-D3) having a back side structure of the TBC battery of Comparative Example 3;

[0293] A TBC battery (TBC-D4) having a back side structure of the TBC battery of Comparative Example 4;

[0294] A TBC battery (TBC-3) having the back side structure of the TBC battery of Example 3;

[0295] A TBC battery (TBC-4) having the back side structure of the TBC battery of Example 4;

[0296] A TBC battery (TBC-5) having the back side structure of the TBC battery of Example 5;

[0297] Table 1. Performance and yield of various TBC batteries

[0298]

[0299] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The back structure of the TBC battery is characterized by: The back structure includes a first emission region, an isolation region, and a second emission region located on the back of the base silicon wafer. The first emitter region includes a first tunneling oxide layer, a first doped polysilicon layer, a passivation layer and a first metal electrode stacked on the back of the base silicon wafer, and the first metal electrode passes through the passivation layer and contacts the first doped polysilicon layer; The second emitter region includes a second tunneling oxide layer, a second doped polysilicon layer, a passivation layer and a second metal electrode stacked on the back of the base silicon wafer, and the second metal electrode passes through the passivation layer and contacts the second doped polysilicon layer; The isolation region is disposed between the first emission region and the second emission region; Wherein, the first doped polysilicon layer includes a high-concentration doping region and a low-concentration doping region; In the direction toward the base silicon wafer, the doping concentration of the low-concentration doping region increases from N1 to N2 in thickness, and the highest doping concentration N2 of the low-concentration doping region does not exceed the doping concentration of the high-concentration doping region; The high-concentration doping region is located on a side close to the back side of the base silicon wafer, and the first metal electrode passes through the low-concentration doping region and contacts the high-concentration doping region; The doping concentration of the high concentration doping area is 5 E19atom / cm 3 ~1E20tom / cm 3 ; The doping concentration N1 of the low-concentration doping area is 1E19atom / cm 3 ~4E19atom / cm 3 The doping concentration N2 of the low-concentration doping area is 5E19atom / cm 3 ~1E20 atoms / cm 3 ; The N2 / N1≥1.

25.

2. The back structure of the TBC battery according to claim 1, characterized in that: The thickness of the first doped polysilicon layer is D1, the thickness of the low-concentration doping region is D2, the thickness of the high-concentration doping region is D1-D2, and 2<D1 / D2<10 is satisfied.

3. The back structure of the TBC battery according to claim 2, characterized in that: The thickness of the first doped polysilicon layer is D1, and satisfies 50nm≤D1≤400nm; The thickness of the low-concentration doping region is D2, and satisfies 10nm<D2<150nm.

4. The back structure of the TBC battery according to claim 2, characterized in that: The thickness of the second doped polysilicon layer is 30-300 nm, and the doping concentration of the second doped polysilicon layer is 1E20 atom / cm 3 ~1E21tom / cm 3 .

5. The back side structure of a TBC battery according to any one of claims 1 to 4, characterized in that: The thickness of the first tunnel oxide layer is 0.5-2.5 nm; and / or, The thickness of the second tunneling oxide layer is 0.5-2.5 nm; and / or, The thickness of the passivation layer is 40-80 nm.

6. The back side structure of a TBC battery according to any one of claims 1 to 4, characterized in that: The depth of the isolation region is 0.05-3 μm.

7. A method for preparing a back surface structure of a TBC battery according to any one of claims 1 to 6, characterized in that: include: Step S1: polishing the surface of the base silicon wafer; Step S2: firstly depositing a tunnel oxide layer and then depositing a polysilicon layer on the surface treated in step S1; The polysilicon layer deposition includes a first stage and a second stage; the deposition temperature of the first stage is greater than the deposition temperature of the second stage; and / or, the deposition pressure in the first stage is less than the deposition pressure in the second stage; Step S3: performing doping by thermal diffusion to form a first doped polysilicon layer with a doped oxide layer; Step S4: removing the doped oxide layer in a specific area by laser or etching to expose the polysilicon layer; Step S5: removing the polysilicon layer exposed in step S4 by alkaline polishing; Step S6: depositing a tunneling oxide layer and a polysilicon layer on the surface of the specific area processed in step S5; Step S7: performing doping by thermal diffusion to form a second doped polysilicon layer with a doped oxide layer in the specific area; Step S8: removing the doped oxide in the first doped polysilicon layer region and the doped oxide in the second doped polysilicon layer region by using laser or etching; Step S9: removing the second doped polysilicon on the area where the first doped polysilicon layer is located on the back side of the base silicon wafer, and forming a groove between the area where the first doped polysilicon layer is located and the area where the second doped polysilicon layer is located; Step S10: depositing a passivation layer on the back side of the base silicon wafer; Step S11: Printing and sintering the back side of the base silicon wafer to form a first metal electrode and a second metal electrode.

8. The method for preparing the back structure of a TBC battery according to claim 7, characterized in that: In step S2, the surface deposition of the polysilicon layer includes stage one and stage two; The deposition temperature of the first stage is 580-600°C; The deposition temperature of the second stage is 550-580°C; and / or, The deposition pressure in the first stage is 150-250 mTorr; The deposition pressure in the second stage is 200-400 mTorr.

9. The method for preparing the back structure of a TBC battery according to claim 7 or 8, characterized in that: In step S2, during the deposition process of the stage 1, the deposition temperature is kept constant; During the deposition process of the second stage, the deposition temperature is gradually reduced from 580° C. to 550° C.; and / or, During the deposition process of the first stage, the deposition pressure is kept constant; During the deposition process of the second stage, the deposition pressure is constant or gradually increases.

10. TBC battery, characterized in that include: Base silicon wafer; A back contact structure disposed on the back side of the base silicon wafer, wherein the back contact structure is the back side structure of the TBC battery according to any one of claims 1 to 6, or is a back contact structure prepared by the method for preparing the back side structure of the TBC battery according to any one of claims 7 to 9; A third passivation layer is arranged on the front side of the base silicon wafer.

11. A method for preparing a TBC battery as claimed in claim 10, characterized in that: include: Step A1: polishing the surface of the base silicon wafer; Step A2: firstly depositing a tunnel oxide layer and then depositing a polysilicon layer on the surface treated in step A1; The polysilicon layer deposition includes a first stage and a second stage; the deposition temperature of the first stage is greater than the deposition temperature of the second stage; and / or, the deposition pressure in the first stage is less than the deposition pressure in the second stage; Step A3: performing doping by thermal diffusion to form a first doped polysilicon layer with a doped oxide layer; Step A4: removing the doped oxide layer in a specific area by laser or etching to expose the polysilicon layer; Step A5: removing the polysilicon layer exposed in step A4 by alkaline polishing; Step A6: depositing a tunneling oxide layer and a polysilicon layer on the surface of the specific area treated in step A5; Step A7: performing doping by thermal diffusion to form a second doped polysilicon layer with a doped oxide layer in the specific region; Step A8: removing the doped oxide in the first doped polysilicon layer region and the doped oxide in the second doped polysilicon layer region by using laser or etching; Step A9: etching and texturing the front side of the base silicon wafer; Removing the second doped polysilicon on the area where the first doped polysilicon layer is located on the back side of the base silicon wafer, and forming a groove between the area where the first doped polysilicon layer is located and the area where the second doped polysilicon layer is located; Step A10: depositing a passivation layer on the front and back sides of the base silicon wafer; Step A11: Printing and sintering to form a first metal electrode and a second metal electrode on the back side of the base silicon wafer.

12. The method for preparing a TBC battery according to claim 11, characterized in that: In step A2, the surface deposition of the polysilicon layer includes stage one and stage two; The deposition temperature of the first stage is 580-600°C; The deposition temperature of the second stage is 550-580°C; and / or, The deposition pressure in the first stage is 150-250 mTorr; The deposition pressure in the second stage is 200-400 mTorr.

13. The method for preparing a TBC battery according to claim 11 or 12, characterized in that: In step A2, during the deposition process of the stage 1, the deposition temperature is kept constant; During the deposition process of the second stage, the deposition temperature is gradually reduced from 580° C. to 550° C.; and / or, During the deposition process of the first stage, the deposition pressure is kept constant; During the deposition process of the second stage, the deposition pressure is constant or gradually increases.

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