Silicon-based back-contact heterojunction solar cell and preparation method thereof, and battery assembly

Abstract

The present invention belongs to the technical field of solar cells, and specifically relates to a silicon-based back-contact heterojunction solar cell and a preparation method and a cell assembly thereof. The silicon-based back-contact heterojunction solar cell adds a layer of ultra-thin oxygen-doped amorphous silicon to the amorphous silicon passivation layer, thereby avoiding the single crystal epitaxial growth affecting the film quality and passivation effect of the amorphous silicon passivation layer when the amorphous silicon passivation layer is deposited. At the same time, an oxygen-doped amorphous silicon layer is prepared on the outermost layer of the P-type amorphous silicon layer as a sacrificial layer. In addition, boron and oxygen easily form a stable structure, so the oxygen-doped amorphous silicon layer can well cover the P-type amorphous silicon layer to prevent boron from overflowing, thereby realizing that the amorphous silicon passivation layer and the P-type amorphous silicon layer are deposited in the same PECVD system, thereby reducing a set of PECVD systems and reducing equipment costs.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a silicon-based back-contact heterojunction solar cell and a preparation method and a cell assembly thereof. Background Art

[0002] In the manufacturing process of existing silicon-based back-contact heterojunction solar cells, plate-type PECVD equipment is required to deposit an amorphous silicon passivation layer and a doped semiconductor layer. However, if the amorphous silicon passivation layer and the doped semiconductor layer are deposited using the same carrier, there is a problem of cross-contamination. In particular, the boron in P-type amorphous silicon will seriously affect the passivation effect on the silicon wafer surface. In addition, epitaxy is easily generated when the amorphous silicon passivation layer is deposited on the surface of single crystal silicon, and the single crystal epitaxial growth will also affect the passivation effect of the amorphous silicon passivation layer on the single crystal silicon surface.

[0003] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0004] The purpose of the present invention is to overcome the problem that when an amorphous silicon passivation layer is deposited on the single crystal silicon surface of the existing silicon-based back contact heterojunction solar cell, single crystal silicon is prone to epitaxy, thereby affecting the quality of amorphous silicon and the passivation effect of the single silicon wafer interface, and the technical problem that the P-type amorphous silicon deposition system has serious boron contamination, resulting in the need to separate the amorphous silicon passivation layer and the P-type amorphous silicon into two sets of PECVD systems for separate deposition.

[0005] In order to achieve the above object, an embodiment of the present invention provides a silicon-based back-contact heterojunction solar cell, comprising:

[0006] A silicon wafer having a front side and a back side;

[0007] A first semiconductor layer is arranged on the back side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and a doped polysilicon layer sequentially formed on the silicon wafer;

[0008] The first semiconductor layer is separated by a plurality of second semiconductor opening regions, the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with a second semiconductor layer, and the second semiconductor layer is composed of an ultra-thin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer and a P-type amorphous silicon layer;

[0009] A passivation layer and an anti-reflection layer are sequentially arranged on the front side of the silicon wafer, wherein the passivation layer is any one or more materials selected from aluminum oxide, silicon oxide, amorphous silicon or microcrystalline silicon, and the anti-reflection layer is at least one selected from silicon nitride, silicon oxynitride and silicon oxide;

[0010] The thickness of the ultra-thin oxygen-doped amorphous silicon layer is 0.2-1 nm, and the oxygen-doped content is 3%-30%.

[0011] Optionally, a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer;

[0012] The first semiconductor opening region and the second semiconductor layer are both covered with a transparent conductive film layer, and an isolation groove is arranged between the adjacent first semiconductor opening region and the second semiconductor opening region; the isolation groove separates the transparent conductive film layer located in the first semiconductor opening region from the transparent conductive film layer located on the second semiconductor layer.

[0013] Optionally, the thickness of the tunneling silicon oxide layer is 1~2nm, the thickness of the doped polysilicon layer is 50~150nm, and the thickness of the amorphous silicon passivation layer is 3-10nm; the ratio of the thickness of the amorphous silicon passivation layer to the thickness of the ultra-thin oxygen-doped amorphous silicon layer is 3~50:1.

[0014] Optionally, the anti-reflection layer has a thickness of 70 nm to 150 nm.

[0015] Optionally, a textured surface is formed on the front side of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening area, the second semiconductor layer and the third semiconductor layer fill the textured surfaces in corresponding areas respectively, and the third semiconductor layer includes the passivation layer and the anti-reflection layer.

[0016] Optionally, the thickness of the amorphous silicon passivation layer is 3-10 nm, the thickness of the P-type amorphous silicon layer is 5-15 nm, and the boron doping concentration in the P-type amorphous silicon layer is 5e18 cm-3-4e20 cm-3.

[0017] Optionally, the silicon-based back-contact heterojunction solar cell further includes: a metal electrode; the metal electrode is arranged on the transparent conductive film layer in the first semiconductor opening region and the second semiconductor opening region.

[0018] Optionally, an ultra-thin oxygen-doped amorphous silicon layer is formed between the passivation layer and the silicon wafer.

[0019] In a second aspect, an embodiment of the present invention further provides a battery assembly, which includes the silicon-based back-contact heterojunction solar cell as described in the first aspect.

[0020] In a third aspect, an embodiment of the present invention further provides a method for preparing a silicon-based back-contact heterojunction solar cell, which is used to prepare the silicon-based back-contact heterojunction solar cell as described in the first aspect, and the method for preparing the silicon-based back-contact heterojunction solar cell comprises the following steps:

[0021] S01, providing a silicon wafer;

[0022] S02, sequentially preparing a tunneling silicon oxide layer and a doped polysilicon layer on the back side of the silicon wafer to obtain a first semiconductor layer;

[0023] S03, preparing a mask layer on the surface of the first semiconductor layer;

[0024] S04, removing a portion of the mask layer and a corresponding portion of the first semiconductor layer to form alternately arranged second semiconductor opening regions;

[0025] S05, removing the remaining mask layer, N-type doped polycrystalline layer and tunneling silicon oxide layer in the second semiconductor opening region by texturing and cleaning, and forming a texture surface on the front side of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening region, and then removing part or all of the mask layer on the back side of the silicon wafer located outside the second semiconductor opening region;

[0026] S06, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer, and preparing an ultra-thin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer, a P-type amorphous silicon layer, and an oxygen-doped amorphous silicon layer in sequence on the back side of the silicon wafer;

[0027] When preparing the ultra-thin oxygen-doped amorphous silicon layer on the back of the silicon wafer, silane and carbon dioxide or other gases that can provide an oxygen source are introduced; wherein the ratio of carbon dioxide to silane is 3-30:100, the deposition power density is 10-100 mW / cm2, the gas pressure is 30-150 Pa, the thickness of the ultra-thin oxygen-doped amorphous silicon layer is 0.2-1 nm, and the oxygen content is 3-30%; when preparing the oxygen-doped amorphous silicon layer, nitrous oxide or other gases that can provide an oxygen source, silane and hydrogen are introduced, wherein the ratio of nitrous oxide, silane and hydrogen is 1-10:1:0-10, the deposition power density is 5-50 mW / cm2, the gas pressure is 30-150 Pa, the oxygen content is 20-70%, and the hydrogen content is 0-10%;

[0028] S07, etching an opening on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region, wherein the first semiconductor opening region exposes the doped polysilicon layer;

[0029] S08, removing the residual oxygen-doped amorphous silicon layer on the surface of the P-type amorphous silicon layer, and then depositing a transparent conductive film layer on the back of the obtained silicon wafer;

[0030] S09, opening the transparent conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0031] S10, forming metal electrodes on the transparent conductive film layer in the first semiconductor opening region and on the transparent conductive film layer in the second semiconductor opening region.

[0032] The embodiments of the present invention have at least the following beneficial effects:

[0033] The silicon-based back-contact heterojunction solar cell and its preparation method provided by the embodiment of the present invention add a layer of ultra-thin oxygen-doped amorphous silicon to the amorphous silicon passivation layer, thereby avoiding the single crystal epitaxial growth affecting the film quality and passivation effect of the amorphous silicon passivation layer when depositing the amorphous silicon passivation layer. At the same time, an oxygen-doped amorphous silicon layer is prepared as a sacrificial layer on the outermost layer of the P-type amorphous silicon layer. In addition, boron and oxygen easily form a stable structure, so the oxygen-doped amorphous silicon layer can well cover the P-type amorphous silicon layer to prevent boron from overflowing, thereby achieving the deposition of the amorphous silicon passivation layer and the P-type amorphous silicon layer in the same PECVD system, thereby reducing a set of PECVD systems and reducing equipment costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 It is a schematic diagram of the internal structure of a silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention.

[0036] Figure 2 A process flow chart of a method for preparing a silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention;

[0037] Figure 3 A process structure diagram corresponding to steps S01 to S05 in a method for preparing a silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention;

[0038] Figure 4 A process structure diagram corresponding to step S06 in a method for preparing a silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention;

[0039] Figure 5 A process structure diagram corresponding to step S07 in a method for preparing a silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention;

[0040] Figure 6 A process structure diagram corresponding to step S08 in a method for preparing a silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention;

[0041] Figure 7This is a process structure diagram corresponding to steps S08 to S10 in a method for preparing a silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0043] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0044] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0045] The first aspect, such as Figure 1 As shown, an embodiment of the present invention provides a silicon-based back-contact heterojunction solar cell, including: a silicon wafer 10, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The silicon wafer 10 has a front side and a back side, the front side refers to the light-receiving side of the silicon wafer 10, and the back side is the opposite back side of the light-receiving side. Figure 1 The upward surface of the silicon wafer 10 is the back surface, and the downward surface is the front surface. In the embodiment of the present invention, the area close to the silicon wafer 10 is usually the inside, and the area far from the silicon wafer 10 is the outside. The silicon wafer 10 is N-type or P-type, preferably N-type.

[0046] Specifically, the first semiconductor layer is arranged on the back side of the silicon wafer 10, and the first semiconductor layer includes a tunneling silicon oxide layer 11 and a doped polysilicon layer 12 sequentially formed on the silicon wafer 10, that is, the tunneling silicon oxide layer 11 is closer to the back side of the silicon wafer 10 than the doped polysilicon layer 12. Optionally, the doped polysilicon layer 12 is composed of an intrinsic polysilicon layer and a phosphorus-doped polysilicon layer, the intrinsic polysilicon layer is closer to the back side of the silicon wafer 10 than the phosphorus-doped polysilicon layer, and the doped polysilicon layer 12 is preferably N-type.

[0047] In the embodiment of the present invention, a plurality of openings are formed on the first semiconductor layer by an etching process, thereby obtaining a second semiconductor opening region W2, that is, the first semiconductor layer is separated by a plurality of second semiconductor opening regions W2. The second semiconductor layer covers the second semiconductor opening region W2 (including the sidewalls of the second semiconductor opening region W2) and the surface of the first semiconductor layer around the second semiconductor opening region W2. A first semiconductor opening region W1 is provided between adjacent second semiconductor opening regions W2, and the first semiconductor opening region W1 separates the second semiconductor layer. The second semiconductor layer is composed of an ultra-thin oxygen-doped amorphous silicon layer 15B, an amorphous silicon passivation layer 15 and a P-type amorphous silicon layer 16, and the amorphous silicon passivation layer 14 is closer to the back of the silicon wafer 10 than the P-type amorphous silicon layer.

[0048] Optionally, the thickness of the amorphous silicon passivation layer 14 is 3-10 nm, the thickness of the P-type amorphous silicon layer is 5-15 nm, and the boron doping concentration in the P-type amorphous silicon layer is 5e18 cm -3 ~4e20 cm -3 .

[0049] In order to ensure the passivation effect of the amorphous silicon passivation layer 14 on the silicon wafer 10, an ultra-thin oxygen-doped amorphous silicon layer 15B is arranged before the amorphous silicon passivation layer 14 of the second semiconductor layer, and the thickness of the ultra-thin oxygen-doped amorphous silicon layer 15B is 0.2~1nm, and the oxygen content is 3%~30%. Optionally, the thickness of the tunneling silicon oxide layer 11 is 1-2nm, the thickness of the doped polysilicon layer 12 is 50-150nm, and the ratio of the thickness of the amorphous silicon passivation layer 15 to the thickness of the ultra-thin oxygen-doped amorphous silicon layer 15B is 3-50:1, which comprehensively considers the passivation effect of the silicon wafer interface and the effect of the tunneling transmission of carriers, and can obtain better passivation, while not increasing the series resistance to affect the FF.

[0050] Optionally, on the front side of the silicon wafer 10, an ultra-thin oxygen-doped amorphous silicon layer 14B is also formed between the third semiconductor layer (including the passivation layer 14 and the anti-reflection layer 17) and the silicon wafer 10. The ultra-thin oxygen-doped amorphous silicon layer 14B and the ultra-thin oxygen-doped amorphous silicon layer 15B have the same process parameters and thickness. The ultra-thin oxygen-doped amorphous silicon layer 14B has a thickness of 0.2-1 nm and an oxygen-doped content of 3%-30%. The ultra-thin oxygen-doped amorphous silicon layer 14B is equivalent to separating the passivation layer from the front side of the silicon wafer 10.

[0051] Optionally, the thickness of the passivation layer 14 is 3-10 nm, and the ratio of the thickness of the passivation layer 14 to the thickness of the ultra-thin oxygen-doped amorphous silicon layer 14B is 3-50:1.

[0052] In some embodiments, a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer; the first semiconductor opening region and the second semiconductor layer are both covered with a transparent conductive film layer 18, and an isolation groove is provided between adjacent first semiconductor opening regions and second semiconductor opening regions; the isolation groove separates the transparent conductive film layer 18 located in the first semiconductor opening region from the transparent conductive film layer 18 located on the second semiconductor layer.

[0053] Optionally, the width of the first semiconductor opening region is 0.1 mm to 0.3 mm; the width of the second semiconductor opening region is 0.3 mm to 0.6 mm, and the width of the isolation trench is 30 um to 200 um.

[0054] In some embodiments, continue to refer to Figure 1 , the silicon-based back-contact heterojunction solar cell also includes: an anti-reflection layer 17; the anti-reflection layer 17 is arranged on the side of the passivation layer away from the silicon wafer 10. The anti-reflection layer 17 is mainly used to reduce the reflection of light, thereby improving the photoelectric conversion efficiency. The thickness of the anti-reflection layer 17 is generally 80mm~100mm. If it is too thick, it is not conducive to the penetration of light, and if it is too thin, the reflection effect of the incident light is not good. Optionally, the anti-reflection layer 17 is composed of at least one of a silicon nitride anti-reflection layer, a silicon oxynitride layer, a silicon oxynitride anti-reflection layer and a silicon oxide layer.

[0055] A velvet surface is formed on the front side of the silicon wafer 10 and the surface of the silicon wafer 10 located in the second semiconductor opening area. The second semiconductor layer and the third semiconductor layer fill the velvet surfaces in the corresponding areas respectively. The velvet surface is formed by an acid cleaning process, which can not only remove excess film layer material, but also help to increase the bonding strength between the film layers.

[0056] Optionally, continue to Figure 1 The silicon-based back-contact heterojunction solar cell provided in an embodiment of the present invention further includes: a metal electrode 19; the metal electrode 19 is arranged on the transparent conductive film layer 18 in the first semiconductor opening area and the second semiconductor opening area, wherein the metal electrode 19 in the first semiconductor opening area and the metal electrode 19 in the second semiconductor opening area correspond to different polarities respectively.

[0057] In a second aspect, an embodiment of the present invention further provides a battery assembly, which includes a silicon-based back-contact heterojunction solar cell as described in any one of the first aspects. In a third aspect, an embodiment of the present invention further provides a method for preparing a silicon-based back-contact heterojunction solar cell, which is used to prepare a silicon-based back-contact heterojunction solar cell as described in the first aspect. Figure 2 As shown, the method for preparing a silicon-based back-contact heterojunction solar cell comprises the following steps:

[0058] S01. Provide a silicon wafer 10.

[0059] Optionally, step S01 may also include other conventional operations, such as double-sided polishing and optional cleaning of the silicon wafer 10. The silicon wafer 10 is preferably an N-type single crystal silicon wafer 10. The silicon wafer 101 may be a Czochralski single crystal silicon wafer 10 or a cast single crystal silicon wafer 10.

[0060] S02. A tunneling silicon oxide layer 11 and a doped polysilicon layer 12 are sequentially prepared on the back side of the silicon wafer 10 to obtain a first semiconductor layer.

[0061] Optionally, the first semiconductor layer can be formed by in-situ doping deposition annealing by tubular PECVD, LPCVD or PVD, preferably using tubular PECVD in-situ doping. In the first stage, laughing gas is introduced, the glow is turned on, and a tunneling silicon oxide layer 11 is formed by chemical reaction. The reaction temperature of the first stage is 400~550℃, the reaction pressure is 100~2000mtorr (mitorr), the time is 10~60 seconds, and the thickness of the tunneling silicon oxide layer 11 is 1~2nm; in the second stage, silane, phosphine and hydrogen are introduced, the glow is turned on, and a phosphorus-doped polysilicon layer is formed by chemical reaction. The reaction temperature of the second stage is 400~550℃, the reaction time is 400~1200 seconds, the reaction pressure is 1000~4000mtorr, and the thickness of the phosphorus-doped polysilicon layer is 80~100nm, which is then formed by annealing and crystallization at 900℃.

[0062] S03, preparing a mask layer 13 on the surface of the first semiconductor layer.

[0063] Optionally, a mask layer 13 is grown on the surface of the cleaned first semiconductor layer. The mask layer 13 may be silicon nitride, silicon oxide or silicon oxynitride. Preferably, silicon nitride is deposited as the mask layer 13 by tubular PECVD with a thickness of 50 to 200 nm, and hydrofluoric acid is used to remove the silicon nitride coated on the front side.

[0064] S04, removing a portion of the mask layer 13 and a corresponding portion of the first semiconductor layer to form alternately arranged second semiconductor opening regions.

[0065] Optionally, see Figure 3 , an opening is etched on the back of the silicon wafer 10 by laser or mask etching to form a second semiconductor opening region W2. The width of the second semiconductor opening region W2 is 0.3-0.6 mm, and the mask layer 13, the N-type doped polycrystalline layer and the tunneling silicon oxide layer 11 in the second semiconductor opening region W2 are etched away.

[0066] S05. Remove the remaining mask layer 13, N-type doped polycrystalline layer and tunneling silicon oxide layer 11 in the second semiconductor opening area by texturing and cleaning, and at the same time form a texture surface on the front side of the silicon wafer 10 and the surface of the silicon wafer 10 located in the second semiconductor opening area, and then remove all or part of the mask layer 13 on the back side of the silicon wafer 10 outside the second semiconductor opening area.

[0067] Optionally, continue to Figure 3 The mask layer 13 outside the second semiconductor opening region W2 on the back side of the silicon wafer 10 is removed by hydrofluoric acid cleaning.

[0068] S06, forming a passivation layer 14 and an anti-reflection layer 17 on the front side of the silicon wafer 10 in sequence; and preparing an ultra-thin oxygen-doped amorphous silicon layer 15B, an amorphous silicon passivation layer 15, a P-type amorphous silicon layer 16, and an oxygen-doped amorphous silicon layer 16B on the back side of the silicon wafer 10 in sequence, for details, see Figure 4 When preparing the ultra-thin oxygen-doped amorphous silicon layer 15B, silane and carbon dioxide or other gases that can provide an oxygen source are introduced; wherein the ratio of carbon dioxide to silane is 3-30:100, and the deposition power density is 10-100 mW / cm 2 , the air pressure is 30~150pa, and the oxygen content is 3~30%.

[0069] When preparing the oxygen-doped amorphous silicon layer 16B, laughing gas or other gas that can provide an oxygen source, silane and hydrogen are introduced, wherein the ratio of laughing gas, silane and hydrogen is 1-5:1:0-10, and the deposition power density is 5-50 mW / cm 2 , the gas pressure is 30~150pa, the oxygen content is 20~70%, and the hydrogen content is 0~10%.

[0070] Optionally, the ultra-thin oxygen-doped amorphous silicon layer 15B, the amorphous silicon passivation layer 15 and the P-type amorphous silicon layer 16 and the oxygen-doped amorphous silicon layer 16B on the back of the silicon wafer 10 are completed in the same system without breaking the air or replacing the carrier.

[0071] Optionally, the passivation layer 14 on the front side of the silicon wafer may be any one or more materials selected from aluminum oxide, silicon oxide, amorphous silicon or microcrystalline silicon, and the anti-reflection layer may be at least one selected from silicon nitride, silicon oxynitride and silicon oxide.

[0072] S07 , etching an opening on the back side of the silicon wafer 10 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, wherein the first semiconductor opening region exposes the doped polysilicon layer 12 .

[0073] Optionally, see Figure 5, using laser or mask etching, using the oxygen-doped amorphous silicon layer 16B as the mask layer 13 to etch an opening on the back of the silicon wafer 10, forming a first semiconductor opening region W1 spaced apart from the second semiconductor opening region W2, and then cleaning. The width of the first semiconductor opening region W1 is 0.1 mm to 0.3 mm. Optionally, the laser is an ultraviolet or green laser, and the pulse width is less than 50 ns.

[0074] S08 , removing the residual oxygen-doped amorphous silicon layer 16B on the surface of the P-type amorphous silicon layer, and then depositing a transparent conductive film layer 18 on the back side of the obtained silicon wafer 10 .

[0075] Specifically, see Figure 6 and Figure 7 In this embodiment, an oxygen-doped amorphous silicon layer 16B of a certain thickness is prepared on the P-type amorphous silicon layer of the second semiconductor layer. The oxygen-doped amorphous silicon layer 16B can be used as a mask layer 13 for preparing the first semiconductor opening area to protect other film layers below and avoid etching contamination. The oxygen-doped amorphous silicon layer is easy to remove, which is beneficial to improving process efficiency and saving production costs.

[0076] Optionally, a transparent conductive film layer 18 is deposited on the back side of the silicon wafer 10 by physical vapor deposition (PVD) or activated plasma deposition (RPD). The thickness of the transparent conductive film layer 18 is 30 nm to 120 nm. The material of the transparent conductive film layer 18 can be an indium oxide film doped with tin oxide, titanium oxide, zinc oxide or gallium oxide, or a zinc oxide film doped with aluminum oxide, gallium oxide or boron oxide.

[0077] S09 , opening the transparent conductive film layer 18 between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove.

[0078] Optionally, continue to Figure 7 An isolation groove is formed between the first semiconductor opening region and the second semiconductor region by laser or etching, and the width of the isolation groove is 30um~200um.

[0079] S10 , forming a metal electrode 19 on the transparent conductive film layer 18 in the first semiconductor opening region and on the transparent conductive film layer 18 in the second semiconductor opening region.

[0080] Optionally, continue to Figure 7 A first electrode is formed on the conductive film layer 18 of the first semiconductor region, and a second electrode is correspondingly formed on the conductive film layer 18 of the second semiconductor region. A silver gate electrode can be formed by a screen printing process and low-temperature sintering, or by electroplating. Preferably, a gate line electrode is formed by electroplating.

[0081] The method for preparing a silicon-based back-contact heterojunction solar cell in the embodiment of the present invention may further include other conventionally required steps, which may be selected according to actual needs and will not be described in detail here.

[0082] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0083] Example 1

[0084] A silicon-based back-contact heterojunction solar cell, the structure of which is as follows Figure 1 As shown, its preparation method is as follows Figure 2 As shown, including:

[0085] S01. Provide a silicon wafer 10.

[0086] S02. A tunneling silicon oxide layer and a doped polysilicon layer are sequentially prepared on the back side of the silicon wafer 10 to obtain a first semiconductor layer.

[0087] S03. Prepare a mask layer on the surface of the first semiconductor layer.

[0088] S04, removing a portion of the mask layer and a corresponding portion of the first semiconductor layer to form alternately arranged second semiconductor opening regions.

[0089] S05. Remove the remaining mask layer, N-type doped polycrystalline layer and tunneling silicon oxide layer in the second semiconductor opening region by texturing and cleaning, and simultaneously form a texturing surface on the front side of the silicon wafer 10 and the surface of the silicon wafer 10 located in the second semiconductor opening region.

[0090] S06, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer 10. Preparing an ultra-thin oxygen-doped amorphous silicon layer 15B, an amorphous silicon passivation layer 15, a P-type amorphous silicon layer 16, and an oxygen-doped amorphous silicon layer 16B on the back side of the silicon wafer 10; introducing silane and carbon dioxide into the ultra-thin oxygen-doped amorphous silicon layer 15B; wherein the ratio of carbon dioxide to silane is 15:100, and the deposition power density is 30 mW / cm 2 , the air pressure is 100pa, the thickness of the ultra-thin oxygen-doped amorphous silicon layer 15B is 0.5nm, the oxygen content is 15%, and the thickness of the amorphous silicon passivation layer 15 is 6nm; when preparing the oxygen-doped amorphous silicon layer 16B, laughing gas or other gas that can provide an oxygen source, silane and hydrogen are introduced, wherein the ratio of laughing gas, silane and hydrogen is 5:1:0, and the deposition power density is 10mW / cm 2 , the gas pressure is 100pa, the oxygen content is 65%, and the hydrogen content is 1%.

[0091] S07 , etching an opening on the back side of the silicon wafer 10 obtained in step S06 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, wherein the first semiconductor opening region exposes the doped polysilicon layer.

[0092] S08 , removing the residual oxygen-doped amorphous silicon layer 16B on the surface of the P-type amorphous silicon layer, and then depositing a transparent conductive film layer on the back side of the obtained silicon wafer 10 .

[0093] S09, making an opening on the transparent conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove.

[0094] S10, forming metal electrodes on the transparent conductive film layer in the first semiconductor opening region and on the transparent conductive film layer in the second semiconductor opening region.

[0095] Example 2

[0096] The method of Example 1 is referred to, except that in step S06, the thickness of the ultra-thin oxygen-doped amorphous silicon layer 15B is 0.2 nm, which is thinner than that of Example 1 and has a relatively poor effect in blocking epitaxial growth.

[0097] Example 3

[0098] The method of Example 1 is referred to, except that in step S06, the oxygen content of the ultra-thin oxygen-doped amorphous silicon layer 15B is 30%, and the conductivity is slightly worse than that of Example 1, thereby reducing the series resistance.

[0099] Example 4

[0100] The method of Example 1 is referred to, except that in step S06, the ratio of carbon dioxide to silane in the ultra-thin oxygen-doped amorphous silicon layer 15B is 3:100, the oxygen content is lower than that in Example 1, and the effect of blocking epitaxial growth is relatively poor.

[0101] Example 5

[0102] The method of Example 1 is followed, except that the deposition power density of the ultra-thin oxygen-doped amorphous silicon layer 15B in step S06 is 10 mW / cm 2 The power density is lower than that of Example 1, the quality of oxygen-doped amorphous silicon is poor, and the effect of blocking epitaxial growth is relatively poor.

[0103] Example 6

[0104] The method of Example 1 is referred to, except that in step S06, the ratio of the thickness of the amorphous silicon passivation layer 15 to the thickness of the ultra-thin oxygen-doped amorphous silicon layer 15B is 20:1.

[0105] Example 7

[0106] The method of Example 1 is referred to, except that in step S06, the oxygen doping content of the oxygen-doped amorphous silicon layer 16B is 35%, and the hydrogen doping content is 1%.

[0107] Example 8

[0108] The method of Example 1 is referred to, except that in step S06, the ratio of carbon dioxide, silane and hydrogen in the oxygen-doped amorphous silicon layer 16B is 3:1:0.

[0109] Comparative Example 1

[0110] The method of Example 1 is referred to, except that step S06 is not performed, that is, the first ultra-thin oxygen-doped amorphous silicon layer 15B is not prepared between the first semiconductor layer and the second semiconductor layer.

[0111] Comparative Example 2

[0112] The method of Example 1 is referred to, except that in step S06, the thickness of the ultra-thin oxygen-doped amorphous silicon layer 15B is 1.5 nm.

[0113] Comparative Example 3

[0114] The method of Example 1 is referred to, except that in step S06, the oxygen content of the ultra-thin oxygen-doped amorphous silicon layer 15B is 40%.

[0115] Comparative Example 4

[0116] The method of Example 1 is referred to, except that in step S06 , the ratio of carbon dioxide to silane in the ultra-thin oxygen-doped amorphous silicon layer 15B is 100:100.

[0117] Comparative Example 5

[0118] The method of Example 1 is referred to, except that in step S06 , the ratio of the thickness of the ultra-thin oxygen-doped amorphous silicon layer 15B to the thickness of the amorphous silicon passivation layer 15 is 1:60.

[0119] Comparative Example 6

[0120] The method of Example 1 is referred to, except that in step S06, the oxygen content of the oxygen-doped amorphous silicon layer 16B is 15%, and the hydrogen content is 1%.

[0121] Comparative Example 7

[0122] The method of Example 1 is referred to, except that in step S06, the ratio of carbon dioxide, silane and hydrogen in the oxygen-doped amorphous silicon layer 16B is 0.5:1:1.

[0123] Comparative Example 8

[0124] The method of Example 1 is followed, except that in step S06, the first ultra-thin oxygen-doped amorphous silicon layer 15B and the oxygen-doped amorphous silicon layer 16B are not prepared on the back of the silicon wafer 10, and the amorphous silicon passivation layer 15 and the P-type amorphous silicon layer 16 are prepared by two sets of PECVD.

[0125] Test Case

[0126] The silicon-based back-contact heterojunction solar cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. The unit of minority carrier lifetime is us, the unit of open circuit voltage Voc is V, the unit of cell conversion efficiency Eta is %, and the equipment cost is 100% with reference to Facility Example 1.

[0127] Table 1 Comparison of performance test results of various embodiments and comparative examples

[0128]

[0129] From the above results, it can be seen that, compared with the comparative example, the embodiment scheme of the present invention can reduce the investment in plate-type PECVD equipment, improve the passivation effect of silicon wafers, and help reduce equipment costs and improve battery conversion efficiency. Further, according to Examples 1 and 2 to 8, it can be seen that the preferred specific preparation method and specific battery structure scheme of the present invention can maintain a good passivation effect while not increasing the series resistance, which is more conducive to improving battery efficiency.

[0130] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0131] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0132] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. In the description of this specification, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a silicon-based back-contact heterojunction solar cell, comprising the following steps: S01, providing a silicon wafer; S02, sequentially preparing a tunneling silicon oxide layer and a doped polysilicon layer on the back side of the silicon wafer to obtain a first semiconductor layer; S03, preparing a mask layer on the surface of the first semiconductor layer; S04, removing a portion of the mask layer and a corresponding portion of the first semiconductor layer to form alternately arranged second semiconductor opening regions; S05, removing the remaining mask layer, N-type doped polycrystalline layer and tunneling silicon oxide layer in the second semiconductor opening region by texturing and cleaning, and forming a texture surface on the front side of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening region, and then removing part or all of the mask layer on the back side of the silicon wafer located outside the second semiconductor opening region; S06, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer, and preparing an ultra-thin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer, a P-type amorphous silicon layer, and an oxygen-doped amorphous silicon layer in sequence on the back side of the silicon wafer; When preparing the ultra-thin oxygen-doped amorphous silicon layer on the back of the silicon wafer, silane and carbon dioxide or other gases that can provide an oxygen source are introduced; wherein the ratio of carbon dioxide to silane is 3-30:100, and the deposition power density is 10-100 mW / cm 2 , the air pressure is 30-150 Pa, the thickness of the ultra-thin oxygen-doped amorphous silicon layer is 0.2-1 nm, the oxygen content is 3-30%, and the thickness of the amorphous silicon passivation layer is 3-10 nm; the ratio of the thickness of the amorphous silicon passivation layer to the thickness of the ultra-thin oxygen-doped amorphous silicon layer is 3-50:1; when preparing the oxygen-doped amorphous silicon layer, laughing gas or other gas that can provide an oxygen source, silane and hydrogen are introduced, wherein the ratio of laughing gas, silane and hydrogen is 1-10:1:0-10, and the deposition power density is 5-50 mW / cm 2 , gas pressure is 30~150pa, oxygen content is 20~70%, hydrogen content is 0~10%; S07, etching an opening on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region, wherein the first semiconductor opening region exposes the doped polysilicon layer; S08, removing the residual oxygen-doped amorphous silicon layer on the surface of the P-type amorphous silicon layer, and then depositing a transparent conductive film layer on the back side of the obtained silicon wafer; S09, making an opening on the transparent conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S10, forming metal electrodes on the transparent conductive film layer in the first semiconductor opening region and on the transparent conductive film layer in the second semiconductor opening region.

2. A silicon-based back-contact heterojunction solar cell, obtained based on the preparation method according to claim 1, characterized in that: The silicon-based back-contact heterojunction solar cell comprises: A silicon wafer having a front side and a back side; A first semiconductor layer is arranged on the back side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and a doped polysilicon layer sequentially formed on the silicon wafer; The first semiconductor layer is separated by a plurality of second semiconductor opening regions, the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with a second semiconductor layer, and the second semiconductor layer is composed of an ultra-thin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer and a P-type amorphous silicon layer; A passivation layer and an anti-reflection layer are sequentially arranged on the front side of the silicon wafer, wherein the passivation layer is any one or more materials selected from aluminum oxide, silicon oxide, amorphous silicon or microcrystalline silicon, and the anti-reflection layer is at least one selected from silicon nitride, silicon oxynitride and silicon oxide; The thickness of the ultra-thin oxygen-doped amorphous silicon layer is 0.2~1nm, and the oxygen content is 3%~30%; the thickness of the tunneling silicon oxide layer is 1~2nm, the thickness of the doped polysilicon layer is 50~150nm, and the thickness of the amorphous silicon passivation layer is 3-10nm; the ratio of the thickness of the amorphous silicon passivation layer to the thickness of the ultra-thin oxygen-doped amorphous silicon layer is 3~50:

1.

3. The silicon-based back-contact heterojunction solar cell according to claim 2, characterized in that: A first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer; The first semiconductor opening region and the second semiconductor layer are both covered with a transparent conductive film layer, and an isolation groove is arranged between the adjacent first semiconductor opening region and the second semiconductor opening region; the isolation groove separates the transparent conductive film layer located in the first semiconductor opening region from the transparent conductive film layer located on the second semiconductor layer.

4. The silicon-based back-contact heterojunction solar cell according to claim 2, characterized in that: The thickness of the anti-reflection layer is 70nm-150nm.

5. The silicon-based back-contact heterojunction solar cell according to claim 2, characterized in that: A textured surface is formed on the front side of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening area. The second semiconductor layer and the third semiconductor layer fill the textured surfaces in corresponding areas respectively. The third semiconductor layer includes the passivation layer and the anti-reflection layer.

6. The silicon-based back-contact heterojunction solar cell according to claim 2, characterized in that: The thickness of the amorphous silicon passivation layer is 3-10 nm, the thickness of the P-type amorphous silicon layer is 5-15 nm, and the boron doping concentration in the P-type amorphous silicon layer is 5e18 cm -3 ~4e20 cm -3 .

7. The silicon-based back-contact heterojunction solar cell according to claim 3, characterized in that: Also includes: Metal electrode; the metal electrode is arranged on the transparent conductive film layer of the first semiconductor opening area and the second semiconductor opening area.

8. The silicon-based back-contact heterojunction solar cell according to claim 2, characterized in that: An ultra-thin oxygen-doped amorphous silicon layer is formed between the passivation layer and the silicon wafer.

9. A battery assembly, characterized in that: It comprises the silicon-based back-contact heterojunction solar cell as claimed in any one of claims 2 to 8.

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