GaN-based LED epitaxial wafers and their fabrication methods

Abstract

This invention relates to the field of LED epitaxial wafer technology, and discloses a GaN-based LED epitaxial wafer and its fabrication method, comprising: a substrate, a buffer layer, an N-type semiconductor layer, a stress relief layer, a multi-quantum-well light-emitting layer, an electron blocking layer, and a P-type semiconductor layer; wherein the N-type semiconductor layer sequentially comprises: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer. Using this invention, the generation of defects in the epitaxial material during growth can be reduced, the dislocation density of the material can be lowered, and the quality of the epitaxial wafer material can be significantly improved, thereby increasing the radiative recombination efficiency in the active region of the light-emitting diode, and simultaneously significantly increasing the proportion of photon emitter material in the active region.

Description

Technical Field

[0001] This invention relates to the field of LED epitaxial wafer technology, and more particularly to a GaN-based LED epitaxial wafer and its preparation method. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor light-emitting device that directly converts electrical energy into light energy, exhibiting high conversion efficiency. As an energy-saving and environmentally friendly new light source, LEDs have received considerable attention in recent years, with many countries considering LED-related semiconductor lighting as a strategic technology. Through extensive research and experimentation, semiconductor lighting technology has made rapid progress, truly realizing the commercialization of semiconductor lighting. Various types of LEDs are widely used in indication, display, backlighting, and projection fields. These achievements are mainly attributed to advancements in GaN-based LED technology. With increased production scale and improved luminous efficiency, costs are continuously decreasing; therefore, GaN-based LEDs have broad application prospects and high commercial value.

[0003] To obtain high-brightness LEDs, it is crucial to improve both the internal and external quantum efficiencies of the device. Currently, LEDs used in the market are all fabricated using heterogeneous substrate epitaxy. Due to the significant lattice and thermal mismatches between the heterogeneous substrate (including sapphire, silicon carbide, and silicon substrates) and the epitaxial material, the epitaxial material is subjected to considerable stress during growth and is prone to dislocation formation and defects, thus reducing the luminous efficiency of the LED. Furthermore, while blue GaN-based LEDs can achieve internal quantum efficiencies exceeding 80%, the external quantum efficiency of high-power LED chips is typically only around 40%. The main factor limiting the improvement of external quantum efficiency is the low light extraction efficiency of the chip. This is because the refractive index of GaN material (n=2.5) differs significantly from that of air (n=1) and sapphire substrate (n=1.75), resulting in critical angles of only 23.6° and 44.4° for total internal reflection at the air-GaN interface and the sapphire-GaN interface, respectively. Only a small portion of the light generated in the active region can escape the bulk material. To improve the light extraction efficiency of the chip, the main technical solutions currently used domestically and internationally include growing distributed Bragg reflector (DBR) structures, patterned substrate (PSS) technology, surface roughening technology, and photonic crystal technology. The high degree of regularity required for the pattern, coupled with the hardness of the sapphire substrate, makes achieving consistent and uniform patterns across the entire wafer challenging, regardless of whether dry or wet etching is used. Furthermore, the fabrication process demands sophisticated equipment and techniques, leading to high costs. DBR and photonic crystal fabrication processes are relatively complex and expensive, while surface roughening techniques using dry or wet etching also present significant challenges. Therefore, to improve the luminous efficiency of light-emitting diodes (LEDs), i.e., to enhance both the internal and external quantum efficiencies of the device, it is essential to optimize the epitaxial structure and fabrication process to improve the quality of the epitaxial material and increase the proportion of photon emitter material in the active region.

[0004] Currently, all LEDs used in the market are fabricated using heteroepitaxial growth. Due to significant lattice and thermal mismatches between the heteroepitaxial substrate (including sapphire, silicon carbide, and silicon substrates) and the epitaxial material, the epitaxial material experiences considerable stress during growth, making it prone to dislocation formation and defects, thus reducing the luminous efficiency of the LED. Simultaneously, the main factor limiting the improvement of external quantum efficiency is the low light extraction efficiency of the chip. This is because the refractive index of GaN (n=2.5) differs significantly from that of air (n=1) and sapphire (n=1.75), resulting in critical internal reflection angles of only 23.6° and 44.4° at the air-GaN interface and the sapphire-GaN interface, respectively. Only a small portion of the light generated in the active region can escape the bulk material. Summary of the Invention

[0005] Based on the above technical background, the technical problem to be solved by the present invention is to provide a GaN-based LED epitaxial wafer and its preparation method, which can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, significantly improve the quality of the epitaxial wafer material, thereby improving the radiative recombination efficiency in the active region of the light-emitting diode, and at the same time significantly increase the proportion of photon egress material in the active region.

[0006] The technical problem to be solved by this invention is to provide a method for preparing GaN-based LED epitaxial wafers, which is simple, highly operable, and has good prospects for industrial application.

[0007] To address the aforementioned technical problems, this invention provides a GaN-based LED epitaxial wafer, comprising: a substrate, a buffer layer, an N-type semiconductor layer, a stress relief layer, a multi-quantum-well light-emitting layer, an electron blocking layer, and a P-type semiconductor layer;

[0008] The N-type semiconductor layer comprises, in sequence: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein,

[0009] The first porous low-temperature GaN layer is provided with a first V-shaped hole that penetrates the first porous low-temperature GaN layer;

[0010] The second porous AlGaN / GaN superlattice layer is provided with a second V-shaped hole and a third V-shaped hole. The second V-shaped hole is grown on the basis of the first V-shaped hole, and the opening size of the second V-shaped hole is larger than the opening size of the third V-shaped hole.

[0011] The third high-temperature GaN layer completely fills the third V-shaped hole and has a fourth V-shaped hole, which is grown on the basis of the second V-shaped hole;

[0012] The fourth porous AlGaN / GaN superlattice layer is deposited on the third high-temperature GaN layer to form a fifth V-shaped hole and stress relief hole. The fifth V-shaped hole is grown on the basis of the fourth V-shaped hole.

[0013] The fifth high-temperature GaN layer completely fills the fifth V-shaped hole and stress relief hole.

[0014] As an improvement to the above technical solution, before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, it is necessary to perform high-temperature H2 gas treatment on the surface of the epitaxial layer material. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, and the pressure is 20 torr~360 torr.

[0015] As an improvement to the above technical solution, a first high-temperature H2 gas treatment is performed before depositing the first porous low-temperature GaN layer. The H2 flow rate of the first high-temperature H2 gas treatment is 50-500 slm, and the treatment time is 15-360 s.

[0016] Before depositing the second porous AlGaN / GaN superlattice layer, a second high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the second high-temperature H2 gas treatment is 30-390 slm and the treatment time is 10-240 s;

[0017] Before depositing the fourth porous AlGaN / GaN superlattice layer, a third high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the third high-temperature H2 gas treatment is 20-350 slm and the treatment time is 5-120 s.

[0018] As an improvement to the above technical solution, the first porous low-temperature GaN layer is a porous GaN material with low Si doping, a thickness of 5 nm to 500 nm, and a Si doping concentration of 2.06 × 10⁻⁶. 17 / cm 3 ~1.2×10 19 / cm 3 The growth temperature is 850℃~1120℃, and the pressure is 30 torr~320 torr.

[0019] As an improvement to the above technical solution, the density of the second V-shaped hole is 1.28 × 10⁻⁶. 8 ~5.68×10 11 / cm 2 ;

[0020] The density of the third V-shaped hole is 2.65 × 10⁻⁶. 8 ~1.85×10 12 / cm 2 .

[0021] As an improvement to the above technical solution, the second porous AlGaN / GaN superlattice layer includes a second porous AlGaN layer and a second porous GaN layer stacked sequentially, with an alternating stacking period of 2 to 20.

[0022] The second porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 5.2 × 10⁻⁶. 17 / cm 3 ~1.6×10 19 / cm 3Al composition 0.2≤X2≤0.8, thickness 1.2nm~20nm, growth temperature 900℃~1150℃, pressure 30torr~320torr;

[0023] The second porous GaN layer is highly doped with Si, with a Si doping concentration of 2.5 × 10⁻⁶. 18 / cm 3 ~3.2×10 19 / cm3, thickness of 1.2nm~20nm, growth temperature of 900℃~1150℃, pressure of 30torr~320torr.

[0024] As an improvement to the above technical solution, the third high-temperature GaN layer is a high-temperature GaN material that is not intentionally doped, the thickness of the third high-temperature GaN layer is 0.03μm to 2μm, the growth temperature is 1050℃ to 1250℃, and the pressure is 30 torr to 320 torr.

[0025] As an improvement to the above technical solution, the fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked sequentially, with an alternating stacking period of 3 to 50.

[0026] The fourth porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 8.5 × 10⁻⁶. 17 / cm 3 ~1.9×10 19 / cm 3 Al composition 0.02≤X4≤0.5, thickness 2nm~30nm, growth temperature 920℃~1180℃, pressure 30torr~320torr;

[0027] The fourth porous GaN layer is highly doped with Si, with a Si doping concentration of 3.0 × 10⁻⁶. 18 / cm 3 ~3.8×10 19 / cm 3 The thickness is 2nm to 30nm, the growth temperature is 920℃ to 1180℃, and the pressure is 30 torr to 320 torr.

[0028] As an improvement to the above technical solution, the fifth high-temperature GaN layer is a high-temperature GaN material heavily doped with Si, with a Si doping concentration of 3.6 × 10⁻⁶. 18 / cm 3 ~5.6×10 19 / cm 3The thickness of the fifth high-temperature GaN layer is 2μm to 8μm, the growth temperature is 1050℃ to 1250℃, and the pressure is 30 torr to 320 torr.

[0029] Accordingly, this invention also discloses a method for preparing a GaN-based LED epitaxial wafer, comprising:

[0030] Select a substrate;

[0031] A buffer layer is grown on the substrate;

[0032] A Si doping source is introduced to grow an N-type semiconductor layer on the buffer layer;

[0033] A low-temperature stress relief layer is grown on an N-type semiconductor layer;

[0034] A multi-quantum-well light-emitting layer is grown on a low-temperature stress-relieving layer;

[0035] An electron blocking layer is grown on a multi-quantum-well light-emitting layer;

[0036] A P-type semiconductor layer is grown on an electron blocking layer;

[0037] The N-type semiconductor layer comprises, from bottom to top, a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer. Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, and the pressure is 20 torr~360 torr.

[0038] The present invention has the following beneficial effects:

[0039] This invention relates to a GaN-based LED epitaxial wafer, comprising five sub-layers stacked sequentially from bottom to top: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer. The first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer are all designed as porous materials. This porous structure design facilitates the full release of stress in the epitaxial layer material, effectively reducing the large stress experienced by the epitaxial layer material during growth and improving the quality of the epitaxial layer material.

[0040] Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, both require high-temperature H2 gas treatment of the epitaxial layer material surface. This involves circulating a mixture of H2 and N2 gases and stabilizing it for a certain period. After H2 gas treatment, materials with poor crystal quality on the epitaxial layer surface will be decomposed, which helps reduce the defect density and improve the crystal quality of the epitaxial layer material. Simultaneously, the formation of an uneven, rough surface facilitates the formation of V-shaped holes and stress-relieving holes of varying sizes in the subsequently deposited epitaxial layer material, further releasing stress and reducing defect density, thus improving the quality of the epitaxial layer material. Furthermore, the uneven, rough surface formed on the epitaxial layer material after H2 gas treatment—meaning the N-type semiconductor layer is designed with three rough surfaces and three porous structures—can reduce in-plane total internal reflection of the N-type material, significantly increasing the proportion of photon-escape materials in the active region, thereby improving the chip's light extraction efficiency.

[0041] All three are high-temperature two-dimensional composite materials. During the process of completely filling the V-shaped holes and stress relief holes of different sizes, some dislocation defects will be continuously deflected and merged, reducing the dislocation density of the epitaxial layer material and thus improving the quality of the epitaxial material.

[0042] Therefore, the LED epitaxial wafer prepared using the present invention can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, significantly improve the quality of the epitaxial wafer material, thereby improving the radiative recombination efficiency in the active region of the light-emitting diode, i.e., the internal quantum efficiency, and at the same time, can significantly increase the proportion of photon efferent material in the active region, i.e., improve the light extraction efficiency of the chip. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of the GaN-based LED epitaxial wafer of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0045] like Figure 1 As shown, the present invention provides a GaN-based LED epitaxial wafer, comprising: a substrate 10, a buffer layer 20, an N-type semiconductor layer 30, a stress relief layer 40, a multi-quantum-well light-emitting layer 50, an electron blocking layer 60, and a P-type semiconductor layer 70;

[0046] The N-type semiconductor layer 30 comprises, from bottom to top: a first porous low-temperature GaN layer 31, a second porous AlGaN / GaN superlattice layer 32, a third high-temperature GaN layer 33, a fourth porous AlGaN / GaN superlattice layer 34, and a fifth high-temperature GaN layer 35; wherein,

[0047] The first porous low-temperature GaN layer 31 is provided with a first V-shaped hole 311 that penetrates the first porous low-temperature GaN layer 31;

[0048] The second porous AlGaN / GaN superlattice layer 32 is provided with a second V-shaped hole 321 and a third V-shaped hole 322. The second V-shaped hole 321 is grown on the basis of the first V-shaped hole 311, and the opening size of the second V-shaped hole 321 is larger than the opening size of the third V-shaped hole 322.

[0049] The third high-temperature GaN layer 33 completely fills the third V-shaped hole 322 and has a fourth V-shaped hole 331, which is grown on the basis of the second V-shaped hole 321;

[0050] The fourth porous AlGaN / GaN superlattice layer 34 is deposited on the third high-temperature GaN layer 33 to form a fifth V-shaped hole 341 and a stress relief hole 342. The fifth V-shaped hole 341 is grown on the basis of the fourth V-shaped hole 331.

[0051] The fifth high-temperature GaN layer 35 completely fills the fifth V-shaped hole 341 and stress relief hole 342.

[0052] This invention relates to a GaN-based LED epitaxial wafer, comprising five sublayers stacked sequentially from bottom to top: a first porous low-temperature GaN layer 31, a second porous AlGaN / GaN superlattice layer 32, a third high-temperature GaN layer 33, a fourth porous AlGaN / GaN superlattice layer 34, and a fifth high-temperature GaN layer 35. The first porous low-temperature GaN layer 31, the second porous AlGaN / GaN superlattice layer 32, and the fourth porous AlGaN / GaN superlattice layer 34 are all designed as porous materials. This porous structure design facilitates the full release of stress in the epitaxial layer material, effectively reducing the large stress experienced by the epitaxial layer material during growth and improving the quality of the epitaxial layer material. The third high-temperature GaN layer 33 and the fifth high-temperature GaN layer 35 are both high-temperature two-dimensional merging materials. During the complete filling of V-shaped holes and stress-relieving holes of varying sizes, some dislocation defects will continuously deflect and merge, reducing the dislocation density of the epitaxial layer material, thereby improving the quality of the epitaxial material.

[0053] In some preferred embodiments, before depositing the first porous low-temperature GaN layer 31, the second porous AlGaN / GaN superlattice layer 32, and the fourth porous AlGaN / GaN superlattice layer 34, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. Specifically, the high-temperature H2 gas treatment involves intermittently and cyclically introducing a mixture of H2 and N2 gas into the reaction chamber and stabilizing it for a certain period of time. The preferred introduction time is 10–360 s, the preferred temperature for the high-temperature H2 gas treatment is 1020°C–1250°C, and the preferred pressure is 20 torr–360 torr. After H2 gas treatment, materials with poor crystal quality on the surface of the epitaxial layer material will be decomposed, which helps to reduce the defect density of the epitaxial layer material and improve its crystal quality. At the same time, it forms an uneven, rough surface, which is beneficial for the subsequent deposition of the epitaxial layer material to form V-shaped holes and stress relief holes of varying sizes, thereby releasing the stress of the epitaxial layer material and improving its quality.

[0054] Preferably, the deposition of the N-type semiconductor layer requires three high-temperature H2 gas treatments. Specifically, a first high-temperature H2 gas treatment is performed before depositing the first porous low-temperature GaN layer 31; a second high-temperature H2 gas treatment is performed before depositing the second porous AlGaN / GaN superlattice layer 32; and a third high-temperature H2 gas treatment is performed before depositing the fourth porous AlGaN / GaN superlattice layer 34. The H2 flow rate of the first high-temperature H2 gas treatment is greater than or equal to the H2 flow rate of the second high-temperature H2 gas treatment, and the H2 flow rate of the second high-temperature H2 gas treatment is greater than or equal to the H2 flow rate of the third high-temperature H2 gas treatment. The duration of the first high-temperature H2 gas treatment is greater than or equal to the duration of the second high-temperature H2 gas treatment, and the duration of the second high-temperature H2 gas treatment is greater than or equal to the duration of the third high-temperature H2 gas treatment.

[0055] More preferably, the H2 flow rate for the first high-temperature H2 gas treatment is 50–500 slm, specifically 50 slm, 100 slm, 150 slm, 200 slm, 250 slm, 300 slm, 350 slm, 400 slm, 450 slm, or 500 slm, but not limited to these values; the treatment time is 15–360 s, specifically 15 s, 50 s, 100 s, 150 s, 200 s, 250 s, 300 s, or 360 s, but not limited to these values.

[0056] The H2 flow rate for the second high-temperature H2 gas treatment is 30–390 slm, specifically 30 slm, 50 slm, 100 slm, 150 slm, 200 slm, 250 slm, 300 slm, 350 slm, or 390 slm, but not limited to these values; the treatment time is 10–240 s, specifically 10 s, 30 s, 50 s, 100 s, 150 s, 200 s, or 240 s, but not limited to these values.

[0057] The H2 flow rate for the third high-temperature H2 gas treatment is 20–350 slm, specifically 20 slm, 50 slm, 100 slm, 150 slm, 200 slm, 250 slm, 300 slm, or 350 slm, but not limited to these values; the treatment time is 5–120 s, specifically 5 s, 25 s, 50 s, 100 s, or 120 s, but not limited to these values.

[0058] Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. This involves circulating a mixture of H2 and N2 gas and stabilizing it for a certain period. After H2 gas treatment, materials with poor crystal quality on the epitaxial layer surface will be decomposed, which helps reduce the defect density and improve the crystal quality of the epitaxial layer material. Simultaneously, the formation of an uneven, rough surface facilitates the formation of V-shaped holes and stress-relieving holes of varying sizes in the subsequently deposited epitaxial layer material, further releasing stress and reducing defect density, thus improving the quality of the epitaxial layer material. Furthermore, the uneven, rough surface formed on the epitaxial layer material after H2 gas treatment—meaning the N-type semiconductor layer is designed with three rough surfaces and three porous structures—can reduce in-plane total internal reflection of the N-type material, significantly increasing the proportion of photon emitter material in the active region, thereby improving the chip's light extraction efficiency.

[0059] In some preferred embodiments, the first porous low-temperature GaN layer 31 has a first V-shaped hole 311 penetrating through it. The first porous low-temperature GaN layer 31 is made of porous GaN material with low Si doping, and its thickness is 5nm to 500nm, specifically 5nm, 50nm, 100nm, 200nm, 300nm, 400nm, or 500nm, but not limited to these. The Si doping concentration is 2.06 × 10⁻⁶. 17 / cm 3 ~1.20×10 19 / cm 3 Specifically, it can be 2.06 × 10 17 / cm 3 5.00×1017 / cm 3 1.00×10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 1.00×10 19 / cm 3 1.20×10 19 / cm 3 However, this is not the only applicable temperature range. The growth temperature is 850℃~1120℃, specifically 850℃, 950℃, 1050℃, 1100℃, 1120℃, but not limited to this. The pressure is 30 torr~320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, 320 torr, but not limited to this.

[0060] The first V-shaped pores 311 in the first porous low-temperature GaN layer 31 are V-shaped and penetrate the first porous low-temperature GaN layer. There are multiple V-shaped pores of the same size, which are uniformly distributed in the first porous low-temperature GaN layer, and the preferred pore density is 1.28 × 10⁻⁶. 8 ~5.68×10 11 / cm 2 Specifically, it can be 1.28 × 10 8 2.0×10 9 5.0×10 9 2.0×10 10 5.0×10 10 2.0×10 11 5.68×10 11 / cm 2 However, it is not limited to this.

[0061] In some preferred embodiments, the second porous AlGaN / GaN superlattice layer 32 is a porous AlGaN / GaN superlattice material with a high Al content, which includes a second porous AlGaN layer and a second porous GaN layer stacked sequentially, with an alternating stacking period of 2 to 20, specifically 2, 5, 10, 15, or 20, but not limited thereto.

[0062] The second porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 5.2 × 10⁻⁶. 17 / cm 3 ~1.6×10 19 / cm 3 Specifically, it can be 5.2 × 10 17 / cm3 8.00×10 17 / cm 3 1.00×10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 1.00×10 19 / cm 3 1.60×10 19 / cm 3 However, this is not limited to the following: Al composition 0.2 ≤ X2 ≤ 0.8, where X2 can specifically be 0.2, 0.4, 0.6, or 0.8, but is not limited to these values. Thickness 1.2 nm to 20 nm, specifically 1.2 nm, 5 nm, 10 nm, 12 nm, 15 nm, 18 nm, or 20 nm, but is not limited to these values. Growth temperature 900℃ to 1150℃, specifically 900℃, 950℃, 1050℃, 1100℃, or 1150℃, but is not limited to these values. Pressure 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, or 320 torr, but is not limited to these values.

[0063] The second porous GaN layer is highly doped with Si, with a Si doping concentration of 2.5 × 10⁻⁶. 18 / cm 3 ~3.2×10 19 / cm 3 Specifically, it can be 2.5 × 10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 1.00×10 19 / cm 3 1.20×10 19 / cm 3 3.20×10 19 / cm 3However, this is not the only applicable thickness. The thickness ranges from 1.2 nm to 20 nm, specifically 1.2 nm, 5 nm, 10 nm, 12 nm, 15 nm, 18 nm, and 20 nm, but is not limited to these values. The growth temperature ranges from 900℃ to 1150℃, specifically 900℃, 950℃, 1050℃, 1100℃, and 1150℃, but is not limited to these values. The pressure ranges from 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, and 320 torr, but is not limited to these values.

[0064] The second porous AlGaN / GaN superlattice layer is deposited on the first porous low-temperature GaN layer after a second high-temperature H2 gas treatment, forming a porous structure material with two pore sizes—a second V-shaped pore 321 and a third V-shaped pore 322. The second V-shaped pore 321 is grown on the basis of the first V-shaped pore 311, and the opening size of the second V-shaped pore 321 is larger than the opening size of the third V-shaped pore 322.

[0065] The second porous AlGaN / GaN superlattice layer contains multiple small V-shaped pores (i.e., the third V-shaped pores 322), all of the same size and uniformly distributed. The preferred density of the second V-shaped pores 321 is 1.28 × 10⁻⁶. 8 ~5.68×10 11 / cm 2 Specifically, it can be 1.28 × 10 8 5.00×10 8 / cm 3 1.00×10 9 / cm 3 5.00×10 9 / cm 3 1.20×10 10 / cm 3 5.00×10 10 / cm 3 5.68×10 11 / cm 2 However, it is not limited to this. The density of the third V-shaped hole 322 is 2.65 × 10⁻⁶. 8 ~1.85×10 12 / cm 2 Specifically, it can be 2.65 × 10 8 5.00×10 8 / cm 3 1.00×10 9 / cm 3 5.00×10 9 / cm 31.20×10 10 / cm 3 5.00×10 10 / cm 3 1.0×10 11 / cm 2 5.0×10 11 / cm 2 1.85×10 12 / cm 2 However, it is not limited to this.

[0066] In some preferred embodiments, the third high-temperature GaN layer 33 is a high-temperature GaN material that is not intentionally doped. The thickness of the third high-temperature GaN layer 33 is 0.03 μm to 2 μm, specifically 0.03 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, or 2 μm, but is not limited thereto. The growth temperature is 1050℃ to 1250℃, specifically 1050℃, 1100℃, 1150℃, 1200℃, or 1250℃, but is not limited thereto. The pressure is 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, or 320 torr, but is not limited thereto.

[0067] In some preferred embodiments, the fourth porous AlGaN / GaN superlattice layer 34 is a low-Al composition porous AlGaN / GaN superlattice material, which includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked sequentially, with an alternating stacking period of 3 to 50, specifically 3, 10, 15, 20, 25, 30, 35, 40, 45, 50, but not limited to these.

[0068] The fourth porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 8.5 × 10⁻⁶. 17 / cm 3 ~1.9×10 19 / cm 3 Specifically, it can be 8.5 × 10 17 / cm 3 1.00×10 18 / cm 3 3.00×10 18 / cm 3 8.00×10 18 / cm 3 1.00×10 19 / cm 3 1.90×10 19 / cm 3However, this is not limited to the following: Al composition 0.02 ≤ X4 ≤ 0.5, where X4 can specifically be 0.02, 0.1, 0.2, 0.3, 0.4, or 0.5, but is not limited to these. Thickness 2 nm to 30 nm, specifically 2 nm, 5 nm, 10 nm, 12 nm, 15 nm, 20 nm, or 30 nm, but is not limited to these. Growth temperature 920℃ to 1180℃, specifically 920℃, 950℃, 1050℃, 1100℃, or 1180℃, but is not limited to these. Pressure 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, or 320 torr, but is not limited to these.

[0069] The fourth porous GaN layer is highly doped with Si, with a Si doping concentration of 3.0 × 10⁻⁶. 18 / cm 3 ~3.8×10 19 / cm 3 Specifically, it can be 3.0 × 10 18 / cm 3 8.0×10 18 / cm 3 1.0×10 19 / cm 3 2.0×10 19 / cm 3 3.8×10 19 / cm 3 However, this is not the only applicable thickness. The thickness ranges from 2nm to 30nm, specifically 2nm, 5nm, 10nm, 12nm, 15nm, 20nm, and 30nm, but is not limited to these values. The growth temperature ranges from 920℃ to 1180℃, specifically 920℃, 950℃, 1050℃, 1100℃, and 1180℃, but is not limited to these values. The pressure ranges from 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, and 320 torr, but is not limited to these values.

[0070] The fourth porous AlGaN / GaN superlattice layer 34 is deposited on top of the third high-temperature GaN layer 33, which has undergone a third high-temperature H2 gas treatment, forming a porous structure material with two pore sizes—a fifth V-shaped pore 341 and stress relief pores 342. The fourth porous AlGaN / GaN superlattice layer has multiple stress relief pores 342 of the same size and uniformly distributed, with a preferred stress relief pore density of 5.27 × 10⁻⁶. 8 ~6.87×10 12 / cm 2 .

[0071] In some preferred embodiments, the fifth high-temperature GaN layer 35 is a high-temperature GaN material heavily doped with Si, and completely fills the fifth V-shaped holes 341 and stress relief holes 342, serving as the host material for the N-type semiconductor layer and providing electrons to the light-emitting diode device. The Si doping concentration is 3.6 × 10⁻⁶. 18 / cm 3 ~5.6×10 19 / cm 3 Specifically, it can be 3.6 × 10 18 / cm 3 8.0×10 18 / cm 3 1.0×10 19 / cm 3 3.0×10 19 / cm 3 5.6×10 19 / cm 3 However, it is not limited to this. The thickness of the fifth high-temperature GaN layer 35 is 2μm to 8μm, specifically 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, or 8μm, but not limited to this. The growth temperature is 1050℃ to 1250℃, specifically 900℃, 950℃, 1050℃, 1100℃, or 1150℃, but not limited to this. The pressure is 30 torr to 320 torr, specifically 30 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, or 320 torr, but not limited to this.

[0072] The first porous low-temperature GaN layer, the third high-temperature GaN layer, and the fifth high-temperature GaN layer in the N-type semiconductor layer are all GaN materials. The first porous low-temperature GaN layer is lightly doped with Si, the third high-temperature GaN layer is not intentionally doped, and the fifth high-temperature GaN layer is heavily doped with Si.

[0073] The second porous AlGaN / GaN superlattice layer and the fourth porous AlGaN / GaN superlattice layer in the N-type semiconductor layer are both porous AlGaN / GaN superlattice materials, and the Al composition of the second porous AlGaN / GaN superlattice layer is greater than that of the fourth porous AlGaN / GaN superlattice layer, i.e., X2 > X4.

[0074] To improve the luminous efficiency of light-emitting diodes (LEDs), i.e., to increase the internal and external quantum efficiencies of the device, the quality of the epitaxial material and the proportion of photon-escape material in the active region are improved by optimizing the epitaxial structure and process of the LED. This invention's GaN-based LED epitaxial wafer, based on the aforementioned structural and process design of the N-type semiconductor layer, includes five sub-layers stacked sequentially from bottom to top: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer. The first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer are all designed as porous materials. This porous structure design facilitates the full release of stress in the epitaxial layer material, effectively reducing the large stress experienced by the epitaxial layer material during growth and improving the quality of the epitaxial layer material.

[0075] Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, both require high-temperature H2 gas treatment of the epitaxial layer material surface. This involves circulating a mixture of H2 and N2 gases and stabilizing it for a certain period. After H2 gas treatment, materials with poor crystal quality on the epitaxial layer surface will be decomposed, which helps reduce the defect density and improve the crystal quality of the epitaxial layer material. Simultaneously, the formation of an uneven, rough surface facilitates the formation of V-shaped holes and stress-relieving holes of varying sizes in the subsequently deposited epitaxial layer material, further releasing stress and reducing defect density, thus improving the quality of the epitaxial layer material. Furthermore, the uneven, rough surface formed on the epitaxial layer material after H2 gas treatment—meaning the N-type semiconductor layer is designed with three rough surfaces and three porous structures—can reduce in-plane total internal reflection of the N-type material, significantly increasing the proportion of photon-escape materials in the active region, thereby improving the chip's light extraction efficiency.

[0076] All three are high-temperature two-dimensional composite materials. During the process of completely filling the V-shaped holes and stress relief holes of different sizes, some dislocation defects will be continuously deflected and merged, reducing the dislocation density of the epitaxial layer material and thus improving the quality of the epitaxial material.

[0077] Therefore, the LED epitaxial wafer prepared using the present invention can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, significantly improve the quality of the epitaxial wafer material, thereby improving the radiative recombination efficiency in the active region of the light-emitting diode, i.e., the internal quantum efficiency, and at the same time, can significantly increase the proportion of photon efferent material in the active region, i.e., improve the light extraction efficiency of the chip.

[0078] Accordingly, this invention also discloses a method for preparing a GaN-based LED epitaxial wafer, comprising:

[0079] (1) Selecting a substrate;

[0080] (2) Grow a buffer layer on the substrate;

[0081] (3) Introduce a Si doping source to grow an N-type semiconductor layer on the buffer layer;

[0082] Specifically, step (3) involves depositing a first porous low-temperature GaN layer 31, a second porous AlGaN / GaN superlattice layer 32, a third high-temperature GaN layer 33, a fourth porous AlGaN / GaN superlattice layer 34, and a fifth high-temperature GaN layer 35 on the buffer layer.

[0083] Before depositing the first porous low-temperature GaN layer 31, the second porous AlGaN / GaN superlattice layer 32, and the fourth porous AlGaN / GaN superlattice layer 34, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, and the pressure is 20 torr~360 torr.

[0084] Preferably, step (3) includes:

[0085] The surface of the buffer layer 20 is subjected to a first high-temperature H2 gas treatment;

[0086] A first porous low-temperature GaN layer 31 is deposited on the surface of the buffer layer 20;

[0087] A second high-temperature H2 gas treatment is performed on the first porous low-temperature GaN layer 31;

[0088] A second porous AlGaN / GaN superlattice layer 32 is deposited on the surface of the first porous low-temperature GaN layer 31;

[0089] A third high-temperature GaN layer 33 is deposited on the surface of the second porous AlGaN / GaN superlattice layer 32;

[0090] A third high-temperature H2 gas treatment was performed on the surface of the third high-temperature GaN layer 33;

[0091] A fourth porous AlGaN / GaN superlattice layer 34 is deposited on the surface of the third high-temperature GaN layer 33;

[0092] A fifth high-temperature GaN layer 35 is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer 34.

[0093] More preferably, step (3) includes:

[0094] The surface of the buffer layer 20 is subjected to a first high-temperature H2 gas treatment, specifically by circulating a mixture of H2 and N2 gas. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, the pressure is 20 torr~360 torr, the H2 flow rate is 50~500 slm, and the treatment time is 15~360s.

[0095] A first porous low-temperature GaN layer 31 is deposited on the surface of the buffer layer 20;

[0096] A second high-temperature H2 gas treatment is performed on the first porous low-temperature GaN layer 31. Specifically, a mixture of H2 and N2 gas is circulated in. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, the pressure is 20 torr~360 torr, the H2 flow rate is 30~390 slm, and the treatment time is 10~240s.

[0097] A second porous AlGaN / GaN superlattice layer 32 is deposited on the surface of the first porous low-temperature GaN layer 31;

[0098] A third high-temperature GaN layer 33 is deposited on the surface of the second porous AlGaN / GaN superlattice layer 32;

[0099] A third high-temperature H2 gas treatment was performed on the surface of the third high-temperature GaN layer 33. Specifically, a mixture of H2 and N2 gas was circulated in. The temperature of the high-temperature H2 gas treatment was 1020℃~1250℃, the pressure was 20 torr~360 torr, the H2 flow rate was 20~350 slm, and the treatment time was 5~120s.

[0100] A fourth porous AlGaN / GaN superlattice layer 34 is deposited on the surface of the third high-temperature GaN layer 33;

[0101] A fifth high-temperature GaN layer 35 is deposited on the surface of the fourth porous AlGaN / GaN superlattice layer 34.

[0102] (4) A low-temperature stress relief layer is grown on the N-type semiconductor layer;

[0103] (5) A multi-quantum well light-emitting layer is grown on the low-temperature stress relief layer;

[0104] (6) An electron blocking layer is grown on the multi-quantum-well light-emitting layer;

[0105] (7) Grow a P-type semiconductor layer on the electron blocking layer.

[0106] In the preparation method provided by this invention, before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. After three high-temperature H2 gas treatments, the material with poor crystal quality on the surface of the epitaxial layer material will be decomposed, which helps to reduce the defect density of the epitaxial layer material and improve the crystal quality of the epitaxial layer material. At the same time, an uneven rough surface is formed, which is beneficial for the subsequent deposition of epitaxial layer material to form V-shaped holes and stress relief holes of different sizes, further fully releasing the stress of the epitaxial layer material, reducing the defect density of the epitaxial layer material, and improving the quality of the epitaxial layer material. Moreover, the uneven rough surface formed on the surface of the epitaxial layer material after H2 gas treatment, that is, the N-type semiconductor layer is designed as three rough surface layers + three porous structure materials, can reduce the in-plane total reflection of the N-type material, significantly increase the proportion of photon escaping material in the active region, thereby improving the light extraction efficiency of the chip.

[0107] The present invention is further illustrated below with examples.

[0108] Example 1

[0109] The GaN-based LED epitaxial wafer comprises: a substrate, a buffer layer, an N-type semiconductor layer, a stress relief layer, a multi-quantum-well light-emitting layer, an electron-blocking layer, and a P-type semiconductor layer; wherein, the N-type semiconductor layer sequentially comprises: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein...

[0110] The first porous low-temperature GaN layer has a first V-shaped pore penetrating through it. The first porous low-temperature GaN layer is a porous GaN material with low Si doping, a thickness of 50 nm, and a Si doping concentration of 2.06 × 10⁻⁶. 17 / cm 3 The growth temperature was 850℃ and the pressure was 30 torr;

[0111] The second porous AlGaN / GaN superlattice layer has a second V-shaped hole and a third V-shaped hole. The second V-shaped hole is grown based on the first V-shaped hole, and the opening size of the second V-shaped hole is larger than that of the third V-shaped hole. The second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked sequentially, with an alternating stacking period of 10. The second porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 5.2 × 10⁻⁶. 17 / cm 3The Al composition is 0.4%, the thickness is 5 nm, the growth temperature is 900℃, and the pressure is 30 torr; the second porous GaN layer is highly doped with Si, with a Si doping concentration of 2.5 × 10⁻⁶. 18 / cm 3 The thickness is 5nm, the growth temperature is 900℃, and the pressure is 30torr;

[0112] The third high-temperature GaN layer completely fills the third V-shaped hole and has a fourth V-shaped hole. The fourth V-shaped hole is grown on the basis of the second V-shaped hole. The thickness of the third high-temperature GaN layer 33 is 0.03 μm, the growth temperature is 1050℃, and the pressure is 30 torr.

[0113] The fourth porous AlGaN / GaN superlattice layer is deposited on top of the third high-temperature GaN layer, forming a fifth V-shaped cavity and stress-relieving pores. The fifth V-shaped cavity is grown based on the fourth V-shaped cavity. The fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked sequentially, with an alternating stacking period of 12. The fourth porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 8.5 × 10⁻⁶. 17 / cm 3 The Al composition is 0.1%, the thickness is 2 nm, the growth temperature is 920℃, and the pressure is 30 torr; the fourth porous GaN layer is highly doped with Si, with a Si doping concentration of 3.0 × 10⁻⁶. 18 / cm 3 The thickness is 2nm, the growth temperature is 920℃, and the pressure is 30 torr.

[0114] The fifth high-temperature GaN layer completely fills the fifth V-shaped void and stress relief void, and the Si doping concentration is 3.6 × 10⁻⁶. 18 / cm 3 The thickness was 2μm, the growth temperature was 1050℃, and the pressure was 30 torr.

[0115] The method for fabricating the N-type semiconductor layer is as follows:

[0116] The surface of the buffer layer was subjected to a first high-temperature H2 gas treatment, specifically by circulating a mixture of H2 and N2 gas. The high-temperature H2 gas treatment temperature was 1020℃, the pressure was 20 torr, the H2 flow rate was 50 slm, and the treatment time was 15s.

[0117] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0118] A second high-temperature H2 gas treatment was performed on the first porous low-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1020℃, the pressure was 20 torr, the H2 flow rate was 30 slm, and the treatment time was 10 s.

[0119] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0120] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0121] A third high-temperature H2 gas treatment was performed on the surface of the third high-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1020℃, the pressure was 20 torr, the H2 flow rate was 20 slm, and the treatment time was 5s.

[0122] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0123] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0124] Example 2

[0125] The GaN-based LED epitaxial wafer comprises: a substrate, a buffer layer, an N-type semiconductor layer, a stress relief layer, a multi-quantum-well light-emitting layer, an electron-blocking layer, and a P-type semiconductor layer; wherein, the N-type semiconductor layer sequentially comprises: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein...

[0126] The first porous low-temperature GaN layer has a first V-shaped pore penetrating through it. The first porous low-temperature GaN layer is a porous GaN material with low Si doping, a thickness of 100 nm, and a Si doping concentration of 1.0 × 10⁻⁶. 18 / cm 3 The growth temperature was 1000℃ and the pressure was 200 torr;

[0127] The second porous AlGaN / GaN superlattice layer has a second V-shaped hole and a third V-shaped hole. The second V-shaped hole is grown based on the first V-shaped hole, and the opening size of the second V-shaped hole is larger than that of the third V-shaped hole. The second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked sequentially, with an alternating stacking period of 2 to 20. The second porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 2.0 × 10⁻⁶. 18 / cm 3 The Al composition is 0.6%, the thickness is 10 nm, the growth temperature is 1000℃, and the pressure is 200 torr; the second porous GaN layer is highly doped with Si, with a Si doping concentration of 6.0 × 10⁻⁶. 18 / cm 3 The thickness is 10nm, the growth temperature is 1000℃, and the pressure is 200torr;

[0128] The third high-temperature GaN layer completely fills the third V-shaped hole and has a fourth V-shaped hole. The fourth V-shaped hole is grown on the basis of the second V-shaped hole. The thickness of the third high-temperature GaN layer 33 is 1 μm, the growth temperature is 1100℃, and the pressure is 200 torr.

[0129] The fourth porous AlGaN / GaN superlattice layer is deposited on top of the third high-temperature GaN layer, forming a fifth V-shaped cavity and stress-relieving pores. The fifth V-shaped cavity is grown based on the fourth V-shaped cavity. The fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked sequentially, with an alternating stacking period of 30. The fourth porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 2.5 × 10⁻⁶. 18 / cm 3 The Al composition is 0.2%, the thickness is 20 nm, the growth temperature is 1050 °C, and the pressure is 200 rpm. The fourth porous GaN layer is highly doped with Si, with a Si doping concentration of 9.0 × 10⁻⁶. 18 / cm 3 The thickness is 20nm, the growth temperature is 1050℃, and the pressure is 200 torr.

[0130] The fifth high-temperature GaN layer completely fills the fifth V-shaped void and stress relief void, and the Si doping concentration is 7.2 × 10⁻⁶. 18 / cm 3 The thickness is 5μm, the growth temperature is 1150℃, and the pressure is 200 torr.

[0131] The method for fabricating the N-type semiconductor layer is as follows:

[0132] The surface of the buffer layer is subjected to a first high-temperature H2 gas treatment, specifically by circulating a mixture of H2 and N2 gas. The high-temperature H2 gas treatment temperature is 1150℃, the pressure is 200 orr, the H2 flow rate is 300 slm, and the treatment time is 250s.

[0133] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0134] A second high-temperature H2 gas treatment was performed on the first porous low-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1150℃, the pressure was 200 torr, the H2 flow rate was 200 slm, and the treatment time was 150 s.

[0135] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0136] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0137] A third high-temperature H2 gas treatment was performed on the surface of the third high-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1150℃, the pressure was 200 torr, the H2 flow rate was 100 slm, and the treatment time was 50s.

[0138] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0139] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0140] Example 3

[0141] The GaN-based LED epitaxial wafer comprises: a substrate, a buffer layer, an N-type semiconductor layer, a stress relief layer, a multi-quantum-well light-emitting layer, an electron-blocking layer, and a P-type semiconductor layer; wherein, the N-type semiconductor layer sequentially comprises: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein...

[0142] The first porous low-temperature GaN layer has a first V-shaped pore penetrating through it. The first porous low-temperature GaN layer is a porous GaN material with low Si doping, a thickness of 500 nm, and a Si doping concentration of 1.2 × 10⁻⁶. 19 / cm 3 The growth temperature was 1120℃ and the pressure was 320 torr.

[0143] The second porous AlGaN / GaN superlattice layer has a second V-shaped hole and a third V-shaped hole. The second V-shaped hole is grown based on the first V-shaped hole, and the opening size of the second V-shaped hole is larger than that of the third V-shaped hole. The second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked sequentially, with an alternating stacking period of 20. The second porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 1.6 × 10⁻⁶. 19 / cm 3 The Al composition is 0.8%, the thickness is 20 nm, the growth temperature is 1150℃, and the pressure is 320 torr; the second porous GaN layer is highly doped with Si, with a Si doping concentration of 0.2 × 10⁻⁶. 19 / cm 3 The thickness is 20nm, the growth temperature is 1150℃, and the pressure is 320torr;

[0144] The third high-temperature GaN layer completely fills the third V-shaped hole and has a fourth V-shaped hole. The fourth V-shaped hole is grown on the basis of the second V-shaped hole. The thickness of the third high-temperature GaN layer 33 is 2μm, the growth temperature is 1250℃, and the pressure is 320 torr.

[0145] The fourth porous AlGaN / GaN superlattice layer is deposited on top of the third high-temperature GaN layer, forming a fifth V-shaped cavity and stress-relieving pores. The fifth V-shaped cavity is grown based on the fourth V-shaped cavity. The fourth porous AlGaN / GaN superlattice layer includes a fourth porous AlGaN layer and a fourth porous GaN layer stacked sequentially, with an alternating stacking period of 50. The fourth porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 1.9 × 10⁻⁶. 19 / cm 3 The Al composition is 0.5%, the thickness is 30 nm, the growth temperature is 1180 °C, and the pressure is 320 torr; the fourth porous GaN layer is highly doped with Si, with a Si doping concentration of 3.8 × 10⁻⁶. 19 / cm 3 The thickness is 30nm, the growth temperature is 1180℃, and the pressure is 320torr.

[0146] The fifth high-temperature GaN layer completely fills the fifth V-shaped void and stress relief void, and the Si doping concentration is 5.6 × 10⁻⁶. 19 / cm 3 The thickness is 8μm, the growth temperature is 1250℃, and the pressure is 320 torr.

[0147] The method for fabricating the N-type semiconductor layer is as follows:

[0148] The surface of the buffer layer is subjected to a first high-temperature H2 gas treatment, specifically by circulating a mixture of H2 and N2 gas. The high-temperature H2 gas treatment temperature is 1250℃, the pressure is 360 torr, the H2 flow rate is 500 slm, and the treatment time is 360s.

[0149] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0150] A second high-temperature H2 gas treatment was performed on the first porous low-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1250℃, the pressure was 360 torr, the H2 flow rate was 390 slm, and the treatment time was 240s.

[0151] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0152] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0153] A third high-temperature H2 gas treatment was performed on the surface of the third high-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1250℃, the pressure was 360 torr, the H2 flow rate was 350 slm, and the treatment time was 120s.

[0154] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0155] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0156] Comparative Example 1

[0157] Unlike Example 2, the method for preparing the N-type semiconductor layer in Comparative Example 1 is as follows:

[0158] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0159] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0160] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0161] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0162] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0163] Comparative Example 2

[0164] Unlike Example 2, the method for preparing the N-type semiconductor layer in Comparative Example 2 is as follows:

[0165] The surface of the buffer layer is subjected to a first high-temperature H2 gas treatment, specifically by circulating a mixture of H2 and N2 gas. The high-temperature H2 gas treatment temperature is 1150℃, the pressure is 200 orr, the H2 flow rate is 300 slm, and the treatment time is 250s.

[0166] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0167] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0168] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0169] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0170] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0171] Comparative Example 3

[0172] Unlike Example 2, the method for preparing the N-type semiconductor layer in Comparative Example 3 is as follows:

[0173] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0174] The first high-temperature H2 gas treatment was carried out on the first porous low-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1150℃, the pressure was 200 torr, the H2 flow rate was 200 slm, and the treatment time was 150s.

[0175] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0176] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0177] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0178] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0179] Comparative Example 4

[0180] Unlike Example 2, the method for preparing the N-type semiconductor layer in Comparative Example 4 is as follows:

[0181] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0182] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0183] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0184] The surface of the third high-temperature GaN layer was subjected to the first high-temperature H2 gas treatment, specifically by circulating a mixture of H2 and N2 gas. The high-temperature H2 gas treatment temperature was 1150℃, the pressure was 200 torr, the H2 flow rate was 100 slm, and the treatment time was 50s.

[0185] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0186] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0187] Comparative Example 5

[0188] Unlike Example 2, the method for preparing the N-type semiconductor layer in Comparative Example 5 is as follows:

[0189] The surface of the buffer layer is subjected to a first high-temperature H2 gas treatment, specifically by circulating a mixture of H2 and N2 gas. The high-temperature H2 gas treatment temperature is 1150℃, the pressure is 200 orr, the H2 flow rate is 300 slm, and the treatment time is 250s.

[0190] A first porous low-temperature GaN layer is deposited on the surface of the buffer layer;

[0191] A second high-temperature H2 gas treatment was performed on the first porous low-temperature GaN layer. Specifically, a mixture of H2 and N2 gas was circulated in. The high-temperature H2 gas treatment temperature was 1150℃, the pressure was 200 torr, the H2 flow rate was 200 slm, and the treatment time was 150 s.

[0192] A second porous AlGaN / GaN superlattice layer is deposited on the surface of the first porous low-temperature GaN layer;

[0193] A third high-temperature GaN layer is deposited on the surface of the second porous AlGaN / GaN superlattice layer;

[0194] A fourth porous AlGaN / GaN superlattice layer is deposited on the surface of the third high-temperature GaN layer;

[0195] A fifth high-temperature GaN layer was deposited on the surface of the fourth porous AlGaN / GaN superlattice layer.

[0196] LED epitaxial wafers were prepared in Examples 1-3 and Comparative Examples 1-5. These wafers were then fabricated into 3mil × 5mil chips using the same chip fabrication process. 300 LED chips were randomly selected from each example and tested at a 3mA current. Using Comparative Example 1 as a reference, the luminous efficiency improvement rate of each example and comparative example was calculated. The specific test results are shown in Table 1.

[0197]

[0198]

[0199] In summary, the LED epitaxial wafer of the present invention can reduce the generation of defects in the epitaxial material during the growth process, reduce the dislocation density of the material, significantly improve the quality of the epitaxial wafer material, thereby improving the radiative recombination efficiency in the active region of the light-emitting diode, and at the same time significantly increase the proportion of photon efferent material in the active region, that is, improve the light extraction efficiency of the chip.

[0200] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered within the scope of protection of the present invention.

Claims

1. A GaN-based LED epitaxial wafer, characterized in that, include: Substrate, buffer layer, N-type semiconductor layer, stress relief layer, multi-quantum-well light-emitting layer, electron blocking layer and P-type semiconductor layer; The N-type semiconductor layer comprises, in sequence: a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer; wherein, The first porous low-temperature GaN layer is provided with a first V-shaped hole that penetrates the first porous low-temperature GaN layer; The second porous AlGaN / GaN superlattice layer is provided with a second V-shaped hole and a third V-shaped hole. The second V-shaped hole is grown on the basis of the first V-shaped hole, and the opening size of the second V-shaped hole is larger than the opening size of the third V-shaped hole. The third high-temperature GaN layer completely fills the third V-shaped hole and has a fourth V-shaped hole, which is grown on the basis of the second V-shaped hole; The fourth porous AlGaN / GaN superlattice layer is deposited on the third high-temperature GaN layer to form a fifth V-shaped hole and stress relief hole. The fifth V-shaped hole is grown on the basis of the fourth V-shaped hole. The fifth high-temperature GaN layer completely fills the fifth V-shaped hole and stress relief hole; The second porous AlGaN / GaN superlattice layer comprises a second porous AlGaN layer and a second porous GaN layer stacked sequentially, with an alternating stacking period of 2 to 20; The second porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 5.2 × 10⁻⁶. 17 / cm 3 ~1.6×10 19 / cm 3 Al composition 0.2≤X2≤0.8, thickness 1.2nm~20nm, growth temperature 900℃~1150℃, pressure 30torr~320torr; The second porous GaN layer is highly doped with Si, with a Si doping concentration of 2.5 × 10⁻⁶. 18 / cm 3 ~3.2×10 19 / cm 3 The thickness is 1.2nm to 20nm, the growth temperature is 900℃ to 1150℃, and the pressure is 30 torr to 320 torr; The fourth porous AlGaN / GaN superlattice layer comprises a fourth porous AlGaN layer and a fourth porous GaN layer stacked sequentially, with an alternating stacking period of 3 to 50. The fourth porous AlGaN layer is lightly doped with Si, with a Si doping concentration of 8.5 × 10⁻⁶. 17 / cm 3 ~1.9×10 19 / cm 3 Al composition 0.02≤X4≤0.5, thickness 2nm~30nm, growth temperature 920℃~1180℃, pressure 30torr~320torr; The fourth porous GaN layer is highly doped with Si, with a Si doping concentration of 3.0 × 10⁻⁶. 18 / cm 3 ~3.8×10 19 / cm 3 The thickness is 2nm to 30nm, the growth temperature is 920℃ to 1180℃, and the pressure is 30 torr to 320 torr. The second porous AlGaN / GaN superlattice layer of the Al composition is larger than the fourth porous AlGaN / GaN superlattice layer, i.e., X2 > X4.

2. The GaN-based LED epitaxial wafer as described in claim 1, characterized in that, Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, and the pressure is 20 torr~360 torr.

3. The GaN-based LED epitaxial wafer as described in claim 2, characterized in that, Before depositing the first porous low-temperature GaN layer, a first high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the first high-temperature H2 gas treatment is 50-500 slm and the treatment time is 15-360 s. Before depositing the second porous AlGaN / GaN superlattice layer, a second high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the second high-temperature H2 gas treatment is 30-390 slm and the treatment time is 10-240 s; Before depositing the fourth porous AlGaN / GaN superlattice layer, a third high-temperature H2 gas treatment is performed, wherein the H2 flow rate of the third high-temperature H2 gas treatment is 20-350 slm and the treatment time is 5-120 s.

4. The GaN-based LED epitaxial wafer as described in claim 1, characterized in that, The first porous low-temperature GaN layer is a porous GaN material with low Si doping, a thickness of 5 nm to 500 nm, and a Si doping concentration of 2.06 × 10⁻⁶. 17 / cm 3 ~1.2×10 19 / cm 3 The growth temperature is 850℃~1120℃, and the pressure is 30 torr~320 torr.

5. The GaN-based LED epitaxial wafer as described in claim 1, characterized in that, The density of the second V-shaped pore is 1.28 × 10⁻⁶. 8 ~5.68×10 11 / cm 2 ; The density of the third V-shaped hole is 2.65 × 10⁻⁶. 8 ~1.85×10 12 / cm 2 .

6. The GaN-based LED epitaxial wafer as described in claim 1, characterized in that, The third high-temperature GaN layer is a high-temperature GaN material without intentional doping. The thickness of the third high-temperature GaN layer is 0.03μm to 2μm, the growth temperature is 1050℃ to 1250℃, and the pressure is 30 torr to 320 torr.

7. The GaN-based LED epitaxial wafer as described in claim 1, characterized in that, The fifth high-temperature GaN layer is a high-temperature GaN material heavily doped with Si, with a Si doping concentration of 3.6 × 10⁻⁶. 18 / cm 3 ~5.6×10 19 / cm 3 The thickness of the fifth high-temperature GaN layer is 2μm to 8μm, the growth temperature is 1050℃ to 1250℃, and the pressure is 30 torr to 320 torr.

8. The method for preparing a GaN-based LED epitaxial wafer according to any one of claims 1 to 7, characterized in that, include: Select a substrate; A buffer layer is grown on the substrate; A Si doping source is introduced to grow an N-type semiconductor layer on the buffer layer; A low-temperature stress relief layer is grown on an N-type semiconductor layer; A multi-quantum-well light-emitting layer is grown on a low-temperature stress-relieving layer; An electron blocking layer is grown on a multi-quantum-well light-emitting layer; A P-type semiconductor layer is grown on an electron blocking layer; The N-type semiconductor layer comprises, from bottom to top, a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer, and a fifth high-temperature GaN layer. Before depositing the first porous low-temperature GaN layer, the second porous AlGaN / GaN superlattice layer, and the fourth porous AlGaN / GaN superlattice layer, the surface of the epitaxial layer material needs to be treated with high-temperature H2 gas. The temperature of the high-temperature H2 gas treatment is 1020℃~1250℃, and the pressure is 20 torr~360 torr.

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