Manufacturing method of zero-layer alignment mark suitable for multi-material active region substrate
By forming a dielectric layer liner in the zero-layer alignment marking region, the problem of zero-layer marking wear in multi-material active region processes is solved, achieving high-precision stacking alignment and chip manufacturing stability.
Patent Information
- Application Number
- CN202511640172.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-02-27
AI Technical Summary
In semiconductor processes with active regions made of multiple materials, traditional zero-layer alignment marks are worn down during epitaxial growth and chemical mechanical planarization, leading to subsequent nesting alignment failures.
A dielectric layer is formed in the zero-layer alignment marking region. Through etching and chemical mechanical planarization, the marking is ensured to maintain a clear step morphology and signal intensity after epitaxial growth and planarization. Silicon oxide is used as a hard mask and planarization stop layer, and a silicon nitride barrier layer is formed in the trench to prevent epitaxial material growth.
It maintains the stability and signal strength of the zero-layer alignment mark, reduces the layout load effect, ensures high-precision nesting alignment, and improves chip manufacturing yield and reliability.
Smart Images
Figure CN121586476A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating zero-layer alignment marks adaptable to active region substrates of various materials. Background Technology
[0002] In the process of integrated circuit manufacturing, the stacking and alignment of layers and the measurement are crucial. Ordinary chips are formed by stacking about 20-30 layers, while advanced processes may require hundreds of layers to complete the entire chip manufacturing process. Therefore, even a slight deviation in the stacking and measurement of each layer may eventually lead to circuit connection interruption and chip failure due to overlay problems (OVL shift).
[0003] Typically, the first layer in chip fabrication is the active area (AA). During the AA fabrication process, overlay alignment marks (OVL marks) are simultaneously fabricated at specific locations on the wafer. Subsequent overlay processes then use the AA OVL marks as a reference for overlay measurement to determine the accuracy of the overlay.
[0004] If there are some photolithography steps before the active region, such as DNW plasma implantation, a zero-mark layer will be made in the first step of wafer fabrication to allow these IMP layers to be stacked and aligned for measurement.
[0005] However, in the recent development of new processes, additional active region multi-material process steps need to be added to the process, involving etching, epitaxy of new materials and CMP polishing. In this process, the ZERO mark is flattened due to filling and polishing, which makes it impossible to measure the overlap relationship with the ZERO mark when the active region is operated in the subsequent process.
[0006] Therefore, the industry urgently needs a new method for fabricating zero-layer alignment markers. The markers produced by this method can resist the adverse effects of epitaxial growth and CMP polishing in multi-material active region processes, and maintain a clear morphology and sufficient step height in the critical alignment steps, thereby providing a stable and reliable signal for high-precision interlayer stacking alignment. Summary of the Invention
[0007] This invention aims to address the problems existing in the prior art. In novel semiconductor processes that introduce multi-material active regions, additional material epitaxial growth and chemical mechanical planarization steps are included. These steps often cause the step morphology of the traditional zero-layer alignment mark, which serves as an alignment reference, to be smoothed out. As a result, subsequent photolithography layers of the active region cannot detect effective alignment signals, leading to overlay alignment failure.
[0008] Therefore, one object of the present invention is to provide a method for fabricating zero-layer alignment marks that are adaptable to active region substrates of multiple materials. This method can ensure that the zero-layer alignment marks can still maintain a clear step morphology and sufficient signal strength after undergoing complex processes such as epitaxial growth and chemical mechanical planarization, so as to meet the requirements of high-precision stacking alignment.
[0009] To achieve the above-mentioned objective, this invention provides a method for fabricating zero-layer alignment marks adaptable to active region substrates of various materials. This method is performed on a substrate having a zero-layer alignment mark region and a channel region, and includes the following steps:
[0010] Step 1: Form a first dielectric layer on the substrate;
[0011] Step 2: Etch the first dielectric layer and the substrate within the zero-layer alignment mark region to form trenches in the substrate for constituting the zero-layer alignment mark, while the channel region is not etched.
[0012] Step 3: A second dielectric layer is formed conformally on the inner surface of the trench and on the first dielectric layer in the trench region. The second dielectric layer is used to block subsequent epitaxial growth.
[0013] Step 4: Perform chemical mechanical planarization on the second dielectric layer until the upper surface of the first dielectric layer is exposed, thereby retaining the second dielectric layer in the trench and removing the second dielectric layer from the trench region;
[0014] Step 5: Remove the first dielectric layer to expose the substrate surface in the channel region.
[0015] Preferably, the substrate is a silicon substrate.
[0016] Preferably, in step one, the first dielectric layer is used as a hard mask layer for etching and a stop layer for chemical mechanical planarization.
[0017] Preferably, the first dielectric layer is a silicon oxide layer.
[0018] Preferably, the thickness of the silicon oxide layer is greater than or equal to 100 angstroms.
[0019] Preferably, the second dielectric layer is a silicon nitride layer.
[0020] Preferably, in step three, before forming the second dielectric layer, a buffer layer is formed on the inner surface of the trench.
[0021] Preferably, the buffer layer is an oxide layer.
[0022] Preferably, after step five, the method further includes step six: ion implantation of the substrate to form a trap region.
[0023] Preferably, after step six, the method further includes: step seven, selectively epitaxially growing a first semiconductor material on the substrate surface of the trench region, wherein a second dielectric layer retained in the trench prevents the first semiconductor material from growing in the trench.
[0024] Preferably, after step seven, the method further includes: step eight, forming an active region composed of a second semiconductor material based on the first semiconductor material within the channel region.
[0025] Preferably, in step seven, the first semiconductor material is silicon.
[0026] Preferably, in step eight, the second semiconductor material is silicon-germanium.
[0027] As described above, the method for fabricating zero-layer alignment marks adaptable to active region substrates of various materials according to the present invention has the following beneficial effects:
[0028] This invention successfully solves the problem of zero-layer alignment marks being worn down and alignment signals disappearing due to epitaxial growth and chemical mechanical planarization in multi-material active region processes by pre-forming a dielectric layer liner within the trench of the zero-layer alignment mark, which acts as a barrier against subsequent epitaxial growth. The zero-layer alignment mark fabricated using this method maintains a stable trench morphology throughout the complex active region formation process. The sidewalls formed by this dielectric layer liner not only prevent epitaxial material from filling the trenches but also provide robust mechanical support for the mark structure, significantly reducing the layout load effect caused by pattern density differences, resulting in a clear final outline and sufficient step height for the mark. Therefore, when subsequent critical photolithography steps require alignment with the zero layer, this mark can provide a stable optical signal for the alignment system, ensuring high-precision overlay alignment, thereby significantly improving chip manufacturing yield and product reliability at advanced process nodes. Attached Figure Description
[0029] Figure 1 The diagram shows a flow chart of a method for fabricating zero-layer alignment marks adapted to multi-material active region substrates according to the present invention.
[0030] Figure 2 The diagram shows a cross-sectional view of the structure after a first dielectric layer is formed on a substrate according to an embodiment of the present invention.
[0031] Figure 3 The diagram shows a cross-sectional view of the structure after etching to form trenches in the zero-layer alignment mark region according to an embodiment of the present invention.
[0032] Figure 4 The diagram shows a cross-sectional view of the structure after forming the buffer layer and the second dielectric layer according to an embodiment of the present invention.
[0033] Figure 5The diagram shows a cross-sectional view of the structure after chemical mechanical planarization according to an embodiment of the present invention.
[0034] Figure 6 The diagram shows a cross-sectional view of the structure after removing the first dielectric layer according to an embodiment of the present invention.
[0035] Figure 7 The diagram shows a cross-sectional view of the structure after selective epitaxial growth of a first semiconductor material according to an embodiment of the present invention.
[0036] Figure 8 The diagram shown is a cross-sectional view of the structure after forming the active region of the second semiconductor material according to an embodiment of the present invention. Detailed Implementation
[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] Figure 1 This is a schematic flowchart of a method for fabricating zero-layer alignment marks for active region substrates adapted to multiple materials, provided by an embodiment of the present invention. Figures 2 to 8 This is a cross-sectional schematic diagram of a semiconductor structure formed at different stages according to an embodiment of the present invention.
[0039] This invention provides a method for fabricating zero-layer alignment marks adaptable to active region substrates of various materials, referring to... Figure 1 The method is performed on a substrate having a zero-layer alignment mark region and a channel region, and includes the following steps:
[0040] Step 1, refer to Figure 2 A first dielectric layer 102 is formed on the substrate 101.
[0041] Substrate 101 may include, but is not limited to, a bulk semiconductor substrate. For example, substrate 101 may be a silicon substrate. In other embodiments, substrate 101 may include semiconductors of other elements, such as germanium or diamond. Alternatively, substrate 101 may include compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium antimonide (InSb), or indium arsenide (InAs). Furthermore, substrate 101 may also include alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium phosphide (AlInAs), aluminum gallium arsenide (AlGaAs), or indium gallium arsenide (GaInAs). Substrate 101 may also be a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator substrate, a germanium-on-insulator (GOI) substrate, or a group III-V semiconductor substrate on an insulator. The SOI substrate may include a buried oxide layer that isolates the semiconductor layer above substrate 101 from the underlying substrate. The substrate 101 may also include epitaxially grown layers, strained layers, buried layers, and / or other structures. One function of the first dielectric layer 102 is to serve as a hard mask for subsequent etching steps, and at the same time, it acts as a stop layer in subsequent chemical mechanical planarization steps to achieve precise control of the planarization endpoint.
[0042] In some embodiments, substrate 101 is a silicon substrate.
[0043] In some embodiments, in step one, the first dielectric layer 102 is used as both a hard mask layer for etching and a stop layer for chemical mechanical planarization. This dual function simplifies the process flow, eliminating the need for additional deposition and removal of dedicated mask or stop layers, thus reducing manufacturing costs and process complexity.
[0044] In some embodiments, the first dielectric layer 102 is a silicon oxide layer. Specifically, the first dielectric layer 102 may be silicon oxide generated by thermal oxidation or deposited by chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Silicon oxide is chosen as the first dielectric layer 102 because it has good etching selectivity and planarization selectivity compared to subsequent materials such as silicon nitride, and is easily selectively removed by wet processes (such as hydrofluoric acid solutions).
[0045] In some embodiments, the thickness of the silicon oxide layer is greater than or equal to 100 angstroms. This thickness is ensured to withstand the wear and tear of the etching process when used as an etch hard mask, and to provide a sufficient process window when used as a chemical mechanical planarization stop layer to prevent premature wear during planarization and subsequent planarization failure.
[0046] Step Two, Refer to Figure 3The first dielectric layer 102 and the substrate 101 within the zero-layer alignment mark region are etched to form trenches in the substrate 101 for constituting the zero-layer alignment mark, while the trench region is not etched.
[0047] This step typically includes two sub-steps: photolithography and etching. First, a patterned photoresist layer defining the zero-layer alignment mark region is formed on the first dielectric layer 102 using standard photolithography processes such as photoresist coating, exposure, and development. Then, using this patterned photoresist layer as a mask, dry etching, such as reactive ion etching (RIE), is employed to first etch the exposed first dielectric layer 102 and then continue etching down to the substrate 101, thereby forming trenches with a predetermined depth. The depth and sidewall morphology of the trenches directly affect the signal intensity of the final alignment mark. During this process, the trench region is protected by photoresist or a hard mask, and its surface remains flat.
[0048] Step 3, refer to Figure 4 A second dielectric layer 104 is formed conformally on the inner surface of the trench and on the first dielectric layer 102 in the trench region. The second dielectric layer 104 is used to block subsequent epitaxial growth.
[0049] Conformal formation refers to the deposition of a film with a thickness that is substantially uniform across the horizontal surface, vertical sidewalls, and bottom. This is important for ensuring that the trench is completely and uniformly lined.
[0050] In some embodiments, the second dielectric layer 104 is a silicon nitride layer. Silicon nitride (SiN) has excellent barrier properties for subsequent silicon or silicon-germanium epitaxial growth, effectively suppressing the nucleation and growth of epitaxial materials within the zero-layer alignment marking trench. Of course, other dielectric materials with similar barrier properties can also be used, such as silicon oxynitride (SiON) or silicon carbide (SiC). The formation method can include LPCVD or PECVD to ensure the formation of a conformal layer of uniform thickness on the bottom and sidewalls of the trench.
[0051] In some embodiments, step three, before forming the second dielectric layer 104, further includes forming a buffer layer 103 on the inner surface of the trench. The purpose of the buffer layer 103 is to improve the interface characteristics between the second dielectric layer 104 and the underlying material (i.e., the substrate 101 within the trench). For example, when the substrate 101 is silicon and the second dielectric layer 104 is silicon nitride, direct contact can lead to defects (such as peeling defects) due to lattice mismatch and internal stress. The buffer layer 103 can effectively alleviate this stress, improving the adhesion and reliability of the thin film. The formation of the buffer layer 103 can be a selective process. For example, when the substrate 101 is silicon and the buffer layer 103 is an oxide layer, it can be achieved through a thermal oxidation process (such as introducing oxygen into a furnace tube). This process selectively grows a thin oxide layer on the surface of the silicon substrate 101 exposed within the trench, without growing it on the surface of the trench region already covered by the first dielectric layer 102 (silicon oxide), thereby achieving the effect of forming the buffer layer 103 only within the trench.
[0052] In some embodiments, the buffer layer 103 is an oxide layer. This oxide layer can be a very thin layer of silicon oxide, and its formation is flexible. For example, in the same equipment (such as a furnace tube) used to deposit the second dielectric layer 104, oxygen is first introduced for in-situ thermal oxidation to grow a thin oxide layer on the silicon substrate surface, and then the gas is switched for silicon nitride deposition. This in-situ process is continuous and can effectively avoid contamination that may occur when transferring wafers between different devices.
[0053] Step 4, Refer to Figure 5 The second dielectric layer 104 is chemically and mechanically planarized until the upper surface of the first dielectric layer 102 is exposed, thereby retaining the second dielectric layer 104 and the buffer layer 103 in the trench, and removing the second dielectric layer 104 and the buffer layer 103 from the trench region.
[0054] This step utilizes the first dielectric layer 102 as a planarization stop layer. Since the first dielectric layer 102 (e.g., silicon oxide) and the second dielectric layer 104 (e.g., silicon nitride) have different polishing rates in a specific polishing slurry, highly selective planarization can be achieved, precisely stopping at the surface of the first dielectric layer 102. After planarization, the second dielectric layer 104 and the buffer layer 103 outside the trench are completely removed, leaving only the inner wall and bottom of the trench, forming a liner structure. This structure provides robust support for maintaining the trench's morphology in subsequent steps.
[0055] Step 5, Refer to Figure 6 Remove the first dielectric layer 102 to expose the surface of the substrate 101 in the channel region.
[0056] This step is typically performed using wet etching, for example, with a dilute hydrofluoric acid (DHF) solution. Because hydrofluoric acid has an extremely high etching rate for silicon oxide but a very low etching rate for silicon nitride and silicon substrates, it can precisely and efficiently remove the residual first dielectric layer 102 on the channel region and the zero-layer alignment marking region, while preserving the lining structure of the second dielectric layer 104 and the buffer layer 103 within the trench, as well as the exposed fresh channel region substrate surface, preparing it for subsequent ion implantation and epitaxial growth.
[0057] In some embodiments, after step five, the method further includes:
[0058] Step 6: Ion implantation is performed on substrate 101 to form a trap region.
[0059] Ion implantation, such as N-well or P-well, is performed on the exposed substrate surface.
[0060] In some embodiments, after step six, the method further includes:
[0061] Step 7, Refer to Figure 7 A first semiconductor material 105 is selectively epitaxially grown on the surface of a substrate 101 in the trench region, wherein a second dielectric layer 104 retained in the trench prevents the first semiconductor material 105 from growing in the trench.
[0062] Selective epitaxial growth refers to the growth of semiconductor materials only on exposed crystalline surfaces (such as the silicon surface in the channel region), and not on amorphous surfaces (such as the silicon nitride liner within the zero-layer alignment mark trench). High selectivity can be achieved by precisely controlling the temperature, pressure, and gas chemistry of the epitaxial process. Due to the blocking effect of the second dielectric layer 104 on the inner walls and bottom of the trench, even during full-wafer epitaxial growth, the zero-layer alignment mark trench will not be filled with epitaxial material, thus completely preserving its step morphology.
[0063] In some embodiments, in step seven, the first semiconductor material 105 is silicon.
[0064] In some embodiments, after step seven, the method further includes:
[0065] Step 8, Refer to Figure 8 Within the channel region, an active region composed of a second semiconductor material 106 is formed based on the first semiconductor material 105.
[0066] This is typically a follow-up step in multi-material active region substrate processes. For example, on silicon (first semiconductor material 105) epitaxially grown in the channel region, embedded silicon germanium (eSiGe) is formed as a channel (second semiconductor material 106) through trench etching and selective epitaxial filling to introduce strain and improve transistor performance. During this process, the morphology of the zero-layer alignment marking region remains unaffected.
[0067] In some embodiments, in step eight, the second semiconductor material 106 is silicon-germanium.
[0068] In summary, the fabrication method provided by this invention successfully solves the problem of zero-layer alignment marks being worn down and alignment signals disappearing due to epitaxial growth and chemical mechanical planarization in multi-material active region processes by forming a dielectric layer liner within the trench of the zero-layer alignment mark, which acts as a barrier to subsequent epitaxial growth. The zero-layer alignment mark fabricated using this method maintains a stable trench morphology throughout the complex active region formation process. The sidewalls formed by the second dielectric layer not only prevent epitaxial filling but also provide mechanical support for the mark structure, significantly reducing the layout load effect caused by differences in pattern density, resulting in a clear final outline and sufficient step height for the mark. Therefore, when subsequent active region photolithography steps require alignment with the zero layer, this mark can provide a stable optical signal, ensuring high-precision overlay alignment, thereby improving the chip manufacturing yield and reliability of advanced process nodes.
[0069] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating zero-layer alignment marks adaptable to active region substrates of multiple materials, characterized in that, At least including: Step 1: Form a first dielectric layer on the substrate; Step 2: Etch the first dielectric layer and the substrate within the zero-layer alignment mark region to form trenches in the substrate for constituting the zero-layer alignment mark, while the trench region is not etched. Step 3: A second dielectric layer is formed conformally on the inner surface of the trench and on the first dielectric layer in the trench region. The second dielectric layer is used to block subsequent epitaxial growth. Step 4: Perform chemical mechanical planarization on the second dielectric layer until the upper surface of the first dielectric layer is exposed, thereby retaining the second dielectric layer in the trench and removing the second dielectric layer from the trench region; Step 5: Remove the first dielectric layer to expose the substrate surface in the channel region.
2. The method of claim 1, wherein: The substrate is a silicon substrate.
3. The method of claim 1, wherein: In step one, the first dielectric layer is used as the hard mask layer for etching and the stop layer for chemical mechanical planarization.
4. The method of claim 1 or 3, wherein: The first dielectric layer is a silicon oxide layer.
5. The method of claim 1, wherein: The thickness of the silicon oxide layer is greater than or equal to 100 angstroms.
6. The method of claim 1, wherein: The second dielectric layer is a silicon nitride layer.
7. The method of claim 1 or 6, wherein: In step three, before forming the second medium layer, a buffer layer is formed on the inner surface of the trench.
8. The method of claim 7, wherein: The buffer layer is an oxide layer.
9. The method of claim 1, wherein: Following step five, the process also includes step six: ion implantation of the substrate to form a trap region.
10. The method of claim 9, wherein: Following step six, the method further includes step seven: selectively epitaxially growing a first semiconductor material on the substrate surface in the trench region, wherein the second dielectric layer retained in the trench prevents the first semiconductor material from growing in the trench.
11. The method of claim 10, wherein: After step seven, the method further includes: step eight, forming an active region composed of a second semiconductor material based on the first semiconductor material within the channel region.
12. The method for fabricating zero-layer alignment marks adaptable to multi-material active region substrates according to claim 10, characterized in that: In step seven, the first semiconductor material is silicon.
13. The method for fabricating zero-layer alignment marks adaptable to multi-material active region substrates according to claim 11, characterized in that: In step eight, the second semiconductor material is silicon-germanium.