Integrated chip and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to an integrated chip and a preparation method thereof.The integrated chip comprises a plurality of monochromatic light-emitting bodies, positive electrodes and negative electrodes, and N-type semiconductor layers of the light-emitting bodies are connected to form a common cathode structure; the integrated chip is used as a pixel of a display screen, or the integrated chip is in counterpoint connection with a driving IC (integrated circuit) to obtain integrated light-emitting modules, and the light-emitting modules are distributed in an array for image display; in the preparation method of the integrated chip, epitaxial materials in a wafer substrate are etched, secondary etching is carried out on N-type semiconductor layers in the epitaxial materials, a plurality of integrated regions are obtained, each integrated region comprises at least three protruding blocks, and the N-type semiconductor layers at the bottoms of the protruding blocks in the same integrated region are connected to form a common cathode structure. And one negative electrode is arranged in the same integrated chip, so that the space occupied by the electrodes is reduced, further reduction of the size of the luminous body is facilitated, and the integration level of the integrated chip is improved.

Description

Technical Field

[0001] This invention relates to the field of light-emitting chip technology, and in particular to an integrated chip and its fabrication method. Background Technology

[0002] In the field of Micro LED display technology, integrated chips are the core components for achieving high-density pixels and improving display performance. They are usually composed of several light-emitting elements arranged in a specific structure.

[0003] In existing integrated chips, each light emitter has a positive electrode and a negative electrode. For flip-chip light emitters, the positive and negative electrodes are located on the same side of the same light emitter, which occupies a lot of space and is not conducive to further miniaturization of the light emitter size, thus affecting the improvement of the integration density of the integrated chip. Summary of the Invention

[0004] In view of the above-mentioned shortcomings in the prior art, one object of this application is to provide an integrated chip that facilitates further reduction in the size of the light-emitting element and can improve the integration density.

[0005] The technical solution adopted in this application is as follows: An integrated chip, characterized in that the integrated chip comprises: A plurality of monochromatic light emitters, each of the light emitters comprising stacked N-type semiconductor layers, light-emitting layers, and P-type semiconductor layers, wherein the N-type semiconductor layers are connected to form a common cathode structure; the bottom of the N-type semiconductor layers of each of the light emitters is continuous, forming a continuous region, and at least one side of the continuous region protrudes outward to form a step; A positive electrode and a negative electrode are provided. The negative electrode is located on the step and electrically connected to the N-type semiconductor layer, and the positive electrode is located on the P-type semiconductor layer and electrically connected to the P-type semiconductor layer.

[0006] Its further feature is that, The size of the light-emitting element is less than or equal to 100 μm.

[0007] Furthermore, the light-emitting element includes, but is not limited to, Mini LED or Micro LED.

[0008] Furthermore, the light color of the light-emitting body includes, but is not limited to, blue, green, or red.

[0009] Furthermore, each of the integrated chips includes at least three light emitters, which are arranged side by side at intervals, or in a triangular or quadrilateral arrangement.

[0010] Furthermore, it also includes a current spreading layer and an ohmic contact layer. The current spreading layer is located on the surface of the P-type semiconductor layer and is used to electrically connect the positive electrode to the P-type semiconductor layer. The ohmic contact layer is located between the negative electrode and the N-type semiconductor layer and is used to achieve ohmic contact between the negative electrode and the N-type semiconductor layer.

[0011] Furthermore, it also includes an insulating layer or a composite layer, which covers the entire surface including the surface of the N-type semiconductor layer and the surface of the P-type semiconductor layer. The composite layer includes two insulating layers and a reflective layer distributed between the two insulating layers. The reflective layer is used for light reflection. The bottom end of the positive electrode penetrates the insulating layer or the composite layer and is electrically connected to the P-type semiconductor layer. The bottom end of the negative electrode penetrates the insulating layer or the composite layer and is electrically connected to the N-type semiconductor layer.

[0012] A color integrated chip, characterized in that it comprises: the aforementioned integrated chip and a color filter, wherein the color filter is disposed on the light-emitting surface of a light-emitting element in the integrated chip and is used to convert the light color of the light-emitting element.

[0013] A further feature is that the color filter includes a contrast enhancement layer and a light color conversion area. The contrast enhancement layer is used to enhance the display contrast, and the light color conversion area is located in the gap between two adjacent contrast enhancement layers, corresponding one-to-one with the light emitter, and is used to convert the light color of the light emitter into other colors.

[0014] A further feature is that each of the light-emitting modules includes N integrated chips, where N is an integer greater than or equal to 1, and when N is greater than or equal to 2, the integrated chip arrays in the same light-emitting module are distributed.

[0015] Furthermore, the light emitter in the integrated chip is aligned and connected to the driver IC.

[0016] A display screen includes: a plurality of integrated chips and a driver IC, characterized in that the integrated chips are integrated with the driver IC to form a light-emitting module, the driver IC is used to control the working state of the light-emitting element, the light-emitting element in the integrated chip is aligned and connected with the driver IC, and the light-emitting module is distributed in an array.

[0017] Its further feature is that, The display screen also includes a driving substrate, and the driving IC in the light-emitting module is electrically connected to the driving substrate.

[0018] Furthermore, the driving substrate includes, but is not limited to, a PCB board.

[0019] Another object of this application is to provide a method for fabricating an integrated chip, for fabricating the aforementioned integrated chip, characterized in that the method includes: A wafer is provided, the wafer including a substrate and an epitaxial material distributed on the substrate, the epitaxial material including N-type semiconductor material, light-emitting material and P-type semiconductor material stacked together; The epitaxial material is etched to a depth that reaches the surface of the N-type semiconductor material or the interior of the N-type semiconductor material. This etching is a single etching process, resulting in a plurality of arrayed bumps. The bumps include stacked P-type semiconductor layers, light-emitting layers, and N-type semiconductor layers, wherein the N-type semiconductor layers are continuous. The N-type semiconductor layer is etched a second time to obtain several integrated regions. Each integrated region includes at least three bumps. The N-type semiconductor layer in the same integrated region is continuously formed into a continuous region to obtain a common cathode structure. At least one side of the continuous region protrudes to form a step. A positive electrode is formed above the bump, and a negative electrode is formed above the step. The positive electrode is electrically connected to the P-type semiconductor layer, and the negative electrode is electrically connected to the N-type semiconductor layer.

[0020] Its further feature is that, The N-type semiconductor material is N-type GaN, the light-emitting material is a quantum well material, and the P-type semiconductor material is P-type GaN.

[0021] Furthermore, both the primary and secondary etching processes employ photolithography.

[0022] Furthermore, prior to the first etching step, a current spreading material is deposited on the surface of the P-type semiconductor material. A photolithography etching process is then used to sequentially etch the current spreading material and the epitaxial material to form the current spreading layer and the bump.

[0023] Furthermore, before the secondary etching, an insulating material or composite material is deposited on the entire surface containing the current spreading layer to form an insulating layer or composite layer. A photolithography etching process is then used to perform a secondary etching based on the gap between the bumps, with the etching depth reaching the surface of the substrate, to obtain an integration area containing the insulating layer or composite layer.

[0024] Furthermore, before preparing the insulating layer or composite layer, an ohmic contact layer is prepared on the surface of the step, the ohmic contact layer being used to achieve ohmic contact between the negative electrode and the N-type semiconductor layer.

[0025] A method for fabricating a color integrated chip, characterized in that the method includes: Several integrated chips are transferred to a temporary substrate, wherein the electrodes of the integrated chips correspond to the temporary substrate, and the light-emitting surface of the light-emitting element in the integrated chip is disposed away from the temporary substrate; A color filter is provided on the light-emitting surface of the light-emitting body, and the color filter is used to convert the light color of the light-emitting body; A light-transmitting substrate is disposed on the surface of the color filter; Remove the temporary substrate; The color integrated chip is obtained by cutting based on the gaps between the integrated chips.

[0026] Its further feature is that, A color filter is applied to the light-emitting surface using semiconductor technology or film-coating technology.

[0027] Furthermore, the color filter includes a contrast enhancement layer and a light color conversion layer. The color filter is deposited on the light-emitting surface using semiconductor technology, including: using photolithography, deposition and lift-off processes to prepare an array of contrast enhancement layers on the light-emitting surface. A light-color conversion layer is prepared in the gap between the contrast enhancement layers using a photolithography etching process.

[0028] Furthermore, the contrast enhancement layer is made of a black or gray material, which includes, but is not limited to, at least one of Al, Ti, and Au.

[0029] Furthermore, the light color conversion zone includes at least a first light color conversion enhancement zone, a second light color conversion zone, and a third light color conversion zone, and the first light color conversion enhancement zone, the second light color conversion zone, and the third light color conversion zone correspond one-to-one with the light-emitting body.

[0030] Furthermore, the light emitter emits blue light, the first color conversion region includes red quantum dot photoresist for converting the blue light into red light, the second color conversion region includes green quantum dot photoresist for converting the blue light into green light, and the third color conversion region includes transparent quantum dot photoresist or an empty region for transmitting the blue light.

[0031] A method for fabricating a light-emitting module, characterized in that the method includes: Provide integrated chips and driver ICs; The integrated chip is aligned and connected with the driver IC to obtain the light-emitting module.

[0032] Its further feature is that, The integrated chip and the driver IC are aligned and connected using a alignment bonding process.

[0033] Furthermore, the fabrication method further includes: setting a redistribution layer on the side where the light-emitting electrode is located in the integrated chip, or setting a redistribution layer on the wiring structure side in the driver IC, wherein the redistribution layer includes an insulating layer and a first connection circuit distributed in the insulating layer, and the electrode of the light-emitting element in the integrated chip is electrically connected to the driver IC through the first connection circuit.

[0034] The above-mentioned solution of this application can achieve the following beneficial effects: In the integrated chip of this application, the N-type semiconductor layers are connected to form a common cathode structure. Therefore, only one negative electrode needs to be set in the same integrated chip, thereby reducing the space occupied by the electrode, which is conducive to further miniaturization of the light-emitting body size, and thus improving the integration degree of the integrated chip. Attached Figure Description

[0035] Figure 1 This is a top view of the integrated chip in Embodiment 1 of this application; Figure 2 This is a side view of the integrated chip in Embodiment 1 of this application. Figure 3 This is a schematic diagram of the main structure of the integrated chip in Embodiment 1 of this application; Figure 4 This is a top view of another embodiment of the integrated chip in this application; Figure 5 This is a top view schematic diagram of other embodiments of the integrated chip in this application; Figure 6 This is a schematic diagram of the main structure of the integrated chip in Embodiment 2 of this application; Figure 7 This is a side view of the integrated chip in Embodiment 2 of this application; Figure 8 This is a schematic diagram of the front view structure of the color integrated chip in this application; Figure 9 This is a schematic diagram of the main view structure of another color integrated chip in this application; Figure 10 This is a schematic diagram of the main structure of the light-emitting module (a single color integrated chip integrated with a driver IC) of this application; Figure 11 This is a schematic diagram of the main structure of another light-emitting module (another single color integrated chip integrated with a driver IC) in this application; Figure 12 This is a top view schematic diagram of the structure after multiple (four) color integrated chips and driver ICs are integrated in this application; Figure 13 This is a top view of the display screen structure of this application; Figure 14 This is a schematic diagram of the wafer structure in the fabrication method of the integrated chip in Embodiment 1 of this application; Figure 15 This is a schematic diagram of the structure after bumps are formed in the fabrication method of the integrated chip in Embodiment 1 of this application; Figure 16 This is a schematic diagram of the structure after secondary etching in the fabrication method of the integrated chip in Embodiment 1 of this application; Figure 17 This is a schematic diagram of the structure after the positive and negative electrodes are formed in the fabrication method of the integrated chip in Embodiment 1 of this application; Figure 18 This is a schematic diagram of the structure after the contrast enhancement layer is formed in the color integrated chip fabrication method of this application; Figure 19 This is a schematic diagram of the structure after the light conversion layer is formed in the color integrated chip fabrication method of this application; Figure 20 This is a schematic diagram of the structure after removing the temporary substrate in the color integrated chip fabrication method of this application. Figure 21 This is a schematic diagram of the structure of the color integrated chip (including the light-transmitting substrate) of this application; Figure 22 This is a schematic diagram of the structure after the current spreading layer and bumps are formed in the fabrication method of the integrated chip in Embodiment 2 of this application; Figure 23 This is a schematic diagram of the structure after secondary etching in the fabrication method of the integrated chip in Embodiment 2 of this application; Figure 24 This is a schematic diagram of the structure after the positive and negative electrodes are formed in the fabrication method of the integrated chip in Embodiment 2 of this application; Figure 25 This is a schematic diagram of the structure after the contrast enhancement layer is formed in another color integrated chip fabrication method of this application; Figure 26 This is a schematic diagram of the structure after the light conversion layer is formed in another method for fabricating a color integrated chip according to this application; Figure 27 This is a schematic diagram of the structure after removing the temporary substrate in another color integrated chip fabrication method of this application; Figure 28 This is a schematic diagram of the structure of another color integrated chip (including a light-transmitting substrate) in this application; Figure 29 This is a schematic diagram of the driver IC structure of this application; Figure 30 This is a schematic diagram of the structure after the integrated chip and driver IC are aligned and connected in this application; Figure 31 This is a schematic diagram of the back of the driver IC in this application.

[0036] Reference numerals: 1. Light emitter; 2. Positive electrode; 3. Negative electrode; 4. Driver IC; 5. Color filter; 6. Driver substrate; 7. Temporary substrate; 8. Transparent substrate; Substrate 100, N-type semiconductor layer 101, light-emitting layer 102, P-type semiconductor layer 103, current spreading layer 104, insulating layer or composite layer 105, ohmic contact layer 106; N-type semiconductor material 1001, luminescent material 1002, P-type semiconductor material 1003, ITO material 1004; Substrate 400, first pad 401, second pad 402, third pad 403, first connection circuit 404, fourth pad 405, second connection circuit 406; Contrast enhancement layer 501, light and color conversion area 502. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product or device.

[0039] The following describes several specific embodiments of integrated chips.

[0040] Integrated Chip Example 1 The integrated chip includes: several monochromatic light emitters 1, a positive electrode 2, and a negative electrode 3. Each light emitter 1 includes an N-type semiconductor layer 101, a light-emitting layer 102, and a P-type semiconductor layer 103 stacked together. The N-type semiconductor layers 101 are connected to form a common cathode structure. The negative electrode 3 is electrically connected to the N-type semiconductor layer 101, and the positive electrode 2 is electrically connected to the P-type semiconductor layer 103.

[0041] In this embodiment, the P-type semiconductor layer 103 is a P-GaN layer, the N-type semiconductor layer 101 is an N-GaN layer, the light-emitting layer is a quantum well layer, and the surface of the N-type semiconductor layer 101 is the light-emitting surface. The size of the light emitter 1 is less than 100 μm, for example, 30 μm, and the emitted light color is blue.

[0042] In this embodiment, three light-emitting bodies 1 are arranged side by side at intervals, and the electrodes of the light-emitting bodies 1 are in the same direction. In this structure, one negative electrode 3 and three positive electrodes 2 are included in the same integrated chip, as Figure 1 , Figure 2 , Figure 3 shown. The bottom regions of the N-type semiconductor layers of the light-emitting bodies 1 in the same integrated chip are connected to form a continuous region, that is, a common cathode structure. At least one side of the continuous region extends outward to form a step. The negative electrode 3 is strip-shaped and is disposed above the step, and its bottom is electrically connected to the N-type semiconductor layer 101; the positive electrodes 2 are respectively located above the P-type semiconductor layers 103 of the light-emitting bodies 1, and the bottom is electrically connected to the P-type semiconductor layer 103.

[0043] It should be noted that in another embodiment, the three light-emitting bodies 1 are distributed in a "pin" shape, refer to Figure 4 , or, a single integrated chip includes four light-emitting bodies 1, and the four light-emitting bodies 1 are distributed in a rectangle, refer to Figure 5 .

[0044] Integrated Chip Embodiment 2 Refer to Figure 6 , Figure 7 , the integrated chip includes: a plurality of monochromatic light-emitting bodies 1, a positive electrode 2, and a negative electrode 3. Each light-emitting body 1 includes an N-type semiconductor layer 101, a light-emitting layer 102, and a P-type semiconductor layer 103 that are stacked. The N-type semiconductor layers 101 are connected to form a common cathode structure. The negative electrode 3 is electrically connected to the N-type semiconductor layer 101, and the positive electrode 2 is electrically connected to the P-type semiconductor layer 103.

[0045] In this embodiment, the P-type semiconductor layer 103 is a P-GaN layer, the N-type semiconductor layer 101 is an N-GaN layer, the light-emitting layer is a quantum well layer, and the surface of the N-type semiconductor layer 101 is the light-emitting surface. The size of the light-emitting body 1 is less than 100 μm, such as 50 μm, and the emitted light color is blue.

[0046] In addition, the integrated chip further includes a current spreading layer 104, an insulating layer or a composite layer 105, and an ohmic contact layer 106. Among them, the current spreading layer 104 is preferably an ITO current spreading layer for quickly and uniformly spreading the current transmitted by the positive electrode 2 to the P-type semiconductor layer 103. The material of the ohmic contact layer 106 is preferably a composite material of Cr, Ni, Al, TiAl, Au and GeAuNi alloy (chromium-gold-nickel alloy), a composite material of Au and AuZn (gold-zinc) alloy, AuZn, GeAuNi alloy or Au, and is located between the negative electrode 3 and the N-type semiconductor layer 101 for realizing ohmic contact between the negative electrode 3 and the N-type semiconductor layer 101. The settings of the current spreading layer 104 and the ohmic contact layer 106 are both beneficial to improving the electrical performance of the integrated chip.

[0047] The integrated chip also includes an insulating layer or composite layer 105, which covers the entire surface including the surface of the N-type semiconductor layer and the surface of the P-type semiconductor layer. The insulating layer material is preferably SiO2 or SiNx, which provides insulation and is used to achieve electrical isolation between the positive and negative electrodes. The composite layer includes two insulating layers and a reflective layer distributed between the two insulating layers. The reflective layer is a metallic reflective layer, a hybrid reflective layer, or a DBR reflective layer. The metallic reflective layer includes stacked Ni, Ag, and Au, while the hybrid reflective layer includes stacked ITO, Ag, and TiW, used for light reflection.

[0048] In this embodiment, three light emitters 1 are arranged side by side with intervals, and the electrodes of the light emitters 1 are in the same direction. In this structure, the same integrated chip contains one negative electrode 3 and three positive electrodes 2. To facilitate the implementation of this structure, the bottom regions of the N-type semiconductor layer 101 of the light emitters 1 in the same integrated chip are connected to form a continuous region, that is, a common cathode structure is formed. At least one side of the continuous region extends outward to form a step. The negative electrode 3 is disposed on the step, and its bottom penetrates the insulating layer or composite layer 105 and is electrically connected to the N-type semiconductor layer 101 through the ohmic contact layer 106. The positive electrode 2 is located above the P-type semiconductor layer 103, and its bottom penetrates the insulating layer or composite layer 105 and is electrically connected to the P-type semiconductor layer 103 through the current spreading layer 104.

[0049] It should be noted that, in another embodiment, a local area of ​​the negative electrode 3 extends from the surface of the insulating layer to above the P-type semiconductor layer 103, forming a larger extended negative electrode. Furthermore, the upper surface of the negative electrode is flush with the upper surface of the positive electrode, which is beneficial for the alignment and bonding of the integrated chip and the driver IC in subsequent processes.

[0050] In the integrated chip of the above embodiment, the light emitters 1 share the same negative electrode 3, and the negative electrode 3 is located on one side of the light emitter 1. This reduces the space occupied by the electrode in the light emitter and is beneficial for further miniaturization of the light emitter size. In addition, sharing the same negative electrode and / or having the negative electrode located on one side of the light emitter not only helps to expand the size of the negative electrode, but also facilitates the fabrication of a larger positive electrode 2 on the light emitter, thereby making it easier for the integrated chip to be flip-chip bonded to the driver IC4.

[0051] In this application, to achieve color display, a color filter 5 is provided on the light-emitting surface of the light-emitting element 1 in the integrated chip of Embodiment 1 or Embodiment 2, respectively forming a color integrated chip, as shown in the reference. Figure 8 , Figure 9The color filter 5 is used to convert the color of light from the light source 1. It mainly includes several contrast enhancement layers 501 and color conversion areas 502. The contrast enhancement layers 501 are used to enhance the display contrast. The color conversion areas 502 are located in the gap between two adjacent contrast enhancement layers 501 and correspond one-to-one with the light source 1. They are used to convert the color of light from the light source 1 into at least two other colors.

[0052] The light color conversion area 502 is designed according to the arrangement structure of the light emitters 1. For example, in Embodiment 1, the integrated chip includes three light emitters 1, then the light color conversion area 502 includes a first light color conversion area, a second light color conversion area, and a third light color conversion area. The first light color conversion enhancement area, the second light color conversion area, and the third light color conversion area correspond one-to-one with the light emitters 1. The first light color conversion area includes red quantum dot photoresist, which is used to convert the blue light emitted by the light emitter 1 into red light. The second light color conversion area includes green quantum dot photoresist, which is used to convert the blue light emitted by the light emitter 1 into green light. The third light color conversion area includes transparent quantum dot photoresist or an empty area, which is used to directly transmit blue light. The blue light, green light, and red light are mixed to achieve color display.

[0053] The contrast enhancement layer 501 is made of black or gray material, and the black or gray material includes at least one of Al, Ti and Au. In this embodiment, Ti is preferred.

[0054] In the color integrated chip of this application, the color filter 5 is disposed on the light-emitting surface of the light emitter 1. It does not require opening nanopores in the semiconductor layer of the light emitter 1, thus avoiding the problem of reduced light emission effect caused by opening nanopores due to the setting of the color filter 5.

[0055] To facilitate drive control, the aforementioned integrated chip or color integrated chip is integrated with driver IC4 to obtain a light-emitting module. The light-emitting element 1 in the integrated chip or color integrated chip is aligned and connected to driver IC4. (Reference) Figure 10 , Figure 11 The number of integrated chips or color integrated chips is 1. It should be noted that, in another embodiment, N integrated chips or color integrated chips can be integrated with driver IC4, where N is greater than or equal to 2, for example, N equals 4. (See reference...) Figure 12 The integrated chips or color integrated chip array is distributed, and the color filter 5 covers the entire surface containing the light-emitting surface of each integrated chip or color integrated chip.

[0056] The wiring structure in the driver IC includes: a first pad 401, a second pad 402, and a third pad 403. The first pad 401 is used for flip-chip alignment with the light emitter 1. The second pad 402 is connected to the first pad 401 through a first connection circuit 404 and to the third pad 403 through a driver circuit. The third pad 403 is used for connecting to an external driver.

[0057] In this embodiment, the first connection circuit 404 and the first pad 401 are located in the center of the front side of the substrate, and the second pad 402 and the third pad 403 are located at the edge of the front side of the substrate. (Refer to...) Figure 29 Furthermore, to facilitate electrical connection between the driver IC4 and the external driver substrate 6 (e.g., a PCB board), in this embodiment, a fourth solder joint 405 is provided on the back side of the substrate. (Refer to...) Figure 31 The third pad 403 is electrically connected to the fourth pad 404 via the second connection circuit. The second connection circuit 406 extends from the front to the back of the substrate along the edge of the substrate. The second pad 402 and the third pad 403 are located at the edge of the substrate, which facilitates the wiring of the second connection circuit 406 and the connection of the fourth pad 405. The fourth pad 405 is located on the back of the substrate, which not only saves the space occupied on the front of the substrate, but also helps to reduce the overall size of the driver IC4, or facilitates the fabrication of a larger fourth pad 405, thereby further facilitating the electrical connection between the driver IC4 and the external driver substrate 6, and also facilitating the subsequent mounting of the light-emitting module onto the driver substrate 6 (e.g., a PCB board) using surface mount technology.

[0058] In an integrated chip or color integrated chip, there are three light emitters 1, and the cathodes of the light emitters 1 are connected to form a common cathode structure. The first pad 401 includes one first negative pad and two first positive pads, with the number of first positive pads matching the number of light emitters. The second pad 402 corresponds to the number of first pads 401. The third pad 403 includes a data transmission terminal, a clock signal terminal, an AVSS terminal, and a voltage source terminal.

[0059] It should be noted that, in order to further reduce the lateral space occupied by the driver IC4 and improve the integration density, in another embodiment, reference is made to... Figure 30 A redistribution layer can be provided on the wiring structure side of the driver IC4. The first connection circuit 404 and the first pad 401 are distributed in the insulating layer of the redistribution layer. The first pad 401 is distributed on the side of the insulating layer away from the substrate to facilitate flip-chip alignment with the light emitter 1. The second pad 402 and the third pad 403 are distributed on the front surface of the substrate, and the fourth pad 405 is disposed on the back surface of the substrate. The light emitter 1 is connected to the second pad 402 through the first pad 401 and the first connection circuit 404. The second pad 402 is connected to the third pad 403 through the driving circuit. The third pad 403 is connected to the fourth pad 405 through the second connection circuit 406, thereby realizing the integration of the driver IC4 with the integrated chip.

[0060] The above-mentioned light-emitting modules are applied to the display screen, and the array distribution of the light-emitting modules is as follows: Figure 13In this embodiment, the driving substrate 6 is a PCB board. The driving IC4 in the light-emitting module is flip-chip bonded to the pads in the driving substrate 6 via the fourth pad 405. It should be noted that, in another embodiment, the driving IC in the light-emitting module can communicate with an external processor via optical communication or other means.

[0061] In this application, a combination structure of the third pad 403, the second connection circuit 406 and the fourth pad 405 is used to replace the lead wire. The lead wire setup is prone to problems such as complex wiring and occupying the outer peripheral space of the driver IC4. The above combination structure makes full use of the substrate space, avoids the above problems, and is conducive to reducing the gap between the light-emitting modules, further improving the integration of the display screen, obtaining a high-density pixel display screen, and is also conducive to the subsequent packaging of the display screen.

[0062] During display, the external processor sends a drive signal to the drive substrate 6. The drive signal is transmitted to the drive IC 4 via the fourth pad 405, the second connection circuit 406, and the third pad 403. After being converted by the drive IC 4, it is transmitted to the light emitter 1 via the drive circuit, the second pad 402, the first connection circuit 404, and the first pad 401 to control the working state of the light emitter 1. The blue light emitted by the light emitter 1 is converted into red light and green light through the first color conversion area and the second color conversion area, respectively. After being transmitted through the third color conversion area, the red light, green light, and blue light are mixed to achieve color display.

[0063] The following provides a method for fabricating an integrated chip, used to fabricate the integrated chip of Example 1. The specific fabrication steps include: S1. A wafer is provided, the wafer including a substrate 100 and epitaxial material distributed on the substrate 100, reference. Figure 14 The epitaxial materials include stacked N-type semiconductor materials, light-emitting materials, and P-type semiconductor materials. The N-type semiconductor material is N-type GaN, the light-emitting material is a quantum well material, and the P-type semiconductor material is P-type GaN.

[0064] S2. Photolithography is used to etch the epitaxial material. Specifically, photoresist is coated on the surface of the epitaxial material, and the photoresist is exposed and developed. Based on the developed pattern, dry or wet etching is used to etch the epitaxial material to a depth reaching the surface or interior of the N-type semiconductor material. This etching is a single etching operation, resulting in several arrayed bumps. See [link to previous section]. Figure 15 The bump includes a stacked P-type semiconductor layer 103, a light-emitting layer 102, and an N-type semiconductor layer 101, with the N-type semiconductor layer 101 being interconnected.

[0065] S3. A second etching process is performed on the N-type semiconductor layer 401 using photolithography. Specifically, photoresist is coated onto the entire surface including the N-type semiconductor layer. The photoresist is exposed and developed. Based on the developed pattern, the N-type semiconductor layer 401 is etched a second time to obtain several integration areas, as shown in [reference needed]. Figure 16 Each integrated region includes at least three bumps. The N-type semiconductor layer 101 at the bottom of the bumps in the same integrated region are connected to form a continuous region, i.e., a common cathode structure is formed. One side of the continuous region protrudes to form a step, which facilitates the setting of the negative electrode 3 in subsequent processes.

[0066] S4. Prepare positive electrode 2 and negative electrode 3 to obtain an integrated chip. Specifically, coat photoresist on the bump surface, expose and develop the photoresist, and deposit conductive material on the photoresist surface using electron beam evaporation or magnetron sputtering. In this embodiment, the conductive material is preferably at least one of Cr, Al, Ti, Pt, Au, and Ni. Based on the developed pattern, the conductive material is stripped to obtain positive electrode 2 and negative electrode 3. Positive electrode 2 is located above the P-type semiconductor layer 103. Figure 17 The negative electrode 3 is located above the step and is electrically connected to the N-type semiconductor layer 101, thus obtaining an integrated chip.

[0067] The following provides another method for fabricating an integrated chip, used to fabricate the integrated chip of Example 2. The specific fabrication steps include: S1. A wafer is provided, the wafer including a substrate 100 and epitaxial materials distributed on the substrate, the epitaxial materials including N-type semiconductor material 1001, light-emitting material 1002, and P-type semiconductor material 1003 stacked together. The N-type semiconductor material is N-type GaN, the light-emitting material is a quantum well material, and the P-type semiconductor material is P-type GaN.

[0068] S2. Using chemical vapor deposition or atomic layer deposition, a current spreading material is deposited on the entire surface including the epitaxial material. The preferred current spreading material is ITO 1004. A photolithography etching process is used to sequentially etch the current spreading material and the epitaxial material. Specifically, a photoresist is coated on the surface of the current spreading material, and the photoresist is exposed and developed. Based on the developed pattern, a dry etching process or a wet etching process is used to sequentially etch the current spreading material and the epitaxial material. The etching depth reaches the surface or interior of the N-type semiconductor material. This etching is a single etching operation, resulting in several arrayed current spreading layers 104 and bumps. See [link to documentation]. Figure 22 The bump includes a P-type semiconductor layer 101, a light-emitting layer 102, and an N-type semiconductor layer 103 stacked sequentially from top to bottom, with the N-type semiconductor layer 101 being continuous.

[0069] S3. Using chemical vapor deposition or atomic layer deposition, an insulating material or composite material is deposited on the entire surface of the current spreading layer 104. The insulating material is preferably SiO2 or SiNx, forming an insulating layer or composite layer 105. The composite layer includes two insulating layers and a reflective layer distributed between the two insulating layers. The reflective layer is a metal reflective layer, a hybrid reflective layer, or a DBR reflective layer. The metal reflective layer includes stacked Ni, Ag, and Au, and the hybrid reflective layer includes stacked ITO, Ag, and Tiw. The reflective layer is used to reflect the light emitted by the light source, which is beneficial to improving the light extraction efficiency of the integrated chip.

[0070] A secondary etching process is performed using photolithography. Specifically, photoresist is coated onto the entire surface including the insulating layer or composite layer and the N-type semiconductor layer. The photoresist is then exposed and developed. Based on the developed pattern, a secondary etching process is performed on the insulating layer or composite layer 105 and the N-type semiconductor layer 101 to obtain several integrated regions. See [link to documentation]. Figure 23 Each integrated region includes at least three bumps. The N-type semiconductor layer 101 at the bottom of the bumps in the same integrated region continuously forms a continuous region, that is, a common cathode structure. One side of the continuous region protrudes to form a step, which facilitates the setting of the negative electrode 3 in subsequent processes.

[0071] S4. Prepare positive electrode 2 and negative electrode 3. Specifically, S41. Use photolithography etching process to etch the insulating layer or composite layer 105 to form a first etching hole above the P-type semiconductor layer 103 and a second etching hole above the step. S42. An ohmic contact material is deposited in the second etched hole using an electron beam evaporation process or a magnetron sputtering process to form an ohmic contact layer 106. The bottom of the ohmic contact layer 106 penetrates the second etched hole and is electrically connected to the N-type semiconductor layer 101. S43. Photoresist is coated on the surface of the insulating layer or composite layer 105, inside the first etched hole, and on the surface of the ohmic contact layer 106. The photoresist is exposed and developed. Electron beam evaporation or magnetron sputtering deposition is used to deposit conductive material on the surface of the photoresist. In this embodiment, the conductive material is preferably at least one of Cr, Al, Ti, Pt, Au, and Ni. S44. Based on the developed pattern, the conductive material is stripped to obtain a positive electrode 2 and a negative electrode 3. The positive electrode 2 is located inside and above the first etched hole, and its bottom penetrates through the first etched hole and is electrically connected to the current spreading layer 104 and the P-type semiconductor layer 103. (See...) Figure 24 The negative electrode 3 is located above the step, and its bottom is electrically connected to the ohmic contact layer 106.

[0072] The following provides a method for fabricating a color integrated chip, which includes the fabrication steps S1 to S4 of the integrated chip in Example 1 or Example 2, and further includes: S5. Transfer several integrated chips to temporary substrate 7. Specifically, apply bonding adhesive to the temporary substrate and fix the integrated chips to the temporary substrate 7 using the bonding adhesive. The electrodes of the light emitter 1 in the integrated chip correspond to the temporary substrate 7, and the light emitting surface of the light emitter 1 in the integrated chip is set away from the temporary substrate 7.

[0073] S6. Using photolithography or film deposition processes, a color filter 5 is deposited on the light-emitting surface of the light emitter 1. The color filter 5 is used to convert the color of the light emitted by the light emitter 1. Specifically, using photolithography, deposition, and lift-off processes, an array of contrast enhancement layers 501 is fabricated on the light-emitting surface. See [link to documentation]. Figure 18 , Figure 25 The contrast enhancement layer 501 is made of black or gray material, including but not limited to at least one of Al, Ti, and Au.

[0074] Using photolithography etching, a first color conversion region, a second color conversion region, and a third color conversion region are sequentially formed within the gaps between the contrast enhancement layers 501, as shown in the figure. Figure 19 , Figure 26 The first color conversion region includes red quantum dot photoresist, the second color conversion region includes green quantum dot photoresist, and the third color conversion region includes transparent quantum dot photoresist or an empty region.

[0075] S7. A light-transmitting substrate 8 is disposed on the surface of the color filter, see Figure 20 , Figure 27 ; S8. Remove temporary substrate 7 and clean to remove bonding adhesive; S9. Cut the integrated chips based on the gaps between them to obtain a color integrated chip. (See...) Figure 21 , Figure 28 It should be noted that, in another embodiment, the light-transmitting substrate 8 can be removed according to actual needs.

[0076] The following provides a method for fabricating a light-emitting module. The method includes: providing an integrated chip or a color integrated chip and a driver IC4. In this embodiment, the first pad 401, the second pad 402, the third pad 403 and the first connection circuit 404 are all located on the front side of the substrate, and no redistribution layer is provided on its wiring structure side; the integrated chip and the driver IC4 are aligned and bonded together using a flip-chip bonding process to obtain the light-emitting module. The electrodes are electrically connected to the driver IC4 through the first pad 401, the first connection circuit 404 and the second pad 402.

[0077] Arrange the above-mentioned light-emitting module array in the driving substrate 6. If the integrated chip in the light-emitting module is used as a pixel unit, a single-color display screen is obtained. If the color integrated chip in the light-emitting module is used as a pixel unit, a color display screen is obtained.

[0078] It is understood that the above detailed description of the present invention is for illustrative purposes only and is not intended to limit the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. An integrated chip, characterized in that, The integrated chip includes: A plurality of monochromatic light emitters, each of the light emitters (1) comprising stacked N-type semiconductor layer (101), light-emitting layer (102), and P-type semiconductor layer (103), wherein the N-type semiconductor layer (101) is connected to form a common cathode structure; the bottom of the N-type semiconductor layer (101) of each of the light emitters (1) is continuous, forming a continuous region, and at least one side of the continuous region protrudes outward to form a step; Positive electrode (2) and negative electrode (3), the negative electrode (3) is located on the step and electrically connected to the N-type semiconductor layer (101), the positive electrode (2) is located on the P-type semiconductor layer (103) and electrically connected to the P-type semiconductor layer (103).

2. The integrated chip according to claim 1, characterized in that, The light color of the light source (1) includes blue, green or red; each integrated chip includes at least three light sources (1), which are arranged side by side, in a triangular arrangement or in a quadrilateral arrangement.

3. The integrated chip according to claim 1 or 2, characterized in that, It also includes a current spreading layer (104) and / or an ohmic contact layer (106), wherein the current spreading layer (104) is located on the surface of the P-type semiconductor layer (103) and is used to electrically connect the positive electrode (2) to the P-type semiconductor layer (103), and the ohmic contact layer (106) is located between the negative electrode (3) and the N-type semiconductor layer (101) and is used to achieve ohmic contact between the negative electrode (3) and the N-type semiconductor layer (101).

4. The integrated chip according to claim 3, characterized in that, It also includes an insulating layer or a composite layer (105), which covers the entire surface including the surface of the N-type semiconductor layer and the surface of the P-type semiconductor layer. The composite layer includes two insulating layers and a reflective layer distributed between the two insulating layers. The reflective layer is used for light reflection. The bottom end of the positive electrode (2) passes through the insulating layer or the composite layer (105) and is electrically connected to the P-type semiconductor layer (103). The bottom end of the negative electrode (3) passes through the insulating layer or the composite layer (105) and is electrically connected to the N-type semiconductor layer (101).

5. The integrated chip according to claim 4, characterized in that, It also includes a color filter, which is disposed on the light-emitting surface of the light source (1) in the integrated chip and is used to convert the light color of the light source (1).

6. The integrated chip according to claim 5, characterized in that, The color filter includes a contrast enhancement layer (501) and a light color conversion area (502). The contrast enhancement layer (501) is used to enhance the display contrast. The light color conversion area (502) is located in the gap between two adjacent contrast enhancement layers (501) and corresponds one-to-one with the light emitter (1). It is used to convert the light color of the light emitter (1) into other colors.

7. A method for fabricating an integrated chip, used to fabricate the integrated chip according to claim 1, characterized in that, The method includes: A wafer is provided, the wafer including a substrate and an epitaxial material distributed on the substrate, the epitaxial material including N-type semiconductor material, light-emitting material and P-type semiconductor material stacked together; The epitaxial material is etched to a depth that reaches the surface of the N-type semiconductor material or the interior of the N-type semiconductor material. This etching is a single etching process, resulting in a plurality of arrayed bumps. The bumps include stacked P-type semiconductor layers, light-emitting layers, and N-type semiconductor layers, wherein the N-type semiconductor layers are continuous. The N-type semiconductor layer is etched a second time to obtain several integrated regions. Each integrated region includes at least three bumps. The N-type semiconductor layer in the same integrated region is continuously formed into a continuous region to obtain a common cathode structure. At least one side of the continuous region protrudes to form a step. A positive electrode is formed above the bump, and a negative electrode is formed above the step. The positive electrode is electrically connected to the P-type semiconductor layer, and the negative electrode is electrically connected to the N-type semiconductor layer.

8. The method for fabricating an integrated chip according to claim 7, characterized in that, Both the primary and secondary etching processes employ photolithography.

9. The method for fabricating an integrated chip according to claim 7 or 8, characterized in that, Before the first etching, a current spreading material is deposited on the surface of the P-type semiconductor material. The current spreading material and the epitaxial material are etched sequentially using photolithography to form a current spreading layer and the bumps. Before the second etching, an insulating material or composite material is deposited on the entire surface containing the current spreading layer to form an insulating layer or composite layer. The second etching is performed using photolithography based on the gaps between the bumps, with the etching depth reaching the surface of the substrate to obtain an integration area containing the insulating layer or composite layer.

10. The method for fabricating an integrated chip according to claim 7, wherein a color integrated chip is prepared, characterized in that, The method includes: Several integrated chips are transferred to a temporary substrate, wherein the electrodes of the integrated chips correspond to the temporary substrate, and the light-emitting surface of the light-emitting element in the integrated chip is disposed away from the temporary substrate; A color filter is formed on the light-emitting surface of the light emitter using semiconductor technology or film bonding technology. The color filter is used to convert the light color of the light emitter. A light-transmitting substrate is disposed on the surface of the color filter; Remove the temporary substrate; The color integrated chip is obtained by cutting based on the gaps between the integrated chips.

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