Method for manufacturing diode and diode

Abstract

The application discloses a manufacturing method of a diode and the diode manufactured by the method, wherein the method comprises the following steps: S1, setting a substrate layer and an epitaxial material parameter of a diode model, and establishing a diode physical model; S2, changing a concentration gradient factor of acceptor ions of an active region of the diode physical model, simulating a reverse breakdown voltage under different concentration gradient factors, and obtaining a relationship curve graph of the concentration gradient factor and the reverse breakdown voltage; S3, obtaining a concentration gradient factor range corresponding to a maximum reverse breakdown voltage from the relationship curve graph of the concentration gradient factor and the reverse breakdown voltage; S4, formulating and simulating a manufacturing process of the diode, and obtaining a process parameter for enabling the concentration gradient factor of the acceptor ions of the active region of the diode to fall within the concentration gradient factor range; and S5, manufacturing the diode according to the manufacturing process of the diode and the obtained process parameter. The diode manufactured by the method has an optimal reverse breakdown voltage and an optimal anti-avalanche capability under the same thickness of the epitaxial layer.

Description

Technical Field

[0001] This invention relates to the field of power semiconductors, and in particular to a method for manufacturing a diode and the diode itself. Background Technology

[0002] A switching diode is a type of semiconductor diode that primarily utilizes the unidirectional conductivity of a PN junction. This electronic switching device not only boasts excellent switching speed and short reverse recovery time, but also offers advantages such as small size and high reliability. It is mainly used in switching circuits of electronic devices and some pulse rectifier circuits. Under reverse bias, when the reverse bias voltage reaches a certain level, the reverse current density increases rapidly, leading to PN junction breakdown. This phenomenon is mainly due to the rapid increase in the number of charge carriers, resulting in current accumulation and an excessively large peak electric field in the depletion region, making avalanche breakdown more likely and ultimately damaging the device. Therefore, improving the avalanche resistance of power devices is of great significance. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to propose a method for manufacturing a diode that can produce a diode with optimal reverse breakdown voltage under the same epitaxial layer thickness. This method not only improves the peak electric field in the depletion region but also optimizes the reverse breakdown performance of the diode, thereby enhancing the device's resistance to avalanche.

[0004] Another object of the present invention is to provide a diode manufactured by the above-described diode manufacturing method, which has excellent avalanche resistance.

[0005] Technical solution: The diode manufacturing method of the present invention includes the following steps:

[0006] S1: Set the substrate and epitaxial material parameters of the diode model to establish the diode physical model;

[0007] S2: Change the concentration gradient factor of the acceptor ions in the active region of the diode physical model, simulate the reverse breakdown voltage under different concentration gradient factors, and obtain the relationship curve between the concentration gradient factor and the reverse breakdown voltage.

[0008] S3: Obtain the range of concentration gradient factor corresponding to the maximum reverse breakdown voltage from the relationship curve between concentration gradient factor and reverse breakdown voltage;

[0009] S4: Develop and simulate the diode manufacturing process to obtain process parameters that ensure the concentration gradient factor of the acceptor ions in the active region of the diode falls within the concentration gradient factor range.

[0010] S5: Manufacture diodes according to the diode manufacturing process and obtain the process parameters.

[0011] Furthermore, the diode fabrication process in steps S4 and S5 includes:

[0012] Epitaxial layer growth: A lightly doped epitaxial layer is deposited on a single-crystal substrate;

[0013] Oxide layer growth: An oxide layer is grown at high temperature on the front side of the epitaxial layer;

[0014] Forming an ion implantation window: A uniform photoresist layer is coated on the oxide layer surface, and then exposed, developed, etched and the photoresist removed to form an ion implantation window;

[0015] Forming a PN junction: A certain amount of boron ions are injected through the ion implantation window, and high-temperature annealing is performed to advance the junction depth. The concentration gradient factor of boron ions is controlled within the concentration gradient factor range, and the ion damage caused by ion implantation is repaired to form a doped P-region.

[0016] Nitride deposition: A layer of silicon nitride is deposited on the front side of the silicon wafer to form a nitride layer;

[0017] Forming lead holes: A uniform layer of photoresist is coated on the surface of the nitride layer, and then exposed, developed, etched and stripped to form lead holes;

[0018] Formation of P+ region: A certain amount of boron ions are implanted again through the ion implantation window, and high-temperature annealing is performed. The annealing temperature and time are lower than those in the PN junction formation step.

[0019] Forming the front metal electrode: Metal is evaporated or sputtered on the front side of the silicon wafer, and then formed through spin coating, exposure, development, etching and resist removal.

[0020] Forming the back metal electrode: Metal is evaporated on the back of the silicon wafer to form the back metal electrode.

[0021] Furthermore, the ion implantation window, the lead hole, and the front metal electrode are all concentric circular holes.

[0022] Furthermore, in the step of forming the P+ region, the annealing temperature ranges from 800°C to 1000°C.

[0023] The diode of the present invention is manufactured by the diode manufacturing method described above, and includes an active region, a substrate layer, an epitaxial layer, an oxide layer, a nitride layer, a front metal electrode, and a back metal electrode. The epitaxial layer has a thickness ranging from 11.5 μm to 12.5 μm, and a doping concentration ranging from 5.2e13 cm⁻¹. --3 up to 5.46e13cm -3The thickness of the substrate layer ranges from 500 to 525 μm, the resistivity of the substrate layer ranges from 0.002 Ω·cm to 0.004 Ω·cm, and the concentration gradient factor of the acceptor ions in the active region ranges from -13 cm⁻¹. -3 / μm to -12.15cm -3 / μm.

[0024] Furthermore, the thickness of the oxide layer ranges from 1 μm to 1.5 μm.

[0025] Furthermore, the thickness of the back metal electrode ranges from 1.5 μm to 2 μm.

[0026] Furthermore, the active region includes a P-region and a P+ region, wherein the ion implantation dose range of the P+ region is 1e13cm. -2 Up to 1e14cm -2 .

[0027] Furthermore, the ion implantation dose range of the P region is 1e12cm. -2 up to 1e13cm -2 .

[0028] Furthermore, the thickness of the front metal electrode ranges from 4 μm to 6 μm.

[0029] Beneficial effects: Compared with the prior art, the present invention has the following advantages: it has the optimal reverse breakdown voltage under the same thickness epitaxial layer, which improves the avalanche resistance of the device. Attached Figure Description

[0030] Figure 1 This is a flowchart of a diode manufacturing method according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the diode structure according to an embodiment of the present invention;

[0032] Figure 3 This is a flowchart illustrating the fabrication process of a diode according to an embodiment of the present invention.

[0033] Figure 4 The graph shows the relationship between reverse breakdown voltage under different doping doses.

[0034] Figure 5 The graph shows the relationship between different concentration gradient factors and reverse breakdown voltage.

[0035] Figure 6 This is a graph showing the IV characteristic curves of the diode in this embodiment of the invention and a conventional diode. Detailed Implementation

[0036] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0037] A method for manufacturing a diode according to an embodiment of the present invention includes the following steps:

[0038] S1: Set the substrate and epitaxial material parameters of the diode model to establish the diode physical model;

[0039] S2: Change the concentration gradient factor of the acceptor ions in the active region of the diode physical model, simulate the reverse breakdown voltage under different concentration gradient factors, and obtain the relationship curve between the concentration gradient factor and the reverse breakdown voltage.

[0040] S3: Obtain the range of concentration gradient factor corresponding to the maximum reverse breakdown voltage from the relationship curve between concentration gradient factor and reverse breakdown voltage;

[0041] S4: Develop and simulate the diode manufacturing process to obtain process parameters that ensure the concentration gradient factor of the acceptor ions in the active region of the diode falls within the concentration gradient factor range.

[0042] S5: Manufacture diodes according to the diode manufacturing process and obtain the process parameters.

[0043] In this embodiment, the epitaxial layer 2 has a thickness of 12 μm and a doping concentration of 5.33e13cm. -3 Substrate layer 1 has a crystal orientation of <111> Arsenic-doped single-crystal silicon diodes with resistivity ranging from 0.002 Ω·cm to 0.004 Ω·cm and a thickness of approximately 500 μm were used. Simulations of the reverse breakdown voltage of these diodes under different acceptor ion concentration gradient factors in the active region were performed using Silvaco TCDA software. The results are as follows: Figure 5 The graph showing the relationship between the concentration gradient factor and the reverse breakdown voltage reveals that, under the parameters of the epitaxial layer and the substrate layer, the concentration gradient factor of the acceptor ions in the active region is at -13 cm⁻¹. -3 / μm to -12.15cm -3 The highest reverse breakdown voltage is found at a concentration of / μm. In practice, the concentration distribution of acceptor ions is mainly adjusted by regulating the annealing temperature and time after ion implantation. In this embodiment, simulation of the diode's process flow shows that the concentration gradient factor in the active region can be controlled within the above range when the main annealing temperature is 1150℃ and the annealing time is 360min. The diode manufactured using the above method exhibits the optimal reverse breakdown voltage with the same epitaxial material and thickness, improving not only the peak electric field in the depletion region and reverse breakdown performance, but also higher avalanche resistance.

[0044] Reference Figure 2According to an embodiment of the present invention, a diode includes an active region, a substrate layer 1, an epitaxial layer 2, an oxide layer 3, a nitride layer 5, a front metal electrode 7, and a back metal electrode 8. In this embodiment, both the substrate layer 1 and the epitaxial layer 2 are N-type. The substrate layer 1 is made of single-crystal silicon, doped with a high dose of arsenic ions to form a heavily doped substrate with a resistivity of approximately 0.002 Ω·cm to 0.004 Ω·cm. The corresponding active region includes a P-region 4 and a P+ region 6, obtained by implanting a certain concentration of boron ions. In practice, since the junction depth of the P+ region 6 is relatively shallow, it is only necessary to ensure that the concentration gradient factor of the P-region 4 is within the specified range. The thickness of the oxide layer 3 is preferably between 1 μm and 1.5 μm. An oxide layer of this thickness can effectively isolate the main junction region from the external region, and the oxide layer is non-conductive, which can effectively prevent leakage. The thickness of the front metal electrode 7 is preferably between 4 μm and 6 μm, and the thickness of the back metal electrode 8 is preferably between 1.5 μm and 2 μm. Figure 4 As shown, simulations of reverse breakdown voltage at different ion implantation concentrations revealed that when the ion implantation dose is 1e13cm... -2 The maximum reverse breakdown voltage can be obtained when the ion implantation dose is near the target value, so the ion implantation dose in region 6 of P+ should be around 1e13cm. -2 Up to 1e14cm -2 Between these values, the ion implantation dose in region P4 should be approximately 1e12cm. -2 up to 1e13cm -2 It is understood that the technical solution claimed in this application can also be applied to N-type semiconductors implanted with N in a P-type substrate.

[0045] like Figure 6 As shown, the breakdown voltage of the diode before and after optimization according to the above technical solution increased from 135.52V to 160.75V under the test condition of IR=0.1mA.

[0046] Reference Figure 3 The manufacturing process of the diode in this embodiment of the invention is as follows:

[0047] Epitaxial layer growth: A lightly doped epitaxial layer 2 is deposited on a single crystal substrate; in practice, before growing epitaxial layer 2, the natural oxide layer 3 and impurities on the silicon wafer surface need to be removed.

[0048] Oxide layer growth: Oxide layer 3 is grown at high temperature on the front side of epitaxial layer 2;

[0049] Forming an ion implantation window: A uniform photoresist layer is coated on the surface of oxide layer 3, and then an ion implantation window is formed through exposure, development, etching and photoresist removal.

[0050] Forming a PN junction: A certain amount of boron ions is injected through the ion implantation window, and high-temperature annealing is performed to advance the junction depth, controlling the boron ion concentration gradient factor within the range of -13cm.-3 / μm to -12.15cm -3 Within the μm range, ion implantation damage is repaired to form a doped P-region 4. In practice, a thin oxide layer 3 can be grown on the silicon wafer surface as a "sacrificial layer" before ion implantation to avoid damage to the silicon wafer surface during ion implantation and provide protection. By implanting a certain dose of boron ions, a P-channel is formed, and high-temperature annealing repairs the lattice damage caused by ion implantation, allowing silicon atoms to return to their lattice sites. In this step, the preferred annealing temperature range is 1000℃ to 1200℃. This annealing temperature effectively repairs the lattice damage caused by ion implantation and controls the junction depth within a certain range, ensuring the stability of the forward conduction voltage drop and thus effectively reducing switching losses.

[0051] Nitride deposition: A layer of silicon nitride is deposited on the front side of the silicon wafer to form nitride layer 5; nitride layer 5 is deposited by LP_CVD and is used as a masking layer and a nitriding protection layer for the silicon wafer.

[0052] Forming lead holes: A uniform photoresist layer is coated on the surface of nitride layer 5, and then exposed, developed, etched and stripped to form lead holes; in practice, the nitride at the lead hole port is first etched away, and then the photoresist is stripped.

[0053] Forming the P+ region: A certain amount of boron ions is implanted again through the ion implantation window, followed by high-temperature annealing. The heavily doped P region, i.e., P+ region 6, has a higher concentration of boron ions on the silicon surface, which enhances the conductivity of the device and facilitates ohmic contacts. Because the junction depth of P+ region 6 is shallower, the annealing temperature and time are lower than those of the P region. The preferred annealing temperature is between 800°C and 1000°C. In this embodiment, the actual annealing temperature is 950°C, and the annealing time is 5 minutes.

[0054] Forming the front metal electrode: Metal is evaporated or sputtered on the front side of the silicon wafer, and then the front metal electrode 7 is formed by homogenization, exposure, development, etching and resist removal; in this embodiment, the metal sputtered on the front metal electrode 7 is Al.

[0055] Forming the back metal electrode: Metal is evaporated on the back of the silicon wafer to form the back metal electrode 8.

[0056] In this embodiment, to improve the heat dissipation of the diode, the back side of the semi-finished diode needs to be thinned before forming the back metal electrode 8, preferably to a thickness of 150 μm to 180 μm. The ion implantation window, lead hole, and front metal electrode 7 are preferably concentric circles.

Claims

1. A diode comprising an active region, a substrate layer, an epitaxial layer, an oxide layer, a nitride layer, a front metal electrode, and a back metal electrode, characterized in that, a thickness of the epitaxial layer ranges from 11.5 μm to 12.5 μm, a doping concentration of the epitaxial layer ranges from 5.2e13 cm -3 to 5.46e13 cm -3 , a thickness of the substrate layer ranges from 500 to 525 μm, a resistivity of the substrate layer ranges from 0.002 Ω·cm to 0.004 Ω·cm, and a concentration gradient factor of the acceptor ions of the active region ranges from -13 cm -3 / μm to -12.15 cm -3 / μm.

2. The diode of claim 1, wherein The thickness of the oxide layer ranges from 1 μm to 1.5 μm.

3. The diode of claim 1, wherein The thickness of the back metal electrode ranges from 1.5 μm to 2 μm.

4. The diode of claim 1, wherein The active region includes a P region and a P+ region, the ion implantation dose of the P+ region ranges from 1e13 cm -2 to 1e14 cm -2 .

5. The diode of claim 4, wherein The ion implantation dose of the P region ranges from 1e12 cm -2 to 1e13 cm -2 .

6. The diode of claim 1, wherein The thickness of the front metal electrode ranges from 4 μm to 6 μm.

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