Laminated cell and preparation method thereof

Abstract

The invention discloses a laminated cell and a preparation method thereof, and the method comprises the steps: preparing a transparent conductive layer of a first cell, and preparing a P1 scribing line on the transparent conductive layer; sequentially preparing a first functional layer, an active layer and a second functional layer on the transparent conductive layer, and preparing a P2 scribing line on the first functional layer, the active layer and the second functional layer; a first electrode layer is prepared on the second functional layer, the first electrode layer is a grid line electrode layer prepared through first mask plates, and grooves, where the first electrode layer is not deposited, between the first mask plates are P3 scribing lines; a second battery located below the first battery is obtained, the surface of the second battery comprises a second electrode layer of grid lines, and the grid lines of the first electrode layer and the grid lines of the second electrode layer are aligned and consistent up and down. According to the invention, heat influence and damage caused by a P3 scribing process can be eliminated, so that the stability of the device is enhanced, and any loss is not generated in an effective power generation area of a bottom battery.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a laminated cell and a method for preparing the laminated cell. Background Art

[0002] Perovskite tandem cells combine the advantages of crystalline silicon cells and perovskite cells, aiming to achieve higher photoelectric conversion efficiency. Crystalline silicon cells are close to the theoretical efficiency limit, so there is limited room for improvement, while perovskite materials have high light absorption coefficients and long electron and hole diffusion lengths, which help achieve efficient photoelectric conversion. The theoretical limit efficiency of crystalline silicon-perovskite tandem cells can reach more than 40%, far exceeding the SQ limit efficiency of single-junction solar cells.

[0003] Perovskite battery technology has developed rapidly. Since its birth in 2009, the conversion efficiency has rapidly increased from 3.8% to 26.1%, and the conversion efficiency of crystalline silicon-perovskite tandem battery has reached 33.9%. Perovskite batteries have the advantages of high conversion efficiency, low cost, and simple technical processes, and are regarded as a new direction for the transformation of photovoltaic technology. In the tandem battery technology, by optimizing the electron transport layer thin film deposition process, introducing high-efficiency defect passivation materials, and designing and developing high-quality interface passivation structures, LONGi Green Energy has successfully achieved a new breakthrough in crystalline silicon-perovskite tandem battery technology, with a photoelectric conversion efficiency of up to 34.6%.

[0004] Perovskite cells have broad application prospects in the photovoltaic market due to their high efficiency and low cost. With the advancement of technology and the advancement of industrialization, perovskite cells have shown great potential in the fields of building integrated photovoltaics (BIPV), vehicle integrated photovoltaics (CIPV), large-scale ground power stations, etc. Perovskite crystalline silicon tandem cells are regarded as the mainstream technology route for the next generation of ultra-high-efficiency solar cells in the photovoltaic industry due to their high efficiency and good compatibility. In addition, the development of tandem cell technology has also driven the rapid growth of related equipment and material markets. It is expected that by 2030, the market space for perovskite equipment and materials will expand significantly.

[0005] Although perovskite battery technology shows broad development prospects, it still faces challenges in terms of stability, efficiency loss when applied over a large area, etc. The industry is overcoming these difficulties through continuous technological innovation and industrialization exploration in order to achieve wider market applications.

[0006] At present, in the process of various attempts to modify semi-transparent perovskite solar cells, it is necessary to first reduce the influence of the light transmittance of the upper perovskite cell on the bottom crystalline silicon cell as much as possible. At present, for semi-transparent perovskite solar cells, in addition to conventional transparent conductive oxide (Transparent Conductive Oxides, TCO) electrodes, most of them use TCO and metal composite electrodes or alloy electrodes to improve the electron transmission of the battery. However, for the mechanically stacked crystalline silicon-perovskite stacked cells with a 4-terminal structure, the light transmittance and stability of the top still need to be improved. Secondly, the prior art does not take into account the influence of thermal damage and edge collapse and warping caused by laser scratching P1, P2, and P3 after the components are prepared on the stability of the device. In particular, after the TCO electrode is scratched on P3, obvious protrusions will appear on both sides of the scratched groove, so that during the packaging lamination process, it is easy for the TCO on both sides to fall into the groove, resulting in a short circuit of the device. In addition, the grid lines of the top cell and the bottom cell of the stacked cell are inconsistent, which will also cause the loss of the effective power generation area of ​​the bottom cell.

[0007] In order to solve the above-mentioned problems existing in the prior art, the art is in urgent need of a stacked battery preparation technology that can avoid the thermal impact and damage caused by the P3 scratching process, reduce the failure of the upper perovskite caused by stress generated during the packaging process, thereby enhancing the stability of the device, and will not cause any loss to the effective power generation area of ​​the bottom battery. Summary of the invention

[0008] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or decisive elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0009] In order to overcome the above-mentioned defects of the prior art, the present invention provides a method for preparing a stacked battery, and a stacked battery, which can avoid the thermal impact and damage caused by the P3 scratching process, reduce the failure of the upper perovskite caused by the stress generated during the packaging process, thereby enhancing the stability of the device, and will not cause any loss to the effective power generation area of ​​the bottom battery.

[0010] Specifically, the method for preparing a stacked battery provided in accordance with the first aspect of the present invention includes: preparing a transparent conductive layer of a first battery, and preparing a P1 line on the transparent conductive layer; sequentially preparing a first functional layer, an active layer, and a second functional layer on the transparent conductive layer, and preparing a P2 line on the first functional layer, the active layer, and the second functional layer; preparing a first electrode layer on the second functional layer, wherein the first electrode layer is a gate line electrode layer prepared by a first mask plate, and grooves P3 lines are formed between each of the first mask plates where the first electrode layer is not deposited; and obtaining a second battery located below the first battery, wherein a second electrode layer including gate lines is provided on a surface of the second battery, and the gate lines of the first electrode layer are aligned up and down with the gate lines of the second electrode layer.

[0011] Furthermore, in some embodiments of the present invention, the step of preparing the first electrode layer on the second functional layer includes: fixing a plurality of first mask plates having a reverse hollowed-out gate line structure so that they are laid flat on the second functional layer at a certain distance; preparing a metal electrode layer on the surface of each of the first mask plates; and after the metal electrode is cooled, removing the first mask plates to obtain a metal first electrode layer including the gate line, and the grooves between adjacent first mask plates form the P3 scribe line.

[0012] Furthermore, in some embodiments of the present invention, the material of the metal electrode layer includes any one or more of silver, gold, copper and aluminum.

[0013] Furthermore, in some embodiments of the present invention, the method for preparing the metal electrode layer includes one or more of evaporation, magnetron sputtering, printing, spin coating, blade coating, spraying, spray pyrolysis, and slit coating.

[0014] Furthermore, in some embodiments of the present invention, the step of preparing a transparent conductive layer of the first battery and preparing P1 lines on the transparent conductive layer includes: obtaining a transparent substrate; fixing a plurality of second mask plates so that they are laid flat on the transparent substrate at a certain distance; preparing an indium tin oxide film or a fluorine-doped tin oxide film on the surface of each of the second mask plates by magnetron sputtering; and after the indium tin oxide film or the fluorine-doped tin oxide film is cooled, removing the second mask plate to obtain the transparent conductive layer including the P1 lines, wherein the grooves between each of the second mask plates where the transparent conductive layer is not deposited are the P1 lines.

[0015] Further, in some embodiments of the present invention, the steps of sequentially preparing a first functional layer, an active layer, and a second functional layer on the transparent conductive layer, and preparing P2 lines on the first functional layer, the active layer, and the second functional layer include: fixing a plurality of third mask plates so that they are laid flat on the transparent conductive layer at a certain distance; sequentially preparing the first functional layer, the active layer, and the second functional layer on the surface of each of the third mask plates by an evaporation method; and after the first functional layer, the active layer, and the second functional layer are cooled, removing the third mask plate to obtain the first functional layer, the active layer, and the second functional layer including the P2 lines, wherein the grooves between the third mask plates where the first functional layer, the active layer, and the second functional layer are not deposited are the P2 lines.

[0016] Furthermore, in some embodiments of the present invention, the preparation method also includes: in response to preparing the first battery and the second battery; and stacking the first battery on top of the second battery, and packaging the first battery and the second battery through heat-bearing pressure equipment to obtain the stacked battery.

[0017] In addition, the above-mentioned stacked battery provided according to the second aspect of the present invention includes: a first battery prepared using the above-mentioned stacked battery preparation method provided by the first aspect of the present invention, and a second battery located below the first battery.

[0018] Furthermore, in some embodiments of the present invention, the first battery includes a plurality of sub-battery units connected in series, and the plurality of sub-battery units are arranged in a single row in the length direction and in an array in the width direction.

[0019] Furthermore, in some embodiments of the present invention, the first functional layer in the first battery is an electron transport layer or a hole transport layer, the active layer is a perovskite layer, and the second functional layer is a hole transport layer or an electron transport layer corresponding to the electron transport layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above features and advantages of the present invention can be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily drawn to scale, and components with similar related properties or features may have the same or similar reference numerals.

[0021] Figure 1 A flow chart showing a method for preparing a stacked battery according to some embodiments of the present invention is shown;

[0022] Figure 2A schematic front view of the structure of a stacked battery provided according to some embodiments of the present invention is shown;

[0023] Figure 3 A schematic diagram of a first mask structure provided according to some embodiments of the present invention is shown;

[0024] Figure 4 A schematic structural diagram of a first battery and its surface grid lines provided according to some embodiments of the present invention is shown;

[0025] Figure 5A A schematic structural diagram of a first electrode layer of a first battery provided in some embodiments of the present invention is shown; and

[0026] Figure 5B A schematic structural diagram of a second electrode layer of a second battery provided according to some embodiments of the present invention is shown.

[0027] Reference numerals:

[0028] 200 laminated batteries;

[0029] 210 First Battery;

[0030] 211 transparent substrate;

[0031] 212 transparent conductive layer;

[0032] 213 First functional layer;

[0033] 214 active layer;

[0034] 215, 216 second functional layer;

[0035] 217 first electrode layer;

[0036] 220 Second Battery;

[0037] 230 sub-battery unit;

[0038] 221 packaging film;

[0039] 222 second electrode layer;

[0040] 300 first mask plate;

[0041] 310 grid line structure;

[0042] 411, 412 grid lines; and

[0043] Steps S110 to S140. DETAILED DESCRIPTION

[0044] The following specific embodiments illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this implementation. On the contrary, the purpose of introducing the invention in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description.

[0045] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] In addition, the terms "upper", "lower", "left", "right", "top", "bottom", "horizontal" and "vertical" used in the following description should be understood as the directions shown in the paragraph and the related drawings. Such relative terms are only used for the convenience of description and do not mean that the device described therein must be manufactured or operated in a specific direction, and therefore should not be understood as limiting the present invention.

[0047] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, regions, layers and / or parts, these components, regions, layers and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers and / or parts. Therefore, the first component, region, layer and / or part discussed below may be referred to as a second component, region, layer and / or part without departing from some embodiments of the present invention.

[0048] As mentioned above, currently for semi-transparent perovskite solar cells, in addition to conventional transparent conductive oxide (Transparent Conductive Oxides, TCO) electrodes, most use TCO and metal composite electrodes or alloy electrodes to improve the electron transmission of the battery. However, for the mechanically stacked crystalline silicon-perovskite stacked cells with a 4-terminal structure, the light transmittance and stability of the top still need to be improved. Secondly, the prior art does not take into account the effects of thermal damage and edge collapse caused by laser scratching of P1, P2, and P3 after the components are prepared on the stability of the device. In particular, after the TCO electrode is scratched on P3, obvious protrusions will appear on both sides of the scratched groove, so that during the packaging lamination process, it is easy for the TCO on both sides to fall into the groove, resulting in a short circuit of the device. In addition, the inconsistent grid lines of the top cell and the bottom cell of the stacked cell will also cause a loss of the effective power generation area of ​​the bottom cell.

[0049] In order to solve the above-mentioned problems existing in the prior art, the present invention provides a method for preparing a stacked battery, and a stacked battery, which can avoid the thermal impact and damage caused by the P3 scratching process, reduce the failure of the upper perovskite caused by the stress generated during the packaging process, thereby enhancing the stability of the device, and will not cause any loss to the effective power generation area of ​​the bottom battery.

[0050] In some non-limiting embodiments, the method for preparing the stacked battery provided in the first aspect of the present invention can prepare the stacked battery provided in the second aspect of the present invention.

[0051] The following will describe the method for preparing the above-mentioned laminated battery in combination with some embodiments of laminated batteries. Those skilled in the art will understand that the embodiments of the method for preparing these laminated batteries are only some non-limiting embodiments provided by the present invention, which are intended to clearly demonstrate the main concept of the present invention and provide some specific solutions that are convenient for the public to implement, rather than to limit all functions of the laminated battery. Similarly, the laminated battery is also only a non-limiting embodiment provided by the present invention, and does not constitute a limitation on the implementation subject of each step in the method for preparing these laminated batteries.

[0052] Please see Figure 1 , Figure 1 The flowchart of a method for preparing a laminated battery according to some embodiments of the present invention is shown. Figure 2 Common understanding, Figure 2 A schematic front view of the structure of a stacked battery provided according to some embodiments of the present invention is shown.

[0053] like Figure 1As shown, in some embodiments of the present invention, the method for preparing a stacked battery may include the following steps: Step S110: preparing a transparent conductive layer of a first battery, and preparing a P1 scribe line on the transparent conductive layer.

[0054] Specifically, if Figure 2 As shown, optionally, in the process of preparing the first battery 210 of the stacked battery 200, a transparent substrate 211 is first obtained. For example, the transparent substrate 211 can be a transparent glass substrate.

[0055] Then, a transparent conductive layer 212 can be prepared on the surface of the transparent substrate 211, wherein the material for preparing the transparent conductive electrode of the transparent conductive layer 212 can be selected from indium tin oxide (ITO) or fluorine-doped tin oxide (FTO). ITO and FTO are the mainstream types in TCO, thanks to their large-scale mass production, stable preparation process, and are relatively reliable in terms of price and conductivity. Although other TCO materials can also achieve the same function, ITO and FTO have more obvious advantages in terms of price and conductivity. In this embodiment, magnetron sputtering and other methods can be used to deposit the transparent conductive electrode on the surface of the transparent substrate 211, and the deposition thickness can be 200nm to 800nm.

[0056] In some optional embodiments, such as Figure 2 As shown, a laser scribing device can be used to perform a laser scribing process on the transparent conductive layer 212, so as to obtain a transparent conductive layer 212 including a P1 scribing line. The P1 scribing line is a scribing line that divides the bottom transparent conductive layer 212 without damaging the transparent substrate 211. By performing laser scribing to form the P1 scribing line after the deposition of the transparent conductive electrode ITO or FTO and before the deposition of the first functional layer 213, independent strip-shaped conductive electrodes can be formed. At the same time, the P1 scribing line can also be used as a positioning point for subsequent P2 and P3 scribing lines. The laser light sources used for laser scribing include but are not limited to nanosecond infrared, picosecond green light, picosecond infrared, picosecond ultraviolet, femtosecond green light and femtosecond infrared. Optionally, the line width of the P1 scribing line can be 20μm to 50μm.

[0057] Furthermore, in order to avoid damage to the transparent conductive layer 212 caused by laser scribing, in some preferred embodiments, a mask plate may be used to prepare the transparent conductive layer 212 including the P1 scribing line.

[0058] Specifically, after obtaining the transparent substrate 211, a plurality of second mask plates can be fixed so that they are laid flat on the transparent substrate 211 at a certain distance. Optionally, a plurality of split second mask plates can be selected here, which are laid flat at a certain distance from each other, or a whole second mask plate can be selected, but the whole second mask plate includes a plurality of mask areas that are on the same plane and spaced from each other. Then, on the surface of each second mask plate, an ITO film or a FTO film can be deposited by magnetron sputtering. After the ITO film or the FTO film is cooled, the second mask plate can be removed to obtain a transparent conductive layer 212 including a P1 line, and the grooves between the second mask plates spaced from each other where the transparent conductive electrode is not deposited are the P1 lines. In this embodiment, compared with the preparation method of the above-mentioned laser scribing P1 lines, no thermal impact or damage will be caused to the transparent conductive layer 212.

[0059] Please continue to return Figure 1 The method for preparing the above-mentioned stacked battery provided by the present invention may also include step S120: sequentially preparing a first functional layer, an active layer, and a second functional layer on the transparent conductive layer, and preparing P2 lines on the first functional layer, the active layer, and the second functional layer.

[0060] Specifically, the active layer 214 may be a perovskite light absorbing layer. The first functional layer 213 and the second functional layer 215 located on both sides of the active layer 214 may be a hole transport layer and an electron transport layer, and an electron transport layer and a hole transport layer, respectively. Figure 2 In the illustrated embodiment, the first functional layer 213 is a hole transport layer, and the second functional layers 215 and 216 may both be electron transport layers.

[0061] In some optional embodiments, such as Figure 2 As shown, a laser scribing device can be used to perform a laser scribing process on the first functional layer 213, the active layer 214, and the second functional layers 215 and 216, so as to obtain the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 including P2 scribing lines. The P2 scribing lines are etched on the first functional layer 213, the active layer 214, and the second functional layers 215 and 216. After the second functional layers 215 and 216 are deposited and before the first electrode layer 217 is deposited, laser scribing is performed to form the P2 scribing lines, and the second functional layers 215 and 216, the active layer 214, and the first functional layer 213 are etched to expose the transparent conductive layer 212, so that the first electrode layer 217 to be deposited in the next step can directly contact the transparent conductive layer 212, forming a current path, so that the positive and negative electrodes of the sub-battery units 230 are connected.

[0062] The laser light source used for laser scribing includes but is not limited to nanosecond infrared, picosecond green light, picosecond infrared, picosecond ultraviolet light, femtosecond green light and femtosecond infrared. Optionally, the line width of the P2 scribing line can be 50 μm to 200 μm. And, as Figure 2 As shown, the distance between the P1 scribe line and the P2 scribe line may be 200 to 300 μm.

[0063] Furthermore, in order to avoid damage to the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 caused by laser scribing, in some preferred embodiments, a mask plate method can also be used to prepare the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 including P2 scribing lines.

[0064] Specifically, after the transparent conductive layer 212 is prepared, a plurality of third mask plates can be fixed so that they are laid flat on the transparent conductive layer 212 at a certain distance. The width dimension of the third mask plate can be different from that of the second mask plate, so that the P2 scribe line is staggered with the previous P1 scribe line. The width dimension of the third mask plate can also be the same as that of the second mask plate. By adjusting the position of the third mask plate, the P2 scribe line can also be staggered with the previous P1 scribe line. And, optionally, a plurality of split third mask plates can be selected here, which are laid flat at a certain distance from each other, or a whole third mask plate can be selected, but the whole third mask plate includes a plurality of mask areas on the same plane and spaced from each other. Then, on the surface of each third mask plate, the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 can be prepared in sequence by evaporation. After the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 are cooled, the third mask plate can be removed to obtain the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 including the P2 scribe line. The grooves between the mutually spaced third mask plates where the materials of the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 are not deposited are the P2 scribe lines. In this embodiment, compared with the preparation method of the laser scribing P2 scribe line, the first functional layer 213, the active layer 214, and the second functional layers 215 and 216 will not be thermally affected or damaged.

[0065] Further, in an embodiment of the present invention, the perovskite compound of the active layer 214 may be expressed as ABX3, wherein A represents an organic cation, B represents a metal cation, and X represents a halogen anion. Optionally, the active layer 214 may be made of Cs 0.1 FA 0.9 PbI3、Cs 0.1 FA 0.9 PbBr3、Cs 0.1 FA 0.9Sn(I 0.8 Br 0.2 )3, etc. Preferably, in this embodiment, the active layer 214 can be specifically selected from Cs 0.25 FA 0.75 Pb(I 0.8 Br 0.2 )3, the band gap can be about 1.68 eV, and the thickness can be 500 nm. The perovskite first cell 210 prepared by this group of perovskite materials has high photoelectric conversion efficiency, good stability, and a suitable band gap. The preparation method of the active layer 214 can include but is not limited to one or more of spin coating, scraping, evaporation, printing, spraying, spray pyrolysis, and slit coating.

[0066] The composition of the hole transport layer may include, but is not limited to, one or more of 2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene (Spiro-OMeTAD), triphenylamine derivatives, non-triphenylamine nitrogen-containing small molecule materials, cuprous iodide (CuI), cuprous thiocyanate (CuSCN), quaternary compound semiconductor copper zinc tin sulfur (Cu2ZnSnS4), copper oxide (CuO), cuprous oxide (Cu2O), nickel dioxide (NiO2), [2-(9H-carbazole-9-yl)ethyl]phosphonic acid (2PACz), [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid (MeO-2PACz). Optionally, as Figure 2 As shown, when the first functional layer 213 is a hole transport layer, its thickness may be 1 nm to 100 nm.

[0067] The composition of the electron transport layer may include, but is not limited to, titanium dioxide (TiO2), zinc oxide (ZnO), tungsten oxide (WO3), tin dioxide (SnO2), ternary oxide semiconductors (Zn2SnO4), fullerene and its derivatives (C 60 , PC61BM, ICBA) or more. The preparation method of the electron transport layer may include but is not limited to one or more of spin coating, spray coating, spray pyrolysis, slit coating, and atomic layer deposition. Optionally, as Figure 2 As shown, when the second functional layer 215 is an electron transport layer, its thickness may be 10 nm to 100 nm.

[0068] Continue back Figure 1 The method for preparing the above-mentioned stacked battery provided by the present invention may also include step S130: preparing a first electrode layer on the second functional layer, wherein the first electrode layer is a gate line electrode layer prepared by a first mask plate, and the grooves between each first mask plate where the first electrode layer is not deposited are P3 lines.

[0069] like Figure 2As shown, the first electrode layer 217 may be a gate electrode layer prepared using a mask. Figure 3 , Figure 3 A schematic diagram of a first mask structure provided according to some embodiments of the present invention is shown.

[0070] Combination Figure 2 and Figure 3 As shown, a plurality of first mask plates 300 with reverse hollowed-out gate line structures 310 may be fixed so as to be laid flat on the second functional layer 216 at a certain distance. Optionally, a plurality of split first mask plates 300 may be selected here, which are laid flat at a certain distance from each other, or a whole first mask plate 300 may be selected, but the whole first mask plate 300 includes a plurality of mask areas on the same plane and spaced from each other.

[0071] Then, a metal electrode layer is prepared on the surface of each first mask plate 300. Optionally, the method of preparing the metal electrode layer may include, but is not limited to, one or more of evaporation method, magnetron sputtering method, printing method, spin coating method, scraping method, spray coating method, spray pyrolysis method, and slit coating method. The material of the metal electrode layer may include any one or more conductive alloys of silver, gold, copper, and aluminum.

[0072] After the metal electrode is cooled, the first mask plate 300 can be removed to obtain the metal first electrode layer 217 including the grid lines and the P1 scribe lines, wherein the grooves between the first mask plates 300 where the metal electrode is not deposited are the P3 scribe lines. The P3 scribe lines are scribe lines for etching the first electrode layer 217, and are used to separate the sub-battery units 230. Preferably, the first electrode layer 217 can be a silver grid line, which is used to optimize the conductivity of the first battery 210 of the upper perovskite.

[0073] For further information, see Figure 4 , Figure 4 A schematic structural diagram of a first battery and its surface grid lines provided according to some embodiments of the present invention is shown.

[0074] like Figure 4 As shown, optionally, the width of the gate line 411 can be 100μm, the spacing between adjacent gate lines 411 can be 0.5μm to 1mm, and there is no gate line 411 at the P3 line groove. In this embodiment, compared with the preparation method of laser scribing P3 lines in the prior art, the P3 lines are groove structures naturally formed during the deposition of the first electrode layer 217 on the surface of the first mask plate 300 due to the spacing between adjacent first mask plates 300, and no subsequent laser scribing is required, thereby eliminating the thermal impact and damage to the first electrode layer 217 caused by the laser scribing P3 lines.

[0075] In an embodiment of the present invention, since the preparation process of the P3 scribing is different from the existing laser scribing process, the line width of the P3 scribing can be narrower than the conventional laser scribing P3 scribing, thereby reducing the dead zone area. In addition, in the structure of the first battery 210, since there is no TCO electrode, the P3 scribing process can be omitted. In addition, the P3 scribing formed by natural isolation through the above method will not have protrusions on both sides of the groove caused by laser scribing. Therefore, during the packaging lamination process, it can avoid the problem of the TCO on both sides falling into the groove and causing the device to short-circuit. At the same time, compared with the laser scribing scribing preparation method, there will be no failure area caused by thermal influence.

[0076] Can be combined Figure 3 and Figure 4 In some embodiments of the present invention, by performing three parallel scribings starting from the P1 scribing on the first battery 210, namely the P1 scribing, the P2 scribing and the P3 scribing, a plurality of groove lines can be formed, thereby dividing the entire film layer into sub-battery units 230 connected in series. A plurality of sub-battery units 230 are arranged in an array of a single row in the long direction and N columns in the wide direction on the transparent substrate 211. Optionally, the width of the sub-battery unit 230 can range from 10 mm to 100 mm, the length can range from 30 mm to 500 mm, and the spacing between the unit columns can be 0.1 mm to 2 mm. By connecting a plurality of sub-battery units 230 in series, a separate module that blocks current conduction can be formed, thereby achieving the effect of increasing the voltage and connecting batteries in series.

[0077] Continue back Figure 1 The method for preparing the above-mentioned stacked battery provided by the present invention may further include step S140: obtaining a second battery located below the first battery, wherein a second electrode layer including grid lines is provided on the surface of the second battery, and the grid lines of the first electrode layer are aligned with the grid lines of the second electrode layer in the vertical direction.

[0078] After the first cell 210 is prepared, a crystalline silicon cell can be prepared below it as the second cell 220. In order to clearly describe the preparation method of the above-mentioned stacked cell, Figure 2 The upper and lower positions of the first battery 210 and the second battery 220 are opposite to the actual configuration. The four-terminal stacked battery 200 is a stacked battery formed by mechanically stacking two batteries up and down, and each electrode is independent. In the stacked battery 200, the first battery 210 with a large bandgap perovskite is used as the top battery, and the second battery 220 with a small bandgap crystalline silicon is used as the bottom battery.

[0079] The second cell 220 of crystalline silicon may include but is not limited to a Passivated Emitter Rear Cell (PERC), a Tunnel Oxide Passivated Contact (TOPCon), and a Heterojunction with Intrinsic Thin-film (HJT) cell.

[0080] Since in the present invention, the first perovskite cell 210 located on the upper layer does not have a nano-layer metal or TCO top electrode, it will not block light for the second crystalline silicon cell 220 on the lower layer, thereby maximizing the light utilization rate of the crystalline silicon second cell 220 at the bottom, which is beneficial to improving the photoelectric conversion efficiency of the stacked cell 200.

[0081] For further information, see Figure 5A and Figure 5B , Figure 5A shows a schematic structural diagram of a first electrode layer of a first battery provided according to some embodiments of the present invention, Figure 5B A schematic structural diagram of a second electrode layer of a second battery provided according to some embodiments of the present invention is shown.

[0082] like Figure 5A and 5B As shown, the surface of the second battery 220 is provided with a second electrode layer 222 including a gate line 412. In the present invention, by preparing a gate line electrode layer of a specific format on the top first battery 210, the gate line 411 of the first electrode layer 217 and the gate line 412 of the second electrode layer 222 are aligned up and down, so that any effective power generation area of ​​the crystalline silicon second battery 220 can be not lost.

[0083] In response to the preparation of the first battery 210 and the second battery 220, the first battery 210 can be stacked on top of the second battery 220, and the first battery 210 and the second battery 220 can be packaged by a heat-bearing pressure device to obtain a stacked battery 200. Further, optionally, as Figure 2 As shown, in order to effectively improve the service life and power generation efficiency of the photovoltaic module, a layer of photovoltaic encapsulation film 221 can also be provided on the side of the second cell 220 facing the first cell 210. The material of the encapsulation film 221 includes but is not limited to polyolefin elastomer (POE), ethylene-vinyl acetate copolymer (EVA), ultraviolet curing glue (epoxy resin), and thermal curing glue.

[0084] Next, a specific embodiment will be cited to more clearly describe the stacked battery 200 and the preparation method thereof provided by the present invention.

[0085] Please combine Figure 2 It is commonly understood that first, FTO can be prepared on the transparent substrate 211 by magnetron sputtering as a transparent conductive layer 212, and its thickness can be 300nm. Then, the transparent substrate 211 coated with the transparent conductive layer 212 can be scribed by nanosecond infrared laser to obtain a P1 scribe line with a width of 30μm and a depth of 500nm. After that, NiOx can be prepared on the transparent conductive layer 212 by sputtering as a hole transport layer (i.e., the first functional layer 213), and the thickness of the hole transport layer can be 30nm. .

[0086] After that, the perovskite compound Cs can be deposited on the hole transport layer (i.e., the first functional layer 213) by a one-step spin coating method. 0.25 FA 0.75 Pb(I 0.8 Br 0.2 )3 as the active layer 214, wherein the band gap of the active layer 214 can be about 1.68 eV and the thickness can be 500 nm. Then, the C 60 The layer is used as an electron transport layer (i.e., the second functional layer 215), and its thickness can be 30nm. Furthermore, SnO2 can be prepared by atomic layer deposition as an electron transport layer (i.e., the second functional layer 216), and its thickness can be 15nm. After that, picosecond green light can be used to perform laser scribing of P2 scribing, and a P2 scribing with a width of 70μm and a depth of 600nm can be obtained.

[0087] Those skilled in the art will appreciate that the above-mentioned scheme of using nanosecond infrared scribing P1 for marking and using picosecond green light scribing P2 for marking is only a preferred non-restrictive implementation scheme provided by the present invention, which is the best in practical applications and is intended to clearly demonstrate the main concept of the present invention and provide a specific scheme that is easy for the public to implement, rather than to limit the scope of protection of the present invention.

[0088] After that, the first electrode layer 217 may be prepared by using a magnetron sputtering method using a first mask. Figure 3 It is commonly understood that a plurality of first mask plates 300 with reverse hollowed-out grid line structures 310 can be closely attached to the surface of the second functional layer 216, and then fixed at equal intervals with high-temperature tape. After that, silver electrodes are formed on the surface of the first mask plate 300 by thermal evaporation or magnetron sputtering. After cooling, the first mask plate 300 is removed to obtain a first electrode layer 217 with silver grid lines and including P3 scribe lines. Optionally, the total thickness of the first electrode layer 217 can be 110 nm.

[0089] Finally, the first battery 210 and the second battery 220 may be subjected to heat pressing at 140° C. for 30 minutes using a POE packaging film 221 , thereby completing the preparation of the stacked battery 200 .

[0090] Although the above methods are illustrated and described as a series of actions for simplicity of explanation, it should be understood and appreciated that these methods are not limited by the order of the actions, because according to one or more embodiments, some actions may occur in a different order and / or concurrently with other actions from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art.

[0091] In summary, the present invention provides a method for preparing a stacked battery, and a stacked battery, which can avoid the thermal impact and damage caused by the P3 scratching process, reduce the failure of the upper perovskite caused by stress generated during the packaging process, thereby enhancing the stability of the device, and will not cause any loss to the effective power generation area of ​​the bottom battery.

[0092] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a laminated battery, characterized in that: include: Prepare a transparent conductive layer of a first battery, and prepare a P1 scribe line on the transparent conductive layer; Sequentially preparing a first functional layer, an active layer, and a second functional layer on the transparent conductive layer, and preparing P2 scribe lines on the first functional layer, the active layer, and the second functional layer; Preparing a first electrode layer on the second functional layer, wherein the first electrode layer is a gate line electrode layer prepared by a first mask plate, and the grooves between the first mask plates where the first electrode layer is not deposited are P3 scribe lines; and A second battery located below the first battery is obtained, wherein a second electrode layer including grid lines is disposed on a surface of the second battery, and the grid lines of the first electrode layer are aligned with the grid lines of the second electrode layer in the vertical direction.

2. The preparation method according to claim 1, characterized in that The step of preparing the first electrode layer on the second functional layer comprises: Fixing a plurality of first mask plates with reverse hollowed-out grid line structures so that they are laid flat on the second functional layer at a certain distance; Preparing a metal electrode layer on the surface of each of the first mask plates; and After the metal electrode is cooled, the first mask is removed to obtain a metal first electrode layer including the gate line and the P3 scribe line.

3. The preparation method according to claim 2, characterized in that: The material of the metal electrode layer includes any one or more of silver, gold, copper and aluminum.

4. The preparation method according to claim 2, characterized in that: The method for preparing the metal electrode layer includes one or more of evaporation, magnetron sputtering, printing, spin coating, blade coating, spray coating, spray pyrolysis, and slit coating.

5. The preparation method according to claim 1, characterized in that: The step of preparing the transparent conductive layer of the first battery and preparing the P1 line on the transparent conductive layer comprises: obtaining a transparent substrate; Fixing a plurality of second mask plates so that they are laid flat on the transparent substrate at a certain distance; On the surface of each of the second mask plates, an indium tin oxide film or a fluorine-doped tin oxide film is prepared by magnetron sputtering; and After the indium tin oxide film or the fluorine-doped tin oxide film is cooled, the second mask plate is removed to obtain the transparent conductive layer including the P1 scribe line, wherein the grooves between the second mask plates where the transparent conductive layer is not deposited are the P1 scribe lines.

6. The preparation method according to claim 1, characterized in that: The step of sequentially preparing a first functional layer, an active layer, and a second functional layer on the transparent conductive layer, and preparing P2 scribe lines on the first functional layer, the active layer, and the second functional layer comprises: Fixing a plurality of third mask plates so that they are laid flat on the transparent conductive layer at a certain distance; On the surface of each of the third mask plates, the first functional layer, the active layer, and the second functional layer are sequentially prepared by evaporation method; and After the first functional layer, the active layer, and the second functional layer are cooled, the third mask plate is removed to obtain the first functional layer, the active layer, and the second functional layer including the P2 scribe line, wherein the grooves between each block of the third mask plate where the first functional layer, the active layer, and the second functional layer are not deposited are the P2 scribe lines.

7. The preparation method according to claim 1, characterized in that: Also includes: In response to preparing the first battery and the second battery; as well as The first battery is stacked on top of the second battery, and the first battery and the second battery are packaged by a heat-pressure device to obtain the stacked battery.

8. A laminated battery, characterized in that: include: A first battery prepared by the method for preparing a stacked battery according to any one of claims 1 to 7, and a second battery located below the first battery.

9. The laminated battery according to claim 8, characterized in that: The first battery includes a plurality of sub-battery units connected in series, and the plurality of sub-battery units are arranged in a single row in the length direction and in an array in the width direction.

10. The stacked battery according to claim 8, characterized in that: The first functional layer in the first battery is an electron transport layer or a hole transport layer, the active layer is a perovskite layer, and the second functional layer is a hole transport layer or an electron transport layer corresponding to the electron transport layer.

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