Doped silicon oxide cooled etch

Abstract

Examples disclosed relate to etching features in a silicon oxide layer doped with an etch rate adjusting dopant. An example presents a method of performing a memory device fabrication process. The method includes placing a substrate in a processing chamber of a processing tool, the substrate including a first structure including alternating layers in a mold stack of a 3D memory structure, the substrate further including a second structure including a silicon oxide layer doped with an etch rate adjusting dopant. The method further includes controlling the processing tool to perform an etch cycle including etching at least a portion of a channel hole in the first structure of the substrate and at least a portion of a hole in the second structure of the substrate.

Description

Background Art

[0001] Electronic device manufacturing processes may involve many steps of material deposition, patterning, and removal to form integrated circuits and / or memory structures on a substrate. Various methods may be used to deposit a film of material onto a substrate. As an example, chemical vapor deposition (CVD) involves reacting precursors to form a film on a substrate. As another example, dry etching may be used to etch features into one or more material layers on a substrate. Summary of the invention

[0002] This summary is provided to introduce a selection of concepts in a simplified form, which will be further described in the following detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that address any or all of the disadvantages mentioned in any part of this disclosure.

[0003] The disclosed examples involve etching features in a silicon oxide layer doped with an etch rate-modifying dopant. One example provides a method of performing a memory device manufacturing process, comprising: placing a substrate in a process chamber of a processing tool. The substrate includes a first structure, the first structure including alternating layers in a mold stack of a 3D memory structure. The substrate also includes a second structure, the second structure including a silicon oxide layer doped with an etch rate-modifying dopant. The method also includes: controlling the processing tool to perform an etching cycle, the etching cycle including: etching at least a portion of a channel hole in the first structure of the substrate and at least a portion of a hole in the second structure.

[0004] In some such examples, the method further includes controlling the processing tool to cool the substrate to a temperature of 0° C. or less during the etching cycle.

[0005] Additionally or alternatively, in some such examples, controlling the processing tool to perform the etching cycle includes controlling the processing tool to introduce a fluorine-containing etchant into the processing chamber.

[0006] Additionally or alternatively, in some such examples, the hole in the second substrate structure includes a contact hole.

[0007] Additionally or alternatively, in some such examples, the method further includes depositing the second structure by reacting a silicon-containing precursor, an oxygen-containing precursor, and an etch rate adjusting dopant precursor to form the silicon oxide doped with the etch rate adjusting dopant.

[0008] Additionally or alternatively, in some such examples, the etch rate modulating dopant includes one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0009] Additionally or alternatively, in some such examples, the second structure includes two or more etch rate adjusting dopants.

[0010] Additionally or alternatively, in some such examples, the two or more etch rate adjusting dopants include a first etch rate adjusting dopant that includes nitrogen.

[0011] Additionally or alternatively, in some such examples, the second structure includes a nitrogen concentration in a range of 5 atomic % to 10 atomic %.

[0012] Additionally or alternatively, in some such examples, the etch rate modulating dopant precursor includes one or more of ammonia, bis(isopropylamino)silane, or bis(tert-butylamino)silane.

[0013] Additionally or alternatively, in some such examples, the etch rate adjusting dopant includes a second etch rate adjusting dopant including phosphorus.

[0014] Additionally or alternatively, in some such examples, the silicon oxide layer includes a phosphorus concentration in a range of 0.1 atomic % to 1 atomic %.

[0015] Additionally or alternatively, in some such examples, the etch rate adjusting dopant precursor further includes a second etch rate adjusting dopant precursor including one or more of a phosphine or an alkyl phosphine.

[0016] Another example provides a method of etching a substrate. The method includes placing a substrate in a process chamber of a process tool, the substrate including a dielectric material, the dielectric material including silicon oxide and an etch rate adjusting dopant. The method also includes controlling the process tool to cool the substrate to a substrate temperature of 0° C. or less. The method also includes controlling the process tool to introduce an etchant into the process chamber. The method also includes controlling the process tool to form a plasma including the etchant to etch a feature into the dielectric material, the feature including an aspect ratio of 10:1 or greater.

[0017] In some such examples, the etch rate modulating dopant includes one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0018] Additionally or alternatively, in some such examples, the etch rate adjusting dopant is a first etch rate adjusting dopant and wherein the dielectric material further comprises a second etch rate adjusting dopant, wherein the first etch rate adjusting dopant comprises nitrogen and the second etch rate adjusting dopant comprises phosphorus.

[0019] Another example provides a 3D memory structure. The 3D memory structure includes: a channel hole extending through a first substrate structure, the first substrate structure including alternating material layers. The 3D memory structure also includes: a hole extending through a second substrate structure, the second substrate structure including a silicon oxide layer doped with a first etch rate adjusting dopant and a second etch rate adjusting dopant.

[0020] In some such examples, the first etch rate adjusting dopant includes nitrogen and the second etch rate adjusting dopant includes phosphorus.

[0021] In some such examples, the silicon oxide layer additionally or alternatively includes a nitrogen concentration in a range of 5 atomic % to 10 atomic %.

[0022] In some such examples, the silicon oxide layer additionally or alternatively includes a phosphorus concentration in a range of 0.1 atomic % to 1.0 atomic %.

[0023] In some such examples, the alternating material layers additionally or alternatively include a stepped structure, and the silicon oxide layer doped with the first etch rate adjusting dopant and the second etch rate adjusting dopant is located over at least a portion of the stepped structure.

[0024] In some such examples, the hole extending through the second substrate structure additionally or alternatively includes a contact hole filled with a contact material. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Graphs are shown illustrating exemplary etch rates of silicon oxide and silicon nitride as a function of temperature.

[0026] Figure 2 An exemplary deposition tool that may be used to deposit a doped silicon oxide film is schematically shown.

[0027] Figure 3 An exemplary reduced temperature etch tool is schematically shown.

[0028] Figure 4 A flow chart of an exemplary method for performing a reduced temperature etch of silicon oxide doped with an etch rate adjusting dopant is shown.

[0029] Figure 5A and Figure 5BExemplary high aspect ratio features etched through the hard mask layer and into the silicon oxide layer are shown, compared to exemplary high aspect ratio features etched through the hard mask layer and into the doped silicon oxide gapfill layer.

[0030] Figure 6 A flow chart of an exemplary method for performing a memory device manufacturing process including simultaneously etching a channel hole and a hole in a gap fill material is shown.

[0031] Figure 7 The deposition of a dielectric layer comprising silicon oxide and an etch rate adjusting dopant on the stepped structure is schematically shown.

[0032] Figure 8 An exemplary 3D memory structure including a channel hole and a contact hole is schematically shown.

[0033] Fig. 9 A flow chart of an exemplary method for performing a reduced temperature etch of silicon oxide doped with two etch rate adjusting dopants is shown.

[0034] Fig.10 A flow chart of another exemplary method for performing a memory device manufacturing process is shown.

[0035] Fig.11 A block diagram of an exemplary computing system is schematically shown. DETAILED DESCRIPTION

[0036] The term "aspect ratio" generally refers to the ratio between the depth of a substrate feature (eg, a hole) and the average width of the feature.

[0037] The term "channel hole" generally refers to a hole etched into a stack of alternating material layers to form a channel that defines a memory cell in a 3D memory structure.

[0038] The term "contact hole" generally refers to a hole in a dielectric material structure that can be filled with a conductive material to form a contact.

[0039] The term "etching" and its variations generally refer to a process of selectively removing material from a substrate. Etching using a gas phase etchant is called "dry etching." Etching using a liquid phase etchant is called "wet etching." Reactive ion etching (RIE) is a dry etching process that uses a plasma that includes chemically reactive ions to etch material. In some etching processes, a mask is used to protect certain areas of the substrate surface from being etched.

[0040] The term "etch rate-modifying dopant" generally refers to a dopant in a silicon oxide film that allows the film to be etched at a different rate than an undoped film. Examples of etch rate-modifying dopants for silicon oxide films include nitrogen, phosphorus, carbon, boron, arsenic, and combinations of two or more thereof.

[0041] The term "etch rate adjusting dopant precursor" generally refers to a material containing an etch rate adjusting dopant that can react with a silicon-containing precursor and an oxygen-containing gas to deposit a doped silicon oxide layer. Examples of etch rate adjusting dopant precursors include nitrogen-containing precursors, phosphorus-containing precursors, carbon-containing precursors, boron-containing precursors, and arsenic-containing precursors.

[0042] Examples of nitrogen-containing precursors include ammonia (NH3) and aminosilanes. Examples of aminosilanes include bis(diethylamino)silane, di(isopropylamino)silane (DIPAS), bis(tert-butylamino)silane (BTBAS), (di-sec-butylamino)silane, and tris(dimethylamino)silane (3DMAS).

[0043] Examples of phosphorus-containing precursors include phosphine (PH3) and alkyl phosphines, such as trimethylphosphine, triethylphosphine, and tributylphosphine.

[0044] An example of a suitable boron-containing precursor is diborane (B2H6).

[0045] Examples of carbon-containing precursors include carbon monoxide (CO), alkanes, alkenes, alkynes, cyclic hydrocarbons, aromatics, alcohols, diols, aldehydes, esters, ethers, ketones, alkylamines, alkyldiamines, and organosilicon compounds. Suitable alkanes (C n H 2n+2 Examples of suitable olefins (C n H 2n , wherein n=2 to 10, examples of alkenes having a single carbon-carbon double bond may include ethylene, propylene, and butene. Suitable alkynes (C n H 2n-2, where n=2 to 10, for alkynes having a single carbon-carbon triple bond) examples may include acetylene, propyne, and butyne. Examples of suitable cyclic hydrocarbons may include cyclobutane, cyclopentane, and cyclohexane. Examples of suitable aromatics may include benzene, toluene, pyridine, and pyrimidine. Examples of suitable alcohols may include methanol, ethanol, and propanol. Examples of suitable diols may include ethylene glycol, propylene glycol, and hydroquinone. Examples of suitable aldehydes may include formaldehyde and acetaldehyde. Examples of suitable esters may include ethyl formate, methyl acetate, and ethyl acetate. Examples of suitable ethers may include ethyl ether, methyl phenyl ether, and aromatic ethers, such as furan. Examples of suitable ketones may include acetone and methyl ethyl ketone. Examples of suitable alkyl halides may include ethyl fluoride, isopropyl bromide, and tert-butyl chloride. Examples of suitable alkylamines may include methylamine, dimethylamine, trimethylamine, and piperidine. Examples of suitable alkyldiamines may include ethylenediamine and 1,3-diaminopropane. Examples of suitable organosilicon compounds include methylsilane, dimethylsilane, trimethylsilane, and siloxanes such as dimethyldiethoxysilane.

[0046] An example of an arsenic-containing precursor is arsenic (AsH3).

[0047] The term "etchant" generally refers to a chemical used in an etching process that chemically removes material from a substrate and / or facilitates the chemical removal of material. Exemplary etchants for plasma etching of silicon oxide include fluorine-containing etchants such as HF, NF3, CF4, and C2F6.

[0048] The term "feature" generally refers to an area of ​​a substrate where material has been removed (eg, by etching) to form a depression in the substrate surface. Exemplary features that can be formed by etching include holes and gaps.

[0049] The term "film" generally refers to a layer of material deposited on a substrate.

[0050] The term "oxygen-containing gas" generally refers to a gaseous substance containing oxygen, which can be used to react with an oxide film precursor to form an oxide film. Examples of oxygen-containing gases include molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), and water vapor (H2O).

[0051] The term "processing chamber" generally refers to a housing in which chemical and / or physical processes are performed on a substrate. The pressure, temperature, and gas composition within the processing chamber may be controllable to perform the chemical and / or physical processes.

[0052] The term "processing tool" generally refers to a machine that includes a processing chamber, and other hardware configured to enable a process to be performed in the processing chamber.

[0053] The term "radio frequency (RF) power source" generally refers to a component of a processing tool that is configured to apply power to a pair of electrodes in a processing chamber to form a plasma between the pair of electrodes.

[0054] The term "silicon-containing precursor" generally refers to any material that can be introduced into a processing chamber in a vapor phase to form a silicon oxide film on a substrate. Exemplary silicon-containing precursors for forming silicon oxide films may include materials having the following general structure: Wherein R1, R2 and R3 can be the same or different substituents and can include silane, silane alkoxy group, amine, halide, hydrogen, or organic groups such as alkylamine, alkoxy, alkyl, alkenyl, alkynyl, and aromatic groups.

[0055] Exemplary silicon-containing precursors include polysilane (H3Si-(SiH2) n -SiH3), wherein n≥1, such as monosilane, disilane, trisilane, tetrasilane, and trisilylamine.

[0056] In some examples, the silicon-containing precursor is an alkoxysilane. Alkoxysilanes that can be used include: H x -Si-(OR) y , wherein x=1-3, x+y=4, and each R is a substituted or unsubstituted alkyl, alkenyl, alkynyl, or aromatic group; and H x (RO) y -Si-Si-(OR) y H x , is a substituted or unsubstituted alkyl, alkenyl, alkynyl, or aromatic group.

[0057] Examples of silicon-containing precursors include tetraethylorthosilicate (TEOS), tetramethoxysilane (TMOS), methylsilane, trimethylsilane (3MS), ethylsilane, butasilane, pentasilane, octylsilane, heptylsilane, hexasilane, cyclotetrasilane, cycloheptylsilane, cyclohexasilane, cyclooctylsilane, cyclopentasilane, 1,4-dioxa-2,3,5,6-tetrasilacyclohexane, diethoxymethylsilane (DEMS), diethoxysilane (DES), dimethoxymethylsilane, dimethoxysilane (DMOS), methyldiethoxysilane (MDES), methyldimethoxysilane (MDMS), tert-butoxydisilane, triethoxysilane (TES), and trimethoxysilane (TMS or TriMOS).

[0058] In some examples, the silicon-containing precursor may be a siloxane. Exemplary siloxanes include octamethylcyclotetrasiloxane (OMCTS), octamethoxydodecylsiloxane (OMODDS), tetramethylcyclotetrasiloxane (TMCTS), triethoxysiloxane (TRIES), and tetraoxymethylcyclotetrasiloxane (TOMCTS).

[0059] As described above, in some examples, the silicon-containing precursor may be an aminosilane, such as bis(diethylamino)silane, di(isopropylamino)silane (DIPAS), bis(tert-butylamino)silane (BTBAS), (di-sec-butylamino)silane, and tris(dimethylamino)silane (3DMAS). Aminosilane precursors include: x -Si-(NR) y , wherein x=1-3, x+y=4, and R is a substituted or unsubstituted alkyl, alkenyl, alkynyl, or aromatic group, or a hydride group.

[0060] In some examples, a halogen-containing silane may be used, such that the silane includes at least one hydrogen atom. Such a silane may have the chemical formula SiX a H y , where y ≥ 1. For example, in some examples, dichlorosilane (H2SiCl2) may be used.

[0061] The term "showerhead" generally refers to a treatment chemical outlet comprising a plurality of holes distributed over an area.

[0062] The term "step structure" generally refers to a substrate structure including two or more stacked layers in which each subsequent layer extends laterally to a greater distance than the previous layer.

[0063] The term "substrate" generally refers to anything on which a film may be deposited.

[0064] The term "substrate support" generally refers to any structure used to support a substrate in a processing chamber. Examples include chucks, pedestals, and showerhead pedestals for backside deposition processing.

[0065] The term "3D memory structure" generally refers to a structure formed at any point in a manufacturing process for forming a memory device that includes a stacked architecture in which memory cells are layered vertically. Examples of 3D memory structures include structures formed in 3D NAND memory and 3D NOR memory manufacturing processes.

[0066] The term “3D NAND” is an acronym for Three-Dimensional NOT AND Memory, and refers to a memory architecture based on NOT AND logic gates.

[0067] The term “3D NOR” is an acronym for Three-Dimensional NOT OR Memory, and refers to a memory architecture based on NOT OR logic gates.

[0068] As described above, the manufacture of memory structures may involve many steps of material deposition, patterning, and removal. For example, 3D memory devices (e.g., 3D NAND and 3D NOR semiconductor devices) are constructed on stacked material pairs, where the "active" device layer is one of the material pairs and the other is a dielectric for electrical isolation. By stacking these paired layers, manufacturers are able to build more active layers, ultimately forming a so-called "mold stack." Patterning, etching, and metallization of the mold stack are performed to build 3D NAND memory chips. During the 3D NAND device integration process, large areas are constructed within the device that are actually empty spaces (also called gaps). These gaps are often filled with dielectric materials to provide materials for further patterning steps. The material that fills the gap is referred to as a gap filler material in this article.

[0069] Patterning and device integration often involve etching holes (e.g., cylindrical holes) through gap fill materials. The depth of the etch depends on the total height of the die stack. As the height of features in 3D memory technology continues to increase, the amount of material that needs to be removed in the etching process continues to increase. The amount of time used to remove the material also increases with the increased etching depth. This can slow down the production line and introduce additional complexity to the integration process.

[0070] Dry etching may be used to etch features into the gap fill material. Variables to consider in a dry etching environment include gas mixture, process chamber pressure, and process temperature.

[0071] In some dry etching processes, the material exposed to the dry etching environment is actively cooled. Such an etching process is called cryogenic etching. When chemical and physical reactions occur between the deposited material and the etchant, the exposed material is cooled to remove heat energy from the substrate. Keeping the feature sidewalls cool during etching allows the ions in the etching process to move deeper into the gap. When more reactants are located at the bottom of the gap, the etching rate can be increased. This may have a beneficial effect on relatively long and deep etching to keep the surrounding materials intact in time when etching is carried out. Therefore, cryogenic etching tools can be used to etch features in 3D memory device technology. Although described below in the context of 3D NAND manufacturing, the disclosed examples can also be used to manufacture other types of 3D devices, such as 3D NOR memory devices.

[0072] Existing 3D NAND gap filling materials may include silicon, oxygen, carbon and hydrogen, with silicon and oxygen being the main elements. Figure 1 , it can be seen that the etching rate of the silicon oxide dry etching process increases as the substrate temperature decreases, as shown at 102. Therefore, low temperature etching can be used to help achieve faster silicon oxide etching rates. In addition, it can be seen that silicon nitride has a higher etching rate than silicon oxide over the entire temperature range, as shown at 104. Therefore, the silicon oxide film can be doped with nitrogen to increase the etching rate at a given temperature. Other etching rate regulating dopants can also be used to modify the etching rate of silicon oxide. Examples of other etching rate regulating dopants may include one or more of carbon, boron, arsenic, or phosphorus.

[0073] The use of cryogenic etching and doped silicon oxide films to increase the etching rate of the silicon oxide film can facilitate the etching of features in the gap filling material, such as in the 3D NAND or 3D NOR manufacturing process. For example, as described in more detail below, when dry etching is used to etch relatively deep and narrow features into the gap filling material, the etching rate affects the various sizes of the features. As a more specific example, a slower dry etching rate may cause a bow (non-uniformity of the feature diameter as a function of the feature depth), and may also cause a faster rate of lateral growth (e.g., growth of the feature diameter) as a function of vertical growth (depth). In addition, a slower dry etching rate may also result in longer processing times and more costs. Compared to the cryogenic etching of undoped silicon oxide films, the cryogenic etching of doped silicon oxide gap filling materials can help alleviate such problems. Exemplary etching processes are described in more detail below.

[0074] Figure 2 Schematically shown is a schematic diagram of an exemplary processing tool 200 that can be used to deposit a silicon oxide gap fill material doped with an etch rate adjusting dopant. The processing tool 200 is configured as a plasma enhanced chemical vapor deposition (PECVD) tool. In other examples, any other suitable deposition tool can be used to deposit a silicon oxide gap fill material doped with an etch rate adjusting dopant. Examples can include an atomic layer deposition (ALD) tool.

[0075] The processing tool 200 includes a processing chamber 202, and a substrate support 204 within the processing chamber. The substrate support 204 is configured to support a substrate 206 disposed within the processing chamber 202. In some examples, the processing tool 200 includes a substrate heater 208 disposed adjacent to the substrate 206. In other examples, the heater may be omitted or may be located elsewhere within the processing chamber 202. The substrate support 204 may include a pedestal, a chuck, and / or any other suitable structure.

[0076] The processing tool 200 also includes a showerhead 210, a gas inlet 212 connected to the showerhead 210, and a flow control hardware 214. In other examples, the processing tool may also include a nozzle or other device for introducing gas into the processing chamber 202, opposite to or in addition to the showerhead. The flow control hardware 214 is connected to a silicon precursor gas source 216, a first etch rate adjustment dopant gas source 217, an optional second etch rate adjustment dopant gas source 218, an oxygen-containing gas source 219, and an inert gas source 220. The silicon precursor gas source 216 may include any suitable silicon-containing precursor that forms a silicon oxide film when reacted with the oxygen-containing gas. An exemplary silicon-containing precursor is silane. In some examples, one or more aminosilanes may be used. Suitable aminosilanes include di(isopropylamino)silane (DIPAS) and bis(tert-butylamino)silane (BTBAS). Other exemplary silicon-containing precursors include those described above.

[0077] The oxygen-containing gas source 219 may include, for example, O 2 , O 3 , N 2 O, H 2 O 2 , water vapor, or a mixture of two or more thereof.

[0078] The first etch rate adjusting dopant gas source 217 may include any suitable gas for introducing the first etch rate adjusting dopant into the silicon oxide film. The optional second etch rate adjusting dopant gas source 218 may include a second etch rate adjusting dopant precursor different from the first etch rate adjusting dopant precursor. In some examples, the processing tool may include additional etch rate adjusting dopant gas sources.

[0079] Examples of suitable etch rate regulating dopant precursors include nitrogen-containing precursors, phosphorus-containing precursors, carbon-containing precursors, boron-containing precursors, and arsenic-containing precursors. For films using two or more etch rate regulating dopants, any suitable combination of etch rate regulating dopants can be used. In some examples, the first etch rate regulating dopant gas source 217 includes a nitrogen-containing precursor. In some such examples, the second etch rate regulating dopant gas source 218 includes a phosphorus-containing precursor. Examples of nitrogen-containing precursors include ammonia (NH3) and aminosilanes. For example, aminosilanes can be used to provide both silicon and nitrogen to grow nitrogen-doped silicon oxide films. Suitable aminosilanes include DIPAS and BTBAS. Examples of phosphorus-containing precursors include phosphine (PH3) and alkyl phosphines, such as trimethylphosphine, triethylphosphine, and tributylphosphine. An example of a boron-containing precursor is diborane (B2H6). Examples of carbon-containing precursors include carbon monoxide (CO), alkanes, alkenes, alkynes, cyclic hydrocarbons, aromatics, alcohols, aldehydes, esters, ethers, ketones, alkylamines, alkyldiamines, and organosilicon precursors (e.g., methylsilane, dimethylsilane, trimethylsilane, and siloxane). An example of an arsenic-containing precursor is arsenic (AsH3).

[0080] The inert gas source 220 may include any suitable inert gas, such as one or more of helium, neon, argon, krypton, xenon, or nitrogen.

[0081] The flow control hardware 214 may be controlled to flow gases from various gas sources into the process chamber 202 via the gas inlet 212. The flow control hardware 214 may include one or more valves that are controllable to fluidly connect a selected gas source to the gas inlet 212.

[0082] The processing tool 200 also includes an exhaust system 224. The exhaust system 224 is configured to receive gases flowing from the processing chamber 202. In some examples, the exhaust system 224 is configured to actively remove gases and / or apply a partial vacuum from the processing chamber 202. The exhaust system 224 can include any suitable hardware, including one or a pump.

[0083] The processing tool 200 also includes an RF power source 228 electrically connected to the substrate support 204. The RF power source 228 is configured to form a plasma including an oxygen-containing gas. The processing tool 200 also includes a matching network 229 for impedance matching of the RF power source 228. The plasma may also include an inert dilution gas from the inert gas source 220. The RF power source 228 may be configured to any suitable frequency (e.g., 400 kHz, or 13.56 MHz as examples) and power (e.g., between 0 and 6500 watts). In some examples, the RF power source 228 is configured to operate at a plurality of different frequencies and / or powers.

[0084] The controller 230 is operably coupled to the substrate heater 208, the flow control hardware 214, the exhaust system 224, and the RF power source 228. The controller 230 is configured to control various functions of the processing tool 200, such as operating the substrate heater 208 to heat to a desired temperature. The controller 230 is also configured to operate the flow control hardware 214 to flow selected gases into the processing chamber 202. The controller 230 is also configured to operate the exhaust system 224. The controller 230 is also configured to operate the RF power source 228 to form a plasma. The controller 230 may include any suitable computing system, examples of which are shown in FIG. Fig.11 Described below.

[0085] Figure 3An exemplary etching tool 300 is schematically shown, which is configured to perform a low temperature dry etching process, also referred to herein as a reduced temperature etching process. The etching tool 300 includes a processing chamber 302, and a substrate support 304 within the processing chamber. The substrate support 304 is configured to support a substrate 306 disposed within the processing chamber 302. The substrate support 304 may include a pedestal, a chuck, and / or any other suitable structure.

[0086] The etching tool 300 also includes a gas inlet 312 and flow control hardware 314. The flow control hardware 314 is connected to an etchant gas source 316 and an inert gas source 320. The etchant gas source 316 may include any suitable etchant chemistry. Examples include fluorine-containing etchants. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6. The inert gas source 320 may include any suitable inert gas, such as one or more of helium, neon, argon, krypton, xenon, or nitrogen.

[0087] Flow control hardware 314 is controllable to flow gases from etchant gas source 316 and inert gas source 320 into process chamber 302 via gas inlet 312. Flow control hardware 314 includes one or more valves controllable to fluidly connect selected gas sources to gas inlet 312.

[0088] The etching tool 300 also includes an exhaust system 324. The exhaust system 324 is configured to receive gas flowing from the processing chamber 302. In some examples, the exhaust system 324 is configured to actively remove gas and / or apply a partial vacuum from the processing chamber 302. The exhaust system 324 can include any suitable hardware, including a pump.

[0089] The etching tool 300 also includes an RF power source 328 electrically connected to the substrate support 304. Thus, the substrate support 304 forms a first electrode. The etching tool 300 also includes a second electrode 350. The RF power source 328 is configured to form a plasma including an etchant gas. The etching tool 300 may include a matching network 329 for impedance matching of the RF power source 328. The plasma may also include an inert dilution gas from an inert gas source 320. The RF power source 328 may be configured to any suitable frequency and power. In some examples, the RF power source 328 is configured to operate at a plurality of different frequencies and / or powers.

[0090] The etching tool 300 also includes a chiller 352 configured to circulate a coolant through the substrate support 304 to cool the substrate, thereby achieving a reduced temperature etching process.

[0091] The controller 330 is operably coupled to the flow control hardware 314, the exhaust system 324, the RF power source 328, and the cooler 352. The controller 330 is configured to control various functions of the etching tool 300, such as operating the substrate cooler 352 to cool the substrate to a desired temperature. The controller 330 is also configured to operate the flow control hardware 314 to flow selected gases into the processing chamber 302. The controller 330 is also configured to operate the exhaust system 324. The controller 330 is also configured to operate the RF power source 328 to form a plasma. The controller 330 may include any suitable computing system, examples of which are shown in FIG. Fig.11 Described below.

[0092] Figure 4 A flow chart is shown depicting a method 400 of performing a reduced temperature etching process. Etching tool 300 is an exemplary processing tool for performing method 400. Method 400 includes, at 402, placing a substrate in a processing chamber of a processing tool, the substrate including a dielectric material including silicon oxide and an etch rate adjusting dopant. In some examples, at 404, the etch rate adjusting dopant includes one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0093] The method 400 also includes, at 406, controlling the processing tool to cool the substrate to a substrate temperature of 0° C. or less. In some examples, the processing tool may cool the substrate to a substrate temperature in the range of -60° C. to -10° C. In other examples, substrate temperatures outside of this range may be used.

[0094] Continuing, at 410, method 400 also includes controlling the processing tool to introduce an etchant into the processing chamber. In some examples, at 412, the etchant includes a fluorine-containing etchant. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6.

[0095] The method 400 also includes, at 416, controlling a processing tool to form a plasma containing an etchant to etch a feature having a depth-to-width ratio in a range of 10:1 to 100:1 into a dielectric material. In some examples, at 418, the feature includes a depth-to-width ratio in a range of 30:1 to 70:1. All ranges described herein include endpoints. In some examples, the feature may include a depth-to-width ratio greater than 100:1. In some examples, the feature includes a hole in a memory device structure. In some examples, at 420, the feature includes a contact hole in a 3D NAND memory structure. In other examples, the feature includes a contact hole in a 3D NAND memory structure. In addition, in some examples, the substrate includes a first substrate structure and a second substrate structure, the first substrate structure including alternating layers in a mold stack of a 3D NAND structure, and the second substrate structure including a dielectric material. In such an example, the method also includes controlling a processing tool to simultaneously etch a hole in the second substrate structure and at least a portion of a channel hole in the first substrate structure, as shown at 422.

[0096] Figure 5A and Figure 5B Exemplary high aspect ratio features etched through a hard mask layer and into a silicon oxide layer are shown, compared to exemplary high aspect ratio features etched through a hard mask layer and into a nitrogen doped silicon oxide layer.

[0097] More specifically, Figure 5A Schematically shown, using a temperature drop etching process, etching into a feature 500 in a gap filler material 502, the gap filler material 502 comprising undoped silicon oxide. The feature is defined by a hard mark 504. As shown, in some examples, the relatively slow dry etch rate of the undoped silicon oxide can cause a bow. This is shown as an increase and then decrease in the width of the feature 500 at the interface of the gap filler material 502 and the hard mask 504. Therefore, the width (e.g., diameter) dimension of the feature 500 at the interface is greater than the width (e.g., diameter) dimension of the corresponding opening in the hard mask 504. In addition, the bow and the wider dimension may be apparent before the feature 500 is etched to its full depth.

[0098] Figure 5BSchematically shown is a feature 550 etched into a gap fill material 552 under similar etching conditions as feature 500 using a reduced temperature etching process, the gap fill material 552 comprising silicon oxide doped with an etch rate regulating dopant. As described above, the use of an etch rate regulating dopant can provide a faster etch rate than etching undoped silicon oxide. Any suitable dopant concentration can be used. In some examples, an N-doped silicon oxide film containing a nitrogen concentration between 16 and 20 atomic % can have an etch rate of ~180 nm / min. Under similar etching conditions, an undoped oxide film can have an etch rate of ~100 nm / min.

[0099] Feature 550 has a smaller bow (compared to feature 500) and a width that more closely matches the width of a corresponding opening in hard mask 554 (compared to feature 500 and hard mask 504). Feature 550 can have any suitable aspect ratio. In some examples, feature 550 can have an aspect ratio of 10:1 or greater. For example, feature 550 can have an aspect ratio between 10:1 and 100:1. In some examples, feature 550 can have an aspect ratio between 50:1 and 100:1.

[0100] Feature 550 can be any suitable structure in an integrated circuit. In some examples, feature 550 can include a contact hole in a 3D NAND manufacturing process or a 3D NOR manufacturing process. In addition, as described above, the etch rate adjusting dopant can include any suitable material. Examples include one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

[0101] exist Figure 5A and 5B In addition to the advantages shown in , the use of etch rate regulating dopants can provide other advantages. For example, a 3D NAND device may include high aspect ratio features formed through alternating layers (e.g., channel holes) of a die stack and also through a silicon oxide gap filler material. As a more specific example, a high aspect ratio feature may be formed through a silicon oxide gap filler material to make contacts in a NAND device. Such high aspect ratio features may also be referred to herein as contact holes. In a typical NAND manufacturing process, channel holes and contact holes are etched in different processes. This is, at least in part, because the alternating layers of the die stack are etched at a different rate than the silicon oxide gap filler material using the same etching chemistry and etching conditions.

[0102] The use of one or more etch rate regulating dopants in the silicon oxide gap filling material allows the etch rate of the gap filling material to be adjusted to appropriately approach the etch rate of the alternating layers of the mold stack. As an illustrative example, the mold stack includes alternating silicon oxide and silicon nitride layers, and the etch rate regulating dopant may include nitrogen, and / or one or more other suitable materials. The following describes in more detail an example using two or more co-dopants. The concentration of nitrogen and / or other dopants in the silicon oxide gap filling material is selected to adjust the etch rate to match the average etch rate of the material in the alternating layers of the mold stack. This allows the channel hole etching and the gap filling etching to proceed at similar rates. Similarly, the concentration of the etching regulating dopant can also be selected to achieve a controlled difference in etching rate, thereby allowing features of different depths to be etched in the same step. The amount of dopant incorporated into the gap filling material during deposition can be controlled by controlling the concentration of the dopant precursor gas used (compared to the silicon-containing precursor gas).

[0103] Figure 6 A flow chart of an exemplary method is shown for performing a memory device manufacturing process including simultaneously etching at least a portion of a channel hole and a hole in a gap fill material. At 602, method 600 includes placing a substrate in a processing chamber of a processing tool, the substrate including a first substrate structure including alternating layers in a mold stack of a 3D memory structure, and the substrate also including a second substrate structure including a silicon oxide layer doped with one or more etch rate adjusting dopants. In some examples, at 604, method 600 also includes depositing the second substrate structure by reacting a silicon-containing precursor, an oxygen-containing gas, and an etch rate adjusting dopant precursor to form a silicon oxide layer doped with an etch rate adjusting dopant. In some examples, at 606, the etch rate adjusting dopant precursor includes one or more of a nitrogen-containing precursor, a phosphorus-containing precursor, a carbon-containing precursor, a boron-containing precursor, or an arsenic-containing precursor. Continuing, at 610, method 600 also includes controlling a processing tool to perform an etching cycle, the etching cycle including simultaneously etching at least a portion of a channel hole in the first substrate structure and at least a portion of a hole in the second substrate structure. In some examples, the hole in the second substrate structure includes a contact hole in the 3D memory structure.

[0104] In some examples, at 612, the method includes controlling the processing tool to cool the substrate to a substrate temperature equal to or below 0° C. during the etching cycle. In some examples, at 614, the method includes introducing a fluorine-containing etchant into the processing chamber. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6. In some examples, at 616, the method 600 includes forming a plasma in the processing chamber. For example, the method may include controlling the processing tool to form a plasma including the fluorine-containing etchant. In some examples, at 618, the hole in the second substrate structure includes a contact hole. In some examples, at 620, controlling the processing tool to perform the etching cycle includes controlling the processing tool to etch the channel hole to a depth-to-width ratio in the range of 50:1 to 100:1. In some examples, at 622, controlling the processing tool to perform the etching cycle includes controlling the processing tool to etch the hole in the second substrate structure to a depth-to-width ratio in the range of 10:1 to 100:1. In some examples, the processing tool can be controlled to etch the hole in the second substrate structure to an aspect ratio greater than 100:1.

[0105] Figure 7 Schematically showing the start and end structures before and after implementing an exemplary gap fill process in a 3D NAND manufacturing process. First, a "staircase" structure is shown at 702. The staircase structure 702 is etched from a mold stack including alternating layers 704, 706. In some examples, the alternating layers 704, 706 may include silicon oxide and silicon nitride layers. In other examples, the alternating layers 704, 706 may include alternating silicon oxide and polysilicon layers. In other examples, the alternating layers 704, 706 may include any other suitable material.

[0106] Next, a layer of gap fill material 710 is deposited. The layer of gap fill material 710 may be deposited in a series of steps (not shown). Figure 7 In some examples, such processing may include patterning, deposition, and etching steps.

[0107] The gap fill material 710 includes silicon oxide and an etch rate adjusting dopant. Exemplary dopants include one or more of nitrogen, carbon, boron, arsenic, or phosphorus. The dopant may have any suitable concentration to change the etch rate.

[0108] The gap fill material 710 may be deposited in any suitable manner. For example, a silicon-containing precursor (e.g., silane, etc.), an oxygen precursor (e.g., one or more of O2, O3, H2O, N2O, etc.), and an etch rate adjusting dopant precursor (e.g., ammonia, aminosilane, etc.) may be introduced into a PECVD chamber under suitable conditions to form a film of the gap fill material on the substrate. In other examples, the gap fill material 710 may be deposited by an ALD process.

[0109] Figure 8 An exemplary 3D memory structure 800 is schematically shown, which includes a channel hole, and a plurality of holes etched through a gap fill material 710. The 3D memory structure 800 includes a first substrate structure 802 and a second substrate structure 804. The first substrate structure 802 includes alternating layers 704, 706. The first substrate structure 802 also includes a channel hole 808 extending through the alternating layers 704, 706. Any suitable number of alternating layers can be used. In addition, the channel hole 808 can extend through any suitable number of layers within the first substrate structure 802. The channel hole 808 can be filled with one or more materials to form a 3D NAND memory cell structure, or a 3D NOR memory cell structure.

[0110] The second substrate structure 804 includes a gap fill material 710. The gap fill material 710 includes a silicon oxide layer doped with an etch rate adjusting dopant. As described above, suitable etch rate adjusting dopants may include one or more of nitrogen, carbon, boron, arsenic, or phosphorus. The 3D memory structure 800 also includes holes 814, 815, 816, 817 extending through the gap fill material 710. Each of the holes 814, 815, 816, 817 extends to a different layer within the step structure. Each of the holes 814, 815, 816, 817 may include a contact hole and may be filled with one or more materials to form an electrical contact. For example, the method 600 may be used to simultaneously etch at least a portion of the channel hole 808 and at least a portion of one or more of the holes 814, 815, 816, or 817 to form the 3D memory structure 800.

[0111] As described above, a doped silicon oxide film having a relatively high nitrogen concentration can provide a relatively large etch rate compared to a film having a relatively low nitrogen concentration. However, the relatively high concentration of dopants may affect the dielectric properties of the film. For example, a silicon oxide film containing a relatively high nitrogen concentration may have a lower breakdown voltage and / or a higher leakage current compared to a film having a relatively low nitrogen concentration.

[0112] Therefore, examples are also disclosed, using two or more etch rate regulating dopants to dope silicon oxide films. Co-doped silicon oxide films can help achieve the above-mentioned etch rate advantages, while using relatively low dopant concentrations (compared to examples with a single dopant). Therefore, compared to silicon oxide films with a single dopant, co-doped silicon oxide films can have a smaller effect on the dielectric properties of the film. For example, compared to silicon oxide films doped with only nitrogen, silicon oxide films doped with nitrogen and phosphorus can help achieve similar or faster etching rates, and the dopant concentration is reduced by 50%. In some examples, a co-doped silicon oxide film containing a nitrogen concentration between 5 and 10 atomic % and a phosphorus concentration between 0.1 and 1.0 atomic % may have an etching rate of ~190nm / min. As described above, under similar etching conditions, an N-doped silicon oxide film containing a nitrogen concentration between 16 and 20 atomic % may have an etching rate of ~180nm / min. In addition, compared to silicon oxide films doped with only nitrogen, co-doped silicon oxide films may have a relatively small hydrogen concentration. In various examples, the doped silicon oxide film may include one, two, or more etch rate adjusting dopants.

[0113] Fig. 9 A flow chart of an exemplary method 900 is shown for performing a reduced temperature etch of silicon oxide doped with two etch rate adjusting dopants. In other examples, three or more etch rate adjusting dopants may be used to perform a reduced temperature etch.

[0114] For example, method 900 may be performed in etching tool 300. Method 900 includes, at 902, controlling a processing tool to cool a substrate to a substrate temperature of 0° C. or less within a processing chamber of the processing tool. The substrate includes a dielectric material, the dielectric material including silicon oxide, a first etch rate adjusting dopant, and a second etch rate adjusting dopant. Any suitable combination of etch rate adjusting dopants may be used. In some examples, at 904, the first etch rate adjusting dopant includes nitrogen. In some such examples, at 906, the dielectric material includes silicon oxide, the silicon oxide including a nitrogen concentration in a range of 5 atomic % to 10 atomic %. Further, in some examples, at 908, the second etch rate adjusting dopant includes phosphorus. In some such examples, at 910, the dielectric material includes silicon oxide, the silicon oxide including a phosphorus concentration in a range of 0.1 to 1.0 atomic %.

[0115] Continuing, method 900 also includes, at 912, controlling the processing tool to introduce an etchant into the processing chamber. Any suitable etchant can be used. In some examples, at 914, the etchant includes a fluorine-containing etchant. Suitable fluorine-containing etchants include HF, NF3, CF4, and C2F6.

[0116] The method 900 also includes controlling a processing tool to form a plasma containing an etchant to etch features with a depth-to-width ratio in a range of 10:1 or greater into a dielectric material. In some examples, at 916, the features include a depth-to-width ratio of 10:1 to 100:1. In some examples, at 918, the features include a depth-to-width ratio in a range of 30:1 to 70:1. In some examples, the features include holes in a memory device structure (e.g., holes 814, 815, 816, 817 of 3D memory structure 800). In some examples, at 920, the features include contact holes in a 3D memory structure (e.g., 3D NAND or 3DNOR). In some examples, the substrate includes a first substrate structure and a second substrate structure, the first substrate structure including alternating layers in a mold stack of the 3D memory structure, and the second substrate structure including a dielectric material. In such an example, the method 900 may further include controlling a processing tool to simultaneously etch the hole in the second substrate structure and at least a portion of the channel hole in the first substrate structure, as shown at 922 .

[0117] Fig.10 A flow chart of another exemplary method 1000 is shown for performing a memory device manufacturing process using a processing tool. At 1002, the method 1000 includes obtaining a substrate including a first substrate structure, the first substrate structure including alternating layers of a mold stack of a 3D memory structure. The substrate also includes a second substrate structure, the second substrate structure including a silicon oxide layer doped with two or more etch rate adjusting dopants. In some examples, at 1004, the two or more etch rate adjusting dopants include a first etch rate adjusting dopant including nitrogen. In some examples, at 1006, the silicon oxide layer includes a nitrogen concentration in the range of 5 atomic % to 10 atomic %. In some such examples, at 1008, the two or more etch rate adjusting dopants also include a second etch rate adjusting dopant including phosphorus. In some examples, at 1010, the silicon oxide layer includes a phosphorus concentration in the range of 0.1 atomic % to 1 atomic %.

[0118] In some examples, at 1012, obtaining a substrate including a second substrate structure includes, in a CVD tool, reacting a silicon-containing precursor, an oxygen-containing gas, a nitrogen-containing precursor, and a phosphorus-containing precursor to deposit the second substrate structure. Any suitable precursor may be used. In some examples, at 1014, the phosphorus-containing precursor includes one or more of a phosphine or an alkylphosphine. In addition, in some examples, at 1016, the nitrogen-containing precursor includes one or more of ammonia, di(isopropylamino)silane, or di(tert-butylamino)silane. In some examples, the oxygen-containing gas includes one or more of O2, O3, nitrous oxide (N2O), or water vapor. Processing tool 200 is an exemplary tool for depositing a second substrate structure at 1012. Gap fill material 710 is an example of a second substrate structure that may be deposited at 1012. In other examples, a substrate including a previously deposited second substrate structure may be obtained.

[0119] In some examples, the dopant concentration can be selected to achieve a desired etch rate for the holes. This can facilitate etching the channel holes in the first substrate structure (e.g., channel holes 808 of the first substrate structure 802) and the holes in the second substrate structure (e.g., holes 814, 815, 816, 817 of the second substrate structure 804) simultaneously.

[0120] The method 1000 also includes, at 1020, placing the substrate in an etching tool, and controlling the etching tool to perform an etching cycle. The etching cycle includes etching at least a portion of a channel hole in the first substrate structure, and etching at least a portion of a hole in the second substrate structure. Channel hole 808 is an example of a channel hole in the first substrate structure, which can be etched at 1020. Holes 814, 815, 816, 817 are examples of holes in the second substrate structure, which can be etched at 1020. In some examples, at 1022, the hole in the second substrate structure includes a contact hole. In some examples, at 1024, the processing tool includes a processing chamber, and controlling the processing tool to perform the etching cycle includes controlling the processing tool to introduce a fluorine-containing etchant into the processing chamber. Suitable fluorine-containing etchants may include HF, NF3, CF4, and C2F6. Various patterning steps not described in detail herein may be used to form channel holes in the first substrate structure, and to form holes in the second substrate structure. In some examples, at 1026 , method 1000 also includes controlling the processing tool to cool the substrate to 0° C. or less during the etching cycle.

[0121] Fig.11A block diagram of an exemplary computing system is schematically shown. Computing system 1100 is shown in simplified form. Computing system 1100 may take the form of one or more personal computers, workstations, computers integrated with substrate processing tools, and / or network accessible server computers.

[0122] The computing system 1100 includes a logic machine 1102 and a storage machine 1104. The computing system 1100 may optionally include a display subsystem 1106, an input subsystem 1108, a communication subsystem 1110, and / or Fig.11 Controller 230 and controller 330 are examples of computing system 1100 .

[0123] The logic machine 1102 includes one or more physical devices configured to execute instructions. For example, the logic machine can be configured to execute instructions that are part of one or more applications, services, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions can be implemented to perform tasks, implement data types, transform the state of one or more components, achieve technical effects, or otherwise achieve desired results.

[0124] The logic machine may include one or more processors configured to execute software instructions. Additionally or alternatively, the logic machine may include one or more hardware or firmware logic machines configured to execute hardware or firmware instructions. The processors of the logic machine may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel and / or distributed processing. The various components of the logic machine may optionally be distributed in two or more separate devices that may be remotely located and / or configured for coordinated processing. Various aspects of the logic machine may be virtualized and executed by a remotely accessible networked computing device configured in a cloud computing configuration.

[0125] The storage machine 1104 includes one or more physical devices configured to store instructions 1112 that can be executed by a logic machine to implement the methods and processes described herein. When such methods and processes are implemented, the state of the storage machine 1104 can be transformed—for example, to store different data.

[0126] The storage machine 1104 may include removable and / or built-in devices. The storage machine 1104 may include optical storage (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), semiconductor storage (e.g., RAM, EPROM, EEPROM, etc.), and / or magnetic storage (e.g., hard disk drive, floppy disk drive, tape drive, MRAM, etc.). The storage machine 1104 may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location addressable, file addressable, and / or content addressable devices.

[0127] It should be understood that storage 1104 includes one or more physical devices. However, alternatively, aspects of the instructions described herein may be propagated via a communication medium (eg, electromagnetic signals, optical signals, etc.) that is not held for a finite duration by a physical device.

[0128] Aspects of the logic machine 1102 and the storage machine 1104 may be integrated together into one or more hardware logic components. For example, such hardware logic components may include field programmable gate arrays (FPGAs), program and application specific integrated circuits (PASIC / ASIC), program and application specific standard products (PSSP / ASSP), systems on chips (SOCs), and complex programmable logic devices (CPLDs).

[0129] When included, display subsystem 1106 can be used to present a visual representation of the data stored by storage machine 1104. This visual representation can take the form of a graphical user interface (GUI). Since the methods and processes described herein change the data held by the storage machine, and therefore change the state of the storage machine, the state of display subsystem 1106 can also be converted to visually represent the change of the underlying data. Display subsystem 1106 can include one or more display devices using almost any type of technology. Such display devices can be combined with logic machines 1102 and / or storage machines 1104 in a shared enclosure, or such display devices can be peripheral display devices.

[0130] When included, input subsystem 1108 may include or may interact with one or more user input devices (e.g., a keyboard, mouse, or touch screen). In some examples, the input subsystem may include or interact with selected natural user input (NUI) components. Such components may be integrated or peripheral, and conversion and / or processing of input actions may be handled on-board or off-board. Exemplary NUI components may include microphones for voice and / or sound recognition, and infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition.

[0131] When included, the communication subsystem 1110 can be configured to communicatively couple the computing system 1100 with one or more other computing devices. The communication subsystem 1110 can include wired and / or wireless communication devices compatible with one or more different communication protocols. As non-limiting examples, the communication subsystem can be configured to communicate using a wireless telephone network, or a wired or wireless local area network or wide area network. In some examples, the communication subsystem can allow the computing system 1100 to send messages to other devices and / or receive messages from other devices over a network such as the Internet.

[0132] It should be understood that the configuration and / or method described herein is exemplary in nature, and these specific one or more examples should not be considered restrictive, because many variations are possible. The specific routine or method described herein can represent one or more of any number of processing strategies. Therefore, the various actions shown and / or described can be performed in the order shown and / or described, in other orders, in parallel or omitted. Similarly, the order of the above-mentioned processing can be changed.

[0133] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.

Claims

1. A method of performing a memory device manufacturing process, the method comprising: placing a substrate in a process chamber of a process tool, the substrate comprising a first structure comprising alternating layers in a die stack of a 3D memory structure, the substrate further comprising a second structure comprising a silicon oxide layer doped with an etch rate modulating dopant; as well as The processing tool is controlled to perform an etch cycle comprising etching at least a portion of a channel hole in the first structure of the substrate and at least a portion of a hole in the second structure of the substrate.

2. The method according to claim 1, further comprising: The processing tool is controlled to cool the substrate to a temperature at or below 0° C. during the etching cycle.

3. The method of claim 1 , wherein controlling the processing tool to perform the etching cycle comprises: The processing tool is controlled to introduce a fluorine-based etchant into the processing chamber. The method of claim 1 , wherein the etch rate adjusting dopant comprises two or more etch rate adjusting dopants.

5. The method of claim 4, wherein the two or more etch rate adjusting dopants include two or more of nitrogen, carbon, boron, arsenic, or phosphorus. The method of claim 4 , wherein the second structure comprises a nitrogen concentration in a range of 5 atomic % to 10 atomic %. 7 . The method of claim 6 , wherein the second structure comprises a phosphorus concentration in a range of 0.1 atomic % to 1 atomic %.

8. The method according to claim 1, further comprising: The second structure is deposited by reacting a silicon-containing precursor, an oxygen-containing precursor, and an etch rate adjusting dopant precursor to form the silicon oxide doped with the etch rate adjusting dopant.

9. The method of claim 8, wherein depositing the second structure further comprises: Two or more etch rate adjusting dopant precursors, the silicon-containing precursor, and the oxygen-containing precursor are reacted.

10. The method of claim 9, wherein the two or more etch rate adjusting dopant precursors include ammonia, bis(isopropylamino)silane, or bis(tert-butylamino)silane.

11. The method of claim 9, wherein the two or more etch rate adjusting dopant precursors include one or more of a phosphine or an alkyl phosphine.

12. A method for etching a substrate, the method comprising: placing a substrate in a process chamber of a processing tool, the substrate comprising a dielectric material including silicon oxide and an etch rate adjusting dopant; controlling the processing tool to cool the substrate to a substrate temperature of 0° C. or less; controlling the processing tool to introduce an etchant into the processing chamber; as well as The processing tool is controlled to form a plasma including the etchant to etch features into the dielectric material, the features including an aspect ratio of 10:1 or greater.

13. The method of claim 12, wherein the etch rate adjusting dopant comprises one or more of nitrogen, carbon, boron, arsenic, or phosphorus.

14. The method of claim 12, wherein the etch rate adjusting dopant is a first etch rate adjusting dopant, and wherein the dielectric material further comprises a second etch rate adjusting dopant. 15 . The method of claim 14 , wherein the first etch rate adjusting dopant comprises nitrogen and the second etch rate adjusting dopant comprises phosphorus.

16. A 3D memory structure, comprising: a channel hole extending through a first substrate structure comprising alternating layers of material; as well as A hole extends through a second substrate structure including a silicon oxide layer doped with a first etch rate adjusting dopant and a second etch rate adjusting dopant. 17 . The 3D memory structure of claim 16 , wherein the first etch rate adjusting dopant comprises nitrogen and the second etch rate adjusting dopant comprises phosphorus.

18. The 3D memory structure of claim 17, wherein the silicon oxide layer comprises a nitrogen concentration in a range of 5 atomic % to 10 atomic % and a phosphorus concentration in a range of 0.1 atomic % to 1.0 atomic %. 19 . The 3D memory structure of claim 16 , wherein the alternating material layers include a step structure, the silicon oxide layer doped with the first etch rate adjusting dopant and the second etch rate adjusting dopant being located over at least a portion of the step structure.

20. The 3D memory structure of claim 16, wherein the hole extending through the second substrate structure comprises a contact hole filled with a contact material.

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