Multi-mode template triggering and reanalysis method based on FPGA
Through the implementation of multi -mode template trigger and re -analysis methods on FPGA, the problem of the existing technology mid -frequency selectivity and insufficient trigger diversity is solved, and higher calculation accuracy and system flexibility are achieved. Signal processing application.
Patent Information
- Application Number
- CN202411467613.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art has limitations in frequency selectivity, trigger diversity, real-time response or accuracy, and flexibility, making it difficult to quickly and accurately identify and trigger specific frequency components in complex electromagnetic environments.
The FPGA -based multi -mode template trigger and re -analysis method is used to optimize the use and calculation accuracy by determining the format and accuracy of the frequency template data (such as an integer, fixed -point or floating point number). This method includes frequency template storage, multi -way parallel processing, IQ data storage, and FFT processing module to achieve 18 triggers and dynamic mode template analysis.
It improves the calculation accuracy of frequency template data and the utilization efficiency of hardware resources, achieves faster and more accurate signal identification and triggering, and enhances the flexibility and adaptability of the system.
Smart Images
Figure CN119355365A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of signal spectrum analysis, and in particular relates to a multi-mode template triggering and re-analysis method based on FPGA. Background Art
[0002] In today's complex electromagnetic environment, higher requirements are placed on signal processing. Rapidly and accurately identifying and triggering specific frequency components has become the key in signal processing applications. Existing technologies may have limitations in frequency selectivity, trigger diversity, real-time response or accuracy, and flexibility. Summary of the invention
[0003] The object of the present invention is to provide a multi-mode template triggering and reanalysis method based on FPGA, which determines the format and precision of frequency template data through data type. For example, the data can be an integer, a fixed-point number or a floating-point number, so that the operator can determine the format and precision of the data, which helps to optimize the use of FPGA resources and calculation accuracy. Selecting the appropriate data type (integer, fixed-point number or floating-point number) can balance the calculation accuracy and hardware resource requirements, thereby improving the overall performance and solving the existing problems.
[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention is a multi-mode template triggering method based on FPGA, comprising the following steps: S1: Frequency template storage module: The host computer configures the quantized frequency template data and stores it in BLOCKRAM. The frequency template data is divided into upper template data and lower template data; S2: Trigger module: For a frame of spectrum data with extra-long points, a multi-channel parallel processing method is adopted. Different template types are configured and selected, which are divided into upper template, lower template and upper and lower template. The configuration trigger mode type is divided into triggering within the template, triggering outside the template, triggering after leaving the template, triggering after entering the template, triggering after leaving the template and then entering the template, and triggering after entering the template and then leaving the template. A total of 18 triggers can be realized. After the configuration is completed, the template trigger is performed; S3: IQ data storage module: When a trigger occurs, the synchronized IQ data is saved. Depending on the trigger mode, the storage length of the data is different. Taking the upper and lower templates entering the template and then leaving the template trigger mode as an example, 3 frames of data length will be saved and the number of triggers will be recorded. IQ data can be selected in DDR or BLOCKRAM. When other trigger modes are triggered, the IQ data storage length will change; S4: FFT processing module and host computer module: re-analysis of IQ trigger data. After the trigger is completed, by configuring the trigger count value, the address where the trigger data is stored can be calculated, and the data can be read from the storage module and sent to the FFT module for processing. The FFT module performs FFT calculations of the corresponding number of points based on the length N of a frame of data, and the calculation results are transmitted to the host computer for processing and display of the spectrum diagram at the trigger time.
[0005] The present invention is a multi-mode template analysis method based on FPGA, comprising the following steps: Q1: Requirements Analysis and Design: Clarify the application scenarios and requirements of multi-modal template analysis. For example, template matching may be used in image recognition, signal processing, and other fields. Determine the template patterns to be used and their characteristics. These templates will be used to match the input data; Q2: Feature extraction: Preprocess the input data, such as denoising, normalization, etc., to improve matching accuracy and speed, and extract useful features from the input data and template. This can include edge detection, corner detection, texture analysis, etc. Q3: Template matching algorithm design: Select the appropriate template matching algorithm according to application requirements. For example, commonly used algorithms include correlation matching, template matching, statistical matching, etc. According to the characteristics of FPGA, the algorithm is optimized to ensure efficient hardware implementation. Including algorithm parallelization, pipeline design, etc.; Q4: FPGA design and implementation: Use HDL (such as Verilog or VHDL) to write the hardware description code of the template matching algorithm, and decompose the entire design into multiple modules, such as feature extraction module, matching module, control module, etc. Each module can be implemented independently in the FPGA, and hardware resources are allocated according to the resources of the FPGA (such as logic units, memory, DSP blocks, etc.) to optimize performance and power consumption.
[0006] Preferably, the S1 is further expressed as: S1.1: Data type: Determines the format and precision of the frequency mask data. For example, the data can be integer, fixed point, or floating point; S1.2: Storage requirements: Understand the storage size requirements, including the number of templates and the amount of data in each template; S1.3: Data structure: It may be necessary to design different storage structures for upper template data and lower template data respectively; S1.4: Data quantization: quantize the frequency mask data into data suitable for FPGA storage format. For example, convert floating point numbers into fixed point numbers; S1.5: Data transmission: The host computer transmits the quantized template data to the FPGA. The data transmission can be through a serial port, parallel interface or other communication protocols.
[0007] Preferably, S2 is further expressed as: S2.1: Parallel processing: Due to the large amount of data, multi-path parallel processing is used to accelerate data analysis. Each parallel path processes a subset of spectrum data; S2.2: Data segmentation: The spectrum data of the ultra-long points is divided into multiple sub-blocks, each of which is processed by a processing unit; S2.3: Data receiving module: receives spectrum data of super-long points from a data source and distributes it to multiple processing units; S2.4: Trigger response: Execute corresponding response operations according to the trigger event, such as generating interrupts, updating status, etc.; S2.5: Real-time monitoring: In a real-time signal monitoring system, multi-channel parallel processing is used to analyze spectrum data and generate real-time responses based on configured triggering methods.
[0008] Preferably, S3 is further expressed as: S3.1: Data caching: When a trigger event occurs, the synchronized IQ data is cached to the specified storage medium; S3.2: DDR storage implementation: Write IQ data into DDR and perform efficient data transmission through DMA controller or AXI interface; S3.3: Counter Design: Design a counter to record each trigger and store it in a specified register or memory location; S3.4: Storage optimization: Optimize the use of DDR or BRAM according to application requirements to balance storage capacity and access speed; S3.5: System maintenance: Monitor and maintain the data storage module and handle possible failures or performance issues.
[0009] Preferably, the S4 is further expressed as: S4.1: Calculation method: Calculate the starting address of the data in the storage module according to the number of triggers and the length of the data stored in each trigger. Take the trigger mode of entering the template and then leaving the template with the upper and lower templates as an example. Compare the corresponding frequency point data in frames. When the spectrum data is greater than the upper template or less than the lower template, the comparison output signal compare_out[i] is 1, otherwise it is 0. S4.2: FFT algorithm: Implement the FFT algorithm and calculate the spectrum data. At this time, the comparison value output of i channels will be generated. The comparison output value is bitwise ORed to obtain the compare_bit_out signal. The detection is performed in frames. When the compare_bit_out signal value in a frame is 1, the frame is judged as leaving the template, and the sign_out signal value is "1". Otherwise, the frame is judged as entering the template, and the sign_out signal value is "0". S4.3: Number of points N: The number of points for FFT processing, which is set according to the length of the data frame. For example, if the data frame length is 1024 points, a 1024-point FFT calculation is performed; S4.4: Data format: The data format of the processing results should be adapted to the requirements of subsequent transmission and display (such as the format of the spectrum graph); S4.5: Performance test: Test the system's real-time processing capabilities and data transmission speed to ensure that the system can complete all processing tasks within the specified time.
[0010] Preferably, the Q1 is further expressed as: Q1.1: Dynamic pattern template: a template that is automatically generated or adjusted based on input data, such as adaptive filters, dynamic feature matching, etc. Q1.2: Composite pattern template: composed of multiple templates, used for complex matching tasks, such as multi-level feature extraction; Q1.3: Adaptability: The template should be able to adapt to different input changes, such as different lighting conditions, changes in viewing angle, etc. Q1.4: Template matching algorithm: Select or design appropriate algorithms, such as correlation matching, distance measurement, machine learning methods, etc.
[0011] Preferably, Q2 is further expressed as: Q2.1: Denoising filtering method: Use Gaussian filtering, median filtering or mean filtering to remove noise; Q2.2: Mean and variance standardization: Standardize the data to a mean of 0 and a variance of 1; Q2.3: Canny edge detection: detect edges through multi-level processing (smoothing, gradient calculation, non-maximum suppression, hysteresis threshold); Q2.4: Gray Level Co-occurrence Matrix (GLCM): Analyze the statistical characteristics of texture, such as contrast and correlation; Q2.5: IFT (Scale-Invariant Feature Transform): Extracts feature points and their descriptors from an image with scale invariance.
[0012] Preferably, Q3 is further expressed as: Q3.1: Overview of correlation matching: Calculate the correlation coefficient between the template and the input data area, and determine the matching position by the maximum correlation coefficient; Q3.2: Parallelization Algorithm level parallelization: Process different template matching tasks in parallel, such as processing multiple image regions at the same time; Q3.3: FPGA implementation: By designing a pipeline architecture, tasks at each stage are processed separately to reduce data processing delays and bottlenecks; Q3.4: Specific hardware units: Implement specialized hardware units to accelerate key computing tasks, such as accelerating convolution operations or correlation calculations; Q3.5: Tuning and iterative optimization: Adjust and optimize the design based on the test results to improve performance and resource usage.
[0013] Preferably, Q4 is further expressed as: Q4.1: Function and interface definition The functional requirements and interface definition of each module, including input and output signals, control signals, etc. Q4.2: Feature extraction module edge detection: implement edge detection algorithms (such as Sobel, Canny), using filters and gradient calculations; Q4.3: Optimize design: Use FPGA logic units to implement data processing and control functions to reduce the use of logic resources; Q4.4: DSP block multipliers and adders: Use DSP blocks in FPGA to perform efficient multiplication and addition operations to improve computing performance; Q4.5: Board-level testing: Testing on the FPGA development board to verify the performance of the design on actual hardware The present invention has the following beneficial effects: 1. The present invention determines the format and precision of the frequency template data through data types. For example, the data can be an integer, a fixed-point number, or a floating-point number, so that the operator can determine the format and precision of the data, which helps to optimize the use of FPGA resources and calculation accuracy. Selecting the appropriate data type (integer, fixed-point number, or floating-point number) can balance the calculation accuracy and hardware resource requirements, thereby improving the overall performance.
[0014] 2. The present invention uses dynamic pattern templates: templates automatically generated or adjusted according to input data, such as adaptive filters, dynamic feature matching, etc., which enable operators to automatically generate or adjust templates according to input data, thereby improving the system's adaptability in a constantly changing environment. For example, adaptive filters and dynamic feature matching can optimize templates in real time to cope with data changes.
[0015] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.
[0017] Figure 1 is a flowchart of the present invention; Figure 2 It is a flow chart of the present invention. DETAILED DESCRIPTION
[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0019] See also Figure 1 The present invention is a multi-mode template triggering method based on FPGA, comprising the following steps: S1: Frequency template storage module: The host computer configures the quantized frequency template data and stores it in BLOCKRAM. The frequency template data is divided into upper template data and lower template data; S2: Trigger module: For a frame of spectrum data with extra-long points, a multi-channel parallel processing method is adopted. Different template types are configured and selected, which are divided into upper template, lower template and upper and lower template. The configuration trigger mode type is divided into triggering within the template, triggering outside the template, triggering after leaving the template, triggering after entering the template, triggering after leaving the template and then entering the template, and triggering after entering the template and then leaving the template. A total of 18 triggers can be realized. After the configuration is completed, the template trigger is performed; S3: IQ data storage module: When a trigger occurs, the synchronized IQ data is saved. Depending on the trigger mode, the storage length of the data is different. Taking the upper and lower templates entering the template and then leaving the template trigger mode as an example, 3 frames of data length will be saved and the number of triggers will be recorded. IQ data can be selected in DDR or BLOCKRAM. When other trigger modes are triggered, the IQ data storage length will change; S4: FFT processing module and host computer module: re-analysis of IQ trigger data. After the trigger is completed, by configuring the trigger count value, the address where the trigger data is stored can be calculated, and the data can be read from the storage module and sent to the FFT module for processing. The FFT module performs FFT calculations of the corresponding number of points based on the length N of a frame of data, and the calculation results are transmitted to the host computer for processing and display of the spectrum diagram at the trigger time.
[0020] See also Figure 2 The present invention is a multi-mode template reanalysis method based on FPGA, comprising the following steps: Q1: Requirements Analysis and Design: Clarify the application scenarios and requirements of multi-modal template analysis. For example, template matching may be used in image recognition, signal processing, and other fields. Determine the template patterns to be used and their characteristics. These templates will be used to match the input data; Q2: Feature extraction: Preprocess the input data, such as denoising, normalization, etc., to improve matching accuracy and speed, and extract useful features from the input data and template. This can include edge detection, corner detection, texture analysis, etc. Q3: Template matching algorithm design: Select the appropriate template matching algorithm according to the application requirements. For example, commonly used algorithms include correlation matching, template matching, statistical matching, etc. According to the characteristics of FPGA, the algorithm is optimized to ensure efficient hardware implementation. Including algorithm parallelization, pipeline design, etc. Q4: FPGA design and implementation: Use HDL (such as Verilog or VHDL) to write the hardware description code of the template matching algorithm, and decompose the entire design into multiple modules, such as feature extraction module, matching module, control module, etc. Each module can be implemented independently in the FPGA, and hardware resources are allocated according to the resources of the FPGA (such as logic units, memory, DSP blocks, etc.) to optimize performance and power consumption.
[0021] S1 is further expressed as: S1.1: Data type: Determines the format and precision of the frequency mask data. For example, the data can be integer, fixed point, or floating point; S1.2: Storage requirements: Understand the storage size requirements, including the number of templates and the amount of data in each template; S1.3: Data structure: It may be necessary to design different storage structures for upper template data and lower template data respectively; S1.4: Data quantization: quantize the frequency mask data into data suitable for FPGA storage format. For example, convert floating point numbers into fixed point numbers; S1.5: Data transmission: The host computer transmits the quantized template data to the FPGA. The data transmission can be through a serial port, parallel interface or other communication protocols.
[0022] Role of data type: Determining the format and precision of data helps optimize FPGA resource usage and calculation accuracy. Choosing the right data type (integer, fixed-point number, or floating-point number) can balance calculation accuracy and hardware resource requirements, thereby improving overall performance. Role of storage requirements: Understanding storage requirements ensures that the FPGA has enough resources to store template data and avoid data overflow or insufficient storage. This helps design efficient memory management strategies to ensure stable system operation. Role of data structure: Designing a suitable storage structure (separating upper template from lower template data) can improve data access efficiency and processing speed. This makes data reading and writing more efficient, thereby optimizing overall algorithm performance. Role of data quantization: Quantizing data into data suitable for FPGA storage format can reduce storage requirements and computational complexity. Quantizing floating-point numbers into fixed-point numbers can significantly improve FPGA processing speed and reduce power consumption. Role of data transmission: Choosing the right data transmission method (serial port, parallel interface, etc.) affects the speed and reliability of data transmission. An effective data transmission mechanism can ensure that data between the host computer and the FPGA is accurately transmitted, ensuring the overall efficiency and stability of the system.
[0023] S2 is further expressed as: S2.1: Parallel processing: Due to the large amount of data, multi-path parallel processing is used to accelerate data analysis. Each parallel path processes a subset of spectrum data; S2.2: Data segmentation: The spectrum data of the ultra-long points is divided into multiple sub-blocks, each of which is processed by a processing unit; S2.3: Data receiving module: receives spectrum data of super-long points from a data source and distributes it to multiple processing units; S2.4: Trigger response: Execute corresponding response operations according to the trigger event, such as generating interrupts, updating status, etc.; S2.5: Real-time monitoring: In a real-time signal monitoring system, multi-channel parallel processing is used to analyze spectrum data and generate real-time responses based on configured triggering methods.
[0024] Parallel processing function: accelerate data analysis through multi-channel parallel processing, significantly improving processing speed and efficiency. Each parallel path processes different data subsets, which can effectively cope with large amounts of data and reduce processing time. Data segmentation function: splitting spectrum data of ultra-long points into multiple sub-blocks helps to distribute the processing load to multiple units, optimize resource utilization, and improve processing efficiency and response speed. Data receiving module function: responsible for receiving data from the data source and distributing it to the processing unit, ensuring that the data can be quickly and correctly transmitted to each processing unit, avoiding data bottlenecks and loss, and improving the smoothness of the overall system. Trigger response function: execute response operations (such as interrupts, status updates) according to trigger events, realize dynamic adjustment and timely feedback of the system, and improve the flexibility and real-time performance of the system. Real-time monitoring function: through multi-channel parallel processing and trigger mechanisms, real-time spectrum data analysis is carried out to ensure that the system can quickly respond to real-time signal changes and provide efficient real-time monitoring and data processing capabilities.
[0025] S3 is further expressed as: S3.1: Data caching: When a trigger event occurs, the synchronized IQ data is cached to the specified storage medium; S3.2: DDR storage implementation: Write IQ data into DDR and perform efficient data transmission through DMA controller or AXI interface; S3.3: Counter Design: Design a counter to record each trigger and store it in a specified register or memory location; S3.4: Storage optimization: Optimize the use of DDR or BRAM according to application requirements to balance storage capacity and access speed; S3.5: System maintenance: Monitor and maintain the data storage module and handle possible failures or performance issues.
[0026] Data caching role: When a trigger event occurs, the synchronized IQ data is cached to the specified storage medium to ensure that the data can be reliably stored and processed. This helps to avoid data loss and provide a stable data source for subsequent data processing. DDR storage implementation role: By writing IQ data to DDR (double data rate memory) and using DMA (direct memory access) controller or AXI (advanced extensible interface) interface for efficient data transmission, the data storage and reading speed is improved. This efficient data transmission method reduces the CPU burden and improves the overall system performance. Counter design role: The counter is designed to record the number of occurrences of each trigger event and store this information in a specified register or memory location. The counter provides statistical information about the occurrence of events, which helps the monitoring and analysis of the system and supports accurate tracking and subsequent processing of data. Storage optimization role: Optimize the use of DDR or BRAM (block RAM) according to specific application requirements to balance storage capacity and access speed. This optimization helps to improve data access efficiency, reduce storage bottlenecks, and ensure that the system maintains high performance when processing large-scale data. System maintenance role: Monitor and maintain data storage modules to handle possible failures or performance issues. System maintenance ensures the reliability and stability of the data storage module. Timely problem solving can prevent system crashes or data corruption and ensure long-term stable operation of the system.
[0027] S4 is further expressed as: S4.1: Calculation method: Calculate the starting address of the data in the storage module according to the number of triggers and the length of the data stored in each trigger; S4.2: FFT algorithm: implement FFT algorithm and calculate spectrum data; S4.3: Number of points N: The number of points for FFT processing, which is set according to the length of the data frame. For example, if the data frame length is 1024 points, a 1024-point FFT calculation is performed; S4.4: Data format: The data format of the processing results should be adapted to the requirements of subsequent transmission and display (such as the format of the spectrum graph); S4.5: Performance test: Test the system's real-time processing capabilities and data transmission speed to ensure that the system can complete all processing tasks within the specified time.
[0028] Function of calculation method: By calculating the starting address of data in the storage module, it ensures that data can be accurately read and managed, and supports efficient data retrieval and processing. Function of FFT algorithm: Implement FFT (Fast Fourier Transform) algorithm to calculate spectrum data, convert time domain signals into frequency domain signals, and reveal the frequency components in the data, which is crucial for signal analysis. Function of point number N: Determine the number of points for FFT processing (such as 1024 points) to ensure consistency with the data frame length, ensure the accuracy of spectrum calculation and data integrity. Function of data format: Adjust the data format of the processing results to adapt to subsequent transmission and display requirements, ensure that the spectrum data can be correctly displayed and further analyzed, and improve user experience. Function of performance testing: Test the system's real-time processing capability and data transmission speed, ensure that the system completes all processing tasks within the specified time, and verify that the system performance meets the design requirements.
[0029] Q1 is further expressed as: Q1.1: Dynamic pattern template: a template that is automatically generated or adjusted based on input data, such as adaptive filters, dynamic feature matching, etc. Q1.2: Composite pattern template: composed of multiple templates, used for complex matching tasks, such as multi-level feature extraction; Q1.3: Adaptability: The template should be able to adapt to different input changes, such as different lighting conditions, changes in viewing angle, etc. Q1.4: Template matching algorithm: Select or design appropriate algorithms, such as correlation matching, distance measurement, machine learning methods, etc.
[0030] The role of dynamic pattern templates: automatically generate or adjust templates according to input data to improve the system's adaptability in a changing environment. For example, adaptive filters and dynamic feature matching can optimize templates in real time to cope with data changes. The role of composite pattern templates: by combining multiple templates to handle complex matching tasks and multi-level feature extraction, the system's recognition ability and accuracy for complex patterns are enhanced. The role of adaptability: ensure that the template can adapt to different input changes (such as changes in lighting and viewing angle), improve the robustness and versatility of the system, and enable it to maintain stable performance under various conditions. The role of template matching algorithm: select or design appropriate algorithms (such as correlation matching, distance measurement, machine learning methods), improve the accuracy and efficiency of template matching, and ensure that the system can accurately identify and process input data.
[0031] Q2 is further expressed as: Q2.1: Denoising filtering method: Use Gaussian filtering, median filtering or mean filtering to remove noise; Q2.2: Mean and variance standardization: Standardize the data to a mean of 0 and a variance of 1; Q2.3: Canny edge detection: detect edges through multi-level processing (smoothing, gradient calculation, non-maximum suppression, hysteresis threshold); Q2.4: Gray Level Co-occurrence Matrix (GLCM): Analyze the statistical characteristics of texture, such as contrast and correlation; Q2.5: IFT (Scale-Invariant Feature Transform): Extracts feature points and their descriptors from an image with scale invariance.
[0032] The role of denoising filtering method: Use Gaussian filtering, median filtering or mean filtering to remove noise from the image, improve image quality, and make subsequent processing and analysis more accurate. The role of mean and variance standardization: Standardize the data with a mean of 0 and a variance of 1 to ensure that the data is analyzed at the same scale, increase the training effect and stability of the model, the role of Canny edge detection: Detect edges in the image through multi-level processing steps, identify and locate image contours, and help extract important structural information of the image, the role of gray-level co-occurrence matrix: Analyze the texture features of the image (such as contrast and correlation), provide statistical characteristics of the image, and enhance the understanding of the image content and feature description, the role of IFT (scale-invariant feature transform): Extract feature points and their descriptors in the image, with scale invariance, so that image features can still be recognized at different scales, and enhance the robustness of feature matching.
[0033] Q3 is further expressed as: Q3.1: Overview of correlation matching: Calculate the correlation coefficient between the template and the input data area, and determine the matching position by the maximum correlation coefficient; Q3.2: Parallelization Algorithm level parallelization: Process different template matching tasks in parallel, such as processing multiple image regions at the same time; Q3.3: FPGA implementation: By designing a pipeline architecture, tasks at each stage are processed separately to reduce data processing delays and bottlenecks; Q3.4: Specific hardware units: Implement specialized hardware units to accelerate key computing tasks, such as accelerating convolution operations or correlation calculations; Q3.5: Tuning and iterative optimization: Adjust and optimize the design based on the test results to improve performance and resource usage.
[0034] Correlation matching overview Role: Determine the matching position by calculating the correlation coefficient between the template and the input data area. The maximum correlation coefficient indicates the best matching position between the template and the input data area. It is widely used in image matching and target detection. Parallelization algorithm level Parallelization role: Process different template matching tasks in parallel to improve processing efficiency. For example, processing multiple image areas at the same time can significantly reduce processing time and enhance the overall performance and response speed of the system. FPGA implementation role: By designing a pipeline architecture, tasks at each stage are processed separately on the FPGA (field programmable gate array) to reduce data processing delays and bottlenecks. The parallel processing capability of FPGA can accelerate the template matching process and improve system throughput and real-time performance. Specific hardware unit role: Implement specialized hardware units (such as accelerators) to accelerate key computing tasks (such as convolution operations or correlation calculations). Specialized hardware design can significantly increase computing speed, reduce processing time, and improve overall system performance. Tuning Iterative optimization role: Adjust and optimize the design based on test results to improve performance and resource usage. The iterative optimization process can improve the efficiency and stability of the system and ensure that the system achieves optimal performance in actual applications.
[0035] Q4 is further expressed as: Q4.1: Function and interface definition The functional requirements and interface definition of each module, including input and output signals, control signals, etc. Q4.2: Feature extraction module edge detection: implement edge detection algorithms (such as Sobel, Canny), using filters and gradient calculations; Q4.3: Optimize design: Use FPGA logic units to implement data processing and control functions to reduce the use of logic resources; Q4.4: DSP block multipliers and adders: Use DSP blocks in FPGA to perform efficient multiplication and addition operations to improve computing performance; Q4.5: Board-level testing: Test on the FPGA development board to verify the performance of the design on actual hardware.
[0036] Function and interface definition: clarify the functional requirements and interface definitions of each module, ensure correct data exchange and control signal transmission between modules, and promote the overall coordination and integration of the system. Edge detection function of feature extraction module: implement edge detection algorithms (such as Sobel, Canny), extract edge information in the image through filters and gradient calculations, and help identify and analyze image features. Optimization design function: use the logic unit of FPGA to optimize data processing and control functions, reduce the occupation of logic resources, and improve system efficiency and resource utilization. DSP block multiplier and adder function: use the DSP block in FPGA to perform efficient multiplication and addition operations, improve computing performance, shorten processing time, and is suitable for computing tasks that require high throughput. Board-level testing function: perform actual hardware testing on the FPGA development board to verify the performance of the design in a real environment and ensure that the design meets the requirements and can run stably.
[0037] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0038] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A multi-mode template triggering method based on FPGA, characterized in that: The following steps are involved: S1: Frequency template storage module: The host computer configures the quantized frequency template data and stores it in BLOCKRAM. The frequency template data is divided into upper template data and lower template data; S2: Trigger module: For a frame of spectrum data with extra-long points, a multi-channel parallel processing method is adopted. Different template types are configured and selected, which are divided into upper template, lower template and upper and lower template. The configuration trigger mode type is divided into triggering within the template, triggering outside the template, triggering after leaving the template, triggering after entering the template, triggering after leaving the template and then entering the template, and triggering after entering the template and then leaving the template. A total of 18 triggers can be realized. After the configuration is completed, the template trigger is performed; S3: IQ data storage module: When a trigger occurs, the synchronized IQ data is saved. Depending on the trigger mode, the storage length of the data is different. Taking the upper and lower templates entering the template and then leaving the template trigger mode as an example, 3 frames of data length will be saved and the number of triggers will be recorded. IQ data can be selected in DDR or BLOCKRAM. When other trigger modes are triggered, the IQ data storage length will change; S4: FFT processing module and host computer module: re-analysis of IQ trigger data. After the trigger is completed, by configuring the trigger count value, the address where the trigger data is stored can be calculated, and the data can be read from the storage module and sent to the FFT module for processing. The FFT module performs FFT calculations of the corresponding number of points based on the length N of a frame of data, and the calculation results are transmitted to the host computer for processing and display of the spectrum diagram at the trigger time.
2. A multi-mode template analysis method based on FPGA, characterized in that: The following steps are involved: Q1: Requirements Analysis and Design: Clarify the application scenarios and requirements of multi-modal template analysis. For example, template matching may be used in image recognition, signal processing, and other fields. Determine the template patterns to be used and their characteristics. These templates will be used to match the input data; Q2: Feature extraction: Preprocess the input data, such as denoising, normalization, etc., to improve matching accuracy and speed, and extract useful features from the input data and template. This can include edge detection, corner detection, texture analysis, etc. Q3: Template matching algorithm design: Select the appropriate template matching algorithm according to the application requirements. For example, commonly used algorithms include correlation matching, template matching, statistical matching, etc. According to the characteristics of FPGA, the algorithm is optimized to ensure efficient hardware implementation. Including algorithm parallelization, pipeline design, etc. Q4: FPGA design and implementation: Use HDL (such as Verilog or VHDL) to write the hardware description code of the template matching algorithm, and decompose the entire design into multiple modules, such as feature extraction module, matching module, control module, etc. Each module can be implemented independently in the FPGA, and hardware resources are allocated according to the resources of the FPGA (such as logic units, memory, DSP blocks, etc.) to optimize performance and power consumption.
3. The FPGA-based multi-mode template triggering and re-analysis method according to claim 1, characterized in that: The S1 is further expressed as: S1.1: Data type: Determines the format and precision of the frequency mask data. For example, the data can be integer, fixed point, or floating point; S1.2: Storage requirements: Understand the storage size requirements, including the number of templates and the amount of data in each template; S1.3: Data structure: It may be necessary to design different storage structures for upper template data and lower template data respectively; S1.4: Data quantization: quantize the frequency mask data into data suitable for FPGA storage format. For example, convert floating point numbers into fixed point numbers; S1.5: Data transmission: The host computer transmits the quantized template data to the FPGA. The data transmission can be through a serial port, parallel interface or other communication protocols.
4. The FPGA-based multi-mode template triggering and re-analysis method according to claim 1, characterized in that: The S2 is further expressed as: S2.1: Parallel processing: Due to the large amount of data, multi-path parallel processing is used to accelerate data analysis. Each parallel path processes a subset of spectrum data; S2.2: Data segmentation: The spectrum data of the ultra-long points is divided into multiple sub-blocks, each of which is processed by a processing unit; S2.3: Data receiving module: receives spectrum data of ultra-long points from a data source and distributes it to multiple processing units; S2.4: Trigger response: Execute corresponding response operations according to the trigger event, such as generating interrupts, updating status, etc.; S2.5: Real-time monitoring: In a real-time signal monitoring system, multi-channel parallel processing is used to analyze spectrum data and generate real-time responses based on configured triggering methods.
5. The FPGA-based multi-mode template triggering and re-analysis method according to claim 1, characterized in that: The S3 is further expressed as: S3.1: Data caching: When a trigger event occurs, the synchronized IQ data is cached to the specified storage medium; S3.2: DDR storage implementation: Write IQ data into DDR and perform efficient data transmission through DMA controller or AXI interface; S3.3: Counter Design: Design a counter to record each trigger and store it in a specified register or memory location; S3.4: Storage optimization: Optimize the use of DDR or BRAM according to application requirements to balance storage capacity and access speed; S3.5: System maintenance: Monitor and maintain the data storage module and handle possible failures or performance issues.
6. The FPGA-based multi-mode template triggering and re-analysis method according to claim 1, characterized in that: The S4 is further expressed as: S4.1: Calculation method: Calculate the starting address of the data in the storage module according to the number of triggers and the length of the data stored in each trigger; S4.2: FFT algorithm: implement FFT algorithm and calculate spectrum data; S4.3: Number of points N: The number of points for FFT processing, which is set according to the length of the data frame. For example, if the data frame length is 1024 points, a 1024-point FFT calculation is performed; S4.4: Data format: The data format of the processing results should be adapted to the requirements of subsequent transmission and display (such as the format of the spectrum graph); S4.5: Performance test: Test the system's real-time processing capabilities and data transmission speed to ensure that the system can complete all processing tasks within the specified time.
7. The FPGA-based multi-mode template triggering and re-analysis method according to claim 2, characterized in that: The Q1 is further expressed as: Q1.1: Dynamic pattern template: a template that is automatically generated or adjusted based on input data, such as adaptive filters, dynamic feature matching, etc. Q1.2: Composite pattern template: composed of multiple templates, used for complex matching tasks, such as multi-level feature extraction; Q1.3: Adaptability: The template should be able to adapt to different input changes, such as different lighting conditions, changes in viewing angle, etc. Q1.4: Template matching algorithm: Select or design appropriate algorithms, such as correlation matching, distance measurement, machine learning methods, etc.
8. The FPGA-based multi-mode template triggering and re-analysis method according to claim 2, characterized in that: The Q2 is further expressed as: Q2.1: Denoising filtering method: Use Gaussian filtering, median filtering or mean filtering to remove noise; Q2.2: Mean and variance standardization: Standardize the data to a mean of 0 and a variance of 1; Q2.3: Canny edge detection: detect edges through multi-level processing (smoothing, gradient calculation, non-maximum suppression, hysteresis threshold); Q2.4: Gray Level Co-occurrence Matrix (GLCM): Analyze the statistical characteristics of texture, such as contrast and correlation; Q2.5: IFT (Scale-Invariant Feature Transform): Extracts feature points and their descriptors from an image with scale invariance.
9. The FPGA-based multi-mode template triggering and re-analysis method according to claim 2, characterized in that: The Q3 is further expressed as: Q3.1: Overview of correlation matching: Calculate the correlation coefficient between the template and the input data area, and determine the matching position by the maximum correlation coefficient; Q3.2: Parallelization Algorithm level parallelization: Process different template matching tasks in parallel, such as processing multiple image regions at the same time; Q3.3: FPGA implementation: By designing a pipeline architecture, tasks at each stage are processed separately to reduce data processing delays and bottlenecks; Q3.4: Specific hardware units: Implement specialized hardware units to accelerate key computing tasks, such as accelerating convolution operations or correlation calculations; Q3.5: Tuning and iterative optimization: Adjust and optimize the design based on the test results to improve performance and resource usage.
10. The FPGA-based multi-mode template triggering and re-analysis method according to claim 2, characterized in that: The Q4 is further expressed as: Q4.1: Function and interface definition The functional requirements and interface definition of each module, including input and output signals, control signals, etc. Q4.2: Feature extraction module edge detection: implement edge detection algorithms (such as Sobel, Canny), using filters and gradient calculations; Q4.3: Optimize design: Use FPGA logic units to implement data processing and control functions to reduce the use of logic resources; Q4.4: DSP block multipliers and adders: Use DSP blocks in FPGA to perform efficient multiplication and addition operations to improve computing performance; Q4.5: Board-level testing: Test on the FPGA development board to verify the performance of the design on actual hardware.