A timing circuit and method applicable to multi-physical quantity observation of rock friction experiments

Abstract

The present invention discloses a timing circuit and method applicable to multi-physical quantity observation in rock friction experiments. The GPS signal receiving, transforming and transmitting module transforms the received GPS clock signal and transmits it to the computer terminal. The power supply module receives the 5V power supply from the USB port and transforms it into positive and negative power supplies for the analog part of the circuit. The timing processing module performs timed on-off operations on the GPS timing signal and the analog timing square wave pulse sent by the entire circuit according to the timing function set by the user. The synchronous analog timing pulse square wave generating module synchronously generates a full-power low-voltage analog timing pulse square wave according to the GPS timing signal and supplies it to different types of physical quantity sampling devices. The present invention can monitor and modify in real time the absolute time of the computer system that records short-term signals of different types of physical quantities, enabling multiple computer recording systems to perform absolute time alignment at the millisecond level during long-term operation.

Description

Technical Field

[0001] The present invention relates to the technical field of simulating the indoor earthquake occurrence process, and particularly to a timing circuit and method applicable to multi-physical quantity observation in rock friction experiments. Background Art

[0002] Rock friction experiment is one of the important research means for simulating the indoor earthquake occurrence process. During the experiment, the rock is deformed under force and then fault displacement occurs. In this process, the rock will generate deformation signals, acoustic emission signals, temperature changes, etc., which can reflect the precursor information before the rock fault displacement (i.e., indoor earthquake simulation). These multi-physical quantity signals reflecting precursor information usually need to be continuously monitored by different computer recording systems. Previous studies have shown that the time when the precursor critical information in indoor earthquake experiments appears is very short, usually at the millisecond level. And due to the running time error of multiple computer recording systems themselves, after a long time of operation, multiple computers will have an accumulated time difference of more than one second or even at the minute level in absolute time; in addition, due to the different signal bandwidth ranges of various physical quantity precursor signals, the sampling rates of the sampling devices used are quite different (ranging from 1 kHz to the MHz level). This makes the sampling clock difference of the critical marks of the digitized multi-physical quantity precursor signals naturally exist at least at the level of dozens of milliseconds. For the above two reasons, the accumulated time difference will lead to a high probability of misjudgment when researchers combine the critical marks of different types of physical quantity precursor information in the later data analysis for the short-term and impending earthquake prediction of rock friction experiments.

[0003] In view of the above problems, the present invention provides a timing circuit and method applicable to multi-physical quantity observation in rock friction experiments, which can improve the success probability of short-term and impending earthquake prediction in indoor earthquake simulation experiments. Summary of the Invention

[0004] The present invention provides a timing circuit and method applicable to multi-physical quantity observation in rock friction experiments, which can improve the success probability of short-term and impending earthquake prediction in indoor earthquake simulation experiments.

[0005] The object of the present invention is to provide a timing circuit applicable to multi-physical quantity observation in rock friction experiments, including a GPS signal receiving, transforming and transmitting module, a power supply module, a timing processing module, and a synchronous analog timing pulse square wave generating module circuit. The synchronous analog timing pulse square wave generating module circuit, the power supply module, and the timing processing module are all connected to the GPS signal transforming and transmitting module.

[0006] Furthermore, the GPS signal receiving, transforming and transmitting module includes the signal interface P7 of the GPS receiving module, the output second pulse signal level adjustment and enhancement circuit, and the execution module of the system timing processing module. The 3rd pin of the signal interface P7 of the GPS receiving module is the TXD data transmission signal of the RS232 interface, which is connected in series with the resistor R33 and then connected to the 3rd pin of the DB9-pin interface J1. The 4th pin of the signal interface P7 of the GPS receiving module is the RXD data receiving signal of the RS232 interface, which is connected in series with the resistor R32 and then connected to the 3rd pin of the DB9-pin interface J1. The resistors R32 and R33 are used for overcurrent protection of the TXD and RXD lines. The 5th pin of the signal interface P7 of the GPS receiving module is the VCC power supply pin, which is connected to the 5V external input power supply VCC5 of the circuit. At the same time, the 5th pin is connected to the cathode of the voltage stabilizing diode D5. The 5th, 10th, and 11th pins of J1 are connected to the system ground AGND. The 2nd and 3rd pins of J1 are connected to the TXD and RXD signals respectively, and are connected to the bidirectional TVS diodes D6 and D7 to the ground respectively. The 6th pin of J1 is connected to the 9th pin of the Max1 chip to output a pulse. The 2nd pin of the Max1 chip is connected to the capacitor C55, and the 2nd pin of the capacitor C55 is connected to the 3rd pin of the Max1 chip. The 2nd pin of the Max chip is connected to the capacitor C56, and the 2nd pin of the capacitor C56 is connected to the 5th pin of the Max chip. The 6th pin of the Max1 chip is connected to the 1st pin of the capacitor C58, and the 2nd pin of the capacitor C58 is connected to the system ground AGND. The 16th pin of the Max chip is connected with the capacitors C53 and C54, and serves as the power supply bypass and decoupling capacitors of the Max1 chip. The 15th pin of the Max1 chip is connected to the system ground AGND.

[0007] Furthermore, the execution module of the system timing processing module includes the resistor R35, the resistor R36, the triode Q4, the diode D8, and the relay P8. The 2nd pin of the relay P8 is connected to the 1st pin of the signal interface P7 of the GPS receiving module. The resistor R35 is connected to the base of the triode Q4. The resistor R36 is connected to the resistor R35 and at the same time connected to the base of the triode Q4 and then connected to the system ground. The resistors R35 and R36 form a voltage dividing circuit and divide the 3.3V level timing output signal PWM_Time of the system timing processing module into about 2.7V. The emitter of the triode Q4 is connected to the system ground, and the collector is connected to the 8th pin of the relay P8. The 1st pin of the relay P8 is the power supply pin and is connected to the external input 5V power supply VCC5. The cathode of the diode D8 is connected to the 1st pin of the relay P8, and the anode is connected to the 8th pin of the relay P8. The 3rd pin of the relay P8 is connected to the Pluse2 signal.

[0008] Further, the output second pulse signal level adjustment and enhancement circuit includes resistor R29, resistor R30, resistor R25, triode Q2, resistor R27, resistor R31, resistor R26, triode Q3, capacitor C50, capacitor C51, USB2 interface and resistor R25. Resistor R29, resistor R30, resistor R25 and triode Q2 form the output second pulse signal level conversion and inversion circuit of the GPS receiving module. The 1st pin of resistor R29 is connected to the Pluse2 signal and connected to the 3rd pin of relay P8. The 2nd pin of resistor R29 is connected to the 1st pin of resistor R30 and simultaneously connected to the base of triode Q2. The 2nd pin of resistor R30 is connected to the system ground. The emitter of triode Q2 is connected to the system ground. The collector of triode Q2 is connected to the 1st pin of resistor R25. The 2nd pin of resistor R25 is externally connected to the input 5V power supply VCC5. The collector of triode Q2 simultaneously outputs the inverted 5V pulse Ready signal and is connected to the 8th pin of the Max1 chip. A resistor R34 is connected in series between the 9th pin of the Max1 chip and the 6th pin of J1. The collector of triode Q2 is simultaneously connected to the 1st pin of resistor R27. The 2nd pin of resistor R27 is connected to the 1st pin of resistor R31 and the base of triode Q3. The emitter of triode Q3 is connected to the system ground. The collector is connected to the 1st pin of resistor R26. The 2nd pin of resistor R26 is connected to the external input 5V power supply VCC5. Capacitor C5 and capacitor C51 are connected in parallel as bypass decoupling capacitors. The 4th pin of the USB2 interface is connected to the system ground AGND. The 5th pin of USB2 is the connection pin for the technical shell of the interface. Resistor R28 and high-voltage capacitor C52 are connected in parallel and then connected to the 5th pin and also connected to the system ground.

[0009] Further, the synchronous analog timing pulse square wave generation module circuit includes a voltage follower, operational amplifier AD3, a first RC filter circuit, a second RC filter circuit, a third RC filter circuit, and a subtraction circuit. The voltage follower consists of resistor R42, resistor R40, and operational amplifier AD3. The 1-foot of resistor R42 is connected to the 2-foot of operational amplifier AD3, and the 2-foot of resistor R42 is connected to the 6-foot of operational amplifier AD3. The 3-foot of AD3 is connected to the SYN_Time signal sent by the GPS signal receiving, transforming, and transmitting module. At the same time, the 3-foot is connected to the 1-foot of resistor R40, and the 2-foot of resistor R40 is grounded. The 4-foot of operational amplifier AD3 is connected to the 1-foot of bead R41. The 1-foot of bead R41 is connected to the negative 5V analog power supply and the 4-foot of operational amplifier AD3 at the same time. The 2-foot of bead R41 is connected to the 1-foot of capacitor C63, capacitor C64, and capacitor C65. The 2-feet of the capacitor C63, capacitor C64, and capacitor C65 are connected to the system ground. The first RC filter circuit includes resistor R41, capacitor C63, capacitor C64, and capacitor C65 to filter out the high-frequency noise of the negative 5V analog power supply. The 7-foot of operational amplifier AD3 is connected to the 1-foot of bead R43. The 1-foot of bead R43 is connected to the positive 5V analog power supply at the same time. The 2-foot of bead R43 is connected to the 1-foot of capacitor C60, capacitor C61, and capacitor C62. The 2-feet of capacitor C60, capacitor C61, and capacitor C62 are connected to the system ground. Resistor R43, capacitor C60, capacitor C61, and capacitor C62 form a second RC filter circuit to filter out the high-frequency noise of the positive 5V analog power supply. The 6-foot of operational amplifier AD3 is connected to the 1-foot of resistor R44.

[0010] Further, the subtraction circuit includes resistor R46, resistor R47, resistor R49, resistor R50, adjustable resistor R45, and operational amplifier AD4. The 1-foot of adjustable resistor R45 is connected to the 2-foot of bead R48. The 2-foot of resistor R48 is connected to the 5V analog power supply AVCC5. The 3-foot of adjustable resistor R45 is connected to the 2-foot of bead R52. The 1-foot of bead R52 is connected to the negative 5V analog power supply AVSS5. The 2-foot of resistor R45 is connected to the 1-foot of resistor R46. The 2-foot of resistor R46 is connected to the 1-foot of resistor R47 and the 2-foot of operational amplifier AD4. The 2-foot of resistor R47, the 2-foot of resistor R46 is connected to the 1-foot of resistor R47 and the 2-foot of operational amplifier AD4. The 2-foot of resistor R47 is connected to the output of the 6-foot of operational amplifier AD. The 1-foot of resistor R49 is connected to the system ground AGND, and the 2-foot is connected to the 3-foot of operational amplifier AD4 and the 1-foot of resistor R50. The 2-foot of resistor R50 is connected to the 3-foot of resistor R44 to receive the output signal of operational amplifier AD3. The 6-foot of operational amplifier AD4 is connected to the 1-foot of resistor R51. The 2-foot of resistor R51 is connected to the 1-foot of P11 interface BNG output. The 2-foot of the P11 interface BNG is grounded. The 4-foot of operational amplifier AD4 is connected to bead R52 and the negative 5V analog power supply AVSS5. The 2-foot of bead R52 is connected to the 1-foot of capacitor C66, capacitor C67, and capacitor C68. The 2-feet of capacitor C66, capacitor C67, and capacitor C68 are all connected to the system ground.

[0011] Further, the second RC filter circuit includes a resistor R62, capacitors C66, C67, and C68, and is used to filter out high-frequency noise of the -5V analog power supply. The 7th pin of the operational amplifier AD is connected to the 1st pin of the bead R48 and connected to the -5V analog power supply. The 2nd pin of the bead R48 is connected to the 1st pins of capacitors C69, C70, and C71. The 2nd pins of the capacitors C69, C70, and C71 are all connected to the system ground. The third RC filter circuit includes a resistor RC48, capacitors C69, and C71 and is used to filter out high-frequency noise of the +5V analog power supply.

[0012] Further, the timing module includes a clock oscillation circuit and an STM1 chip. The clock oscillation circuit includes capacitors C72, C73, and a passive crystal oscillator Y1. The 1st pin of the capacitor C72 is grounded, the 1st pin of the capacitor C73 is grounded, the 2nd pin of the capacitor C72 is connected to the 1st pin of the passive crystal oscillator Y1, the 2nd pin of the capacitor C73 is connected to the 2nd pin of the passive crystal oscillator Y1. The 1st pin of the passive crystal oscillator is connected to the 5th pin of the STM1 chip, the 2nd pin of the passive crystal oscillator Y1 is connected to the 6th pin of the STM1 chip. The 7th pin of the STM1 chip is connected to the 1st pin of the capacitor C74, the 2nd pin of the capacitor C74 is grounded. The 8th, 23rd, 35th, and 47th pins of the STM1 chip are grounded. The 1st, 9th, 24th, 36th, and 48th pins of the STM1 chip are connected to the 3.3V power supply of the circuit system. The 20th pin of the STM1 chip is connected to the 1st pin of the resistor R54, the 2nd pin of the resistor R54 is grounded. The 44th pin of the STM1 chip is connected to the 1st pin of the resistor R53, the 2nd pin of the resistor R53 is grounded. The 22nd pin of the STM1 chip is connected to the 1st pin of the capacitor C75, the 2nd pin of the capacitor C75 is grounded. The 16th pin of the STM1 chip outputs a PWM_time signal and is connected to the 1st pin of the resistor R35, and controls the on / off of the P8 relay.

[0013] Further, the power supply module includes an AX1 chip, an AX2 chip, an AX3 chip, and an XL1 chip. The 3rd pin of the AX1 chip is connected in parallel with capacitor C76 and capacitor C77 as the input filter capacitor of the AX1 chip. The 2nd pin of the AX1 chip is connected in parallel with capacitor C78 and capacitor C79 as the output filter capacitor of the AX1 chip. The 1st pin and the 2nd pin of the XL1 chip are commonly connected to the external input 5V power supply VCC5 for power supply. The feedback pin of the 3rd pin of the XL1 chip is connected to the 1st pin of resistor R55. The 2nd pin of resistor R55 is connected to GND, which is the 7th pin and the 8th pin of the XL chip. The 3rd pin of the XL1 chip is also connected to the 1st pin of resistor R56. The 2nd pin of resistor R56 is connected to the cathode of diode D6. The 7th pin and the 8th pin of the XL chip are short-circuited to its working ground GND and resistor R57. The 5th pin and the 6th pin of the XLI chip are combined and connected to the 1st pin of power inductor L2. The 2nd pin of power inductor L2 is connected to the VCC5 power supply. The 5th pin and the 6th pin of the XL1 chip are connected to the cathode of diode D6 and also connected to the 1st pin of capacitor C80. The 2nd pin of capacitor C80 is connected to the anode of diode D7 and also connected to the cathode of diode D8 at the same time. The cathode of diode D7 is connected to the 1st pin of capacitor C82 and the 2nd pin of capacitor C81 and connected to the working ground GND at the same time. The 1st pin of capacitor C81 is connected to the cathode of diode D6. The 2nd pin of capacitor C82 is connected to the anode of diode D8. The 3rd pin input of the AX2 chip is connected to the cathode of diode D6. The 3rd pin of the AX2 chip is connected in parallel with capacitor C83 and capacitor C84 as the input filter capacitor of the AX2 chip. The 2nd pin of the AX2 chip is connected in parallel with capacitor C85 and capacitor C86 as the output filter capacitor of the AX2 chip. The 2nd pin input of the AX3 chip is connected to the anode of diode D8. The 2nd pin of the AX3 chip is connected in parallel with capacitor C87 and capacitor C88 as the input filter capacitor of the AX3 chip. The 3rd pin of the AX3 chip is connected in parallel with capacitor C89 and capacitor C90 as the output filter capacitor of the AX3 chip.

[0014] A method suitable for observing multiple physical quantities in rock friction experiments. The specific steps of the method are as follows:

[0015] Step 1: After power-on, the GPS receiving module connected to the P7 interface starts to receive the GPS timing signal and generates a 3.3V second pulse PPS signal. At the same time, the P7 port outputs the TXD signal to the RS232 interface of J1. The computer connected to J1 receives the message information sent on the TXD line through its own RS232 interface and parses the GPS time. The computer also receives the data ready signal of the 6th pin of the J1 port through the upper computer timing processing software. If there is a data ready signal, the computer decides whether the current computer system time needs to be modified according to the parsed GPS time. If so, it is modified to the parsed GPS time. Multiple computers simultaneously modify their respective system times through their own upper computer timing processing software so that their respective system times can be calibrated at the second level.

[0016] Step 2: The timing circuit processes the synchronous low-voltage analog pulse signal output from port P11 and connects it to the input ports of different physical quantity sampling devices connected to each computer. The synchronous low-voltage analog pulse signal with consistent sampling amplitude from each sampling device is written into a data file together with the sampled physical quantity. This data file can be used to calibrate the absolute time of different physical quantity signals at the millisecond level during subsequent data analysis using the respective synchronous low-voltage analog pulse signals. At this point, the timing calibration process for the multi-physical quantity observation of the entire rock friction experiment is completed.

[0017] Step 3, the timing processing module of the timing circuit is responsible for shutting off the 6-pin data ready signal of the J1 port and the synchronous low-voltage analog pulse signal output by the P11 port for 5 seconds after the user-written timing time is reached. After that, if the computer system does not receive the 6-pin data ready signal, the system time will not be modified. After the 5-second shutdown time, the timing processing module of the timing circuit reconnects the 6-pin data ready signal of the J1 port and the synchronous low-voltage analog pulse signal output by the P11 port;

[0018] Step 4: The entire 5-second off time window can be used as a starting window for absolute time calibration during subsequent analysis of data files of different types of physical quantity signals.

[0019] The present invention has the following advantages: the circuit used in the present invention can output a low-voltage analog pulse signal synchronized with the trigger signal received by the host computer timing processing software for recognition by multiple physical quantity observation, recording and sampling systems, and its output impedance is low enough to make the amplitude of the low-voltage analog pulse signal collected by each sampling system consistent, making it convenient for researchers to use this signal to perform time calibration on the physical quantities recorded by different recording systems in the future.

[0020] The present invention can be applied to the absolute time calibration of various short-term marker signals at the millisecond time level in the observation of multiple physical quantities in rock friction experiments. The entire process is realized only by using GPS signals. In conjunction with the host computer timing processing software, the clock of the recording computer system can be automatically adjusted without human intervention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a circuit diagram of the GPS signal receiving, transforming and transmitting module of the present invention;

[0022] Figure 2 This is a circuit diagram of a synchronous analog timing pulse square wave generating module of the present invention;

[0023] Figure 3 This is a circuit diagram of a timing processing module of the present invention;

[0024] Figure 4 This is the circuit diagram of the power supply module of the present invention. DETAILED DESCRIPTION

[0025] The present invention provides a timing circuit applicable to multi - physical quantity observation in rock friction experiments, including a GPS signal receiving, transforming and transmitting module, a power supply module, a timing processing module, and a synchronous analog timing pulse square - wave generating module circuit. The synchronous analog timing pulse square - wave generating module circuit, the power supply module, and the timing processing module are all connected to the GPS signal transforming and transmitting module.

[0026] In this embodiment, the GPS signal receiving, transforming and transmitting module includes the signal interface P7 of the GPS receiving module, an output second - pulse signal level adjustment and enhancement circuit, and an execution module of the system timing processing module. The 3rd pin of the signal interface P7 of the GPS receiving module is the TXD data transmission signal of the RS232 interface, which is connected in series with the resistor R33 and then connected to the 3rd pin of the DB9 - pin interface J1. The 4th pin of the signal interface P7 of the GPS receiving module is the RXD data receiving signal of the RS232 interface, which is connected in series with the resistor R32 and then connected to the 3rd pin of the DB9 - pin interface J1. The resistors R32 and R33 are used for over - current protection of the TXD and RXD lines. The 5th pin of the signal interface P7 of the GPS receiving module is the VCC power supply pin, connected to the 5V external input power supply VCC5 of the circuit. At the same time, the 5th pin is connected to the cathode of the voltage - stabilizing diode D5. The 5th, 10th, and 11th pins of J1 are connected to the system ground AGND. The 2nd and 3rd pins of J1 are connected to the TXD and RXD signals and are respectively connected to the bidirectional TVS tubes D6 and D7 to the ground. The 6th pin of J1 is connected to the 9th - pin output pulse of the Max1 chip. The 2nd pin of the Max1 chip is connected to the capacitor C55, and the 2nd pin of the capacitor C55 is connected to the 3rd pin of the Max1 chip. The 2nd pin of the Max chip is connected to the capacitor C56, and the 2nd pin of the capacitor C56 is connected to the 5th pin of the Max chip. The 6th pin of the Max1 chip is connected to the 1st pin of the capacitor C58, and the 2nd pin of the capacitor C58 is connected to the system ground AGND. The 16th pin of the Max chip is connected with the capacitors C53 and C54 and serves as the power supply bypass and decoupling capacitors of the Max1 chip. The 15th pin of the Max1 chip is connected to the system ground AGND.

[0027] In this embodiment, the execution module of the system timing processing module includes the resistor R35, the resistor R36, the triode Q4, the diode D8, and the relay P8. The 2nd pin of the relay P8 is connected to the 1st pin of the signal interface P7 of the GPS receiving module. The resistor R35 is connected to the base of the triode Q4. The resistor R36 is connected to the resistor R35 and also connected to the base of the triode Q4 and then connected to the system ground. The resistors R35 and R36 form a voltage - dividing circuit and divide the 3.3V level timing output signal PWM_Time of the system timing processing module to about 2.7V. The emitter of the triode Q4 is connected to the system ground, and the collector is connected to the 8th pin of the relay P8. The 1st pin of the relay P8 is the power supply pin, connected to the external input 5V power supply VCC5. The cathode of the diode D8 is connected to the 1st pin of the relay P8, and the anode is connected to the 8th pin of the relay P8. The 3rd pin of the relay P8 is connected to the Pluse2 signal.

[0028] In this embodiment, the output second pulse signal level adjustment and enhancement circuit includes resistor R29, resistor R30, resistor R25, triode Q2, resistor R27, resistor R31, resistor R26, triode Q3, capacitor C50, capacitor C51, USB2 interface and resistor R25. Resistor R29, resistor R30, resistor R25 and triode Q2 form the output second pulse signal level conversion and inversion circuit of the GPS receiving module. The pin 1 of resistor R29 is connected to the Pluse2 signal, which is connected to the pin 3 of relay P8. The pin 2 of resistor R29 is connected to the pin 1 of resistor R30 and the base of triode Q2 at the same time. The pin 2 of resistor R30 is connected to the system ground. The emitter of triode Q2 is connected to the system ground. The collector of triode Q2 is connected to the pin 1 of resistor R25. The pin 2 of resistor R25 is externally connected to the input 5V power supply VCC5. The collector of triode Q2 outputs the inverted 5V pulse Ready signal to the pin 8 of the Max1 chip at the same time. A resistor R34 is connected in series between the pin 9 of the Max1 chip and the pin 6 of J1. The collector of triode Q2 is connected to the pin 1 of resistor R27 at the same time. The pin 2 of resistor R27 is connected to the pin 1 of resistor R31 and the base of triode Q3. The emitter of triode Q3 is connected to the system ground. The collector is connected to the pin 1 of resistor R26. The pin 2 of resistor R26 is connected to the external input 5V power supply VCC5. Capacitor C5 and capacitor C51 are connected in parallel as bypass decoupling capacitors. The pin 4 of the USB2 interface is connected to the system ground AGND. The pin 5 of USB2 is the connection pin of the technical shell of the interface. Resistor R28 and high-voltage capacitor C52 are connected in parallel and then connected to the pin 5 and also connected to the system ground.

[0029] In this embodiment, the synchronous analog timing pulse square wave generation module circuit includes a voltage follower, operational amplifier AD3, a first RC filter circuit, a second RC filter circuit, a third RC filter circuit, and a subtraction circuit. The voltage follower consists of resistor R42, resistor R40, and operational amplifier AD3. The pin 1 of resistor R42 is connected to the pin 2 of operational amplifier AD3, and the pin 2 of resistor R42 is connected to the pin 6 of operational amplifier AD3. The pin 3 of AD3 is connected to the SYN_Time signal sent by the GPS signal receiving, transforming, and transmitting module. At the same time, the pin 3 is connected to the pin 1 of resistor R40. The pin 2 of the resistor R40 is grounded. The pin 4 of operational amplifier AD3 is connected to the pin 1 of bead R41. The pin 1 of bead R41 is connected to the -5V analog power supply and to the pin 4 of operational amplifier AD3. The pin 2 of bead R41 is connected to the pins 1 of capacitor C63, capacitor C64, and capacitor C65. The pins 2 of capacitor C63, capacitor C64, and capacitor C65 are connected to the system ground. The first RC filter circuit includes resistor R41, capacitor C63, capacitor C64, and capacitor C65, which are used to filter out the high-frequency noise of the -5V analog power supply. The pin 7 of operational amplifier AD3 is connected to the pin 1 of bead R43. The pin 1 of bead R43 is connected to the +5V analog power supply. The pin 2 of bead R43 is connected to the pins 1 of capacitor C60, capacitor C61, and capacitor C62. The pins 2 of capacitor C60, capacitor C61, and capacitor C62 are connected to the system ground. Resistor R43, capacitor C60, capacitor C61, and capacitor C62 form the second RC filter circuit, which is used to filter out the high-frequency noise of the +5V analog power supply. The pin 6 of operational amplifier AD3 is connected to the pin 1 of resistor R44.

[0030] In this embodiment, the subtraction circuit includes resistor R46, resistor R47, resistor R49, resistor R50, adjustable resistor R45, and operational amplifier AD4. The pin 1 of adjustable resistor R45 is connected to the pin 2 of bead R48. The pin 2 of resistor R48 is connected to the 5V analog power supply AVCC5. The pin 3 of adjustable resistor R45 is connected to the pin 2 of bead R52. The pin 1 of bead R52 is connected to the -5V analog power supply AVSS5. The pin 2 of resistor R45 is connected to the pin 1 of resistor R46. The pin 2 of resistor R46 is connected to the pin 1 of resistor R47 and to the pin 2 of operational amplifier AD4. The pin 2 of resistor R47 is connected to the output of the pin 6 of operational amplifier AD. The pin 1 of resistor R49 is connected to the system ground AGND, and the pin 2 is connected to the pin 3 of operational amplifier AD4 and to the pin 1 of resistor R50. The pin 2 of resistor R50 is connected to the pin 3 of resistor R44 to receive the output signal of operational amplifier AD3. The pin 6 of operational amplifier AD4 is connected to the pin 1 of resistor R51. The pin 2 of resistor R51 is connected to the pin 1 of the P11 interface BNG output. The pin 2 of the P11 interface BNG is grounded. The pin 4 of operational amplifier AD4 is connected to bead R52 and to the -5V analog power supply AVSS5. The pin 2 of bead R52 is connected to the pins 1 of capacitor C66, capacitor C67, and capacitor C68. The pins 2 of capacitor C66, capacitor C67, and capacitor C68 are all connected to the system ground.

[0031] In this embodiment, the second RC filter circuit includes a resistor R62, capacitors C66, C67 and C68, and is used to filter out the high-frequency noise of the -5V analog power supply. The 7th pin of the operational amplifier AD is connected to the 1st pin of the bead R48 and is connected to the -5V analog power supply. The 2nd pin of the bead R48 is connected to the 1st pins of capacitors C69, C70 and C71. The 2nd pins of capacitors C69, C70 and C71 are all connected to the system ground. The third RC filter circuit includes a resistor RC48, capacitors C69 and C71 and is used to filter out the high-frequency noise of the +5V analog power supply.

[0032] In this embodiment, the timing module includes a clock oscillation circuit and an STM1 chip. The clock oscillation circuit includes capacitors C72, C73 and a passive crystal oscillator Y1. The 1st pin of capacitor C72 is grounded. The 1st pin of capacitor C73 is grounded. The 2nd pin of capacitor C72 is connected to the 1st pin of the passive crystal oscillator Y1. The 2nd pin of capacitor C73 is connected to the 2nd pin of the passive crystal oscillator Y1. The 1st pin of the passive crystal oscillator is connected to the 5th pin of the STM1 chip. The 2nd pin of the passive crystal oscillator Y1 is connected to the 6th pin of the STM1 chip. The 7th pin of the STM1 chip is connected to the 1st pin of capacitor C74. The 2nd pin of capacitor C74 is grounded. The 8th, 23rd, 35th and 47th pins of the STM1 chip are grounded. The 1st, 9th, 24th, 36th and 48th pins of the STM1 chip are connected to the 3.3V power supply of the circuit system. The 20th pin of the STM1 chip is connected to the 1st pin of resistor R54. The 2nd pin of resistor R54 is grounded. The 44th pin of the STM1 chip is connected to the 1st pin of resistor R53. The 2nd pin of resistor R53 is grounded. The 22nd pin of the STM1 chip is connected to the 1st pin of capacitor C75. The 2nd pin of capacitor C75 is grounded. The 16th pin of the STM1 chip outputs the PWM_time signal and is connected to the 1st pin of resistor R35 to control the on / off of the P8 relay.

[0033] In this embodiment, the power supply module includes an AX1 chip, an AX2 chip, an AX3 chip, and an XL1 chip. The 3rd pin of the AX1 chip is connected in parallel with a capacitor C76 and a capacitor C77 as the input filter capacitor of the AX1 chip. The 2nd pin of the AX1 chip is connected in parallel with a capacitor C78 and a capacitor C79 as the output filter capacitor of the AX1 chip. The 1st pin and the 2nd pin of the XL1 chip are jointly connected to an external input 5V power supply VCC5 for power supply. The feedback pin of the 3rd pin of the XL1 chip is connected to the 1st pin of a resistor R55. The 2nd pin of the resistor R55 is connected to GND, that is, the 7th pin and the 8th pin of the XL chip. The 3rd pin of the XL1 chip is also connected to the 1st pin of a resistor R56. The 2nd pin of the resistor R56 is connected to the cathode of a diode D6. The 7th pin and the 8th pin of the XL chip are short-circuited with its working ground GND and a resistor R57. The 5th pin and the 6th pin of the XLI chip are combined and connected to the 1st pin of a power inductor L2. The 2nd pin of the power inductor L2 is connected to the VCC5 power supply. The 5th pin and the 6th pin of the XL1 chip are connected to the cathode of the diode D6 and also connected to the 1st pin of a capacitor C80. The 2nd pin of the capacitor C80 is connected to the anode of a diode D7 and also connected to the cathode of a diode D8 at the same time. The cathode of the diode D7 is connected to the 1st pin of a capacitor C82 and the 2nd pin of a capacitor C81 and connected to the working ground GND at the same time. The 1st pin of the capacitor C81 is connected to the cathode of the diode D6. The 2nd pin of the capacitor C82 is connected to the anode of the diode D8. The 3rd pin input of the AX2 chip is connected to the cathode of the diode D6. The 3rd pin of the AX2 chip is connected in parallel with a capacitor C83 and a capacitor C84 as the input filter capacitor of the AX2 chip. The 2nd pin of the AX2 chip is connected in parallel with a capacitor C85 and a capacitor C86 as the output filter capacitor of the AX2 chip. The 2nd pin input of the AX3 chip is connected to the anode of the diode D8. The 2nd pin of the AX3 chip is connected in parallel with a capacitor C87 and a capacitor C88 as the input filter capacitor of the AX3 chip. The 3rd pin of the AX3 chip is connected in parallel with a capacitor C89 and a capacitor C90 as the output filter capacitor of the AX3 chip.

[0034] A method applicable to the observation of multiple physical quantities in rock friction experiments, and the specific steps of the method are as follows:

[0035] Step 1: After power-on, the GPS receiving module connected to the P7 interface starts to receive the GPS timing signal and generates a 3.3V second pulse PPS signal; at the same time, the P7 port outputs a TXD signal to the RS232 interface of J1. The computer connected to J1 receives the message information sent on the TXD line through its own RS232 interface and parses out the GPS time; the computer also receives the data ready signal of the 6th pin of the J1 port through the upper computer timing processing software. If there is a data ready signal, the computer determines whether the current computer system time needs to be modified according to the parsed GPS time. If so, it is modified to the parsed GPS time. Multiple computers simultaneously modify their respective system times through their respective upper computer timing processing software so that their respective system times can be calibrated at the second level.

[0036] Step 2: The timing circuit accesses the input ports of different types of physical quantity sampling devices connected to each computer through the synchronous low-voltage analog pulse signal output from port P11 via the processing circuit. The synchronous low-voltage analog pulse signals with consistent sampling amplitudes and the sampled physical quantities from each sampling device are written into a data file. This data file can be used to calibrate the absolute time of different types of physical quantity signals at the millisecond level using their respective synchronous low-voltage analog pulse signals during later data analysis. Thus, the timing calibration process for multi-physical quantity observation in the entire rock friction experiment is completed;

[0037] Step 3: The timing processing module of the timing circuit is responsible for turning off the data ready signal at pin 6 of port J1 and the synchronous low-voltage analog pulse signal output from port P11 for 5 seconds when the timing time written by the user is reached. After that, if the computer system does not receive the data ready signal at pin 6, it will not modify the system time. After the 5-second turn-off time has passed, the timing processing module of the timing circuit reconnects the data ready signal at pin 6 of port J1 and the synchronous low-voltage analog pulse signal output from port P11;

[0038] Step 4: The entire 5-second time window of turn-off can be used as the starting window for absolute time calibration during later data analysis of different types of physical quantity signals.

[0039] Although the specific embodiments of the present invention have been described in detail with reference to the accompanying drawings, it should not be construed as a limitation on the protection scope of the present invention. Within the scope described in the claims, various modifications and deformations that can be made by those skilled in the art without creative efforts still fall within the protection scope of the present invention.

Claims

1. A timing circuit applicable to multi-physical quantity observation in rock friction experiments, comprising a GPS signal receiving, transforming and transmitting module, a power supply module, a timing processing module and a synchronous analog timing pulse square wave generating module circuit, characterized in that: The synchronous analog timing pulse square wave generation module circuit, power supply module, and timing processing module are all connected to the GPS signal receiving, transforming, and transmitting module. The GPS signal receiving, transforming, and transmitting module transforms the received GPS clock signal and sends it to the computer side. The power supply module receives the 5V power supply from the USB port and transforms it into positive and negative power supplies for the analog part of the circuit. The timing processing module turns on and off the GPS timing signal and the analog timing square wave pulse sent by the entire circuit according to the timing function set by the user. The synchronous analog timing pulse square wave generation module circuit synchronously generates a full-power low-voltage analog timing pulse square wave according to the GPS timing signal to supply different types of physical quantity sampling devices; The synchronous analog timing pulse square wave generation module circuit includes a voltage follower, a first RC filter circuit, a second RC filter circuit, a third RC filter circuit, and a subtraction circuit. The voltage follower includes resistor R42, resistor R40, and operational amplifier AD3. The 1-foot of resistor R42 is connected to the 2-foot of operational amplifier AD3, and the 2-foot of resistor R42 is connected to the 6-foot of operational amplifier AD3. The 3-foot of AD3 is connected to the SYN_Time signal sent by the GPS signal receiving, transforming, and transmitting module. At the same time, the 3-foot is connected to the 1-foot of resistor R40. The 2-foot of resistor R40 is grounded. The 4-foot of operational amplifier AD3 is connected to the 1-foot of bead R41. The 2-foot of bead R41 is connected to the negative 5V analog power supply. The 1-foot of bead R41 is connected to the 1-foot of capacitor C63, capacitor C64, and capacitor C65. The 2-foot of capacitor C63, capacitor C64, and capacitor C65 is connected to the system ground. The first RC filter circuit includes resistor R41, capacitor C63, capacitor C64, and capacitor C65 to filter out the high-frequency noise of the negative 5V analog power supply. The 7-foot of operational amplifier AD3 is connected to the 1-foot of bead R43. The 2-foot of bead R43 is connected to the positive 5V analog power supply. The 1-foot of bead R43 is connected to the 1-foot of capacitor C60, capacitor C61, and capacitor C62. The 2-foot of capacitor C60, capacitor C61, and capacitor C62 is connected to the system ground. Resistor R43, capacitor C60, capacitor C61, and capacitor C62 form a second RC filter circuit to filter out the high-frequency noise of the positive 5V analog power supply. The 6-foot of operational amplifier AD3 is connected to the 1-foot of resistor R44.

2. The timing circuit applicable to multi-physical quantity observation in rock friction experiments according to claim 1, wherein: The GPS signal receiving, transforming and transmitting module includes the signal interface P7 of the GPS receiving module, the output second pulse signal level adjustment and enhancement circuit, and the execution module of the system timing processing module. The 3rd pin of the signal interface P7 of the GPS receiving module is the TXD data transmission signal of the RS232 interface, which is connected in series with the resistor R33 and then connected to the 2nd pin of the DB9-pin interface J1. The 4th pin of the signal interface P7 of the GPS receiving module is the RXD data receiving signal of the RS232 interface, which is connected in series with the resistor R32 and then connected to the 3rd pin of the DB9-pin interface J1. The resistors R32 and R33 are used for overcurrent protection of the TXD and RXD lines. The 5th pin of the signal interface P7 of the GPS receiving module is the VCC power supply pin, which is connected to the 5V external input power supply VCC5 of the circuit. At the same time, the 5th pin is connected to the cathode of the voltage stabilizing diode D5. The 5th, 10th, and 11th pins of the J1 are connected to the system ground AGND. The 2nd and 3rd pins of the J1 are connected to the TXD and RXD signals respectively, and are connected to the bidirectional TVS diodes D6 and D7 to the ground. The 6th pin of the J1 is connected to the 9th pin of the max232D chip to output a pulse. The 1st pin of the max232D chip is connected to the capacitor C55. The 2nd pin of the capacitor C55 is connected to the 3rd pin of the max232D chip. The 2nd pin of the max232D chip is connected to the capacitor C56. The 2nd pin of the capacitor C56 is connected to the system ground AGND. The 6th pin of the max232D chip is connected to the 1st pin of the capacitor C58. The 2nd pin of the capacitor C58 is connected to the system ground AGND. The 16th pin of the max232D chip is connected with the capacitors C53 and C54, and serves as the power supply bypass and decoupling capacitors of the max232D chip. The 15th pin of the max232D chip is connected to the system ground AGND.

3. The timing circuit applicable to multi-physical quantity observation in rock friction experiments according to claim 2, characterized in that: The execution module of the system timing processing module includes the resistor R35, the resistor R36, the triode Q4, the diode D8, and the relay P8. The 2nd pin of the relay is connected to the 1st pin of the signal interface P7 of the GPS receiving module. The resistor R35 is connected to the base of the triode Q4. The resistor R36 is connected to the resistor R35 and at the same time connected to the base of the triode Q4 and then connected to the system ground. The resistors R35 and R36 form a voltage dividing circuit and divide the 3.3V level timing output signal PWM_Time of the system timing processing module into 2.7V. The emitter of the triode Q4 is connected to the system ground, and the collector is connected to the 8th pin of the relay P8. The 1st pin of the relay P8 is the power supply pin and is connected to the external input 5V power supply VCC5. The cathode of the diode D8 is connected to the 1st pin of the relay P8, and the anode is connected to the 8th pin of the relay P8. The 3rd pin of the relay P8 is connected to the Pluse2 signal.

4. The timing circuit applicable to multi-physical quantity observation in rock friction experiments according to claim 2, characterized in that: The output second pulse signal level adjustment and enhancement circuit includes resistor R29, resistor R30, triode Q2, resistor R27, resistor R31, resistor R26, triode Q3, capacitor C50, capacitor C51, USB2 interface and resistor R25. Resistor R29, resistor R30, resistor R25 and triode Q2 form the output second pulse signal level conversion and inversion circuit of the GPS receiving module. The 1st pin of resistor R29 is connected to the 3rd pin of Pluse2 signal connected to relay P8. The 2nd pin of resistor R29 is connected to the 1st pin of resistor R30 and the base of triode Q2 at the same time. The 2nd pin of resistor R30 is connected to the system ground. The emitter of triode Q2 is connected to the system ground. The collector of triode Q2 is connected to the 1st pin of resistor R25. The 2nd pin of resistor R25 is externally connected to the input 5V power supply VCC5. The collector of triode Q2 outputs the inverted 5V pulse Ready signal and connects to the 8th pin of the max232D chip. A resistor R34 is connected in series between the 9th pin of the max232D chip and the 6th pin of J1. The collector of Q2 triode is connected to the 1st pin of R27 resistor at the same time. The 2nd pin of resistor R27 is connected to the 1st pin of resistor R31 and the base of triode Q3. The emitter of triode Q3 is connected to the system ground, and the collector is connected to the 1st pin of resistor R26. The 2nd pin of resistor R26 is connected to the external input 5V power supply VCC5. Capacitor C50 and capacitor C51 are connected in parallel as bypass decoupling capacitors. The 4th pin of the USB2 interface is connected to the system ground AGND. The 5th pin of USB2 is the connection pin of the technical shell of the interface. Resistor R28 and high-voltage capacitor C52 are connected in parallel and then connected to the 5th pin of USB2 and connected to the system ground.

5. The timing circuit applicable to multi-physical quantity observation in rock friction experiments according to claim 2, characterized in that: The subtraction circuit includes resistor R46, resistor R47, resistor R49, resistor R50, adjustable resistor R45 and operational amplifier AD4. The 1st pin of adjustable resistor R45 is connected to the 2nd pin of bead R48. The 1st pin of bead R48 is connected to the 5V analog power supply AVCC5. The 3rd pin of adjustable resistor R45 is connected to the 2nd pin of bead R52. The 1st pin of bead R52 is connected to the negative 5V analog power supply AVSS5. The 2nd pin of resistor R45 is connected to the 1st pin of resistor R46. The 2nd pin of resistor R46 is connected to the 1st pin of resistor R47 and the 2nd pin of operational amplifier AD4 at the same time. The 2nd pin of resistor R47 is connected to the 6th pin output of operational amplifier AD4. The 1st pin of resistor R49 is connected to the system ground AGND, and the 2nd pin is connected to the 3rd pin of operational amplifier AD4 and the 1st pin of resistor R50 at the same time. The 2nd pin of resistor R50 is connected to the 2nd pin of resistor R44 to receive the output signal of operational amplifier AD4. The 6th pin of operational amplifier AD4 is connected to the 1st pin of resistor R51. The 2nd pin of resistor R51 is connected to the 1st pin of the P11 interface BNG output. The 2nd pin of the P11 interface BNG is grounded. The 4th pin of operational amplifier AD4 is connected to bead R52 and the negative 5V analog power supply AVSS5. The 2nd pin of bead R52 is connected to the 1st pins of capacitor C66, capacitor C67 and capacitor C68. The 2nd pins of capacitor C66, capacitor C67 and capacitor C68 are all connected to the system ground.

6. The timing circuit applicable to multi-physical quantity observation in rock friction experiments according to claim 1, characterized in that: Pin 7 of the operational amplifier AD is connected to pin 1 of the bead R48 and is also connected to the -5V analog power supply. Pin 1 of the bead R48 is connected to pins 1 of capacitors C69, C70, and C71. Pins 2 of capacitors C69, C70, and C71 are all connected to the system ground. The third RC filter circuit includes the bead R48, capacitors C69, C70, and C71 and is used to filter out the high-frequency noise of the +5V analog power supply.

7. The timing circuit applicable to multi-physical quantity observation in rock friction experiments according to claim 3, characterized in that: The timing processing module includes a clock oscillation circuit and an STM32F411CEU6 chip. The clock oscillation circuit includes capacitors C72, C73, and a passive crystal oscillator Y1. Pin 1 of capacitor C72 is grounded. Pin 1 of capacitor C73 is grounded. Pin 2 of capacitor C72 is connected to pin 1 of the passive crystal oscillator Y1. Pin 2 of capacitor C73 is connected to pin 2 of the passive crystal oscillator Y1. Pin 1 of the passive crystal oscillator is connected to pin 5 of the STM32F411CEU6 chip. Pin 2 of the passive crystal oscillator Y1 is connected to pin 6 of the STM32F411CEU6 chip. Pin 7 of the STM32F411CEU6 chip is connected to pin 1 of capacitor C74. Pin 2 of capacitor C74 is grounded. Pins 8, 23, 35, and 47 of the STM32F411CEU6 chip are grounded. Pins 1, 9, 24, 36, and 48 of the STM32F411CEU6 chip are connected to the 3.3V power supply of the circuit system. Pin 20 of the STM32F411CEU6 chip is connected to pin 1 of resistor R54. Pin 2 of resistor R54 is grounded. Pin 44 of the STM32F411CEU6 chip is connected to pin 1 of resistor R53. Pin 2 of resistor R53 is grounded. Pin 22 of the STM32F411CEU6 chip is connected to pin 1 of capacitor C75. Pin 2 of capacitor C75 is grounded. Pin 16 of the STM32F411CEU6 chip outputs the PWM_time signal and is connected to pin 1 of resistor R35, and controls the on / off of the P8 relay.

8. The timing circuit applicable to multi-physical quantity observation in rock friction experiments according to claim 1, wherein: The power supply module includes AMS1117-3.3 chip, AMS1117-5 chip, MC79M05 chip and XL6007E1 chip. The 3rd pin of the AMS1117-3.3 chip is shunted with capacitor C76 and capacitor C77 as the input filter capacitor of the AMS1117-3.3 chip. The 2nd pin of the AMS1117-3.3 chip is shunted with capacitor C78 and capacitor C79 as the output filter capacitor of the AMS1117-3.3 chip. The 1st pin and the 2nd pin of the XL6007E1 chip are jointly connected to the external input 5V power supply VCC5 for power supply. The 3rd pin feedback pin of the XL6007E1 chip is connected to the 1st pin of resistor R55. The 2nd pin of resistor R55 is connected to GND, that is, the 7th pin and the 8th pin of the XL6007E1 chip. The 3rd pin of the XL6007E1 chip is also connected to the 1st pin of resistor R56. The 2nd pin of resistor R56 is connected to the cathode of diode D6. The 7th pin and the 8th pin of the XL6007E1 chip are short-circuited with its working ground GND and resistor R57. The 5th pin and the 6th pin of the XL6007E1 chip are combined and connected to the 1st pin of power inductor L2. The 2nd pin of power inductor L2 is connected to the VCC5 power supply. The 5th pin and the 6th pin of the XL6007E1 chip are connected to the anode of diode D6 and also connected to the 1st pin of capacitor C80. The 2nd pin of capacitor C80 is connected to the anode of diode D7 and also connected to the cathode of diode D8 at the same time. The cathode of diode D7 is connected to the 1st pin of capacitor C82 and the 2nd pin of capacitor C81 and connected to the working ground GND at the same time. The 1st pin of capacitor C81 is connected to the cathode of diode D6. The 2nd pin of capacitor C82 is connected to the anode of diode D8. The 3rd pin input of the AMS1117-5 chip is connected to the cathode of diode D6. The 3rd pin of the AMS1117-5 chip is shunted with capacitor C83 and capacitor C84 as the input filter capacitor of the AMS1117-5 chip. The 2nd pin of the AMS1117-5 chip is shunted with capacitor C85 and capacitor C86 as the output filter capacitor of the AMS1117-5 chip. The 2nd pin input of the MC79M05 chip is connected to the anode of diode D8. The 2nd pin of the MC79M05 chip is shunted with capacitor C87 and capacitor C88 as the input filter capacitor of the MC79M05 chip. The 3rd pin of the MC79M05 chip is shunted with capacitor C89 and capacitor C90 as the output filter capacitor of the MC79M05 chip.

9. A method suitable for multi-physical quantity observation in rock friction experiments, characterized in that: The method is applied to the circuit described in claim 5, and the specific steps are as follows: Step 1. After power-on, the GPS receiving module connected to the P7 interface starts to receive the GPS timing signal and generates a 3.3V second pulse PPS signal; at the same time, the P7 port outputs the TXD signal to the RS232 interface of J1. The computer connected to J1 receives the message information sent on the TXD line through its own RS232 interface and parses out the GPS time; the computer also receives the data ready signal from pin 6 of the J1 port through the host computer timing processing software. If there is a data ready signal, the computer determines whether the current computer system time needs to be modified based on the parsed GPS time. If necessary, it is modified to the parsed GPS time. Multiple computers simultaneously modify their respective system times through their respective host computer timing processing software so that their respective system times can be calibrated at the second level. Step 2: The timing circuit processes the synchronous low-voltage analog pulse signal output from port P11 and connects it to the input ports of different physical quantity sampling devices connected to each computer. The synchronous low-voltage analog pulse signal with consistent sampling amplitude from each sampling device is written into a data file together with the sampled physical quantity. This data file can be used to calibrate the absolute time of different physical quantity signals at the millisecond level during subsequent data analysis using the respective synchronous low-voltage analog pulse signals. At this point, the timing calibration process for the multi-physical quantity observation of the entire rock friction experiment is completed. Step 3, the timing processing module of the timing circuit is responsible for shutting off the 6-pin data ready signal of the J1 port and the synchronous low-voltage analog pulse signal output by the P11 port for 5 seconds after the user-written timing time is reached. After that, if the computer system does not receive the 6-pin data ready signal, the system time will not be modified. After the 5-second shutdown time, the timing processing module of the timing circuit reconnects the 6-pin data ready signal of the J1 port and the synchronous low-voltage analog pulse signal output by the P11 port; Step 4: The entire 5-second time window of the shutdown is used as a starting window for absolute time calibration in the subsequent analysis of data files of different types of physical quantity signals.

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