Digital quantity acquisition circuit, circuit board, equipment and method
By designing digital quantity collection circuits, multiple optoelectronic isolation units are used to collect multi -way digital signals at the same time, solving the problem of large -scale collection modules in existing technologies, insufficient data, and only unilateral data can be collected. Multi -way data collection.
Patent Information
- Application Number
- CN202411480958.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-01-24
AI Technical Summary
The acquisition module of the existing programmable logic controller has a large external dimensions and cannot install high-precision equipment, resulting in inaccurate data and can only realize single-channel data acquisition, making it impossible to efficiently collect multiple data.
A digital quantity acquisition circuit is designed, including a main control circuit, a collection circuit, a communication circuit, an output circuit and a code value circuit. It collects multiple digital signals simultaneously through multiple photoelectric isolation units, which improves the collection efficiency.
It achieves efficient collection of multi-channel digital signals, reduces the size and cost of collection equipment, and improves data accuracy and collection flexibility.
Smart Images
Figure CN119356181A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a digital quantity acquisition circuit, circuit board, device and method. Background Art
[0002] In the process of modern industrial production, automatic control technology plays a vital role. Traditional industrial control systems mostly use electrical components such as relays and contactors for control. These control systems have problems such as large size, complex wiring, low reliability, and poor flexibility. With the continuous improvement of the degree of automation in industrial production, higher requirements are placed on the stability, accuracy, and scalability of the control system.
[0003] At present, the signals of industrial equipment are mainly collected and processed through the acquisition module in the programmable logic controller, and the collected and processed data are sent to the corresponding equipment through the corresponding communication protocol.
[0004] However, the acquisition module of the programmable logic controller has large dimensions, which makes it impossible to install high-precision equipment, making the collected data inaccurate. In addition, the programmable logic controller can only collect single-channel data, and external auxiliary equipment is required to collect multiple channels of data. Summary of the invention
[0005] The purpose of the present application is to provide a digital quantity acquisition circuit, circuit board, device and method to address the deficiencies in the above-mentioned prior art. By setting up an acquisition circuit, multiple digital quantity signals can be acquired simultaneously, thereby improving the efficiency of digital quantity signal acquisition and reducing the acquisition cost.
[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
[0007] In a first aspect, an embodiment of the present application provides a digital quantity acquisition circuit, the digital quantity acquisition circuit comprising: a main control circuit, an acquisition circuit, a communication circuit, an output circuit and a code value circuit; wherein the main control circuit comprises: a main control chip, the acquisition circuit comprises: a first socket, a plurality of photoelectric isolation units, and the output circuit comprises: a second socket;
[0008] The input end of the communication circuit is used to receive the acquisition control signal input by the computer device, and the output end of the communication circuit is connected to the communication pin of the main control chip;
[0009] The first socket is used to receive the collected multi-channel digital input signals, the first socket is respectively connected to the first ends of the plurality of photoelectric isolation units, and the second ends of the plurality of photoelectric isolation units are all connected to the plurality of first input pins of the main control chip;
[0010] The multiple output pins of the main control chip are connected to the multiple first pins of the second socket, the second socket is also used to connect to an external device, and the multiple second input pins of the main control circuit are also connected to the code value circuit.
[0011] Optionally, the main control circuit also includes: a crystal oscillator circuit, a reset circuit, a status indication unit and a debugging interface, wherein the crystal oscillator circuit is connected to the clock pin of the main control chip, the reset circuit is connected to the reset pin of the main control chip, the status indication unit is connected to the preset input and output pins of the main control unit, and the two third input pins of the main control unit are also connected to the debugging interface.
[0012] Optionally, the communication circuit includes: a communication chip, an electrostatic protection unit, an overcurrent protection unit and a test terminal, the input pin of the communication chip is the input end of the communication circuit, the input pin of the communication chip is also connected to the electrostatic protection unit and the overcurrent protection unit, the output pin of the communication chip is the output end of the communication circuit, and the input pin of the communication chip is also connected to the test terminal.
[0013] Optionally, the digital quantity acquisition circuit also includes: a power supply circuit, the power supply circuit includes: a first transformer unit and a second transformer unit, the input end of the first transformer unit is used to connect to a preset power supply unit, the output end of the first transformer unit is used to output a first voltage, the output end of the first transformer unit is also connected to the input end of the second transformer unit, and the output end of the second transformer unit is used to output a second voltage.
[0014] Optionally, the plurality of second pins in the second socket are all grounded.
[0015] Optionally, the code value circuit includes: a multi-bit dip switch, and multiple groups of resistors, multiple first ends of the multi-bit dip switch are grounded, each of the multiple second ends of the multi-bit dip switch is respectively connected to multiple resistors in a group of resistors, and the multiple second ends of the multi-bit dip switch are connected to multiple second input pins of the main control chip.
[0016] In a second aspect, another embodiment of the present application provides a digital quantity acquisition circuit board, which includes: an integrated circuit board, and the digital quantity acquisition circuit described in the first aspect above, which is arranged on the integrated circuit board.
[0017] In a third aspect, another embodiment of the present application provides a digital quantity acquisition device, and the digital quantity acquisition device at least includes: a digital quantity acquisition circuit board of the digital quantity acquisition circuit board described in the second aspect above.
[0018] In a fourth aspect, another embodiment of the present application provides a digital quantity acquisition method, which is applied to a main control chip in the digital quantity acquisition circuit described in any one of the first aspects above, and the method includes:
[0019] Acquire a first digital signal from a computer device transmitted by a communication circuit;
[0020] Determine that the digital quantity acquisition circuit is in a digital quantity acquisition mode according to information of a first preset byte bit in the first digital signal, determine an address code of the digital quantity acquisition circuit from a second preset byte bit in the first digital signal, determine a frame end from a third preset byte bit in the first digital signal, and determine digital quantity input state data from each data bit between the second preset byte bit and the third preset byte bit in the first digital signal;
[0021] Generate data volume acquisition status data based on multiple digital quantity input signals transmitted by the acquisition circuit;
[0022] Fill the indication information corresponding to the digital quantity acquisition mode into the first preset byte position, fill the address code into the second preset byte position, fill the data quantity acquisition status data into each data position, and also fill the indication information of the preset frame end into the third preset byte position to generate a second digital signal;
[0023] The second digital signal is transmitted to the computer device through the communication circuit.
[0024] Optionally, the method further comprises:
[0025] Acquire a third digital signal from the computer device transmitted by the communication circuit;
[0026] Determine, according to information of the first preset byte bit in the third digital signal, that the digital quantity acquisition circuit is in a digital quantity output mode, determine the address code of the digital quantity acquisition circuit from the second preset byte bit in the third digital signal, determine the frame end from the third preset byte bit in the third digital signal, and determine the first digital quantity control data from each data bit between the second preset byte bit and the third preset byte bit in the third digital signal;
[0027] Based on the multiple digital quantity output signals, generating second data quantity control data;
[0028] Fill the indication information corresponding to the digital quantity output mode into the first preset byte position, fill the address code into the second preset byte position, fill the second data quantity control data into each data bit, and also fill the indication information of the preset frame end into the third preset byte position, to generate a fourth digital signal;
[0029] The fourth digital signal is transmitted to the computer device through the communication circuit.
[0030] In a fifth aspect, another embodiment of the present application provides a digital quantity acquisition device, which is applied to a main control chip in the digital quantity acquisition circuit described in any one of the first aspects above, and the device includes:
[0031] An acquisition module, used for acquiring a first digital signal from a computer device transmitted by a communication circuit;
[0032] a determination module, configured to determine that the digital quantity acquisition circuit is in a digital quantity acquisition mode according to information of a first preset byte position in the first digital signal, determine an address code of the digital quantity acquisition circuit from a second preset byte position in the first digital signal, determine a frame end from a third preset byte position in the first digital signal, and determine digital quantity input state data from each data bit between the second preset byte position and the third preset byte position in the first digital signal;
[0033] A generating module, used for generating data volume acquisition state data based on multiple digital quantity input signals transmitted by the acquisition circuit;
[0034] A filling module, used to fill the indication information corresponding to the digital quantity acquisition mode into the first preset byte position, fill the address code into the second preset byte position, fill the data quantity acquisition status data into each data position, and also fill the indication information of the preset frame end into the third preset byte position, to generate a second digital signal;
[0035] A transmission module is used to transmit the second digital signal to the computer device through the communication circuit.
[0036] In the sixth aspect, another embodiment of the present application provides a computer device, comprising: a processor and a storage medium, wherein the storage medium stores machine-readable instructions executable by the processor, and when the computer device is running, the processor communicates with the storage medium, and the processor executes the machine-readable instructions to perform the steps of the digital quantity acquisition method as described in any one of the fourth aspects above.
[0037] In the seventh aspect, another embodiment of the present application provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the digital quantity acquisition method as described in any one of the fourth aspects above are executed.
[0038] The beneficial effects of this application are:
[0039] The present application provides a digital quantity acquisition circuit, a circuit board, a device and a method. The present application provides a digital quantity acquisition circuit, which includes: a main control circuit, an acquisition circuit, a communication circuit, an output circuit and a code value circuit; wherein the main control circuit includes: a main control chip, the acquisition circuit includes: a first socket, a plurality of photoelectric isolation units, and the output circuit includes: a second socket; the input end of the communication circuit is used to receive the acquisition control signal input by the computer device, and the output end of the communication circuit is connected to the communication pin of the main control chip; the first socket is used to receive the acquired multi-channel digital quantity input signals, the first socket is respectively connected to the first ends of the plurality of photoelectric isolation units, and the second ends of the plurality of photoelectric isolation units are all connected to the plurality of first input pins of the main control chip; the plurality of output pins of the main control chip are connected to the plurality of first pins of the second socket, the second socket is also used to connect to an external device, and the plurality of second input pins of the main control circuit are also connected to the code value circuit. The present application can acquire multi-channel digital quantity input signals at the same time through the acquisition circuit, and can realize the acquisition of digital quantity signals without the need for multiple acquisition devices, thereby reducing the volume of the acquisition device and the cost of acquiring digital quantity signals. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0041] Figure 1 A schematic diagram of the structure of a first digital quantity acquisition circuit provided in an embodiment of the present application;
[0042] Figure 2 A schematic diagram of the structure of a collection circuit provided in an embodiment of the present application;
[0043] Figure 3 A schematic diagram of the structure of a second digital quantity acquisition circuit provided in an embodiment of the present application;
[0044] Figure 4 A schematic diagram of the structure of a main control circuit provided in an embodiment of the present application;
[0045] Figure 5 A schematic diagram of the structure of a third digital quantity acquisition circuit provided in an embodiment of the present application;
[0046] Figure 6 A schematic diagram of the structure of a communication circuit provided in an embodiment of the present application;
[0047] Figure 7 A schematic diagram of the structure of a fourth digital quantity acquisition circuit provided in an embodiment of the present application;
[0048] Figure 8 A schematic diagram of a power supply circuit provided in an embodiment of the present application;
[0049] Fig. 9 A schematic diagram of the structure of a fifth digital quantity acquisition circuit provided in an embodiment of the present application;
[0050] Fig.10 A schematic diagram of the structure of a sixth digital quantity acquisition circuit provided in an embodiment of the present application;
[0051] Fig.11 A schematic diagram of the structure of a code value circuit provided in an embodiment of the present application;
[0052] Fig.12 A schematic diagram of the structure of a digital quantity acquisition circuit board provided in an embodiment of the present application;
[0053] Fig.13 A second structural schematic diagram of a digital quantity acquisition circuit board provided in an embodiment of the present application;
[0054] Fig.14 A structural schematic diagram of a digital quantity acquisition device provided in an embodiment of the present application;
[0055] Fig.15 A flowchart of a digital quantity acquisition method provided in an embodiment of the present application;
[0056] Fig.16 A flowchart of another digital quantity acquisition method provided in an embodiment of the present application;
[0057] Fig.17 A schematic diagram of the structure of a digital quantity acquisition device provided in an embodiment of the present application;
[0058] Fig.18 A schematic diagram of the structure of a computer device provided in an embodiment of the present application.
[0059] Marked figure: 2000-digital quantity acquisition circuit board; 100-main control circuit; 200-acquisition circuit; 300-communication circuit; 400-output circuit; 500-code value circuit; 600-power supply circuit; 101-main control chip; 102-crystal oscillator circuit; 103-reset circuit; 104-status indication unit; 105-debugging interface; 201-photoelectric isolation unit; 301-communication chip; 302-static protection unit; 303-overcurrent protection unit; 304-test terminal; 501-multi-position dial switch; 502-resistance exclusion; 601-first transformer unit; 602-second transformer unit; JP1-first socket; JP2-second socket; U-photoelectric coupler; Y1-crystal; L1-first inductor; V1-first voltage; V2-second voltage; F1 -first fuse; F2-second fuse; D1-first light-emitting diode; D2-first bidirectional diode; D3-second bidirectional diode; D4-fourth diode; D5-fifth diode; R1-first resistor; R2-second resistor; R3-third resistor; R4-fourth resistor; R5-fifth resistor; R6-sixth resistor; R7-seventh resistor; R8-eighth resistor; R9-ninth resistor; R10-tenth resistor; R11-eleventh resistor; C1-first capacitor; C2-second capacitor; C3-third capacitor; C4-fourth capacitor; C5-fifth capacitor; C6-sixth capacitor; C7-seventh capacitor; C8-eighth capacitor; C9-ninth capacitor; C10-tenth capacitor; C11-eleventh capacitor; C12-twelfth capacitor; C13-thirteenth capacitor. DETAILED DESCRIPTION
[0060] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.
[0061] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0062] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.
[0063] In order to clearly describe the digital quantity acquisition circuit provided in the embodiment of the present application, the digital quantity acquisition circuit provided in the embodiment of the present application is explained below in combination with multiple drawings. Figure 1 The first embodiment of the present invention provides a schematic diagram of the structure of the digital quantity acquisition circuit. Figure 1 As shown, the digital quantity acquisition circuit includes: a main control circuit 100, an acquisition circuit 200, a communication circuit 300, an output circuit 400 and a code value circuit 500; wherein the main control circuit 100 includes: a main control chip 101, the acquisition circuit 200 includes: a first socket JP1, a plurality of photoelectric isolation units 201, and the output circuit 400 includes: a second socket JP2;
[0064] The input terminal IN of the communication circuit 300 is used to receive the acquisition control signal input by the computer device, and the output terminal OUT of the communication circuit 300 is connected to the communication pin CAN of the main control chip 101;
[0065] The first socket JP1 is used to receive the collected multi-channel digital input signals. The first socket JP1 is respectively connected to the first ends of the plurality of photoelectric isolation units 201, and the second ends of the plurality of photoelectric isolation units 201 are all connected to the plurality of first input pins IN1 of the main control chip 101;
[0066] The multiple output pins OUT of the main control chip 101 are connected to the multiple first pins of the second socket JP2 . The second socket JP2 is also used to connect external devices. The multiple second input pins IN2 of the main control circuit 100 are also connected to the code value circuit 500 .
[0067] Among them, the main control chip 101 can be an ARM chip with 64 pins, and the model of the main control chip can be STM32F103RCT6. The main control chip 101 has a communication pin CAN, multiple first input pins IN1 and multiple second input pins IN2. The first input pin IN1 of the main control chip can be 24, or other numbers, which can be determined according to actual conditions. The embodiment of the present application does not limit this. The second input pin IN2 of the main control chip 101 can be 8 or other numbers, which can be determined according to actual conditions. The embodiment of the present application does not limit this. The output pins of the main control chip 101 can be 16 or other numbers, which can be determined according to actual conditions. The embodiment of the present application does not limit this.
[0068] Among them, the first socket JP1 can collect multi-channel digital input signals through a data acquisition circuit. The photoelectric isolation unit 201 is used to isolate the input multi-channel digital input signals from the signals in the digital acquisition circuit to avoid mutual interference between the multi-channel digital input signals and the signal isolation in the digital acquisition circuit. There can be multiple photoelectric isolation units 201, each photoelectric isolation unit 201 can receive 4 groups of digital input signals. When there are 6 photoelectric isolation units 201, 24 groups of digital input signals can be received. At this time, the first socket JP1 is a 24P bull-horn socket.
[0069] For example, Figure 2 A schematic diagram of a collection circuit provided in an embodiment of the present application is shown in FIG. Figure 2As shown, the present application takes a photoelectric isolation unit 201 as an example and the first socket JP1 is a 24P bull horn socket as an example. The photoelectric isolation unit 201 can be composed of four photoelectric couplers U. The positive electrode of the light-emitting diode in the photoelectric coupler U is connected to the preset power supply unit, and the negative electrode of the light-emitting diode is connected to the first socket JP1 through the first resistor R1. The negative electrode of the light-emitting diode is also grounded through the first capacitor C1, which can achieve filtering of the digital input signal and ensure the stability of the digital input signal. At the same time, one end of the isolation medium is connected to multiple first input pins IN1 of the main control chip. While one end of the isolation medium is connected to multiple first input pins IN1 of the main control chip, it is also connected to the second preset power supply through multiple second resistors R2. The second preset power supply is a 3.3 volt power supply. The protection of the photoelectric isolator can be achieved through multiple resistors. The other end of the isolation medium is grounded. Among them, multiple first resistors R1 can be the same or different, which is determined according to actual conditions and the present application does not impose any restrictions on this. The first resistor R1 in the present application can all be a 2000 ohm resistor; multiple second resistors R2 can be the same or different, which is determined according to actual conditions and the present application does not impose any restrictions on this. The second resistor R2 in the present application can be a 10 kilo-ohm resistor; multiple first capacitors C1 can be the same or different, which is determined according to actual conditions and the present application does not impose any restrictions on this. The first capacitors C1 in the present application can all be 1 μF.
[0070] The present application provides a digital quantity acquisition circuit, which includes: a main control circuit, an acquisition circuit, a communication circuit, an output circuit and a code value circuit; wherein the main control circuit includes: a main control chip, the acquisition circuit includes: a first socket, a plurality of photoelectric isolation units, and the output circuit includes: a second socket; the input end of the communication circuit is used to receive the acquisition control signal input by the computer device, and the output end of the communication circuit is connected to the communication pin of the main control chip; the first socket is used to receive the acquired multi-channel digital quantity input signals, the first socket is respectively connected to the first ends of the plurality of photoelectric isolation units, and the second ends of the plurality of photoelectric isolation units are all connected to the plurality of first input pins of the main control chip; the plurality of output pins of the main control chip are connected to the plurality of first pins of the second socket, the second socket is also used to connect to an external device, and the plurality of second input pins of the main control circuit are also connected to the code value circuit. The present application can acquire multi-channel digital quantity input signals at the same time through the acquisition circuit, and can realize the acquisition of digital quantity signals without the need for multiple acquisition devices, thereby reducing the volume of the acquisition device and the cost of acquiring digital quantity signals.
[0071] On the basis of the above embodiment, the embodiment of the present application also provides a second digital quantity acquisition circuit, Figure 3 A schematic diagram of the structure of a second digital quantity acquisition circuit provided in an embodiment of the present application is shown in FIG. Figure 3 As shown in the above Figure 1On the basis of, the main control circuit 100 also includes: a crystal oscillator circuit 102, a reset circuit 103, a status indication unit 104 and a debugging interface 105, wherein the crystal oscillator circuit 102 is connected to the clock pin OSC of the main control chip 101, the reset circuit 103 is connected to the reset pin NRST of the main control chip 101, the status indication unit 104 is connected to the preset input and output pins IN / OUT of the main control chip 101, and the two third input pins IN3 of the main control chip 101 are also connected to the debugging interface 105.
[0072] When the main control circuit 100 includes a crystal oscillator circuit 102, a reset circuit 103, a status indication unit 104 and a debugging interface 105, the corresponding main control chip 101 also includes a clock pin OSC, a reset pin NRST, a preset input and output pin IN / OUT and two third input pins IN3.
[0073] The crystal oscillator circuit 102 is used to provide a clock signal to ensure the synchronization of data sampling, processing and transmission in the digital quantity acquisition circuit, so that data acquisition can be carried out in an orderly manner. The reset circuit 103 is used to provide a reset signal to the main control chip 101 to ensure that all registers, counters and other storage elements in the digital quantity acquisition circuit are set to a known state, ensuring that the digital quantity acquisition circuit starts working from a certain state. The state indication unit 104 is used to indicate whether the main control chip 101 is powered on, and the debugging interface 105 is used to debug the main control chip 101 to ensure that the main control chip 101 works normally.
[0074] For example, Figure 4 A schematic diagram of the structure of a main control circuit provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the crystal oscillator circuit 102 can be composed of a crystal Y1 and two second capacitors C2, the two ends of the crystal Y1 are respectively connected to the clock signal input pin 0SC_IN and the clock signal input pin 0SC_OUT of the main control chip 101, the clock signal input pin 0SC_IN and the clock signal input pin 0SC_OUT are respectively grounded through two second capacitors C2, the two second capacitors C2 are only examples, and the two second capacitors C2 can be the same or different; the reset circuit 103 may include a third resistor R3 and a third capacitor C3, the reset pin NRST of the main control chip 101 is respectively grounded through the third capacitor C3, and connected to the second preset power supply through the third resistor R3, the second preset power supply voltage is the second voltage V2, and the second voltage V2 is 3.3 negative; the state indicating unit 104 may include a first light-emitting diode D1 and a fourth resistor R4, one end of the fourth resistor R4 is connected to the input / output pin IN / OUT of the main control chip 101, the other end of the fourth resistor R4 is connected to one end of the first light-emitting diode D1, and the other end of the first light-emitting diode D1 is connected to the second preset power supply.
[0075] In the embodiment of the present application, the main control circuit also includes a crystal oscillator circuit, a reset circuit, a status indication unit and a debugging interface, which ensure the normal operation of the main control chip, ensure the accuracy of digital signal acquisition, and improve the security of digital quantity acquisition.
[0076] Based on the above embodiment, the present application embodiment also provides a third digital quantity acquisition circuit, Figure 5 The third digital quantity acquisition circuit provided in the embodiment of the present application is shown in FIG. Figure 5 As shown in the above Figure 1 On the basis of, the communication circuit 300 includes: a communication chip 301, an electrostatic protection unit 302, an overcurrent protection unit 303 and a test terminal 304, the input pins CANH and CANL of the communication chip 301 are the input end IN of the communication circuit 300, the input pins CANH and CANL of the communication chip 301 are also connected to the electrostatic protection unit 302 and the overcurrent protection unit 303, the output pins D and R of the communication chip 301 are the output end OUT of the communication circuit 300, and the input pins CANH and CANL of the communication chip 301 are also connected to the test terminal 304.
[0077] Among them, the model of the communication chip 301 can be TJA1050, the communication chip 301 includes input pins CANH and CANL, output pins D and R, an electrostatic protection unit 302 protects the communication chip 301, an overcurrent protection unit 303 is used to prevent the input signal from being too large to damage the communication chip 301, and the test terminal 304 is used to test the signal input to the communication chip 301, or to detect the input signal when a digital quantity acquisition circuit fails.
[0078] For example, Figure 6 A schematic diagram of a communication circuit provided in an embodiment of the present application is shown in FIG. Figure 6As shown, the communication chip 301 may also include a communication pin RS, a reference voltage pin Vref, a ground pin GND and a voltage pin VCC. The communication pin RS and the ground pin GND are both grounded, the reference voltage pin Vref may be suspended, the voltage pin VCC is connected to a first preset power supply, the first preset power supply outputs a first voltage V1, the first voltage is 5 volts, the voltage pin VCC is also grounded through a fourth capacitor C4, and the fourth capacitor C4 may be 0.1 μF. The electrostatic protection unit 302 includes a first fuse F1 and a second fuse F2, the first input pin CANH of the communication chip 301 is connected to the first fuse F1, and the second input pin CANL of the communication chip 301 is connected to the second fuse F2. The overcurrent protection unit 303 includes a first bidirectional diode D2 and a second bidirectional diode D3, the first input pin CANH of the communication chip 301 is connected to the first bidirectional diode D2, the second input pin CANL of the communication chip 301 is connected to the second bidirectional diode D3, and the other ends of the first bidirectional diode D2 and the second bidirectional diode D3 are grounded. One end of the test terminal 304 is connected to the first input pin CANH through the fifth resistor R5, and the other end of the test terminal 304 is connected to the second input pin CANL. The test terminal 304 can be a double-pin 2.54mm test terminal, and the resistance value of the fifth resistor R5 can be 120 ohms. The first input pin CANH and the second input pin CANL of the communication chip 301 are grounded through the fifth capacitor C5, respectively, and the fifth capacitor C5 can be a 22P capacitor.
[0079] In an embodiment of the present application, the communication circuit includes a communication chip, an overcurrent protection unit, an electrostatic protection unit and a test terminal. The overcurrent protection unit and the electrostatic protection unit can ensure the safe operation of the communication chip. At the same time, the fault of the digital quantity acquisition circuit can be detected through the test terminal to ensure the normal operation of the digital quantity acquisition circuit.
[0080] Based on the above embodiments, the present application also provides a fourth digital quantity acquisition circuit, Figure 7 A schematic diagram of the structure of a fourth digital quantity acquisition circuit provided in an embodiment of the present application is shown in FIG. Figure 7 As shown in the above Figure 1 On the basis of, the digital quantity acquisition circuit also includes: a power supply circuit 600, the power supply circuit 600 includes: a first transformer unit 601 and a second transformer unit 602, the input end of the first transformer unit 601 is used to connect to a preset power supply unit, the output end of the first transformer unit 601 is used to output a first voltage V1, the output end of the first transformer unit 601 is also connected to the input end of the second transformer unit 602, and the output end of the second transformer unit 602 is used to output a second voltage V2.
[0081] The preset power supply unit can output a voltage of 12 volts, the first voltage V1 can be 5 volts, the second voltage V2 can be 3.3 volts, and the first voltage V1 and the second voltage V2 are used to power other power-consuming units in the digital quantity acquisition circuit.
[0082] For example, Figure 8 A schematic diagram of a power supply circuit provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the first transformer unit 601 includes: a first transformer chip, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a fourth diode D4, a fifth diode D5 and a first inductor L1. Among them, the sixth resistor R6 can be 100 kilo-ohms, the seventh resistor R7 can be 200 kilo-ohms, the eighth resistor R8 can be 68 kilo-ohms, the ninth resistor R9 can be 8.2 kilo-ohms, the tenth resistor R10 can be 44.2 kilo-ohms, the sixth capacitor C6 can be 220 μF, the seventh capacitor C7 can be 0.1 μF, the eighth capacitor C8 can be 221 F, the ninth capacitor C9 can be 221 F, the tenth capacitor C10 can be 470 μF, and the first inductor L1 can be 10 Uh. This application does not limit the above values, which are determined according to actual conditions. The model of the first transformer chip may be U8MP1584, and the first transformer chip may include a power pin VIN, an enable pin EN, a reference voltage pin REF, a ground pin GND, a bootstrap pin BST, a switch pin SW, a feedback pin FB, and a supplementary pin COMP. Among them, the power pin VIN and the reference voltage pin REF are respectively connected to the two ends of the preset power supply unit, the reference voltage pin REF is connected to the preset power supply unit through the seventh resistor R7, and the seventh resistor R7 is also grounded. The power pin VIN is connected to the preset power supply unit through the fourth diode D4, and the fourth diode D4 can be a voltage-stabilizing diode. The enable pin EN is connected to the power pin VIN through the sixth resistor R6, and the enable pin EN is also grounded through the sixth resistor R6 and the sixth capacitor C6. The bootstrap pin BST and the switch pin SW are connected through the seventh capacitor C7, and the switch pin SW is grounded through the fifth diode D5, and the fifth diode D5 can be a voltage-stabilizing diode. The switch pin SW is also connected to the first inductor L1 and the second transformer unit 602. The feedback pin FB is connected to the second transformer unit 602 through the tenth resistor R10, and one end of the first inductor L1 and the second transformer unit 602 connected to the second transformer unit 602 is grounded through the tenth capacitor C10, and the supplementary pin COMP is grounded through the ninth capacitor C9, and the supplementary pin COMP is also grounded through the eighth capacitor C8 and the eighth resistor R8.
[0083] The second transformer unit 602 includes: a second transformer chip, an eleventh capacitor C11, a twelfth capacitor C12 and a thirteenth capacitor C13. The second transformer chip can be AMS1117-3.3, and the second transformer chip includes: an input pin +VIN, an output pin +VOUT and a ground pin GND. The eleventh capacitor C11 can be 0.1μF, the twelfth capacitor C12 can be 47μF and the thirteenth capacitor C13 can be 01μF. This application does not limit the above values, which are determined according to actual conditions. The input pin +VIN is the input end of the second transformer unit 602, the input pin +VIN is grounded through the eleventh capacitor C11, and the output pin +VOUT is the output end of the second transformer unit 602, which is grounded through the twelfth capacitor C12 and the thirteenth capacitor C13 respectively.
[0084] In an embodiment of the present application, the power supply circuit includes a first transformer unit and a second transformer unit, which can convert the voltage output by the preset power supply unit into a first voltage and a second voltage, thereby meeting the power supply needs of the entire digital quantity acquisition circuit and ensuring the normal operation of the digital quantity acquisition circuit.
[0085] Based on the above embodiments, the present application also provides a fifth digital quantity acquisition circuit. Fig. 9 A schematic diagram of the structure of a fifth digital quantity acquisition circuit provided in an embodiment of the present application is shown in FIG. Figure 6 As shown in the above Figure 1 On the basis of this, a plurality of second pins in the second socket JP2 are all grounded.
[0086] In the embodiment of the present application, there may be four second pins in the second socket, and the embodiment of the present application does not limit this. The second pins are grounded to ensure the normal operation of the entire digital acquisition circuit.
[0087] Based on the above embodiments, the present application also provides a sixth digital quantity acquisition circuit, Fig.10 A schematic diagram of the structure of a sixth digital quantity acquisition circuit provided in an embodiment of the present application is shown in FIG. Fig.10 As shown in the above Figure 1 On the basis of, the code value circuit 500 includes: a multi-bit dip switch 501, and a plurality of groups of resistors 502, a plurality of first ends of the multi-bit dip switch 501 are all grounded, each of a plurality of second ends of the multi-bit dip switch 501 is respectively connected to a plurality of resistors in a group of resistors 502, and a plurality of second ends of the multi-bit dip switch 501 are connected to a plurality of second input pins of the main control chip 101. The multi-bit dip switch 501 and the plurality of groups of resistors 502 are used to number the digital quantity acquisition circuit.
[0088] For example, Fig.11 A schematic diagram of a code value circuit provided in an embodiment of the present application is shown in FIG. Fig.11As shown, the multi-bit DIP switch 501 may be an eight-bit DIP switch, and the corresponding resistor array 502 may be two, and four eleventh resistors R11 are arranged in each resistor array 502. The first ends of the eight-bit DIP switches are all grounded, and each of the multiple second ends of the eight-bit DIP switches is respectively connected to a group of multiple eleventh resistors R11 in the resistor array 502, and each of the multiple second ends of the eight-bit DIP switches is connected to multiple second input pins IN2 of the main control chip 101.
[0089] Another embodiment of the present application further provides a digital quantity acquisition circuit board, Fig.12 A schematic diagram of the structure of a digital quantity acquisition circuit board provided in an embodiment of the present application is shown in FIG. Fig.12 As shown, the digital quantity acquisition circuit board includes: an integrated circuit board, and a digital quantity acquisition circuit arranged on the integrated circuit board.
[0090] For example, Fig.13 A second structural diagram of the digital quantity acquisition circuit board provided in the embodiment of the present application is shown in FIG. Fig.13 As shown, the digital quantity acquisition circuit board includes a main control circuit 100, an acquisition circuit 200, a communication circuit 300, an output circuit 400, a code value circuit 500 and a power supply unit 600. The main control circuit includes: a main control chip 101. The acquisition circuit 200 includes: a photoelectric isolation unit 201 and a first socket JP1. The communication circuit 300 includes: a communication chip 301, an electrostatic protection unit 302, an overcurrent protection unit 303 and a test terminal 304. The output circuit 400 includes a second socket JP2. The code value circuit 500 includes: a multi-position dial switch 501 and a plurality of resistors 502. The power supply circuit 600 includes: a first transformer unit 601 and a second transformer unit 602.
[0091] Another embodiment of the present application further provides a digital quantity acquisition device, Fig.14 A schematic diagram of the structure of a digital quantity acquisition device provided in an embodiment of the present application is shown in FIG. Fig.14 As shown, the digital quantity acquisition device at least includes: a digital quantity acquisition circuit board 2000.
[0092] Another embodiment of the present application further provides a digital quantity acquisition method, which is applied to the main control chip in the above digital quantity acquisition circuit. Fig.15 A flowchart of a digital quantity acquisition method provided in an embodiment of the present application is shown in FIG. Fig.15 As shown, the method includes:
[0093] Step 1501: Acquire a first digital signal from a computer device transmitted by a communication circuit.
[0094] The first digital signal is a digital signal sent by a computer device, and is used to determine specific collected data of a digital quantity collection circuit. The computer device may be any electronic device with digital processing capability, and the present application embodiment does not limit this.
[0095] Step 1502: determine that the digital quantity acquisition circuit is in the digital quantity acquisition mode based on the information of the first preset byte position in the first digital signal, determine the address code of the digital quantity acquisition circuit from the second preset byte position in the first digital signal, determine the frame end from the third preset byte position in the first digital signal, and determine the digital quantity input status data from each data bit between the second preset byte position and the third preset byte position in the first digital signal.
[0096] Optionally, the information of the first preset byte bit is the frame header of the digital signal. When the information of the first preset byte bit is 0x90, it can be determined that the digital quantity acquisition circuit is in the digital quantity acquisition mode. The second preset byte bit is the address code of the digital quantity acquisition circuit, that is, to determine the specific digital quantity acquisition circuit. The third preset byte bit determines the frame tail, which is used to indicate the end of acquisition. The frame tail can be composed of the last data byte in the data bit and the identification data frame. Each data bit between the second preset byte bit and the third preset byte bit in the first digital signal determines the digital quantity input state data. The data bits can be 4. When the digital quantity acquisition circuit has 24 groups of acquisition signals, the four data respectively indicate six digital quantity acquisition states, which are used to indicate the specific acquisition signal of the digital quantity acquisition circuit.
[0097] Step 1503: Generate data volume acquisition status data based on the multi-channel digital quantity input signals transmitted by the acquisition circuit.
[0098] The state data of the data quantity acquisition is used to indicate the data acquisition status of the digital quantity acquisition circuit.
[0099] Step 1504, fill the indication information corresponding to the digital quantity acquisition mode into the first preset byte position, fill the address code into the second preset byte position, fill the data quantity acquisition status data into each data position, and also fill the indication information of the preset frame end into the third preset byte position to generate a second digital signal.
[0100] Optionally, the first preset byte bit is the frame header of the digital signal. When the information of the first preset byte bit is 0x90, it can be determined that the digital quantity acquisition circuit is in the digital quantity acquisition mode. The second preset byte bit is the address code of the digital quantity acquisition circuit, that is, it determines the specific digital quantity acquisition circuit. The third preset byte bit is used to determine the specific acquisition signal of the digital quantity acquisition circuit. The third preset byte bit can be four data bits. When the digital quantity acquisition circuit has 24 groups of acquisition signals, the first three data bits respectively indicate 8 groups of digital quantity acquisition states, and the last data bit is a reserved byte.
[0101] Step 1505: Transmit the second digital signal to the computer device through the communication circuit.
[0102] Optionally, the second digital signal is transmitted to a computer device through a communication circuit. The computer device can determine the specific digital quantity acquisition state of the digital quantity acquisition circuit based on the first digital signal and the second digital signal, thereby determining whether the acquisition is correct, thereby ensuring the accuracy of digital quantity acquisition.
[0103] The present application provides a digital quantity acquisition method, which obtains a first digital signal from a computer device transmitted by a communication circuit; determines that the digital quantity acquisition circuit is in a digital quantity acquisition mode according to information of a first preset byte position in the first digital signal, determines the address code of the digital quantity acquisition circuit from the second preset byte position in the first digital signal, determines the frame end from the third preset byte position in the first digital signal, and also determines digital quantity input state data from each data bit between the second preset byte position and the third preset byte position in the first digital signal; generates data quantity acquisition state data based on multiple digital quantity input signals transmitted by the acquisition circuit; fills the indication information corresponding to the digital quantity acquisition mode into the first preset byte position, fills the address code into the second preset byte position, fills the data quantity acquisition state data into each data bit, and also fills the indication information of the preset frame end into the third preset byte position to generate a second digital signal; and transmits the second digital signal to the computer device through the communication circuit. The computer device controls the sending of the first digital signal, the digital quantity acquisition circuit, and determines the specific acquisition result of the digital quantity acquisition circuit through the second digital signal, thereby ensuring the accuracy of the digital quantity circuit acquisition and improving the security of the digital quantity acquisition circuit.
[0104] Based on the above embodiment, the present application also provides another digital quantity acquisition method: Fig.16 A flow chart of another digital quantity acquisition method provided in an embodiment of the present application is shown as follows: Fig.16 As shown, based on the above steps 1501 to 1505, the method includes:
[0105] Step 1601: Acquire a third digital signal from a computer device transmitted by a communication circuit.
[0106] The third digital signal is a digital signal sent by the computer device and is used to determine specific collection data of the digital quantity collection circuit.
[0107] Step 1602: determine that the digital quantity acquisition circuit is in the digital quantity output mode based on the information of the first preset byte position in the third digital signal, determine the address code of the digital quantity acquisition circuit from the second preset byte position in the third digital signal, determine the frame end from the third preset byte position in the third digital signal, and determine the first digital quantity control data from each data bit between the second preset byte position and the third preset byte position in the third digital signal.
[0108] Optionally, the information of the first preset byte bit is the frame header of the digital signal. When the information of the first preset byte bit is 0x97, it can be determined that the digital quantity acquisition circuit is in the digital quantity output mode. The second preset byte bit is the address code of the digital quantity acquisition circuit, that is, to determine the specific digital quantity acquisition circuit. The third preset byte bit determines the frame tail, which is used to indicate the end of acquisition. The frame tail can be composed of the last data byte in the data bit and the identification data frame. Each data bit between the second preset byte bit and the third preset byte bit in the first digital signal determines the first digital quantity control data. The data bits can be 4. When the digital quantity acquisition circuit has 16 groups of output signals, the first two groups of data bits are used to control the first eight groups of output signals and the last eight groups of output signals respectively, and the last two data bits are reserved data bits.
[0109] Step 1603: Generate second data volume control data based on the multiple digital output signals.
[0110] The second data quantity control data is used to indicate the data output status of the digital quantity acquisition circuit.
[0111] Step 1604, fill the indication information corresponding to the digital output mode into the first preset byte position, fill the address code into the second preset byte position, fill the second data volume control data into each data bit, and also fill the indication information of the preset frame end into the third preset byte position to generate a fourth digital signal.
[0112] Optionally, optionally, the first preset byte bit is the frame header of the digital signal. When the information of the first preset byte bit is 0x97, it can be determined that the digital quantity acquisition circuit is in the digital quantity output mode. The second preset byte bit is the address code of the digital quantity acquisition circuit, that is, it determines the specific digital quantity acquisition circuit. The third preset byte bit is used to determine the specific acquisition signal of the digital quantity acquisition circuit. The third preset byte bit can be four data bits. When the digital quantity acquisition circuit has 16 groups of output signals, the first two data bits respectively indicate 8 groups of digital quantity output states, and the last data bit is a reserved byte.
[0113] Step 1605: Transmit the fourth digital signal to the computer device through the communication circuit.
[0114] Optionally, the fourth digital signal is transmitted to a computer device through a communication circuit. The computer device can determine the specific digital quantity output state of the digital quantity acquisition circuit based on the third digital signal and the fourth digital signal, thereby determining whether the output is correct, thereby ensuring the accuracy of the digital quantity output.
[0115] Based on the same inventive concept, a digital quantity acquisition device corresponding to the digital quantity acquisition method is also provided in the embodiment of the present application. Since the principle of solving the problem by the device in the embodiment of the present application is similar to the above-mentioned digital quantity acquisition method in the embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.
[0116] Fig.17 A schematic diagram of the structure of a digital quantity acquisition device provided in an embodiment of the present application is shown in the figure. The device includes:
[0117] An acquisition module 1701 is used to acquire a first digital signal from a computer device transmitted by a communication circuit;
[0118] The determination module 1702 is used to determine that the digital quantity acquisition circuit is in the digital quantity acquisition mode according to the information of the first preset byte position in the first digital signal, determine the address code of the digital quantity acquisition circuit from the second preset byte position in the first digital signal, determine the frame end from the third preset byte position in the first digital signal, and determine the digital quantity input state data from each data bit between the second preset byte position and the third preset byte position in the first digital signal;
[0119] A generating module 1703, used for generating data volume acquisition state data based on the multi-channel digital quantity input signals transmitted by the acquisition circuit;
[0120] The filling module 1704 is used to fill the indication information corresponding to the digital quantity acquisition mode into the first preset byte position, fill the address code into the second preset byte position, fill the data quantity acquisition status data into each data position, and also fill the indication information of the preset frame end into the third preset byte position to generate a second digital signal;
[0121] The transmission module 1705 is used to transmit the second digital signal to the computer device through the communication circuit.
[0122] In a possible implementation manner, the acquisition module 1701 is further configured to: acquire a third digital signal from the computer device transmitted by the communication circuit;
[0123] In a possible implementation, the determination module 1702 is further used to: determine that the digital quantity acquisition circuit is in the digital quantity output mode according to information of the first preset byte position in the third digital signal, determine the address code of the digital quantity acquisition circuit from the second preset byte position in the third digital signal, determine the frame end from the third preset byte position in the third digital signal, and determine the first digital quantity control data from each data bit between the second preset byte position and the third preset byte position in the third digital signal;
[0124] In a possible implementation manner, the generating module 1703 is further configured to: generate second data volume control data based on the multi-channel digital quantity output signals;
[0125] In a possible implementation manner, the filling module 1704 is further used to: fill the indication information corresponding to the digital quantity output mode into the first preset byte position, fill the address code into the second preset byte position, fill the second data quantity control data into each data bit, and also fill the indication information of the preset frame end into the third preset byte position to generate a fourth digital signal;
[0126] In a possible implementation manner, the transmission module 1705 is further configured to: transmit the fourth digital signal to the computer device via the communication circuit.
[0127] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference may be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.
[0128] The present application also provides a computer device, Fig.18 A schematic diagram of a computer device structure provided in an embodiment of the present application is shown in FIG. Fig.18 As shown, the computer device includes: a processor 1801 and a memory 1802. The memory 1802 stores machine-readable instructions executable by the processor 1801. When the computer device 1800 is running, the processor 1801 communicates with the memory 1802, and when the machine-readable instructions are executed by the processor 1801, the steps of the above-mentioned digital quantity acquisition method are performed.
[0129] The embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned digital quantity acquisition method are executed.
[0130] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0131] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or part of the technical solution that contributes to the prior art or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program code.
[0132] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.
Claims
1. A digital quantity acquisition circuit, characterized in that: The digital quantity acquisition circuit includes: a main control circuit, an acquisition circuit, a communication circuit, an output circuit and a code value circuit; wherein the main control circuit includes: a main control chip, the acquisition circuit includes: a first socket, a plurality of photoelectric isolation units, and the output circuit includes: a second socket; The input end of the communication circuit is used to receive the acquisition control signal input by the computer device, and the output end of the communication circuit is connected to the communication pin of the main control chip; The first socket is used to receive the collected multi-channel digital input signals, the first socket is respectively connected to the first ends of the plurality of photoelectric isolation units, and the second ends of the plurality of photoelectric isolation units are all connected to the plurality of first input pins of the main control chip; The multiple output pins of the main control chip are connected to the multiple first pins of the second socket, the second socket is also used to connect to an external device, and the multiple second input pins of the main control circuit are also connected to the code value circuit.
2. The digital quantity acquisition circuit according to claim 1, characterized in that: The main control circuit also includes: a crystal oscillator circuit, a reset circuit, a status indication unit and a debugging interface, wherein the crystal oscillator circuit is connected to the clock pin of the main control chip, the reset circuit is connected to the reset pin of the main control chip, the status indication unit is connected to the preset input and output pins of the main control chip, and the two third input pins of the main control unit are also connected to the debugging interface.
3. The digital quantity acquisition circuit according to claim 1, characterized in that: The communication circuit includes: a communication chip, an electrostatic protection unit, an overcurrent protection unit and a test terminal. The input pin of the communication chip is the input end of the communication circuit, and the input pin of the communication chip is also connected to the electrostatic protection unit and the overcurrent protection unit. The output pin of the communication chip is the output end of the communication circuit, and the input pin of the communication chip is also connected to the test terminal.
4. The digital quantity acquisition circuit according to claim 1, characterized in that: The digital quantity acquisition circuit also includes: a power supply circuit, which includes: a first transformer unit and a second transformer unit, the input end of the first transformer unit is used to connect to a preset power supply unit, the output end of the first transformer unit is used to output a first voltage, the output end of the first transformer unit is also connected to the input end of the second transformer unit, and the output end of the second transformer unit is used to output a second voltage.
5. The digital quantity acquisition circuit according to claim 1, characterized in that: The plurality of second pins in the second socket are all grounded.
6. The digital quantity acquisition circuit according to claim 1, characterized in that: The code value circuit includes: a multi-bit dip switch and a plurality of groups of resistors, wherein the plurality of first ends of the multi-bit dip switch are all grounded, each of the plurality of second ends of the multi-bit dip switch is respectively connected to a plurality of resistors in a group of resistors, and the plurality of second ends of the multi-bit dip switch are connected to a plurality of second input pins of the main control chip.
7. A digital quantity acquisition circuit board, characterized in that: The digital quantity acquisition circuit board comprises: an integrated circuit board, and the digital quantity acquisition circuit described in any one of claims 1 to 6 arranged on the integrated circuit board.
8. A digital quantity acquisition device, characterized in that: The digital quantity acquisition device at least comprises: the digital quantity acquisition circuit board as described in claim 7 above.
9. A digital quantity communication method, characterized in that: A main control chip used in a digital quantity acquisition circuit as described in any one of claims 1 to 6, wherein the method comprises: Acquire a first digital signal from a computer device transmitted by a communication circuit; Determine that the digital quantity acquisition circuit is in a digital quantity acquisition mode according to information of a first preset byte bit in the first digital signal, determine an address code of the digital quantity acquisition circuit from a second preset byte bit in the first digital signal, determine a frame end from a third preset byte bit in the first digital signal, and determine digital quantity input state data from each data bit between the second preset byte bit and the third preset byte bit in the first digital signal; Generate data volume acquisition status data based on multiple digital quantity input signals transmitted by the acquisition circuit; Fill the indication information corresponding to the digital quantity acquisition mode into the first preset byte position, fill the address code into the second preset byte position, fill the data quantity acquisition status data into each data position, and also fill the indication information of the preset frame end into the third preset byte position to generate a second digital signal; The second digital signal is transmitted to the computer device through the communication circuit.
10. The method according to claim 9, characterized in that The method further comprises: Acquire a third digital signal from the computer device transmitted by the communication circuit; Determine, according to information of the first preset byte bit in the third digital signal, that the digital quantity acquisition circuit is in a digital quantity output mode, determine the address code of the digital quantity acquisition circuit from the second preset byte bit in the third digital signal, determine the frame end from the third preset byte bit in the third digital signal, and determine the first digital quantity control data from each data bit between the second preset byte bit and the third preset byte bit in the third digital signal; Based on the multiple digital quantity output signals, generating second data quantity control data; Fill the indication information corresponding to the digital quantity output mode into the first preset byte position, fill the address code into the second preset byte position, fill the second data quantity control data into each data bit, and also fill the indication information of the preset frame end into the third preset byte position, to generate a fourth digital signal; The fourth digital signal is transmitted to the computer device through the communication circuit.