A high-precision bandgap reference circuit without operational amplifier

Abstract

This invention discloses an op-amp-free high-precision bandgap reference circuit, belonging to the field of analog circuits. It generates a high-precision reference voltage and detects the completion of the reference voltage startup, outputting an enable signal to control the internal startup logic of the analog circuit, thus completing the timing control of the circuit startup process. The op-amp-free high-precision bandgap reference circuit includes a startup circuit, a reference core circuit, and a reference detection circuit. The startup circuit provides a startup current to the bandgap reference, enabling the reference core circuit to start working. The reference core circuit generates a high-precision reference output voltage. When the bandgap reference successfully starts up, the reference detection circuit outputs a high signal to enable subsequent modules. This invention offers a lower starting operating voltage; it eliminates op-amp clamping, avoiding offset introduced by op-amps and the need for high op-amp gain; and its simple circuit structure allows for a low-power design of the entire bandgap reference.

Description

Technical Field

[0001] This invention relates to the field of analog circuit technology, and in particular to a high-precision bandgap reference circuit without operational amplifiers. Background Technology

[0002] Bandgap voltage reference circuits are widely used in analog and mixed-signal circuits, such as DC-DC converters, PLLs, voltage tuners, voltmeters, ammeters, and bias circuits. Bandgap voltage reference circuits typically provide high-precision, low-temperature-coefficient voltage or current to other modules, and their performance directly or indirectly determines the performance indicators of the entire integrated circuit system.

[0003] The basic principle of a bandgap reference voltage circuit is to add a voltage with a negative temperature coefficient to a voltage with a positive temperature coefficient with appropriate weights. Figure 1 This is one implementation of a bandgap reference voltage circuit in the prior art, including an operational amplifier A0, resistors R1 and R2, three PNP transistors and three PMOS transistors. A current mirror implemented by PMOS transistors M1 and M2 forms a negative feedback loop with the operational amplifier A0, thereby making the voltages at nodes A and B equal. The difference between the base and emitter voltages of transistor Q1... The difference between the base and emitter voltages of transistor Q2 Under the same current, the different numbers of transistors Q1 and Q2 connected in parallel result in different current densities for Q1 and Q2, thus causing the voltage drop across resistor R1 to be... and difference , It is directly proportional to absolute temperature, and its expression is as follows:

[0004] (1)

[0005] in The ratio of the current density of transistor Q1 to that of a single transistor Q2. and These represent the currents flowing through Q1 and a single transistor Q2, respectively, where N is the number of transistors Q2 connected in parallel.

[0006] Therefore, the current flowing through resistor R1 It is an electric current that is proportional to the absolute temperature.

[0007] Current With current , There is a mirror image relationship; all three are equal. Final current. A positive temperature voltage and a negative temperature voltage are generated through resistor R2. Summation generates a reference voltage :

[0008] (2)

[0009] As can be seen from equation (2), a reference voltage with a small temperature coefficient can be obtained by reasonably selecting the ratio of R2 to R1 and the value of N. However, the existing method of generating a reference voltage using this bandgap reference voltage circuit has some shortcomings: the circuit requires a differential operational amplifier, which has input offset. It will affect the temperature coefficient of the reference voltage and the reference accuracy under PVT; it requires high gain of the op-amp, which increases the difficulty of circuit design and the power consumption of the circuit; the minimum operating voltage is relatively high, making it difficult to operate at a lower starting voltage. Summary of the Invention

[0010] The purpose of this invention is to provide a high-precision bandgap reference circuit without op-amps to solve the problems of offset error, reference voltage accuracy, and minimum operating voltage of traditional op-amps.

[0011] To solve the above technical problems, the present invention provides a high-precision bandgap reference circuit without operational amplifiers, which generates a high-precision reference voltage and detects the reference voltage to complete the start-up of the output enable signal to control the internal start-up logic of the analog circuit, thereby completing the timing control of the circuit start-up process.

[0012] The operational amplifier-free high-precision bandgap reference circuit includes a startup circuit, a reference core circuit, and a reference detection circuit; wherein...

[0013] The startup circuit provides a startup current to the bandgap reference, enabling the core circuit of the reference to start working.

[0014] The reference core circuit generates a high-precision reference output voltage;

[0015] Once the bandgap reference has been successfully started, the reference detection circuit outputs a high signal to enable subsequent modules.

[0016] In one embodiment, the startup circuit includes a first current source, a first N-type MOS transistor, and a first NPN transistor; the tail end of the first current source is connected to the drain of the first N-type MOS transistor, the gate of the first N-type MOS transistor is shorted to its own drain, the source of the first N-type MOS transistor is connected to the collector of the first NPN transistor, the base of the first NPN transistor is shorted to its own collector, and the emitter of the first NPN transistor is grounded.

[0017] In one embodiment, the reference core circuit includes a second N-type MOSFET, a second NPN transistor, a third N-type MOSFET, a third NPN transistor, a first P-type MOSFET, a fourth NPN transistor, a second P-type MOSFET, a third P-type MOSFET, a fourth N-type MOSFET, a fifth N-type MOSFET, a fifth NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a capacitor;

[0018] The drain of the second N-type MOSFET is simultaneously connected to the gate of the first P-type MOSFET, the gate of the second P-type MOSFET, the drain of the second P-type MOSFET, and the drain of the fourth N-type MOSFET. The source of the second N-type MOSFET is simultaneously connected to the source of the third N-type MOSFET, the beginning of the first resistor, and the beginning of the fourth resistor. The end of the first resistor is simultaneously connected to the beginning of the second resistor and the base of the second NPN transistor. The end of the second resistor is simultaneously connected to the beginning of the third resistor and the collector of the second NPN transistor. The emitter of the second NPN transistor is grounded.

[0019] The drain of the third N-type MOSFET is connected to the power supply. The source of the third N-type MOSFET is simultaneously connected to the first terminal of the fourth resistor, the first terminal of the first resistor, and the source of the second N-type MOSFET. The tail of the fourth resistor is simultaneously connected to the first terminal of the fifth resistor, the tail of the capacitor, the base of the fourth NPN transistor, and the reference detection circuit. The tail of the fifth resistor is connected to the collector of the third NPN transistor. The base of the third NPN transistor is connected to the tail of the third resistor. The emitter of the third NPN transistor is connected to the first terminal of the sixth resistor. The tail of the sixth resistor is grounded.

[0020] The source of the first P-type MOSFET is connected to the power supply. The drain of the first P-type MOSFET is simultaneously connected to the gate of the third N-type MOSFET, the beginning of the capacitor, the gate of the fourth N-type MOSFET, the collector of the fourth NPN transistor, and the gate of the sixth N-type MOSFET. The emitter of the fourth NPN transistor is grounded.

[0021] The source of the second P-type MOSFET is connected to the power supply. The gate of the second P-type MOSFET is simultaneously connected to the drain of the second P-type MOSFET, the gate of the third P-type MOSFET, the gate of the first P-type MOSFET, and the drain of the fourth N-type MOSFET. The source of the third P-type MOSFET is connected to the power supply. The drain of the third P-type MOSFET is simultaneously connected to the drain and gate of the fifth N-type MOSFET. The source of the fourth N-type MOSFET is simultaneously connected to the source of the fifth N-type MOSFET and the collector of the fifth NPN transistor. The emitter of the fourth NPN transistor is grounded. The emitter of the fifth NPN transistor is grounded.

[0022] In one embodiment, the reference detection circuit includes a fourth P-type MOS transistor, a fifth P-type MOS transistor, a sixth P-type MOS transistor, a seventh P-type MOS transistor, a sixth N-type MOS transistor, a sixth NPN transistor, a first inverter, a second inverter, and a seventh resistor;

[0023] The source of the fourth P-type MOSFET is connected to the power supply. The gate of the fourth P-type MOSFET is connected to the drain of the fourth P-type MOSFET, the gate of the fifth P-type MOSFET, the gate of the sixth P-type MOSFET, and the drain of the sixth N-type MOSFET. The source of the sixth N-type MOSFET is connected to the collector of the sixth NPN transistor. The emitter of the sixth NPN transistor is connected to the first terminal of the seventh resistor. The last terminal of the seventh resistor is grounded.

[0024] The source of the fifth P-type MOSFET is connected to the power supply, and its drain is simultaneously connected to the drain of the seventh P-type MOSFET, the input of the first inverter, and the collector of the seventh NPN transistor. The source of the sixth P-type MOSFET is connected to the power supply, and its drain is connected to the source of the seventh P-type MOSFET. The gate of the seventh P-type MOSFET is simultaneously connected to the output of the first inverter and the input of the second inverter. The emitter of the seventh NPN transistor is grounded.

[0025] The gate of the first N-type MOS transistor is connected to the gate of the second N-type MOS transistor; the base of the first NPN transistor is connected to the base of the seventh NPN transistor.

[0026] The gate of the sixth N-type MOSFET is simultaneously connected to the gate of the third N-type MOSFET, the gate of the fourth N-type MOSFET, the drain of the first P-type MOSFET, the collector of the fourth NPN transistor, and the first terminal of the capacitor; the base of the sixth NPN transistor is simultaneously connected to the base of the fourth NPN transistor, the tail of the fourth resistor, the first terminal of the fifth resistor, and the tail of the capacitor.

[0027] In one embodiment, the common terminal of the source of the third N-type MOS transistor, the first terminal of the fourth resistor, the first terminal of the first resistor, and the source of the second N-type MOS transistor is the output reference voltage signal VBG_1.2V of the bandgap reference; the output terminal of the second inverter is the output enable signal VBG_OK_1 of the reference voltage detection circuit.

[0028] The present invention provides a high-precision bandgap reference circuit without operational amplifiers, which has the following gain effects:

[0029] (1) The bandgap reference circuit of the present invention has a low minimum operating voltage of 1.5V, which provides wider voltage applicability in analog circuits;

[0030] (2) This invention has no op-amp clamping, no op-amp gain and bandwidth requirements, and a simple design structure;

[0031] (3) This invention avoids input offset caused by operational amplifier differential input mismatch, resulting in higher accuracy of the output reference voltage;

[0032] (4) The branch current of the entire bandgap reference is an nA level operating current, which can realize the low power consumption design of the circuit. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a bandgap reference voltage circuit in the prior art;

[0034] Figure 2 This is a structural block diagram of the bandgap reference circuit provided by the present invention;

[0035] Figure 3 This is a schematic diagram of the bandgap reference circuit provided by the present invention. Detailed Implementation

[0036] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the operational amp-free high-precision bandgap reference circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0037] This invention provides a high-precision bandgap reference circuit without operational amplifiers, capable of generating a high-precision 1.2V reference voltage and detecting the completion of the reference voltage startup to output an enable signal that controls the internal startup logic of the analog circuit, thus completing the timing control of the circuit startup process. This invention's bandgap reference circuit fully realizes the startup of the reference circuit, the generation of the reference voltage, and the power-on timing control of subsequent modules.

[0038] like Figure 2 As shown, the op-amp-free high-precision bandgap reference circuit of the present invention includes a startup circuit 101, a reference core circuit 102, and a reference detection circuit 103. The startup circuit 101 provides a startup current to the bandgap reference, enabling the reference core circuit 102 to start operating; the reference core circuit 102 generates a high-precision reference output voltage of 1.2V; when the bandgap reference has successfully started, the reference detection circuit 103 outputs a high signal to enable subsequent modules.

[0039] like Figure 3As shown, the startup circuit 101 includes a first current source IDC1, a first N-type MOSFET MN1, and a first NPN transistor Q1. The tail end of the first current source IDC1 is connected to the drain of the first N-type MOSFET MN1. The gate of the first N-type MOSFET MN1 is shorted to its own drain. The source of the first N-type MOSFET MN1 is connected to the collector of the first NPN transistor Q1. The base of the first NPN transistor Q1 is shorted to its own collector. The emitter of the first NPN transistor Q1 is grounded.

[0040] The reference core circuit 102 includes a second N-type MOSFET MN2, a second NPN transistor Q2, a third N-type MOSFET MN3, a third NPN transistor Q3, a first P-type MOSFET MP1, a fourth NPN transistor Q4, a second P-type MOSFET MP2, a third P-type MOSFET MP3, a fourth N-type MOSFET MN4, a fifth N-type MOSFET MN5, a fifth NPN transistor Q5, resistors R1, R2, R3, R4, R5, and R6, and a capacitor C1.

[0041] The drain of the second N-type MOSFET MN2 is simultaneously connected to the gate of the first P-type MOSFET MP1, the gate of the second P-type MOSFET MP2, the drain of the second P-type MOSFET MP2, and the drain of the fourth N-type MOSFET MN4. The source of the second N-type MOSFET MN2 is simultaneously connected to the source of the third N-type MOSFET MN3, the beginning of resistor R1, and the beginning of resistor R4. The end of resistor R1 is simultaneously connected to the beginning of resistor R2 and the base of the second NPN transistor Q2. The end of resistor R2 is simultaneously connected to the beginning of resistor R3 and the collector of the second NPN transistor Q2. The emitter of the second NPN transistor Q2 is grounded.

[0042] The drain of the third N-type MOSFET MN3 is connected to the power supply. The source of the third N-type MOSFET MN3 is simultaneously connected to the first terminal of resistor R4, the first terminal of resistor R1, and the source of the second N-type MOSFET MN2. The tail terminal of resistor R4 is simultaneously connected to the first terminal of resistor R5, the tail terminal of capacitor C1, the base of the fourth NPN transistor Q4, and the base of the sixth NPN transistor Q6. The tail terminal of resistor R5 is connected to the collector of the third NPN transistor Q3. The base of the third NPN transistor Q3 is connected to the tail terminal of resistor R3. The emitter of the third NPN transistor Q3 is connected to the first terminal of resistor R6. The tail terminal of resistor R6 is grounded.

[0043] The source of the first P-type MOSFET MP1 is connected to the power supply. The drain of the first P-type MOSFET MP1 is simultaneously connected to the gate of the third N-type MOSFET MN3, the beginning of capacitor C1, the gate of the fourth N-type MOSFET MN4, the collector of the fourth NPN transistor Q4, and the gate of the sixth N-type MOSFET MN6. The emitter of the fourth NPN transistor Q4 is grounded.

[0044] The source of the second P-type MOSFET MP2 is connected to the power supply. The gate of the second P-type MOSFET MP2 is simultaneously connected to the drain of the second P-type MOSFET MP2, the gate of the third P-type MOSFET MP3, the gate of the first P-type MOSFET MP1, and the drain of the fourth N-type MOSFET MN4. The source of the third P-type MOSFET MP3 is connected to the power supply. The drain of the third P-type MOSFET MP3 is simultaneously connected to the drain and gate of the fifth N-type MOSFET MN5. The source of the fourth N-type MOSFET MN4 is simultaneously connected to the source of the fifth N-type MOSFET MN5 and the collector of the fifth NPN transistor Q5. The emitter of the fourth NPN transistor Q4 is grounded. The emitter of the fifth NPN transistor Q5 is grounded.

[0045] The reference detection circuit 103 includes a fourth P-type MOSFET MP4, a fifth P-type MOSFET MP5, a sixth P-type MOSFET MP6, a seventh P-type MOSFET MP7, a sixth N-type MOSFET MN6, a sixth NPN transistor Q6, a first inverter INV1, a second inverter INV2, and a resistor R7.

[0046] The source of the fourth P-type MOSFET MP4 is connected to the power supply. The gate of the fourth P-type MOSFET MP4 is simultaneously connected to the drain of the fourth P-type MOSFET MP4, the gate of the fifth P-type MOSFET MP5, the gate of the sixth P-type MOSFET MP6, and the drain of the sixth N-type MOSFET MN6. The source of the sixth N-type MOSFET MN6 is connected to the collector of the sixth NPN transistor Q6. The emitter of the sixth NPN transistor Q6 is connected to the first end of resistor R7. The last end of resistor R7 is grounded.

[0047] The source of the fifth P-type MOSFET MP5 is connected to the power supply. The drain of the fifth P-type MOSFET MP5 is simultaneously connected to the drain of the seventh P-type MOSFET MP7, the input terminal of the first inverter INV1, and the collector of the seventh NPN transistor Q7. The source of the sixth P-type MOSFET MP6 is connected to the power supply. The drain of the sixth P-type MOSFET MP6 is connected to the source of the seventh P-type MOSFET MP7. The gate of the seventh P-type MOSFET MP7 is simultaneously connected to the output terminal of the first inverter INV1 and the input terminal of the second inverter INV2. The emitter of the seventh NPN transistor Q7 is grounded.

[0048] The gate of the first N-type MOS transistor MN1 is connected to the gate of the second N-type MOS transistor MN2; the base of the first NPN transistor Q1 is connected to the base of the seventh NPN transistor Q7.

[0049] The gate of the sixth N-type MOSFET MN6 is simultaneously connected to the gate of the third N-type MOSFET MN3, the gate of the fourth N-type MOSFET MN4, the drain of the first P-type MOSFET MP1, the collector of the fourth NPN transistor Q4, and the beginning of capacitor C1; the base of the sixth NPN transistor Q6 is simultaneously connected to the base of the fourth NPN transistor Q4, the end of resistor R4, the beginning of resistor R5, and the end of capacitor C1.

[0050] The common terminal of the source of the third N-type MOSFET MN3, the beginning of resistor R4, the beginning of resistor R1, and the source of the second N-type MOSFET MN2 is the output reference voltage signal VBG_1.2V for the bandgap reference; the output terminal of the second inverter INV2 is the output enable signal VBG_OK_1 for the reference voltage detection circuit.

[0051] The detailed working process of this invention is as follows:

[0052] When Figure 3 As shown, the startup current IDC1 in the startup circuit 101 generates a current that flows through the subsequent reference core circuit 102. The voltage difference ΔV between the base of the second NPN transistor Q2 and the base of the third NPN transistor Q3 in the core reference circuit 102 is... BE The current flows to resistors R2 and R6. Because of the transistor's amplification factor β, the current through resistor R3 is a small current of 1 / β. Therefore, the voltage across resistor R3 can be ignored in the calculation. Resistor R3 serves as a second-order compensation for the bandgap reference.

[0053] The number of second NPN transistors Q2 is 1, the number of fifth NPN transistors Q5 is 1, the number of second P-type MOSFETs MP2 is 1, the number of first P-type MOSFETs MP1 is 4, the number of third P-type MOSFETs MP3 is 3, and the number of fourth NPN transistors MP4 is 1. During normal operation, the IPTAT current generated by the second NPN transistor Q2, after passing through the op-amp's load and being mirrored by a current mirror, reaches the same current as the fourth NPN transistor Q4. Because the number of second NPN transistors Q2 and fourth NPN transistors Q4 is also equal, this clamps the voltage at node A (between resistors R1 and R2) and node B (between resistors R4 and R5) to be equal, resulting in equal IPTAT currents generated by the two branches of the reference core circuit. A 1.2V reference voltage is generated at the common node of the terminals of resistor R4, resistor R1, and the source of the third P-type MOSFET MP3. The voltages in various voltage domains can then be obtained through resistor dividers. The minimum operating voltage for this structure to generate the reference voltage output is 1.5V.

[0054] The number of NPN transistors Q1 is 1, and the number of NPN transistors Q7 is 1. When the bandgap reference is working normally, the voltage at node B will increase, enabling current to flow through the sixth NPN transistor Q6 and the sixth N-type MOSFET MN6. The current mirrors of the fourth P-type MOSFET MP4 and the fifth P-type MOSFET MP5 will cause the voltage at the input node of the first inverter INV1 to rise. That is, after the bandgap reference is started, the reference detection circuit 103 will output the start-up completion enable signal VBG_OK_1 for the second inverter INV2, turning on the subsequent working modules in the analog circuit power supply system, ensuring the power-on startup sequence in the analog circuit. The hysteresis control of the enable signal VBG_OK_1 by the seventh P-type MOSFET MP7 ensures stable signal output, unaffected by power supply voltage fluctuations.

[0055] The op-amp-free high-precision bandgap reference circuit of this invention features a lower starting operating voltage; it eliminates op-amp clamping, thus avoiding offset introduced by op-amps and the need for high op-amp gain; its simple circuit structure allows for low-power design of the entire bandgap reference; it exhibits excellent compatibility with analog circuit power system modules, and its timing control eliminates power-up issues. This invention is characterized by high precision, low power consumption, strong practicality, and simple structure, making it suitable for a wide range of applications in analog circuits.

[0056] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high precision bandgap reference circuit without operational amplifier, characterized in that, It generates a high-precision reference voltage and detects the reference voltage to complete the start-up process. The output enable signal controls the internal startup logic of the analog circuit, thus completing the timing control of the circuit startup process. The operational amplifier-free high-precision bandgap reference circuit includes a startup circuit, a reference core circuit, and a reference detection circuit; wherein... The startup circuit provides a startup current to the bandgap reference, enabling the core circuit of the reference to start working. The reference core circuit generates a high-precision reference output voltage; When the bandgap reference has been successfully started, the reference detection circuit outputs a high signal to enable subsequent modules. The startup circuit includes a first current source, a first N-type MOS transistor, and a first NPN transistor; the tail end of the first current source is connected to the drain of the first N-type MOS transistor, the gate of the first N-type MOS transistor is shorted to its own drain, the source of the first N-type MOS transistor is connected to the collector of the first NPN transistor, the base of the first NPN transistor is shorted to its own collector, and the emitter of the first NPN transistor is grounded; The reference core circuit includes a second N-type MOSFET, a second NPN-type transistor, a third N-type MOSFET, a third NPN-type transistor, a first P-type MOSFET, a fourth NPN-type transistor, a second P-type MOSFET, a third P-type MOSFET, a fourth N-type MOSFET, a fifth N-type MOSFET, a fifth NPN-type transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a capacitor; The drain of the second N-type MOSFET is simultaneously connected to the gate of the first P-type MOSFET, the gate of the second P-type MOSFET, the drain of the second P-type MOSFET, and the drain of the fourth N-type MOSFET. The source of the second N-type MOSFET is simultaneously connected to the source of the third N-type MOSFET, the beginning of the first resistor, and the beginning of the fourth resistor. The end of the first resistor is simultaneously connected to the beginning of the second resistor and the base of the second NPN transistor. The end of the second resistor is simultaneously connected to the beginning of the third resistor and the collector of the second NPN transistor. The emitter of the second NPN transistor is grounded. The drain of the third N-type MOSFET is connected to the power supply. The source of the third N-type MOSFET is simultaneously connected to the first terminal of the fourth resistor, the first terminal of the first resistor, and the source of the second N-type MOSFET. The tail of the fourth resistor is simultaneously connected to the first terminal of the fifth resistor, the tail of the capacitor, the base of the fourth NPN transistor, and the reference detection circuit. The tail of the fifth resistor is connected to the collector of the third NPN transistor. The base of the third NPN transistor is connected to the tail of the third resistor. The emitter of the third NPN transistor is connected to the first terminal of the sixth resistor. The tail of the sixth resistor is grounded. The source of the first P-type MOSFET is connected to the power supply. The drain of the first P-type MOSFET is simultaneously connected to the gate of the third N-type MOSFET, the beginning of the capacitor, the gate of the fourth N-type MOSFET, the collector of the fourth NPN transistor, and the gate of the sixth N-type MOSFET. The emitter of the fourth NPN transistor is grounded. The source of the second P-type MOSFET is connected to the power supply. The gate of the second P-type MOSFET is simultaneously connected to the drain of the second P-type MOSFET, the gate of the third P-type MOSFET, the gate of the first P-type MOSFET, and the drain of the fourth N-type MOSFET. The source of the third P-type MOSFET is connected to the power supply. The drain of the third P-type MOSFET is simultaneously connected to the drain and gate of the fifth N-type MOSFET. The source of the fourth N-type MOSFET is simultaneously connected to the source of the fifth N-type MOSFET and the collector of the fifth NPN transistor. The emitter of the fourth NPN transistor is grounded. The emitter of the fifth NPN transistor is grounded.

2. The op-amp-free high-precision bandgap reference circuit as described in claim 1, characterized in that, The reference detection circuit includes a fourth P-type MOSFET, a fifth P-type MOSFET, a sixth P-type MOSFET, a seventh P-type MOSFET, a sixth N-type MOSFET, a sixth NPN transistor, a first inverter, a second inverter, and a seventh resistor; The source of the fourth P-type MOSFET is connected to the power supply. The gate of the fourth P-type MOSFET is connected to the drain of the fourth P-type MOSFET, the gate of the fifth P-type MOSFET, the gate of the sixth P-type MOSFET, and the drain of the sixth N-type MOSFET. The source of the sixth N-type MOSFET is connected to the collector of the sixth NPN transistor. The emitter of the sixth NPN transistor is connected to the first terminal of the seventh resistor. The last terminal of the seventh resistor is grounded. The source of the fifth P-type MOSFET is connected to the power supply, and the drain of the fifth P-type MOSFET is simultaneously connected to the drain of the seventh P-type MOSFET, the input terminal of the first inverter, and the collector of the seventh NPN transistor; the source of the sixth P-type MOSFET is connected to the power supply, and the drain of the sixth P-type MOSFET is connected to the source of the seventh P-type MOSFET. The gate of the seventh P-type MOSFET is connected to the output of the first inverter and the input of the second inverter; the emitter of the seventh NPN-type transistor is grounded. The gate of the first N-type MOS transistor is connected to the gate of the second N-type MOS transistor; the base of the first NPN transistor is connected to the base of the seventh NPN transistor. The gate of the sixth N-type MOSFET is simultaneously connected to the gate of the third N-type MOSFET, the gate of the fourth N-type MOSFET, the drain of the first P-type MOSFET, the collector of the fourth NPN transistor, and the first terminal of the capacitor; the base of the sixth NPN transistor is simultaneously connected to the base of the fourth NPN transistor, the tail of the fourth resistor, the first terminal of the fifth resistor, and the tail of the capacitor.

3. The op-amp-free high-precision bandgap reference circuit as described in claim 2, characterized in that, The common terminal of the source of the third N-type MOS transistor, the first terminal of the fourth resistor, the first terminal of the first resistor, and the source of the second N-type MOS transistor is the output reference voltage signal VBG_1.2V of the bandgap reference. The output of the second inverter is the output enable signal VBG_OK_1 of the reference voltage detection circuit.

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