Physical layout method, system, device, and storage medium for off switchable power module

Abstract

Embodiments of the application disclose a physical layout method, system, device and storage medium of a turn-off power module, and relate to the technical field of chip low-power consumption design, which facilitates to improve layout efficiency and flexibility. The method comprises the following steps: based on a chip physical design file and a power design intention description file, performing a global layout operation on the turn-off power module in the case that a physical voltage domain is not defined in advance, to obtain an initial layout result, the initial layout result comprising coordinates of logic units; dividing a layout area of the turn-off power module into a plurality of power pixel blocks; determining the power pixel blocks in which the logic units are located according to the coordinates, and counting the number proportion of always-on logic units and turn-off logic units in each power pixel block; according to the number proportion, assigning an initial power type to each power pixel block, and generating distributed physical voltage domains corresponding to the always-on logic units and the turn-off logic units, respectively. The application is applicable to the scenario of power-gated physical layout.

Description

Technical Field

[0001] This application relates to the field of low-power chip design technology, and in particular to a physical layout method, system, device and storage medium for a power-off module. Background Technology

[0002] Power gating is a key technology in low-power chip design, reducing static power consumption by cutting off power to idle modules. This technology requires logically dividing the circuit into constant and turn-off domains, and establishing corresponding physical voltage domains during physical implementation to constrain the circuit cell layout.

[0003] Current mainstream physical layout methods require backend engineers to manually predefine the boundaries and ranges of the physical voltage domains before proceeding with layout and routing. However, reasonable voltage domain division requires comprehensive consideration of multiple factors such as timing, routing, and power consumption. Manually pre-defining and fixing the physical voltage domains leads to cumbersome layout process iterations, limited performance optimization, and an inability to effectively handle complex layout scenarios with a mix of constant power and turn-off circuits. Summary of the Invention

[0004] In view of this, embodiments of this application provide a physical layout method, system, device, and storage medium for a power-off module, which facilitates improved layout efficiency and flexibility.

[0005] In a first aspect, embodiments of this application provide a physical layout method for a power-offable power module, comprising: performing a global layout operation on the power-offable power module based on a chip physical design file and a power design intent description file without pre-defining a physical voltage domain to obtain an initial layout result, wherein the initial layout result includes the coordinates of logic units, and the logic units include constant-power logic units and power-offable logic units; dividing the layout area of ​​the power-offable power module into multiple power pixel blocks; determining the power pixel block where the logic unit is located according to the coordinates, and calculating the ratio of the number of constant-power logic units and power-offable logic units in each power pixel block; assigning an initial power type to each power pixel block according to the ratio of the number, and generating a distributed physical voltage domain corresponding to the constant-power logic units and power-offable logic units defined in the power design intent description file.

[0006] According to a specific implementation of an embodiment of this application, after assigning an initial power type to each power pixel block, the method includes: comparing the initial power type of each logic unit in the power pixel block with the power type defined in the power design intent description file; if the comparison results are inconsistent, adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located, so that the initial power type of the logic unit is consistent with the defined power type; and determining the boundary of the distributed physical voltage domain based on the power types determined after the adjustment of all power pixel blocks.

[0007] According to a specific implementation of an embodiment of this application, adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located includes: if the logic unit is a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then the logic unit is replaced with a dual-track unit; if the logic unit is another logic unit that is not a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then the power type of the power pixel block is adjusted to be consistent with the power type of the logic unit.

[0008] According to a specific implementation of an embodiment of this application, adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located further includes: if there is a power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then the logic unit is moved to the power pixel block with the same power type.

[0009] According to a specific implementation of an embodiment of this application, after determining the boundary of the distributed physical voltage domain, the method includes: checking and correcting the positions of logic units based on the boundary of the distributed physical voltage domain, so as to place all logic units within the correct power pixel block; and inserting power isolation units at the boundary of the distributed physical voltage domain corresponding to the constant power logic units and the turn-off logic units, according to the corrected logic unit positions.

[0010] According to one specific implementation of this application, the size of the power pixel block is the same as the size of a preset minimum power line repeating unit.

[0011] Secondly, embodiments of this application provide a physical layout system for a power-off module, comprising: an initial layout unit, configured to perform a global layout operation on the power-off module based on a chip physical design file and a power design intent description file, without pre-defining a physical voltage domain, to obtain an initial layout result, wherein the initial layout result includes the coordinates of logic units, and the logic units include constant-power logic units and power-off logic units; a partitioning unit, configured to divide the layout area of ​​the power-off module into multiple power pixel blocks; a statistics unit, configured to determine the power pixel block where the logic unit is located according to the coordinates, and to count the proportion of constant-power logic units and power-off logic units in each power pixel block; and a generation unit, configured to assign an initial power type to each power pixel block according to the proportion, and to generate distributed physical voltage domains corresponding to the constant-power logic units and power-off logic units defined in the power design intent description file.

[0012] According to a specific implementation of an embodiment of this application, the generation unit includes: a comparison module, configured to compare the initial power type of each logic unit in the power pixel block with the power type defined in the power design intent description file of the logic unit; an adjustment module, configured to adjust the position of the logic unit or adjust the power type of the power pixel block where the logic unit is located if the comparison results are inconsistent, so that the initial power type of the logic unit is consistent with the defined power type; and a determination module, configured to determine the boundary of the distributed physical voltage domain based on the power type determined after the adjustment of all power pixel blocks.

[0013] According to a specific implementation of an embodiment of this application, the adjustment module includes: a replacement submodule, configured to replace the logic unit with a dual-track unit if the logic unit is a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located; and an adjustment submodule, configured to adjust the power type of the power pixel block to be consistent with the power type of the logic unit if the logic unit is another logic unit that is not a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located.

[0014] According to a specific implementation of an embodiment of this application, the adjustment module is further configured to: if there is a power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then move the logic unit to the power pixel block with the same power type.

[0015] According to a specific implementation of an embodiment of this application, the generation unit further includes: a maintenance module, used to check and correct the positions of logic units based on the boundaries of the distributed physical voltage domain, so as to place all logic units within the correct power pixel block; and an insertion module, used to insert power isolation units at the boundaries of the distributed physical voltage domain corresponding to the constant power logic units and the turn-off logic units, according to the corrected positions of the logic units.

[0016] Thirdly, embodiments of this application provide an electronic device, which includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the physical layout method of the power-off module provided in any embodiment of this application.

[0017] Fourthly, embodiments of this application provide a computer-readable storage medium storing one or more computer programs, which, when executed by one or more processors, implement the physical layout method of the power-off module described in any of the first aspects.

[0018] The physical layout method, system, device, and storage medium for a power-off module provided in this application propose a process of global layout followed by dynamic generation of a distributed physical voltage domain. Compared with traditional methods, this solution eliminates the need for manual, static physical voltage domain division before layout, effectively avoiding the extended layout cycle caused by repeated iterations of voltage domain boundary modifications, and significantly improving layout efficiency. Simultaneously, by dividing the layout area into power pixel blocks and automatically aggregating them based on the actual distribution of logic units after layout, a distributed voltage domain is generated. This allows the voltage domain shape to closely match the physical layout and design intent of the circuit, giving the physical layout process greater flexibility. On the one hand, the layout tool can prioritize optimization based on timing, power consumption, and area, without being limited by preset voltage domain boundaries. On the other hand, the system can adaptively handle complex layout scenarios where constant-power units and power-off units are mixed, dispersed, or have ambiguous boundaries, without requiring special avoidance in the front-end design, reducing overall design constraints. In summary, this application, through the above-mentioned process refactoring and automated aggregation mechanism, improves layout efficiency while enhancing the adaptability and optimization potential of the physical layout, thereby comprehensively improving layout efficiency and flexibility. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating the physical layout method of the power-off module provided in this application embodiment; Figure 2 This is a schematic diagram of the layout area provided in an embodiment of this application; Figure 3 This is a schematic diagram of the layout prior to constant-current polymerization provided in an embodiment of this application; Figure 4 A schematic diagram of the layout after constant-current polymerization provided in an embodiment of this application; Figure 5 A schematic diagram of the physical layout of a turn-off power module for multi-stage constant-current aggregation provided in an embodiment of this application. Figure 6 A schematic diagram of a pixel block for allocating an initial power type, provided in an embodiment of this application; Figure 7 Another schematic diagram of a pixel block with an assigned initial power type provided in an embodiment of this application; Figure 8 Another schematic diagram of a pixel block with an assigned initial power type provided in an embodiment of this application; Figure 9 Another schematic diagram of a pixel block with an assigned initial power type provided in an embodiment of this application; Figure 10 This is a schematic diagram illustrating the specific implementation process of the automatic distributed constant power aggregation algorithm provided in the embodiments of this application; Figure 11 A schematic diagram of the physical layout system of the power-off module provided in the embodiments of this application; Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0022] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0023] In a first aspect, embodiments of this application provide a physical layout method for a power-off module, which facilitates improved layout efficiency and flexibility.

[0024] like Figure 1 The physical layout method for a power-off module provided in this application includes: S11. Based on the chip physical design file and power design intent description file, perform a global layout operation on the power-offable power module without pre-defining the physical voltage domain to obtain an initial layout result, wherein the initial layout result includes the coordinates of logic units, and the logic units include constant power logic units and power-offable logic units. In existing physical implementation processes for turn-off power modules, it is necessary to predefine and set strictly corresponding physical voltage domain boundaries during the layout planning stage based on the logical power domain division declared in the power design intent description file. The power design intent description file is typically a Unified Power Format (UPF) file. These predefined physical regions are then directly imported into the subsequent global placement tool as rigid constraints. When the tool performs cell placement, all cells must be forcibly placed within the predefined physical regions corresponding to their power types, severely limiting the degrees of freedom and solution space of the placement algorithm when optimizing timing, power consumption, and routing congestion. To address this issue, this application proposes a physical placement method for turn-off power modules.

[0025] Specifically, the process begins by reading in two fundamental files: the chip physical design file and the power design intent description file. In some cases, the chip physical design file includes, but is not limited to, the synthesized gate-level netlist, physical libraries for standard cells and macrocells, timing libraries, and design constraint files. These files define the logic function, physical form, and timing requirements of the circuit. The power design intent description file defines the low-power architecture of the layout in a formal language, including power management strategies such as which logic cells belong to constant power domains and which belong to turn-off domains. However, during the file reading phase, the power design intent description file is only read as a logical label for the power attributes of the cells, and is not converted into any area constraints on the physical layout. Subsequently, without predefining any physical voltage domain, a global placement operation is performed on the power-off module. At this point, the placement tool places all logic units within the chip layout area based solely on traditional optimization objectives such as timing, area, and line length, resulting in an initial placement result that tends to be optimized in terms of electrical performance. The logic units include constant-power logic units and power-off logic units identified by UPF. The key output of the initial placement result is the precise physical coordinates of each logic unit, reflecting the true and natural distribution of units with different power attributes in physical space under the current optimization objectives. This provides an objective data basis for subsequent on-demand generation rather than predefining the physical voltage domain.

[0026] S12. Divide the layout area of ​​the power-off module into multiple power pixel blocks; After obtaining the initial layout results, all logic cells have been optimized and placed on the chip layout according to their timing and physical characteristics. However, the problem of how to classify the logic constant power and turn-off cells and map them to separate power supply areas in the actual layout remains unsolved.

[0027] Therefore, this application introduces data transformation and spatial discretization steps, specifically, Figure 2 For a schematic diagram of the division of the layout area provided in the embodiments of this application, please refer to... Figure 2 The entire layout area of ​​the power-off module is physically divided into a matrix composed of countless small, regular grids. Each grid cell is called a power pixel block. In some cases, the division of multiple power pixel blocks is not arbitrary. The scale of the division is directly related to the chip manufacturing process and the underlying power planning. This ensures that any subsequent power network routing adjustments can be accurately implemented on the grid points allowed by the manufacturing process. At the same time, the area of ​​a pixel block also approximately represents the smallest physical granularity at which the back-end tools can perform power gating control.

[0028] This application divides the power pixel blocks into multiple blocks, making each block an atomic unit that can be independently assigned constant or turn-off properties, thus laying a precise and manufacturable spatial analysis foundation for subsequent refined and adaptive power domain synthesis.

[0029] S13. Determine the power pixel block where the logic unit is located based on the coordinates, and count the ratio of the number of constant-power logic units to the number of turn-off logic units in each power pixel block. After completing the mapping from continuous layout space to discrete power pixel blocks, each logic unit obtains precise coordinates in the initial layout, and the coordinates can become a data link connecting physical location and power attributes.

[0030] Specifically, based on the coordinates of each logic unit in the initial layout result, the system systematically traverses and determines which specific power pixel block each logic unit belongs to, placing each logic unit in the corresponding grid where its coordinates lie. This creates a detailed list of all logic units for each power pixel block. Based on this list, for each power pixel block, the specific number of constant-power logic units and turn-off logic units contained within it is counted, and the proportion of each type within the pixel block is calculated. In some cases, the proportion not only objectively reveals, for the first time, the true distribution and mixing degree of different power types of units in physical space after free layout without physical voltage domain constraints, but also directly drives the initial power type assignment for each pixel block based on the proportion statistics. For example, if the proportion of constant-power units in a pixel block exceeds 50%, the pixel block is temporarily marked as a constant-power type.

[0031] Therefore, the proportion of unit types within each pixel block output by this application is an indispensable, data-driven decision bridge connecting the free layout result and the generation of the distributed voltage domain, laying a quantitative foundation based on layout facts for the subsequent intelligent and adaptive generation of the physical voltage domain boundary.

[0032] S14. Based on the stated quantity ratio, assign an initial power type to each power pixel block and generate a distributed physical voltage domain corresponding to the constant power logic unit and the turn-off logic unit defined in the power design intent description file.

[0033] After counting the number of constant and turn-off logic units within each power pixel block based on unit coordinates, an initial power type needs to be assigned to all pixel blocks according to the calculated proportion of unit types within each block. In some cases, each power pixel block can be temporarily assigned to the power type with the higher proportion within it when assigning the initial power type. For example, a pixel block with 70% constant units will be marked as constant, while a pixel block dominated by turn-off units will be marked as turn-off. However, this initial assignment may result in units whose power type does not match the initial type of the pixel block. In some cases, this inconsistency can be gradually corrected by moving neighboring units, replacing them with dual-track units, or flipping the pixel block type. Finally, after the algorithm converges, the set of all pixel block power types automatically forms a distributed physical voltage domain that is completely corresponding to the power design intent description file definition and actually exists on the physical layout. These voltage domains are physically presented as a spatial distribution pattern in which multiple discrete, non-continuous constant power regions and turn-off regions are intertwined. Their specific boundaries and shapes are completely determined by the layout results and the algorithm dynamically, thereby achieving an adaptive match between physical implementation and logical intent at a fine granular level.

[0034] In summary, this application, through the aforementioned automatic distributed constant power aggregation method, automatically analyzes the spatial distribution of constant power units after layout is completed, divides the physical layout into fine-grained power pixel blocks, and dynamically assigns power types, such as constant power or turn-off, to these pixel blocks according to the unit distribution ratio, ultimately forming multiple dispersed and discontinuous constant voltage domain regions, thereby achieving automated and adaptive mapping from logical power intent to physical implementation.

[0035] Figure 3 This is a schematic diagram of the layout before constant-current polymerization provided in an embodiment of this application. Figure 4 This is a schematic diagram of the layout after constant-current polymerization provided in an embodiment of this application, for comparison. Figure 3 and Figure 4 It can be clearly observed that after applying the automatic distributed constant voltage aggregation algorithm, the morphology of the physical voltage domain has undergone a fundamental transformation. Before aggregation, the distribution of constant voltage units was scattered and unorganized, without forming a clear power supply area. After aggregation, the algorithm successfully and intelligently identifies and aggregates these scattered constant voltage units and their adjacent spaces, forming... Figure 4 The multiple discrete, irregularly shaped yellow regions shown are distributed constant-voltage physical voltage domains. These yellow regions are not one or a few continuous large blocks, but rather a large number of scattered island-like regions of varying sizes that enclose constant-voltage unit clusters throughout the layout. The remaining regions not covered by yellow are uniformly defined as the power-off physical voltage domains.

[0036] This application no longer relies on manually pre-delineating large continuous regions. Instead, it generates a better voltage domain topology from the bottom up and adaptively based on the actual distribution of cells after layout. This distributed form can better adapt to the actual location of logic cells, minimize the disturbance to the layout optimization results, and ensure that each constant-power logic cell can be correctly included in a constant-power region. This provides an accurate and efficient physical basis for subsequent power network implementation and low-power function verification, achieving higher layout freedom, better performance optimization potential, and stronger adaptability to complex layouts.

[0037] Figure 5 A schematic diagram of the physical layout of the turn-off power module for multi-stage constant-current aggregation provided in this application embodiment is shown below. Figure 5 ,include: S101, Read in the chip physical design file and power supply design intent description file; After completing the layout planning, the two core inputs required for physical implementation are read in: the chip physical design file and the power design intent description file (UPF). Unlike traditional methods, only the logic power attributes defined in the UPF are read at this stage, without pre-creating or defining any physical voltage domains, thus removing key constraints for subsequent free layout.

[0038] S102, Perform layout operations using electronic design automation tools; The placement tool performs global placement operations on all logic cells, including constant-power cells and turn-off cells, without any physical voltage domain boundary constraints. This allows the placement engine to optimize purely based on objectives such as timing, power consumption, line length, and congestion, thereby obtaining an initial placement result with better electrical performance.

[0039] S103, First-time automatic distributed constant-current aggregation; Based on the optimized layout results generated by S102, the automatic distributed constant power aggregation process is initiated for the first time. Through a series of operations such as dividing power pixel blocks, statistical unit distribution, dynamic allocation and adjustment of power types, a distributed physical voltage domain matching the current layout is automatically generated for the first time, and the power network is adjusted accordingly.

[0040] S104, Clock Tree Synthesis and Optimization; Based on the generated initial voltage domain, clock tree synthesis and related optimization are performed. In some cases, the density and distribution of local cells may change due to the insertion and movement of clock buffers and clock gating units during clock tree synthesis and related optimization.

[0041] S105, Second Automatic Distributed Constant Power Aggregation; In response to the layout changes brought about by the S104 clock tree synthesis, constant voltage aggregation is performed again, so that the physical voltage domain can adaptively adjust according to the clock network optimization results, ensuring that the voltage domain partitioning is always consistent with the latest physical layout state.

[0042] S106. Cabling and Optimization; After the second automatic distributed constant power aggregation, the layout is subjected to detailed signal routing and subsequent timing, crosstalk and other optimizations. The routing process will introduce more metal resources and cell fine-tuning, which will further change the physical state of the layout.

[0043] S107, Third Automatic Distributed Constant Power Aggregation and Final Wiring Adjustment.

[0044] After routing optimization is completed, a final constant-current aggregation operation is performed to conduct a final calibration of the voltage domain. Subsequently, based on the final determined voltage domain boundaries, the power network and potentially affected signal routing are adjusted and repaired to ensure that the design fully meets manufacturability requirements, and the process ends.

[0045] The physical layout method for a power-off module provided in this application proposes a process of first global layout and then dynamically generating a distributed physical voltage domain. Compared with traditional methods, this solution eliminates the need for manual, static physical voltage domain division before layout, effectively avoiding the extended layout cycle caused by repeated iterations and modifications to the voltage domain boundaries, and significantly improving layout efficiency. Simultaneously, by dividing the layout area into power pixel blocks and automatically aggregating them based on the actual distribution of logic units after layout, a distributed voltage domain is generated. This allows the voltage domain shape to closely match the physical layout and design intent of the circuit, giving the physical layout process greater flexibility. On the one hand, the layout tool can prioritize optimization based on timing, power consumption, and area, without being limited by preset voltage domain boundaries. On the other hand, the system can adaptively handle complex layout scenarios where constant-power units and power-off units are mixed, dispersed, or have ambiguous boundaries, without requiring special avoidance in the front-end design, reducing overall design constraints. In summary, this application, through the above-mentioned process refactoring and automated aggregation mechanism, improves layout efficiency while enhancing the adaptability and optimization potential of the physical layout, thereby comprehensively improving layout efficiency and flexibility.

[0046] In some embodiments, after assigning an initial power type to each power pixel block, the method includes: comparing the initial power type of each logic unit in the power pixel block with the power type defined in the power design intent description file; if the comparison results are inconsistent, adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located, so that the initial power type of the logic unit is consistent with the defined power type; and determining the boundary of the distributed physical voltage domain based on the power types determined after the adjustment of all power pixel blocks.

[0047] Figure 6 A schematic diagram of a pixel block for allocating an initial power type provided in an embodiment of this application, such as... Figure 6 After assigning the initial power type to each power pixel block based on the unit proportion, there are still many locally contradictory power types in the entire layout area. Many logic units are placed in pixel blocks that do not conform to their specified power type, such as small white squares. To resolve this contradiction, this application will perform a correction after assigning the initial power type to each power pixel block.

[0048] Specifically, firstly, for each logic unit in a power pixel block, the initial power type of its pixel block is compared one by one with the power type explicitly defined in the power design intent description file, thereby systematically identifying all logic units with inconsistent power types. Subsequently, for these identified inconsistent logic units, their positions or the power type of their respective power pixel blocks are adjusted. Once all inconsistent logic units have been adjusted and placed within power pixel blocks consistent with the power type defined by the UPF, based on the finally determined, stable, and consistent power types of all pixel blocks, the boundary line between the constant-power region and the turn-off region on the physical layout is accurately calculated, thereby determining the specific boundary of the distributed physical voltage domain.

[0049] In some embodiments, adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located includes: if the logic unit is a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then the logic unit is replaced with a dual-track unit; if the logic unit is another logic unit that is not a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then the power type of the power pixel block is adjusted to be consistent with the power type of the logic unit.

[0050] After identifying logic units with inconsistent power supply types through comparison, targeted strategies need to be adopted for correction based on the type characteristics of the logic unit and the local environment.

[0051] Specifically, Figure 7 Another schematic diagram of a pixel block for allocating initial power type provided in an embodiment of this application, as shown below. Figure 7 The green squares represent logic units with inconsistent power types, and these logic units are either buffers or inverters. When there are no pixel blocks with the same power type as the logic unit within a preset neighborhood, the logic unit is not moved or its pixel block type is changed. Instead, the buffer or inverter unit is replaced from the standard unit library with a functionally equivalent dual-track unit. The dual-track unit integrates a power isolation structure and is designed to work normally in both constant power and power-off domains. Therefore, it can be legally and functionally placed in a pixel block with a power type that does not match its original type. This efficiently resolves the placement conflict of such logic units with minimal layout changes and controllable area costs. Meanwhile, the preset neighborhood range is a search radius predefined according to process and design rules, which can cover several adjacent pixel blocks.

[0052] Figure 8 Another schematic diagram of a pixel block for allocating initial power type provided in an embodiment of this application, as shown below. Figure 8 Purple squares represent logic units with inconsistent power types, and these logic units are other logic units besides buffers or inverters. In this case, the logic unit encompasses the vast majority of combinational logic gates, sequential units, and other functional modules. Because their logic functions and circuit structures are usually tightly bound to a specific power domain, they cannot be adapted to different power environments through simple unit replacement. In some examples, the power type of the power pixel block where the logic unit is located can be directly flipped and adjusted from its initial allocation to be completely consistent with the power type defined for that logic unit in the UPF. That is, in the global power type distribution map, to meet the power supply requirements of the logic unit, the power attributes of a small area are dynamically redefined.

[0053] This application achieves a balance between correction efficiency and electrical correctness through a classification and processing strategy based on cell type and local environment. For a large number of buffers or inverters with relatively simple structures, in-situ replacement avoids time-consuming global layout reconstruction and unpredictable timing effects. Secondly, it ensures the integrity of the layout function. For critical logic cells, by ensuring the absolute correctness of their power supply environment, it eliminates the risk of functional failure caused by power domain mismatch. Finally, it supports the adaptability of distributed voltage domain generation, so that the final physical voltage domain boundary can accurately fit the actual needs of each cell, laying a solid foundation for generating high-quality and high-reliability physical layout results.

[0054] In some embodiments, adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located further includes: if there is a power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then the logic unit is moved to the power pixel block with the same power type.

[0055] When correcting units with inconsistent power types, in addition to replacing or flipping pixel block types, when a logic unit with an inconsistent power type is identified, it is also necessary to first check whether there are any power pixel blocks with the same power type in the preset neighborhood around the power pixel block where it is located. If the check result is that such a power pixel block exists, it indicates that the logic unit is very close to a correct target area. Figure 9 Another schematic diagram of a pixel block for allocating initial power type provided in an embodiment of this application, as shown below. Figure 9 The red square represents the logical unit of the adjacent power pixel block that has the same power type as its own. At this time, the logical unit can be taken out from its current position and moved to the nearby pixel block with the same power type. This movement operation is completed by the legal layout engine of the backend tool within a local range, ensuring that the unit placement conforms to all physical design rules and directly solving the power attribute contradiction between the unit and the placement environment.

[0056] This application minimizes the disturbance to the overall design quality caused by layout adjustments through the above operations. Compared with the additional area and power consumption that may be introduced by replacing the cell type, or the chain of power network modifications that may be caused by flipping the pixel block type, simply moving the cell maintains the electrical characteristics and timing model of the original cell, and has the least impact on the timing, power consumption and area of ​​the chip. It solves most of the local misalignment problems caused by the initial statistical allocation, and is a key link to ensure that the algorithm runs efficiently while maintaining the original optimization quality of the layout results.

[0057] In some embodiments, after determining the boundary of the distributed physical voltage domain, the method includes: checking and correcting the logic unit positions based on the boundary of the distributed physical voltage domain to place all logic units within the correct power pixel block; and inserting power isolation units at the boundary of the distributed physical voltage domain corresponding to the constant power logic units and the turn-off logic units, according to the corrected logic unit positions.

[0058] After calculating the boundaries of the distributed physical voltage domain, the physical layout clearly delineates the constant voltage and turn-off regions. However, to ensure the functional correctness and reliability of the layout after manufacturing, physical closure operations are still required.

[0059] Specifically, firstly, based on the finalized voltage domain boundaries, a final compliance check and correction is needed for the positions of all logic cells. Although previous correction steps have addressed most issues, it is still necessary to ensure that, in the final layout, each logic cell is indeed placed in the correct power pixel block within the physical voltage domain corresponding to its own power type. In some cases, the final compliance check and correction may involve fine-tuning a very small number of cells that were still at the boundary or conflicting positions in previous adjustments. This is typically achieved by invoking the legalization function of the placement tool, automatically completing the final placement of the cells while strictly adhering to the constraints of the new voltage domain boundaries, thereby achieving complete physical isolation of the power domain.

[0060] Next, at the boundary between the constant power domain and the turn-off domain, a power isolation unit is inserted. In some cases, the power isolation unit is a physical structure that ensures the safety of the power gating function and prevents the signal current from flowing back into the constant power domain when the turn-off domain is powered off. Based on the corrected unit position and clear voltage domain boundary information, a specified type and number of power isolation units are automatically inserted at the boundary positions adjacent to all constant power and turn-off regions, thereby achieving electrical isolation of signals between the two power domains at the circuit level.

[0061] This application, through the above two steps, ensures the integrity and manufacturability from the logic power intent to the physical layout implementation. The final location correction ensures that each transistor can receive the correct power supply from its power network, avoiding circuit failure caused by power mismatch from the source. The automatic insertion of isolation units ensures the safety and reliability of power-off operations, preventing potential risks such as leakage and level conflicts. This allows the dynamic power management function to be safely implemented in the actual chip, which is a key sealing link for the final physical realization of the low-power design intent.

[0062] In some examples, the size of the power pixel block is the same as the size of a preset minimum power line repeating unit.

[0063] In this scheme, the size of the power pixel block is the same as the size of the preset minimum power line repeating unit. The minimum power line repeating unit refers to the smallest pitch or grid unit in the chip manufacturing layout design where the power network (VDD) and ground network (VSS) can be regularly and repeatedly routed in both horizontal and vertical directions. The area covered by each power pixel block on the physical layout corresponds precisely to the smallest addressable unit where the power network can perform a complete routing operation or form an independent power grid. Aligning the analysis grid and the power grid at the basic unit scale ensures that any subsequent power domain partitioning decisions based on the pixel block can find a corresponding, process-permitted routing scheme in the actual physical implementation of the power network, without creating abstract areas that cannot be implemented.

[0064] This application anchors the power pixel block size to the smallest power line repeating unit, ensuring that the distributed physical voltage domain output by the algorithm is geometrically manufacturable, and its boundary can be aligned with the power line start and end points recognized by the manufacturing process. Secondly, since the voltage domain boundary coincides with the power network mesh, the disconnection, connection, or rerouting of power lines can be completed efficiently and unambiguously based on the same coordinate system. This facilitates the subsequent automatic correction of the power lines in the physical voltage domain, avoids the gap between algorithm decision-making and physical implementation, and is the cornerstone of the engineering practicality of the entire automated process.

[0065] In summary, Figure 10 This is a schematic diagram illustrating the specific implementation process of the automatic distributed constant power aggregation algorithm provided in the embodiments of this application. See also... Figure 10 ,include: S201. Construct an initial power pixel map and divide it into power pixel blocks; The entire chip layout area is physically divided into a matrix composed of countless regular grids. Each grid is called a power pixel block, and its size is consistent with the smallest power line repeating unit in the process, thereby ensuring that all subsequent operations are feasible at the manufacturing level.

[0066] S202, Initial scanning module, allocates power pixel blocks; Analyze the initial layout results, determine the power pixel block where each logic unit is located based on its coordinates, and count the ratio of constant-power logic units to turn-off logic units in each pixel block. Temporarily assign each pixel block to the power type with the higher current ratio to form an initial but contradictory power type distribution map.

[0067] S203, a circuit unit that processes adjacent correct power supply pixel blocks; For logic units with inconsistent power types identified in S202, first check whether there is a pixel block with the same power type as the logic unit in the preset neighborhood around it. If there is, move the logic unit to the correct pixel block.

[0068] S204, handle buffer or inverter units that are far from the correct power supply pixel block; If the logic unit with inconsistent power type is a buffer or inverter unit, and there is no correct pixel block to move in, the ordinary logic unit is replaced with a dual-track unit. Due to its internal power isolation design, the dual-track unit can be legally placed in a pixel block of the current power type, thereby resolving the contradiction by unit replacement and avoiding changes to the local power structure.

[0069] S205, Processing non-buffer or inverter units that are far from the correct power supply pixel block; For other logic units with inconsistent power types that cannot be easily replaced, such as logic gates and flip-flops, the power type of the power pixel block where the logic unit is located is directly flipped to the same power type as the unit.

[0070] S206. Based on the final version of the power pixel block, perform automatic legalization layout; After completing all the above classification adjustments, a stable and final power pixel block type distribution map was obtained, which is the final voltage domain division. Based on this, the validity function of the backend layout engine was invoked to fine-tune the final position of all logic units, ensuring that each unit is strictly located within the pixel block corresponding to its power type, satisfying all physical design rules.

[0071] S207, Power lines that automatically correct physical voltage domain.

[0072] Finally, based on the final voltage domain physical boundary determined in S206, the power supply network routing is automatically generated or corrected. The routing includes correctly connecting or disconnecting the corresponding power rails at the boundary between the constant power and the turn-off domain, ensuring that the final layout has a manufacturable power network that fully matches the aggregation result.

[0073] This embodiment fully demonstrates an automated decision-making closed loop driven by data and processed in layers. It begins with a macro-statistical analysis of the overall layout and, through a series of progressively refined correction steps, including moving neighboring units, replacing specific unit types, and locally adjusting power area attributes, successfully transforms the freely optimized logical unit distribution into a physically accurate and self-consistent distributed voltage domain partition. The entire process ultimately achieves automatic connection from high-level design intent to low-level manufacturable layout, and is a core algorithm that can replace human experience and achieve high-quality physical layout.

[0074] Secondly, embodiments of this application provide a physical layout system for a power-off module, which facilitates improved layout efficiency and flexibility.

[0075] like Figure 11 As shown, embodiments of this application also provide a physical layout system for a power-off module, including: an initial layout unit 31, a partitioning unit 32, a statistics unit 33, and a generation unit 34.

[0076] The initial layout unit 31 is used to perform a global layout operation on the power-off module based on the chip physical design file and the power design intent description file without pre-defining the physical voltage domain, to obtain an initial layout result. The initial layout result includes the coordinates of the logic units, which include constant-power logic units and power-off logic units. The partitioning unit 32 is used to divide the layout area of ​​the power-off module into multiple power pixel blocks. The statistics unit 33 is used to determine the power pixel block where the logic unit is located based on the coordinates, and to count the ratio of the number of constant power logic units to the number of turn-off logic units in each power pixel block. The generation unit 34 is used to assign an initial power type to each power pixel block according to the quantity ratio, and generate a distributed physical voltage domain corresponding to the constant power logic unit and the turn-off logic unit defined in the power design intent description file.

[0077] The physical layout system for a power-off module provided in this application proposes a process of global layout followed by dynamic generation of distributed physical voltage domains. Compared with traditional methods, this solution eliminates the need for manual, static physical voltage domain division before layout, effectively avoiding the extended layout cycle caused by repeated iterations and modifications to voltage domain boundaries, and significantly improving layout efficiency. Simultaneously, by dividing the layout area into power pixel blocks and automatically aggregating them based on the actual distribution of logic units after layout, a distributed voltage domain is generated. This ensures that the voltage domain shape closely matches the physical layout and design intent of the circuit, giving the physical layout process greater flexibility. On the one hand, the layout tool can prioritize optimization based on timing, power consumption, and area, without being limited by preset voltage domain boundaries. On the other hand, the system can adaptively handle complex layout scenarios where constant-power units and power-off units are mixed, dispersed, or have ambiguous boundaries, without requiring special avoidance in the front-end design, reducing overall design constraints. In summary, this application, through the aforementioned process refactoring and automated aggregation mechanism, improves layout efficiency while enhancing the adaptability and optimization potential of the physical layout, thereby comprehensively improving layout efficiency and flexibility.

[0078] In some embodiments, the generation unit includes: a comparison module, configured to compare the initial power type of each logic unit in the power pixel block with the power type defined in the power design intent description file; an adjustment module, configured to adjust the position of the logic unit or adjust the power type of the power pixel block where the logic unit is located if the comparison results are inconsistent, so that the initial power type of the logic unit is consistent with the defined power type; and a determination module, configured to determine the boundary of the distributed physical voltage domain based on the power types determined after the adjustment of all power pixel blocks.

[0079] In some embodiments, the adjustment module includes: a replacement submodule, configured to replace the logic unit with a dual-track unit if the logic unit is a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located; and an adjustment submodule, configured to adjust the power type of the power pixel block to be consistent with the power type of the logic unit if the logic unit is another logic unit that is not a buffer or an inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located.

[0080] In some embodiments, the adjustment module is further configured to: if there is a power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then move the logic unit to the power pixel block with the same power type.

[0081] In some embodiments, the generation unit further includes: a maintenance module, configured to check and correct the positions of logic units based on the boundaries of the distributed physical voltage domain, so as to place all logic units within the correct power pixel block; and an insertion module, configured to insert power isolation units at the boundaries of the distributed physical voltage domains corresponding to the constant power logic units and the turn-off logic units, according to the corrected positions of the logic units.

[0082] Thirdly, embodiments of this application also provide an electronic device that facilitates improved layout efficiency and flexibility.

[0083] like Figure 12 As shown, the electronic device provided in the embodiments of this application may include: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is disposed inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are disposed on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, for executing the physical layout method of the power-off module provided in any of the foregoing embodiments.

[0084] For details on the specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running executable program code, please refer to the description of the foregoing embodiments, which will not be repeated here.

[0085] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the physical layout methods for a power-off module provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0086] This application's solution implements a fully algorithmic approach to physical voltage domain setting. By automatically performing constant voltage aggregation and adaptive voltage domain generation after backend placement, it replaces the traditional operation mode that relies on manual experience for pre-definition and manual iterative correction. This significantly shortens the placement cycle while effectively improving the accuracy and consistency of voltage domain planning. Since the preset boundary constraints of the physical voltage domain are completely removed during the placement stage, the placement tool can be fully optimized in multiple key objectives such as timing, power consumption, and routing congestion, thereby obtaining a better initial placement result. Subsequently, based on the optimized placement, the algorithm generates a voltage domain that matches the design intent through fine pixel block analysis and distributed aggregation. This process can be integrated into subsequent stages such as clock tree synthesis and routing optimization for multiple iterations, achieving adaptive dynamic adjustment of the voltage domain to the placement state, ultimately achieving a comprehensive improvement in performance, power consumption, and area. Furthermore, by establishing a large number of fine-grained distributed constant voltage domains, this application can naturally accommodate complex layouts where constant voltage and turn-off circuits are physically interspersed, thereby freeing the front-end design from architectural constraints imposed to avoid back-end implementation difficulties, improving the flexibility of power architecture layout, and helping to achieve more compact area utilization in larger-scale chips.

[0087] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0088] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0089] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0090] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0091] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0092] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A physical layout method for a power-off module, characterized in that, include: Based on the chip physical design file and power design intent description file, a global layout operation is performed on the power-off module without pre-defining the physical voltage domain to obtain an initial layout result. The initial layout result includes the coordinates of logic units, which include constant-power logic units and power-off logic units. The layout area of ​​the power-off module is divided into multiple power pixel blocks; Determine the power pixel block where the logic unit is located based on the coordinates, and count the ratio of the number of constant-power logic units to the number of turn-off logic units in each power pixel block. Based on the stated proportion, an initial power type is assigned to each power pixel block, and a distributed physical voltage domain is generated corresponding to the constant power logic unit and the turn-off logic unit defined in the power design intent description file.

2. The physical layout method for the power-off module according to claim 1, characterized in that, After assigning an initial power type to each power pixel block, the process includes: The initial power type of each logic unit in the power pixel block is compared with the power type defined in the power design intent description file of the logic unit; If the comparison results are inconsistent, adjust the position of the logic unit or adjust the power type of the power pixel block where the logic unit is located so that the initial power type of the logic unit is consistent with the defined power type. The boundary of the distributed physical voltage domain is determined based on the power type determined after adjustment of all power pixel blocks.

3. The physical layout method for the power-off module according to claim 2, characterized in that, Adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located includes: If the logic unit is a buffer or an inverter, and there is no power pixel block of the same power type within a preset range around the power pixel block where the logic unit is located, then the logic unit is replaced with a dual-track unit. If the logic unit is a non-buffer or non-inverter logic unit, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block, then the power type of the power pixel block is adjusted to be consistent with the power type of the logic unit.

4. The physical layout method of the power-off module according to claim 2 or 3, characterized in that, The step of adjusting the position of the logic unit or adjusting the power type of the power pixel block where the logic unit is located further includes: If there is a power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located, then the logic unit is moved to the power pixel block with the same power type.

5. The physical layout method for the power-off module according to claim 2, characterized in that, After determining the boundary of the distributed physical voltage domain, the following is included: Based on the boundaries of the distributed physical voltage domain, check and correct the positions of logic units to place all logic units within the correct power pixel blocks. Based on the corrected logic unit locations, power isolation units are inserted at the boundaries of the distributed physical voltage domains corresponding to the constant-power logic units and the turn-off logic units.

6. The physical layout method for the power-off module according to claim 1, characterized in that, The size of the power pixel block is the same as the size of the preset minimum power line repeating unit.

7. A physical layout system for a power-off module, characterized in that, include: An initial layout unit is used to perform a global layout operation on the power-off module based on the chip physical design file and power design intent description file without pre-defining the physical voltage domain, to obtain an initial layout result. The initial layout result includes the coordinates of logic units, which include constant-power logic units and power-off logic units. A partitioning unit is used to divide the layout area of ​​the power-off module into multiple power pixel blocks; The statistics unit is used to determine the power pixel block where the logic unit is located based on the coordinates, and to count the ratio of the number of constant-power logic units to the number of turn-off logic units in each power pixel block. The generation unit is used to assign an initial power type to each power pixel block according to the said quantity ratio, and generate a distributed physical voltage domain corresponding to the constant power logic unit and the turn-off logic unit defined in the power design intent description file.

8. The physical layout system of the power-off module according to claim 7, characterized in that, The generation unit includes: The comparison module is used to compare the initial power type of each logic unit in the power pixel block with the power type defined by the logic unit in the power design intent description file. An adjustment module is used to adjust the position of the logic unit or the power type of the power pixel block where the logic unit is located if the comparison results are inconsistent, so that the initial power type of the logic unit is consistent with the defined power type. The determination module is used to determine the boundary of the distributed physical voltage domain based on the power type determined after adjustment of all power pixel blocks.

9. The physical layout system of the power-off module according to claim 8, characterized in that, The adjustment module includes: The replacement submodule is used to replace the logic unit with a dual-track unit if the logic unit is a buffer or an inverter and there is no power pixel block of the same power type within a preset range around the power pixel block where the logic unit is located. The adjustment submodule is used to adjust the power type of the power pixel block to be consistent with the power type of the logic unit if the logic unit is another logic unit that is not a buffer or inverter, and there is no power pixel block with the same power type as the logic unit within a preset range around the power pixel block where the logic unit is located.

10. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the physical layout method of the power-off module according to any one of claims 1 to 6.

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