A high-reliability circuit low-power-consumption design method

Abstract

The application discloses a low-power design method of a digital integrated circuit. The method adjusts input signal probability of the digital integrated circuit to achieve a low-power design target of the digital integrated circuit. According to power voltage of the digital integrated circuit and the input signal probability, the combined effect of the two on aging delay of the digital integrated circuit is used to achieve the low-power design target of the digital integrated circuit. The method comprises establishing an input signal probability propagation model of a key path of the digital integrated circuit, measuring and calculating input signal probability of each logic gate standard cell on the key path. An aging delay prediction model of the digital integrated circuit is constructed, and aging delay of the digital integrated circuit is predicted according to the input signal probability of the standard cell on the key path.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor device reliability and integrated circuit design, and particularly to a high-reliability, low-power circuit design method, and a digital integrated circuit designed using this method. Background Technology

[0002] In the fields of integrated circuit design and semiconductor device reliability, low-power design has become a newly emerging technological focus, including how to reduce the dynamic and static power consumption of circuits. Voltage scaling has been considered an effective method for addressing this issue, operating circuits at the lowest possible voltage while maintaining performance, thereby reducing power consumption. Furthermore, dynamic voltage and frequency scaling techniques significantly improve the energy efficiency of circuits by adjusting voltage and frequency to balance performance and power consumption. However, voltage scaling requires fine control and delicate balancing to avoid accelerating circuit aging, which may reduce system reliability over time. Therefore, the impact on long-term stability needs to be carefully considered when implementing these low-power techniques.

[0003] In low-power integrated circuit design, clock gating is another approach. It reduces dynamic power consumption by disabling the clock signal for inactive circuit components. This method has proven effective in reducing unnecessary switching activity, thereby lowering power consumption. On the other hand, power supply gating reduces static power consumption by completely shutting down the power supply to inactive circuit blocks. This method is particularly effective in minimizing leakage power during idle periods, contributing to overall power savings in systolic arrays. In practical applications, the design and implementation of clock gating require consideration of several factors, including timing, power consumption, area, and design complexity. For example, designers need to decide when and how to introduce clock gating into the design, and how to balance the number of gating cells with the power savings.

[0004] Furthermore, employing approximate computation techniques in circuits has become a promising strategy for improving energy efficiency, especially in applications where a trade-off between computational accuracy and power consumption is necessary. Approximate computation (AC) is a technique used in circuit design to improve energy efficiency. It significantly reduces circuit power consumption by allowing a controlled degree of accuracy loss. This technique is particularly suitable for applications that can tolerate a certain level of error, such as machine learning, image processing, and signal processing. The principle of approximate computation is to intentionally introduce acceptable errors during the computation process to reduce the use of computing resources, thereby reducing energy consumption. For example, in digital circuits, approximate computation is achieved by simplifying computational logic, reducing data precision, or reducing computational steps, thereby reducing computational load and power consumption without significantly affecting the final result. Summary of the Invention

[0005] One embodiment of this disclosure provides a low-power design method for high-reliability digital integrated circuits, which achieves low-power design by adjusting the probability of input signals, including:

[0006] By establishing a new framework for aging delay jointly influenced by power supply voltage and input signal probability, a method is introduced that can reduce voltage by about 10% and maintain the same computing speed after circuit aging, thereby significantly improving energy efficiency.

[0007] A critical path signal probability propagation model is constructed, and the signal probability at the critical path cell is accurately calculated based on the input signal probability through detailed analysis of the netlist.

[0008] Two strategies are proposed to enhance the sensitivity of the path to changes in signal probability, thereby expanding the voltage adjustment space and improving the effectiveness of the method of the present invention.

[0009] By adjusting the signal input probability, the circuit's calculation speed can be kept constant while reducing the operating voltage.

[0010] One of the beneficial effects of the embodiments of this disclosure is that low-power circuit design is achieved by changing the probability of the input signal. Attached Figure Description

[0011] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0012] Figure 1 A schematic diagram of the relationship between circuit aging delay and operating voltage according to one embodiment of the present invention.

[0013] Figure 2 A schematic diagram of the fluctuation of aging delay near the baseline caused by the probability of the input signal according to one embodiment of the present invention.

[0014] Figure 3 A schematic diagram of the basic logic gates, truth table, and signal probability transmission relationship according to one embodiment of the present invention.

[0015] Figure 4 A schematic diagram of the critical path of a pulsating array multiply-accumulate unit at 0.9V according to one embodiment of the present invention.

[0016] Figure 5 A schematic diagram showing the relationship between aging delay of the pulsating array multiply-accumulate unit circuit and operating voltage and input signal probability according to one embodiment of the present invention. Detailed Implementation

[0017] While existing designs have advanced low-power integrated circuit technology, several challenges remain. For example, voltage scaling must balance reduced power consumption with increased sensitivity to aging effects and latency variations. Clock gating requires precise control to avoid timing issues, while power gating must manage switching overhead and potential impacts on system stability.

[0018] For AI chips undergoing rapid technological iteration, it is particularly important to minimize power consumption while ensuring reliability. Although significant progress has been made in optimizing the energy efficiency of systolic arrays and their multiply-accumulate units in AI chips through various hardware and algorithmic innovations, these studies have overlooked the crucial role of signal probability manipulation in reducing power consumption. This indicates that further improving the energy efficiency of computing systems through signal probability manipulation is a technologically promising direction for development.

[0019] The systolic array mentioned here is a parallel computing architecture. The multiply-accumulate (MAC) unit is the processing unit in the systolic array that performs multiplication and addition operations. In a systolic array, the MAC unit typically performs matrix multiplication, a fundamental operation in numerical and machine learning applications. The MAC units can work in parallel to improve computational speed and efficiency.

[0020] For example, in Google's TPU (Tensor Processing Unit), systolic arrays are used as the core structure for accelerating matrix multiplication. The TPU accelerates matrix multiplication through MAC modules in the systolic array, where the elements of two matrices flow into the MAC computation array in a specific arrangement. At each step, an intermediate result is obtained in the MAC computation unit, and when all elements have flowed through the MAC computation array, the complete matrix multiplication result is obtained.

[0021] Therefore, this disclosure proposes a method to optimize circuit energy efficiency by adjusting the input signal probability. By utilizing the optimal signal probability and borrowing timing margin, the operating voltage can be reduced while maintaining the circuit's operating frequency and reliability, thereby improving energy efficiency and providing a new approach for achieving low-power design.

[0022] According to one or more embodiments, a low-power design method for high-reliability circuits is based on adjusting signal probability (SP) to influence circuit aging rate, thereby providing operational space for voltage regulation. Here, signal probability is the probability that a signal is in a high-level or low-level state at a specific time. A high signal probability means that the signal is in a high-level or low-level state most of the time, while a low signal probability means that the signal switches frequently between these two states. This switching frequency has a direct impact on circuit aging, as each state switch can lead to wear and tear on circuit components. Adjusting the signal probability can affect the circuit aging rate; by reducing unnecessary signal switching, the effects of the circuit aging mechanism can be mitigated, thereby extending the circuit's lifespan.

[0023] In this embodiment of the disclosure, the signal setup time and hold time are considered constant, while the signal propagation time when the circuit is not aged is affected by voltage. This is because increasing the voltage changes the charging and discharging rate of the capacitor, causing an adjustment in the signal propagation time when the circuit is not aged.

[0024] On the other hand, circuit aging is affected by voltage and signal probability. Higher voltages accelerate the aging process, while the input signal probability interacts with the aging rate in a complex way due to the different propagation modes in various logic gates. However, adjusting the signal probability reduces the degree of aging, allowing the adjusted voltage to achieve the same margin as the original voltage.

[0025] Therefore, the embodiments of this disclosure can achieve voltage regulation and reduce energy consumption while keeping the circuit operating speed constant. The essence of the embodiments of this disclosure is to utilize a portion of the timing margin allocated to aging at the original circuit voltage, and then return it as the aging process progresses, thereby maintaining the same timing margin and improving energy efficiency through voltage regulation.

[0026] In digital circuits, bias temperature instability (BTI) plays a crucial role in the aging process, causing variations in transistor threshold voltages. This phenomenon is intricately linked to the signal probabilities of different transistors within the circuit. Transistors affected by varying signal probabilities experience different threshold voltage shifts due to BTI, ultimately leading to uneven degradation. Consequently, this uneven degradation results in uneven rise and fall delays in logic gates, especially at the end of their expected lifetime.

[0027] This disclosure, through a detailed analysis of signal propagation within the critical path of different logic units under various voltage conditions, reveals a noteworthy observation. When the input signal probabilities of the circuit are systematically adjusted, the signal probabilities along the critical path exhibit a non-uniform distribution. This distribution reflects the complex interaction between input probabilities and operating voltage levels, summarized by the following general equation:

[0028] Δt aging =f( V DD SP in (1)

[0029] Here, SP in V represents the probability of the input signal. DD The operating voltage of the circuit is represented by Δt. aging This represents the delay time caused by circuit aging. Equation (1) summarizes the relationship between voltage, input signal probability and the resulting aging delay, highlighting the sensitivity of changes in aging delay to changes in the circuit's input signal probability.

[0030] This disclosure further investigates the impact of input signal probability on aging delay under different voltage conditions, revealing a trend in which the aging delay fluctuates around its baseline value. The magnitude of these fluctuations is significantly affected by the input signal probability:

[0031] σ Δt =g(sensity, SP) in (2)

[0032] Where, sensitivity represents the degree to which the critical path of the circuit is sensitive to the probabilistic response of the input signal, SP in (signal probability of input) represents the probability of the input signal in the entire circuit. σ Δt This indicates the magnitude of the aging delay fluctuation around its baseline value. It quantifies the variability or uncertainty of the aging delay, reflecting the degree of performance change in the circuit during aging. In other words, the signal probability of cells in the critical path is affected by the input signal probability; the more sensitive the circuit is to the input signal probability, the greater the range of delay that will fluctuate around the baseline after aging when the input signal probability changes. This helps to provide more operating margin for adjusting the operating voltage.

[0033] Equation (2) highlights the critical role of signal probability management in mitigating the adverse effects of aging, thereby improving circuit reliability and lifespan. The results of this disclosure demonstrate the importance of integrating signal probability considerations into the design and optimization process of digital circuits.

[0034] Therefore, based on the above findings, the operating domain of the integrated circuit power reduction design of the embodiments of this disclosure can be determined. While the general trend indicates that circuit aging delay increases with voltage scaling, the curve exhibits a moderately varying region, such as... Figure 1 As shown in the figure, the Delay Increase is expressed as a percentage (%). Voltage (V) is measured in volts. The horizontal axis represents voltage, and the vertical axis represents delay increase. The curve in the figure shows the trend of delay increase as voltage increases. The voltage starts at 0.7V and ends at 1.2V. The delay increase starts at 0 and increases to over 200%. As the voltage increases from 0.7V to 1.2V, the delay increase decreases from its peak value to 0.

[0035] Figure 1 This moderate variation in the aging delay curve can be attributed to the interaction between voltage scaling and its BTI effect. At each voltage level, adjustments to the input signal probability cause the aging delay of the critical path to fluctuate around the baseline value established before adjustment. Therefore, within the curve segment where the aging delay response to voltage changes is weaker, the fluctuation ranges of the aging delay corresponding to adjacent voltages exhibit considerable overlap, such as... Figure 2 As shown in the figure, the Overlap Area refers to the overlapping region. When the input signal probability of the circuit is modified at a given voltage, the aging delay fluctuates around its initial value, highlighted in different colors. Simultaneously, the aging delay exhibits a smoother plateau in its sensitivity to voltage changes. Figure 2 Taking the multiply-accumulate unit in a pulsating array as an example, the aging delay is less sensitive to voltage changes in the vicinity of 0.9V to 1.0V. Therefore, the intersection of these fluctuations forms Figure 2 The overlapping area shown.

[0036] The importance of the overlap region lies in its impact on circuit optimization. Within this region, signal probabilities can be adjusted to ensure that the aging delay of circuits operating at lower voltages is consistent with that of circuits operating at higher voltages, thereby effectively maintaining a consistent aging delay level across different voltage conditions. This adjustment means that by fine-tuning the input signal probabilities, the circuit can achieve lower voltage and power consumption without sacrificing computational power. Essentially, the overlap region provides an opportunity to optimize energy efficiency through signal probability adjustment, thereby mitigating the impact of aging delay on circuit performance while reducing overall energy consumption.

[0037] Furthermore, greater overlap facilitates adjusting the circuit voltage at the same aging level by adjusting the signal probability, thus highlighting a feasible approach to maintaining consistent aging delay characteristics during voltage scaling. It can be concluded that the aging delay of the circuit is jointly determined by the operating voltage and the input signal probability.

[0038] In this embodiment, an input signal probability propagation model is established. Considering the complex relationship between the circuit input signal probability and the input signal probability of each unit within the critical path in controlling data transmission, the signal probability propagation model introduced in this disclosure aims to accurately calculate the input signal probability (signal probability originating from the circuit input port) of the standard unit along the critical path, thereby addressing the inherent complexity in data transmission dynamics.

[0039] Taking basic gates such as AND, NOT, OR, and XOR as examples, their output signal probabilities can be systematically derived from the input signal probabilities using their respective truth tables, such as... Figure 3 , Figure 4 As shown. This basic approach helps to formulate logical expressions that encapsulate the relationship between the input and output signal probabilities for each gate type.

[0040] Figure 3 -a includes a schematic of a logical AND gate and its truth table. Logical expression:

[0041] SP OUT =(SP A +SP B -SP A ×SP B )

[0042] Among them, SP A The probability of input signal A, SP B The probability of input signal B, SP OUT It represents the probability of the output.

[0043] Figure 3 In the -b parameter, the probability propagation calculation of the output signal of the NOT gate is performed.

[0044] SP OUT =1-SP A

[0045] Figure 4This is a schematic diagram of the critical path of a pulsed array multiplier at 0.9V. A pulsed array multiplier performs multiplication and addition operations and consists of multiple multipliers and adders. The critical path here refers to the signal path that determines the slowest operating speed of the digital circuit. For a pulsed array multiplier, this can include an input register, multipliers, adders, and an output register, or it can include a full adder (FA) and a D flip-flop (DFF).

[0046] Based on this, the logical expressions of more complex standard units can be deduced from the combination of these basic gate circuits.

[0047] To establish an input signal probability propagation model, this disclosure presents a Python program to measure the signal probability of each standard cell on the critical path of a circuit. The program calculates the signal probability of the critical path through two steps: First, it "traces the source" of each standard cell on the critical path, i.e., it tracks the source of the input signal for each standard cell all the way to the circuit input. During this process, the program records the signal propagation path from the circuit input to the critical path, clarifying which standard cells the circuit input passes through to reach the critical path. Then, based on the standard cell model in the PDK library, it quantifies the signal propagation probability relationship of each type of standard cell using mathematical expressions. The signal propagation probability of each standard cell is determined by its logical characteristics. In the main program, the signal probability at the circuit input is first substituted into the signal propagation path, and the signal probability relationship expressions for these paths are used to calculate the signal probability of each standard cell on the critical path. These calculation results are input into the subsequent circuit aging prediction model to help accurately assess the reliability of the circuit in actual operation.

[0048] Meanwhile, in this disclosure, the aging prediction model requires information such as the critical path after circuit aging and the signal probability at the input terminal of each standard cell on the critical path to make accurate aging predictions. That is, the output of the input signal probability model is input into the circuit aging prediction model to help accurately assess the reliability of the circuit in actual operation. In constructing the circuit aging prediction model, this disclosure analyzes the synthesized timing report file and netlist file to extract the critical path and data transmission relationship between the input terminals of each standard cell and the circuit input terminal under a specific voltage after aging. Subsequently, by establishing input / output signal probability transmission logic for the standard cells in the standard cell library, the program derives the input signal probability of each standard cell on the critical path, which, together with the original signal probability, is input into the aging prediction model to obtain the aging delay of the circuit under a specific input probability and the reference delay of the circuit before adjustment.

[0049] This program dynamically calculates the response of each node's signal probability to the circuit's input signal probability, outputting the input signal probability of each unit in the critical path. This allows for the use of an aging prediction model to predict the circuit's delay after aging. Combined with the aging delay prediction model, this disclosure utilizes the calculated signal probabilities to assess performance degradation over time.

[0050] According to one or more embodiments, in a low-power integrated circuit design, a scheme is proposed to enhance the sensitivity of the critical path of the circuit and reduce power consumption.

[0051] To optimize circuit energy efficiency through signal probability modulation, the sensitivity of the critical path to changes in input signal probability becomes a crucial concern. This sensitivity describes the degree to which the unit input along the critical path responds to changes in input signal probability, directly impacting aging delay. Increasing sensitivity helps to expand the overlap region of aging delay curves under different voltages, thereby expanding the voltage adjustment range. Here, sensitivity refers to the drastic change in aging delay with signal probability.

[0052] Given that large-scale digital circuits typically have multiple input ports, it is computationally impractical to explore the probability distribution of all possible input signals across all input bits. Therefore, embodiments of this disclosure employ a more targeted approach, prioritizing the exploration of bits that have the most significant impact on aging delay by calculating the influence factor of each bit, thereby simplifying the computation process. The theoretical basis for this is that not all bits contribute equally to the circuit delay after aging. By conducting detailed analysis to identify these critical components, embodiments of this disclosure ensure that optimization efforts are focused on areas that can produce the greatest energy efficiency improvements.

[0053] Here, signal probability modulation optimizes circuit energy efficiency by altering the probability distribution of input signals (i.e., the probability of a signal being high or low). The critical path refers to the signal paths that determine the minimum delay of a digital circuit. Sensitivity is the degree to which the critical path responds to changes in the probability of the input signal. If the critical path reacts significantly to changes in the input signal, then adjusting the probability distribution of these signals can effectively reduce aging delay. Aging delay refers to the gradual decline in the performance of circuit components over time and with circuit use. Aging can lead to increased signal propagation delay, thus affecting circuit performance. Circuit operational flexibility refers to the ability to maintain circuit performance under different operating conditions by adjusting the input signal probability, thereby achieving operational flexibility. The overlapping region of aging delay curves refers to the area where aging delays are similar under different voltage conditions. Expanding this overlapping region means that the circuit can be operated over a wider voltage range while maintaining similar performance. Increasing sensitivity helps to expand the voltage adjustment range, allowing the circuit to operate over a wider voltage range without significantly increasing aging delay.

[0054] The impact factor is an indicator that measures the magnitude of the impact of each input bit on the aging delay. By calculating the impact factor, it is possible to determine which input bits have the most significant impact on the aging delay.

[0055] Therefore, the optimization strategy disclosed herein does not simply test all possible input signal probability distributions, but rather prioritizes those bits that have the greatest impact on aging delay by calculating the influence factor for each bit. This reduces computational load while ensuring that optimization efforts are focused on the areas most likely to improve energy efficiency. Through meticulous analysis, the circuit components that contribute the most to aging delay can be identified to achieve the greatest energy efficiency improvement.

[0056] However, this approach is not without limitations. Focusing only on signal probability variations of individual bits may limit the impact on the signal probability of standard cells on the critical path, potentially limiting the overlapping area and consequently the voltage adjustment space. To address this issue, embodiments of this disclosure propose two methods to enhance the sensitivity of the critical path.

[0057] Firstly, for a given critical path at a given voltage, calculations reveal that the signal probability of certain bits has a particularly significant impact on path aging delay. This disclosure analyzes the impact of signal probabilities of different bits on each standard cell along the path. For example, assuming the multiply-accumulate cell circuit of a systolic array is at 0.9V, the third and fourth input bits have the most significant impact. The analysis shows that specific bits that have a significant impact on the critical path of the circuit may only affect some standard cells, while the signal probabilities of the next most influential bits affect other standard cells, and the range of standard cells affected by these two types of bits does not overlap. This indicates that the impact of the input signal probabilities of many specific bits is limited to certain standard cells.

[0058] Therefore, this method can iteratively adjust specific bits whose influence ranges do not overlap, while keeping other bits unchanged, thereby generating a relationship between the signal probability change and aging delay of the two bits that have the greatest impact on the circuit. For example, iterating the signal probability of the third bit of the affected standard cell in the multiply-accumulate unit circuit of a systolic array while keeping other bits unchanged generates an aging delay relationship that changes with the signal probability of the third bit. Similarly, iterating the signal probability of the fourth bit generates an aging delay curve in response to the change in the signal probability of the fourth bit. By combining these aging delay relationships, the range of critical path delay changes caused by the signal probability changes of the third and fourth bits can be obtained.

[0059] This method optimizes circuit performance and energy efficiency by adjusting the input signal probability, providing a wider range of variation for the aging delay of the critical path. This method is applicable to various voltage and circuit environments, particularly complex logic circuits in high-performance computing systems.

[0060] The second method enhances the sensitivity of the critical path to the input signal probability by discarding bits with minimal impact on precision. When the influence ranges of the two bits most influential on the circuit overlap, the first method becomes ineffective. In this case, if the critical path is deep in the pipeline, analysis shows that the signal probability of the critical path unit fluctuates around 0.5, indicating poor sensitivity of the critical path to the input probability. This phenomenon is attributed to the critical path being located deep within the pipeline stage. This means that input data must pass through multiple logic gates before reaching the critical path. If the probability of each bit being "1" is high, the data transmitted to the critical path will experience multiple "collisions," closely conforming to statistical norms, thus making the impact of the input signal probability on the critical path negligible. Conversely, if the probability of each bit being "0" is high, the data transmitted through multiple logic gates is more likely to retain its original state (e.g., "0" remains "0," and "1" remains "1" after passing through these logic gates), thereby enhancing the direct transmission of the first bit of data to the critical path unit and thus increasing its sensitivity.

[0061] Therefore, this disclosure proposes a method to amplify the impact of input signal probability on the critical path of a circuit by sacrificing data bits with minimal impact on precision. Taking a multiply-accumulate unit of a systolic array at 1.0V as an example, the input signal probability of bits 2 to 7 of fp16 is adjusted to SPin = 0.999 (i.e., the data of these bits is almost always 0), enhancing the sensitivity of the 1.0V critical path to the input signal probability. This adjustment is more advantageous to fp16 format data than 8-bit int because it has the least impact on precision; compared to 8-bit integer (int8), fp16 provides a larger numerical range and precision. Implementation results show that this significantly improves sensitivity and verifies the viewpoint of this disclosure.

[0062] Here, "fp16" represents a half-precision floating-point number, which follows the binary16 format in the IEEE 754 standard. It uses 16 bits to represent a floating-point number, including 1 sign bit, 5 exponent bits, and 10 decimal bits (mantissa bits). "int" usually refers to the integer data type.

[0063] Therefore, embodiments of this disclosure propose a method to enhance the impact of critical bits on the critical path by setting the bits with the least impact on precision to 0. This method highlights the role of data simplification in enhancing input probability sensitivity.

[0064] In summary, given the inherent correlation between signal probability enhancement strategies and the location and structure of the critical path, embodiments of this disclosure propose the above two different input probability sensitivity enhancement strategies.

[0065] According to one or more embodiments, in a low-power integrated circuit design, embodiments of this disclosure aim to determine which bits of input data have a significant impact on the signal probability of cells within the critical path, thereby promoting targeted voltage reduction through strategic bit manipulation. To this end, a computational framework is designed to quantitatively evaluate the impact of the signal probability of each bit on the signal probability of the critical path. This method iteratively adjusts the signal probability of each input bit from 0.1 to 0.9 while maintaining the signal probabilities of all other bits. The input bits are at their baseline values. For each iteration, the absolute deviation of the critical path cell signal probability from its initial state is calculated and summarized. The cumulative deviation obtained through multiple iterations, or up to nine iterations, serves as an influence factor, quantifying the impact of each bit on the critical path signal probability.

[0066] Therefore, the computational framework here includes the following steps:

[0067] (1) First, identify the critical path in the digital circuit.

[0068] (2) Determine which input data bits may have a significant impact on the signal probability within the critical path.

[0069] (3) For each input bit, the signal probability is adjusted iteratively. In each iteration, the signal probability of the selected input bit is adjusted from 0.1 to 0.9, while keeping the signal probability of other bits unchanged.

[0070] (4) For each iteration, calculate the change in the critical path unit signal probability and compare it with the initial state, and summarize the absolute deviation between the critical path unit signal probability and its initial state.

[0071] (5) The cumulative deviation obtained through 9 iterations (because the signal probability is adjusted from 0.1 to 0.9, there are 9 possible values: 0.1, 0.2, ..., 0.9).

[0072] (6) Use cumulative deviation as an influence factor to quantify the influence of each bit on the probability of the critical path signal.

[0073] The baseline value refers to the original signal probability value of the input bit before any adjustments are made. An input bit being at its baseline value means that during the iteration process, all other input bits, except the one currently being adjusted, remain at their original signal probability values, i.e., without change.

[0074] Therefore, the purpose of this computational framework is to identify which input bit signal probability variations have the greatest impact on the critical path of the circuit, so that the signal probabilities of these bits can be adjusted in a targeted manner to reduce the operating voltage while minimizing the impact on circuit performance.

[0075] Taking the multiply-accumulate unit circuit of a systolic array as an example, experiments revealed that bits 3 and 4 have the greatest impact on the critical path at 0.9V; at 1.0V, they are bits 0 and 1, respectively. This analysis process is systematically applied to all input ports of the digital circuit, and the impact factors of all bits are calculated and compared. Subsequently, the bit with the highest impact factor is designated for adjustment, thereby optimizing the voltage reduction operation. This strategic approach not only emphasizes the key role of the variability of input signal probabilities in promoting voltage scaling, but also enhances the importance of interventions aimed at mitigating performance degradation caused by aging. To pursue optimized voltage reduction, the signal probability of the identified target bit is systematically varied from 0.1 to 0.9. Simultaneously, for each iteration, a signal probability calculation tool is used to determine the input signal probability of each unit on the critical path. These calculated signal probability values ​​are then input into a machine learning model to predict their corresponding aging delay.

[0076] This disclosure employs the aforementioned signal probability sensitivity enhancement method to obtain a significant relationship between aging delay, voltage, and input signal probability. Furthermore, there is a clear overlap region in the aging delay fluctuations near the normal operating voltage. This overlap implies that the voltage and aging delay can be effectively modulated by adjusting the input signal probability. Detailed analysis of the curves at these voltages reveals the behavior of the critical path aging delay in response to changes in the input signal probability.

[0077] Below, taking the multiply-accumulate unit circuit of a pulsating array as an example, the method proposed in the embodiments of this disclosure is used to obtain the following... Figure 5The curve shown represents the relationship between the aging delay of the systolic array multiply-accumulate unit and the operating voltage and input signal probability. At 1.0V, the aging delay fluctuates around the initial value of 317.43ps, with the lowest delay (316.48ps) at SP=0.05 and the highest delay (321.98ps) at SP=0.95. At 0.9V, the aging delay fluctuates around the initial value of 320.40ps, with the lowest delay (316.59ps) at SP=0.55 and SP4=0.8 for the 3rd and 4th bit signal probabilities, respectively, and the highest delay (321.88ps).

[0078] According to the method of this disclosure embodiment, by changing the circuit's operating state from the initial point without signal probability adjustment to the lowest point of the curve at 0.9V, that is, from the initial signal probability of 1.0V to 0.9V, the 3rd and 4th bit signal probabilities are SP=0.55 and SP=0.8 respectively, the operating voltage is reduced by 0.1V and the aging delay is optimized by 1ps, thereby reducing power consumption and optimizing performance.

[0079] Figure 5 This figure illustrates the relationship between the aging delay of a pulsating array multiply-accumulate circuit and the operating voltage and signal probability (SP). The curves and data points in the figure represent the aging delay performance of the circuit under different operating voltages and signal probabilities. Figure 5 The vertical axis represents Delay after aging, measured in picoseconds (PS), and the horizontal axis represents Voltage, measured in volts (V).

[0080] Figure 5 This demonstrates that by adjusting the signal probability and operating voltage, circuit performance can be optimized while reducing power consumption, particularly in terms of aging delay. This optimization is significant for improving the energy efficiency and reliability of digital circuits.

[0081] In summary, this disclosure introduces a groundbreaking low-power design method for integrated circuits to improve energy efficiency and ensure circuit performance. The main contents of this disclosure and its corresponding beneficial effects include:

[0082] 1) A new computational framework was established to determine the aging delay by coordinating the working voltage and the input signal probability, thereby forming an effective method to reduce voltage and thus significantly reduce circuit power consumption.

[0083] 2) By adjusting the signal input probability, the circuit calculation speed can be kept constant while reducing the operating voltage.

[0084] 3) An innovative critical path signal probability propagation model is proposed, which can accurately calculate the signal probability of critical path units based on the input signal probability. By deeply analyzing the data transmission relationship in the netlist, the accuracy of the calculation is ensured.

[0085] 4) Two strategies are proposed to enhance the sensitivity of the path to changes in signal probability, expand the voltage adjustment space and optimize the effectiveness of the proposed method, while also providing insights for future circuit design optimization.

[0086] Therefore, this disclosure provides a comprehensive approach to optimizing circuit design by strategically adjusting input signal probability and critical path sensitivity enhancement strategies, offering new ideas for low-power energy-saving circuit design.

[0087] It should be understood that in the embodiments of the present invention, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0088] It is worth noting that although the spirit and principles of this invention have been described with reference to several specific embodiments, it should be understood that this invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that the features in these aspects cannot be combined; such division is merely for the convenience of description. This invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for low power design of digital integrated circuits, characterized in that, The design method establishes an aging delay framework affected by both power voltage and input signal probability, establishes an input signal probability propagation model of a key path of the digital integrated circuit, measures and calculates input signal probabilities of each standard cell of the key path, constructs an aging delay prediction model of the digital integrated circuit, and predicts the aging delay of the digital integrated circuit according to the input signal probabilities of the standard cells on the key path, under the premise of keeping the initial calculation speed index of the digital integrated circuit unchanged, adjusts the input signal probabilities in the overlapping region to keep the aging delay of the circuit running at a lower voltage consistent with the aging delay of the circuit running at a higher voltage, and realizes the low-power design goal of the digital integrated circuit without sacrificing the calculation capability, The overlapping region refers to the overlapping part of the fluctuation ranges of the aging delays corresponding to adjacent voltages in the curve segment in which the aging delay has a weak response to voltage change. Meanwhile, the sensitivity of the key path is enhanced to expand the overlapping region of the aging delay curve of the digital integrated circuit under different power voltages, thereby expanding the power voltage adjustment space.

2. The design method of claim 1, wherein, In the process of constructing the aging delay prediction model, the following steps are further included: analyzing a timing report file and a netlist file generated by synthesis of the digital integrated circuit, extracting the key path and data transmission relationship between the input end of each standard cell after aging and the input end of the digital integrated circuit under a preset voltage, calculating the input signal probability of each standard cell on the key path by establishing a standard cell input-output signal probability transmission logic.

3. The method of claim 1, wherein, The method for enhancing the sensitivity of the key path includes analyzing and comparing the effects of different bit signal probabilities on the aging delay of each standard cell on the key path, and determining at least two bit positions with the greatest effect.

4. The method of designing according to claim 3, wherein, The method for enhancing the sensitivity of the key path further includes, when the influence ranges of the two bit positions with the greatest effect on the circuit aging delay overlap, giving up adjusting the bit position with less influence on the accuracy among the two bit positions with the greatest effect on the circuit aging delay.

5. A digital integrated circuit, characterized by The digital integrated circuit is designed by the low-power design method of the digital integrated circuit according to any one of claims 1 to 4.

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